Display Panel

Abstract

The present application discloses a display panel, wherein n rows of pixels include an i-th pixel located in the i-th row and an (i+j)-th pixel located in the (i+j)-th row, j is an integer greater than or equal to 2, (i+j) is less than or equal to n, a plurality of first scanning level transmission lines extend along a first direction, the plurality of first scanning level transmission lines include an i-th first scanning level transmission line, the i-th first scanning level transmission line is electrically connected to an i-th level first gate driving unit for outputting an i-th first scanning signal, the i-th first scanning level transmission line is electrically connected to both the i-th pixel and the (i+j)-th pixel to output the i-th first scanning signal to the i-th pixel and the (i+j)-th pixel, at least part of the plurality of first scanning level transmission lines overlaps with the pixels to reduce the space occupied by the plurality of first scanning level transmission lines in the peripheral area, thereby facilitating a reduction in the border size of the display panel.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel. Background Art

[0002] As the demand for organic light-emitting diode display panels continues to increase, the demand for narrow borders is becoming more and more important. In particular, the borders of low-temperature polysilicon oxide organic light-emitting diode display panels include complex gate drive circuits and wiring connected to the gate drive circuits, which increases the width of the borders. Too wide borders will affect taste and user experience.

[0003] Therefore, it is necessary to propose a technical solution to solve the problem of too wide border of low-temperature polycrystalline silicon oxide organic light emitting diode display panel. Summary of the invention

[0004] The purpose of the present application is to provide a display panel to solve the problem of too wide a border of the display panel.

[0005] To achieve the above purpose, the technical solution is as follows:

[0006] A display panel, the display panel having a display area and a peripheral area outside the display area, the display panel comprising:

[0007] a gate driving circuit, located in the peripheral area, the gate driving circuit comprising n stages of first gate driving units arranged side by side along a first direction, the n stages of the first gate driving units comprising an i-th stage of first gate driving unit for outputting an i-th first scanning signal, wherein i is a positive integer less than or equal to n, and n is an integer greater than or equal to 3;

[0008] n rows of pixels are arranged side by side along the first direction, the n rows of pixels are arranged in m columns along a second direction intersecting the first direction, the n rows of pixels include an i-th pixel located in the i-th row and an (i+j)-th pixel located in the (i+j)-th row, j is an integer greater than or equal to 2, (i+j) is less than or equal to n, and m is an integer greater than or equal to 1; and

[0009] A plurality of first scanning level transmission lines extend along the first direction, the plurality of first scanning level transmission lines include an i-th first scanning level transmission line, the i-th first scanning level transmission line is electrically connected to the i-th first gate driving unit, and the i-th first scanning level transmission line is electrically connected to both the i-th pixel and the (i+j)-th pixel, and at least part of the plurality of first scanning level transmission lines overlaps with the pixels.

[0010] In the display panel of some embodiments, the n rows of pixels include a plurality of display pixels arranged in the display area, and at least a portion of the plurality of first scanning level transmission lines overlaps with the display pixels.

[0011] In the display panel of some embodiments, the n rows of pixels include a plurality of redundant pixels disposed in the peripheral region, and at least a portion of the plurality of first scanning level transmission lines overlaps with the redundant pixels.

[0012] In the display panel of some embodiments, the display panel further includes:

[0013] a plurality of data lines extending along the first direction, at least part of the plurality of data lines being located in the display area; and

[0014] A connecting line, wherein the connecting line and the data line are located in different film layers, and one connecting line comprises:

[0015] a first connection line, the first connection line is located in the display area, the first connection line extends along the second direction and is connected to the data line located in the display area; and

[0016] The second connection line is connected to the first connection line, and the second connection line extends along the first direction and extends from the display area to the peripheral area.

[0017] In the display panel of some embodiments, the data line, the first connecting line and the second connecting line are respectively located in three different film layers, multiple first scanning level transmission lines and the second connecting lines are located in the same film layer, and multiple first scanning level transmission lines are insulated from the second connecting lines.

[0018] In the display panel of some embodiments, the n rows of pixels include a plurality of display pixels located in the display area, the display pixels include an anode located in the display area, the film layer where the second connecting line is located is located between the film layer where the anode is located and the film layer where the data line is located, and the film layer where the data line is located is located between the film layer where the second connecting line is located and the film layer where the first connecting line is located.

[0019] In the display panel of some embodiments, in the second direction, the plurality of first scanning level transmission lines are located on one side of the plurality of second connecting lines, or the plurality of first scanning level transmission lines are located on two opposite sides of the plurality of second connecting lines.

[0020] In the display panel of some embodiments, each of the pixels includes a pixel circuit, and each of the pixel circuits includes:

[0021] Driver transistor;

[0022] A compensation transistor, wherein a first electrode and a second electrode of the compensation transistor are connected between the gate electrode and the first electrode of the driving transistor;

[0023] an initialization transistor, wherein a first electrode of the initialization transistor is connected to a first initialization signal, and a second electrode of the initialization transistor is connected to a gate of the driving transistor;

[0024] Wherein, the gate of the compensation transistor of the i-th pixel and the gate of the initialization transistor of the (i+j)-th pixel are both connected to the i-th first scanning stage transmission line.

[0025] In the display panel of some embodiments, the gate driving circuit further includes n-stage second gate driving units arranged side by side along the first direction, and the n-stage second gate driving units include an i-th stage second gate driving unit for outputting an i-th second scanning signal;

[0026] The display panel further includes a plurality of second scanning level transmission lines, the plurality of second scanning level transmission lines include an i-th second scanning level transmission line, and the i-th second scanning level transmission line is electrically connected to the i-th second gate driving unit;

[0027] Each pixel circuit also includes:

[0028] a data writing transistor, wherein a first electrode of the data writing transistor is connected to a second electrode of the driving transistor, and a second electrode of the data writing transistor is connected to a data signal; and

[0029] A reset transistor, wherein a first electrode of the reset transistor is connected to a second initialization signal, and a second electrode of the reset transistor is connected to a first electrode of the drive transistor;

[0030] The n rows of pixels also include the (i+1)th pixel located in the (i+1)th row;

[0031] The gate of the data writing transistor of the i-th pixel and the gate of the reset transistor of the (i+1)-th pixel are connected to the i-th second scanning stage transmission line.

[0032] In the display panel of some embodiments, the gate driving circuit further includes n-stage light emitting control units arranged side by side along the first direction, and the n-stage light emitting control units include an i-th stage light emitting control unit for outputting an i-th light emitting control signal;

[0033] Each of the pixel circuits further comprises:

[0034] a first light emission control transistor, wherein a first electrode and a second electrode of the first light emission control transistor are connected between a first power supply signal and a second electrode of the driving transistor; and

[0035] a second light emitting control transistor, wherein a first electrode and a second electrode of the second light emitting control transistor are connected between the first electrode of the driving transistor and a second power supply signal;

[0036] Among them, the gate of the first light emitting control transistor of the i-th pixel and the gate of the second light emitting control transistor of the i-th pixel are both connected to the i-th light emitting control signal.

[0037] Beneficial effects: The present application provides a display panel, wherein a plurality of first scanning level transmission lines extend along a first direction, the plurality of first scanning level transmission lines include an i-th first scanning level transmission line, the i-th first scanning level transmission line is electrically connected to an i-th first gate driving unit for outputting an i-th first scanning signal, the i-th first scanning level transmission line is electrically connected to an i-th pixel located in an i-th row and an (i+j)-th pixel located in an (i+j)-th row, so as to output the i-th first scanning signal to the i-th pixel and the (i+j)-th pixel, and at least part of the plurality of first scanning level transmission lines overlaps with the pixels, so as to reduce the space occupied by the plurality of first scanning level transmission lines in the peripheral area, thereby facilitating reduction in the border size of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 A schematic plan view of a display panel according to an embodiment of the present application;

[0039] Figure 2 is a circuit diagram of a display pixel;

[0040] Figure 3 for Figure 1 A first partial enlarged schematic diagram of the display panel is shown;

[0041] Figure 4 for Figure 1 A second partial enlarged schematic diagram of the display panel is shown;

[0042] Figure 5 for Figure 2 A schematic cross-sectional view of a display panel is shown;

[0043] Figures 6A-6I for Figure 1 A schematic plan view of multiple film layers of a display panel is shown. DETAILED DESCRIPTION

[0044] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0045] See also Figure 1 , which is a schematic plan view of a display panel according to an embodiment of the present application. The display panel 100 is an organic light emitting diode display panel. The display panel 100 has a display area 100a and a peripheral area 100b located outside the display area 100a.

[0046] Please also see Figure 1 , Figure 3 and Figure 4 , Figure 3 for Figure 1 The first partial enlarged schematic diagram of the display panel is shown, Figure 4 for Figure 1 A second partial enlarged schematic diagram of a display panel is shown. The display panel 100 includes n rows of pixels arranged side by side along a first direction and a gate driving circuit 30, the n rows of pixels are arranged in m columns along a second direction intersecting the first direction, n is an integer greater than or equal to 3, and m is an integer greater than or equal to 1. Specifically, the first direction is perpendicular to the second direction.

[0047] The n-row pixels include a plurality of display pixels P and a plurality of redundant pixels DP. The plurality of display pixels P are located in the display area 100a and arranged in an array along the first direction and the second direction. The plurality of redundant pixels DP are located in the peripheral area 100b and arranged along the edge of the display area 100a.

[0048] It should be noted that the plurality of display pixels P are used for display; the plurality of redundant pixels DP cannot display and are used to improve the process yield of the plurality of display pixels P. The display panel 100 may not include the plurality of redundant pixels DP.

[0049] The n rows of pixels include the ith pixel located in the ith row, the (i+1)th pixel located in the (i+1)th row, and the (i+j)th pixel located in the (i+j)th row. The ith pixel, the (i+1)th pixel, and the (i+j)th pixel may be located in the same column, or the ith pixel, the (i+1)th pixel, and the (i+j)th pixel may be located in different columns. i and (i+1) are both positive integers less than or equal to n, j is an integer greater than or equal to 2, and (i+j) is less than or equal to n. The value of j may be an odd number, for example, j is 3, 5, 7, or 9.

[0050] See also Figure 2 , which is a circuit diagram of a display pixel. Each display pixel P includes a first pixel circuit 101 located in a display area 100a and a light emitting device OLED located in the display area 100a, and the light emitting device OLED is electrically connected to the first pixel circuit 101 located in the display area 100a.

[0051] Each redundant pixel DP is composed of a second pixel circuit located in the peripheral area 100 b , that is, the redundant pixel DP does not include a light emitting device, and the second pixel circuit in the peripheral area 100 b is the same as the first pixel circuit 101 in the display area 100 a .

[0052] The second pixel circuits in the peripheral area 100b and the first pixel circuits 101 in the display area 100a form n rows of pixel circuits arranged side by side along a first direction. The n rows of pixel circuits are arranged in m columns along a second direction intersecting the first direction, where m is an integer greater than or equal to 2.

[0053] Combined with the following Figure 2 The display pixel P in the i-th row and k-th column describes the pixel circuit and the light-emitting device OLED connected to the pixel circuit, k is a positive integer less than or equal to m, and the pixel circuits of other pixels can be deduced similarly, which will not be described in detail here.

[0054] The light emitting device OLED includes an anode, a cathode and an organic light emitting layer located between the cathode and the anode.

[0055] The first pixel circuit 101 includes seven thin film transistors and two capacitors. Each thin film transistor includes a first electrode, a second electrode and a gate electrode, one of the first electrode and the second electrode is a source electrode, and the other of the first electrode and the second electrode is a drain electrode.

[0056] The seven thin film transistors include a driving transistor T1, a data writing transistor T2, a compensation transistor T3, an initialization transistor T4, a first light emission control transistor T5, a second light emission control transistor T6, and a reset transistor T7. The driving transistor T1, the data writing transistor T2, the first light emission control transistor T5, the second light emission control transistor T6, and the reset transistor T7 are all P-type low temperature polysilicon transistors, and the compensation transistor T3 and the initialization transistor T4 are all N-type metal oxide transistors.

[0057] The driving transistor T1 is used to provide a driving current for the light emitting device OLED. A first electrode of the driving transistor T1 is connected to the light emitting device OLED.

[0058] The compensation transistor T3 is used to connect the first electrode and the gate of the driving transistor T1. The first electrode and the second electrode of the compensation transistor T3 are connected between the gate and the first electrode of the driving transistor T1, and the gate of the compensation transistor T3 is connected to the i-th first scanning signal NScan(i).

[0059] The initialization transistor T4 is used to initialize the gate of the driving transistor T1. The first electrode of the initialization transistor T4 is connected to the first initialization signal VI1, the second electrode of the initialization transistor T4 is connected to the gate of the driving transistor T1, and the gate of the initialization transistor T4 is connected to the (ij) first scanning signal NScan(ij).

[0060] The first electrode of the data writing transistor T2 is connected to the second electrode of the driving transistor T1 , the second electrode of the data writing transistor T2 is connected to the kth data signal D(k), and the gate of the data writing transistor T2 is connected to the i-th second scanning signal PScan(i).

[0061] The reset transistor T7 is used to reset the anode of the light emitting device OLED. The first electrode of the reset transistor T7 is connected to the second initialization signal VI2, the second electrode of the reset transistor T7 is connected to the first electrode of the driving transistor T1, and the gate of the reset transistor T7 is connected to the (i-1)th second scanning signal PScan(i-1).

[0062] The first electrode and the second electrode of the first light emitting control transistor T5 are connected between the first power supply signal VDD and the second electrode of the driving transistor T1 , and the gate of the first light emitting control transistor T5 is connected to the i-th light emitting control signal EM(i).

[0063] The first electrode and the second electrode of the second light emitting control transistor T6 are connected between the first electrode of the driving transistor T1 and the second power supply signal VSS, and the gate of the second light emitting control transistor T6 is connected to the i-th light emitting control signal EM(i).

[0064] The two capacitors include a first capacitor C1 and a second capacitor C2. The first capacitor C1 is connected between the first power signal VDD and the gate of the driving transistor T1, and the second capacitor C2 is connected between the i-th second scanning signal PScan(i) and the gate of the driving transistor T1.

[0065] Combination Figure 2 It can be seen that the compensation transistor T3 of the i-th pixel circuit of the i-th pixel located in the i-th row and the initialization transistor T4 of the (i+j)-th pixel circuit located in the (i+j)-th row both receive the i-th first scanning signal NScan(i); the data writing transistor T2 of the i-th pixel circuit located in the i-th row and the reset transistor T7 of the (i+1)-th pixel circuit located in the (i+1)-th row both receive the i-th second scanning signal PScan(i).

[0066] See also Figure 1 , Figure 3 and Figure 4In the second direction, the gate driving circuit 30 is located at two opposite sides of the display area 100a. It can be understood that in the second direction, the gate driving circuit 30 can also be located at only one side of the display area 100a.

[0067] The gate driving circuit 30 is located in the peripheral area 100b. The gate driving circuit 30 located on one side of the display area 100a includes n-level first gate units A, n-level second gate driving units B and n-level light emitting control units C. One first gate driving unit A, one second gate driving unit B and one light emitting control unit C form a repeating unit.

[0068] The n-stage first gate units A are arranged side by side along the first direction, and the n-stage first gate units A include an i-th first gate driving unit A(i) for outputting an i-th first scan signal NScan(i), where i is greater than or equal to 1 and less than or equal to n.

[0069] In order to enable the i-th first scanning signal NScan(i) output by the i-th first gate driving unit A(i) to be output to the i-th pixel located in the i-th row and the (i+j)-th pixel located in the (i+j)-th row, the display panel 100 also includes a plurality of adjacently arranged first scanning level transmission lines L, the plurality of first scanning level transmission lines L extend along the first direction and are arranged side by side along the second direction, each first scanning level transmission line L is connected to the first-level first gate driving unit A, the plurality of first scanning level transmission lines L include the i-th first scanning level transmission line Li, the i-th first scanning level transmission line Li is electrically connected to the i-th first gate driving unit A(i) through the i-th first horizontal line Si extending along the second direction, and the i-th first scanning level transmission line L(i) is connected to both the pixels in the i-th row and the pixels in the (i+j)-th row.

[0070] Specifically, the i-th first scanning level transmission line L(i) is connected to the i-th display pixel P(i) in the i-th row, the i-th redundant pixel DP(i) in the i-th row, the (i+j)-th display pixel P(i+j) in the (i+j)-th row, and the (i+j)-th redundant pixel DP(i+j) in the (i+j)-th row.

[0071] It should be noted that since each of the multiple adjacent first scanning level transmission lines L needs to be connected to pixels spaced more than j rows apart, each first scanning level transmission line L needs to span a larger space in the first direction. In order to avoid the first scanning level transmission lines L from intersecting with other lines extending in the second direction when extending, the multiple first scanning level transmission lines L also need to occupy more space in the second direction.

[0072] In the display panel of the embodiment of the present application, at least part of the plurality of first scanning level transmission lines L overlaps with the pixels, so as to save the independent space required for arranging the plurality of first scanning level transmission lines L in the peripheral area 100b, thereby facilitating reducing the size of the peripheral area 100b in the second direction.

[0073] like Figure 3 As shown, at least a portion of the plurality of first scan level transmission lines L overlaps with the display pixel P, so that at least a portion of the plurality of first scan level transmission lines L is disposed in the display area 100a. Compared with the plurality of first scan level transmission lines L being disposed in the peripheral area 100b between the redundant pixel DP and the gate driving circuit 30, at least a portion of the plurality of first scan level transmission lines L is disposed in the display area 100a, which is more conducive to reducing the size of the peripheral area 100b in the second direction.

[0074] The spacing between any two adjacent first scan level transmission lines L is equal. The plurality of first scan level transmission lines L may all overlap with the display pixels P. For example, the plurality of first scan level transmission lines L overlap with one column, two columns, or more than two columns of display pixels P. It is understandable that part of the plurality of first scan level transmission lines L may also overlap with the display pixels P.

[0075] The plurality of first scanning level transmission lines L overlap with the display pixels P near the peripheral area 100b, so as to reduce the size of the peripheral area in the second direction and reduce the risk of short circuit between the plurality of first scanning level transmission lines L and the circuit of the display area 100a. For example, the plurality of first scanning level transmission lines L overlap with the display pixels P adjacent to the redundant pixels DP, or the plurality of first scanning level transmission lines L overlap with one, two or three columns of display pixels P near the peripheral area 100b.

[0076] It can be understood that the multiple first scanning level transmission lines L can also overlap with the display pixels P in the middle position of the display area 100a in the second direction, or the multiple first scanning level transmission lines L can also overlap with the display pixels P located between the middle position of the display area 100a in the second direction and the edge of the display area 100a in the second direction.

[0077] like Figure 4 As shown, at least part of the multiple first scanning level transmission lines L overlap with the redundant pixels DP, so that at least part of the multiple first scanning level transmission lines L are arranged in the peripheral area 100b, while saving the independent layout space required for at least part of the multiple first scanning level transmission lines L in the peripheral area 100b, which is beneficial to reduce the size of the peripheral area 100b in the second direction.

[0078] The plurality of first scanning level transmission lines L overlap with the redundant pixels DP to save the independent layout space required for the plurality of first scanning level transmission lines L in the peripheral area 100b. For example, the plurality of first scanning level transmission lines L overlap with a column of redundant pixels DP.

[0079] It can be understood that part of the multiple first scanning level lines L can overlap with the redundant pixel DP, and another part of the multiple first scanning level lines L is located between the redundant pixel DP and the gate driving circuit 30; or, part of the multiple first scanning level lines L overlap with the redundant pixel DP, and another part of the multiple first scanning level lines L overlap with the display pixel P.

[0080] In the case where the gate driving circuit 30 is located at one side of the display area 100 a , in the second direction, the plurality of first scanning level transmission lines L are located at one side of the plurality of second connection lines CL2 .

[0081] In the case where the gate driving circuit 30 is located at two opposite sides of the display area 100 a , the plurality of first scanning level transmission lines L are located at two opposite sides of the plurality of second connection lines CL2 .

[0082] Please refer again Figure 1 The display panel 100 further includes a plurality of data lines d extending along a first direction, a portion of the plurality of data lines d being located in the display area 100a, and a portion of the plurality of data lines d being located in the peripheral area 100b, the data lines d located in the display area 100a being electrically connected to the display pixels P, and the data lines d located in the peripheral area 100b being electrically connected to the redundant pixels P.

[0083] The display panel 100 also includes a plurality of connection lines CL, and the plurality of connection lines CL and the plurality of data lines d are located in different film layers. One connection line CL includes a first connection line CL1 and a second connection line CL2. The first connection line CL1 is located in the display area 100a. The first connection line CL1 extends along the second direction and is connected to the data line d located in the display area 100a. The second connection line CL2 is connected to the first connection line CL1. The second connection line CL2 extends along the first direction and extends from the display area 100a to the peripheral area 100b and is electrically connected to the driving chip in the peripheral area 100b.

[0084] The design of the plurality of connection lines CL allows the fan-shaped region disposed in the peripheral region 100 b in the conventional technology to be omitted, so that the size of the peripheral region 100 b in the first direction is reduced.

[0085] See also Figure 5 , which is Figure 2 The display panel includes a substrate 10, a driving circuit layer 20 and a light emitting device layer 40. The driving circuit layer 20 is disposed on the substrate 10, and the light emitting device layer 40 is disposed on a side of the driving circuit layer 20 away from the substrate 10.

[0086] The driving circuit layer 20 includes a first semiconductor layer 201, a first insulating layer 202, a first conductive layer 203, a second insulating layer 204, a second conductive layer 205, a third insulating layer 206, a second semiconductor layer 207, a fourth insulating layer 208, a third conductive layer 209, a fifth insulating layer 210, a fourth conductive layer 211, a sixth insulating layer 212, a fifth conductive layer 213, a seventh insulating layer 214, a sixth conductive layer 215, an eighth insulating layer 216 and a pixel definition layer 217 stacked in sequence.

[0087] The first insulating layer 202, the second insulating layer 204 and the fourth insulating layer 208 are all gate insulating layers. The third insulating layer 206 and the fifth insulating layer 210 are all interlayer insulating layers. The first insulating layer 202, the second insulating layer 204, the fourth insulating layer 208, the third insulating layer 206 and the fifth insulating layer 210 are made of at least one material selected from silicon nitride or silicon oxide.

[0088] The sixth insulating layer 212, the seventh insulating layer 214 and the eighth insulating layer 216 are all organic planarization layers. The sixth insulating layer 212, the seventh insulating layer 214 and the eighth insulating layer 216 are made of a material selected from at least one of polyimide and polyacrylate.

[0089] The first semiconductor layer 201 is a low temperature polycrystalline silicon semiconductor layer. The first semiconductor layer 201 includes a first active pattern 2011 of the driving transistor T1, a second active pattern of the data writing transistor T2, a fifth active pattern of the first light emission control transistor T5, a sixth active pattern 2016 of the second light emission control transistor T6, and a seventh active pattern of the reset transistor T7. The first semiconductor layer 201 also includes an active pattern of a thin film transistor in the gate driving circuit 30.

[0090] The second semiconductor layer 207 is a metal oxide semiconductor layer and includes a third active pattern of the compensation transistor T3 and a fourth active pattern 2071 of the initialization transistor T4.

[0091] The first conductive layer 203 , the second conductive layer 205 , the third conductive layer 209 , the fourth conductive layer 211 , the fifth conductive layer 213 and the sixth conductive layer 215 are made of at least one material selected from molybdenum, aluminum, titanium, copper and silver.

[0092] The first conductive layer 203 includes a first gate 2031 of the driving transistor T1, a second gate of the data writing transistor T2, a fifth gate of the first light emission control transistor T5, a sixth gate 2036 of the second light emission control transistor T6, and a seventh gate of the reset transistor T7. The first conductive layer 203 also includes the gate of the thin film transistor in the gate driving circuit 30.

[0093] The first gate 2031 is disposed corresponding to the first active pattern 2011 , the second gate is disposed corresponding to the second active pattern, the fifth gate is disposed corresponding to the fifth active pattern, the sixth gate 2036 is disposed corresponding to the sixth active pattern 2016 , and the seventh gate is disposed corresponding to the seventh active pattern.

[0094] The second conductive layer 205 includes an electrode plate 2051 , a third lower gate of the compensation transistor T3 , and a fourth lower gate 2054 of the initialization transistor T4 .

[0095] The electrode plate 2051 is disposed corresponding to the first grid 2031 , and the electrode plate 2051 and the first grid 2031 are divided into two electrode plates of the first capacitor C1 . The third lower grid is disposed corresponding to the third active pattern. The fourth lower grid 2054 is disposed corresponding to the fourth active pattern 2071 .

[0096] The third conductive layer 209 includes a third upper gate of the compensation transistor T3 and a fourth upper gate 2094 of the initialization transistor T4 .

[0097] The third upper gate of the compensation transistor T3 is disposed corresponding to the third active pattern and is electrically connected to the third lower gate. The fourth upper gate 2094 of the initialization transistor T4 is disposed corresponding to the fourth active pattern 2071 and is electrically connected to the fourth lower gate 2054.

[0098] The fourth conductive layer 211 includes a first connection line CL1. The fifth conductive layer 213 includes a plurality of data lines d and a first power signal line. The sixth conductive layer 215 includes a second connection line CL2, and the second connection line CL2 is electrically connected to the first connection line CL1 through a via hole penetrating the sixth insulating layer 212 and the seventh insulating layer 214. Therefore, the data line d, the first connection line CL1, and the second connection line CL2 are respectively located in three different film layers.

[0099] Since the extension direction of the first connecting line CL1 intersects with the multiple first scanning level transmission lines L, and the multiple data lines d are densely arranged in the fifth conductive layer 213, and the sixth conductive layer 215 includes more space for laying wires, in order to reduce the risk of short circuit between the multiple first scanning level transmission lines L and other circuits, the multiple first scanning level transmission lines L and the second connecting lines CL2 are located in the same film layer, and the multiple first scanning level transmission lines L and the second connecting lines CL2 are insulated.

[0100] It should be noted that the plurality of first scanning level transmission lines L may also be located in an independent conductive film layer different from the first conductive layer 203 to the sixth conductive layer 215 .

[0101] The pixel definition layer 217 includes a pixel opening and is an organic insulating layer.

[0102] The light emitting device layer 40 includes an anode 401, an organic light emitting layer 402 and a cathode 403. The organic light emitting layer 402 is located between the anode 401 and the cathode 403. The anode 401 is arranged corresponding to the pixel opening, and the pixel opening exposes a portion of the anode 401. The organic light emitting layer 402 is arranged in the pixel opening.

[0103] When multiple first scanning level transmission lines L and second connection lines CL2 are all located in the sixth conductive layer 215, the film layer where the second connection line CL2 is located is located between the film layer where the anode 401 is located and the film layer where the data line d is located, and the film layer where the data line d is located is located between the film layer where the second connection line CL2 is located and the film layer where the first connection line CL1 is located.

[0104] The following Figure 5 The diagram is described with reference to a plan view of multiple film layers in a display panel.

[0105] like Fig. 6A As shown, the first semiconductor layer 201 includes a plurality of first semiconductor patterns 201a of pixels, and the semiconductor patterns 201a of two adjacent pixels are connected and symmetrically arranged. The first semiconductor pattern 201a of each pixel includes a first vertical portion 201b, a first horizontal portion 201c, a second vertical portion 201d, a second horizontal portion 201e, a third vertical portion 201f and a third horizontal portion 201g. The first vertical portion 201b, the second vertical portion 201d and the third vertical portion 201f all extend along the first direction, and the first horizontal portion 201c, the second horizontal portion 201e and the third horizontal portion 201g all extend along the second direction.

[0106] The third horizontal portion 201g of one pixel is connected to the third horizontal portion 201g of another adjacent pixel, the third horizontal portion 201g is connected to the first vertical portion 201b, the first vertical portion 201b is connected to the first horizontal portion 201c, the first horizontal portion 201c is connected to the second vertical portion 201d and the second vertical portion 201d is arranged opposite to the first vertical portion 201b, the second horizontal portion 201e is connected to the second vertical portion 201d and is arranged opposite to the first horizontal portion 201c, and the third vertical portion 201f is connected to the second horizontal portion 201e and the third vertical portion 201f extends in a direction away from the first vertical portion 201b.

[0107] The first horizontal portion 201c includes a first active pattern 2011 of a driving transistor T1. The first vertical portion 201b includes a second active pattern 2012 of a data writing transistor T2 and a fifth active pattern 2015 of a first light emission control transistor T5, and the second active pattern 2012 and the fifth active pattern 2015 are located at opposite ends of the first vertical portion 201b. The second vertical portion 201d includes a sixth active pattern 2016 of a second light emission control transistor T6. The third vertical portion 201f includes a seventh active pattern 2017 of a reset transistor T7.

[0108] like Figure 6B As shown, the first conductive layer 203 includes an (i-1)th second scanning signal line 203a, an i-th light-emitting control signal line 203b, a first gate 2031, and an i-th second scanning signal line 203c. The (i-1)th second scanning signal line 203a, the i-th light-emitting control signal line 203b, and the i-th second scanning signal line 203c all extend along the second direction. The (i-1)th second scanning signal line 203a is disposed adjacent to the i-th light-emitting control signal line 203b, the first gate 2031 is located on a side of the i-th light-emitting control signal line 203b away from the (i-1)th second scanning signal line 203a, and the i-th second scanning signal line 203c is located on a side of the first gate 2031 away from the i-th light-emitting control signal line 203b.

[0109] The (i-1)th second scanning signal line 203a intersects the third vertical portion 201f, and the portion where the (i-1)th second scanning signal line 203a intersects the third vertical portion 201f is the seventh gate 2037 of the reset transistor T7.

[0110] The i-th light-emitting control signal line 203b intersects with the second vertical portion 201d and the first vertical portion 201b. The portion where the i-th light-emitting control signal line 203b intersects with the first vertical portion 201b is the fifth gate 2035 of the first light-emitting control transistor T5, and the portion where the i-th light-emitting control signal line 203b intersects with the second vertical portion 201d is the sixth gate 2036 of the second light-emitting control transistor T6.

[0111] The first gate 2031 is disposed overlapping the first horizontal portion 201 c .

[0112] The i-th second scanning signal line 203c intersects with the first vertical portion 201b, and the portion where the i-th second scanning signal line 203c intersects with the first vertical portion 201b is the second gate 2032 of the data writing transistor T2.

[0113] like Figure 6CAs shown, the second conductive layer 205 includes an electrode plate 2051, an i-th first down scan signal line 205a, an (ij)-th first down scan signal line 205b, and a first initialization signal line 205c. The i-th first down scan signal line 205a, the (ij)-th first down scan signal line 205b, and the first initialization signal line 205c all extend along the second direction.

[0114] The electrode plate 2051 is disposed corresponding to the first grid 2031 , and the electrode plate 2051 includes an electrode plate opening 2051 a disposed corresponding to the first grid 2031 .

[0115] The orthographic projection of the ith first down scan signal line 205a on the substrate 10 is located between the orthographic projection of the electrode plate 2051 on the substrate 10 and the orthographic projection of the ith second down scan signal line 203c on the substrate 10. The ith first down scan signal line 205a includes a third lower gate 2053 of the compensation transistor T3.

[0116] The orth projection of the (ij)th first down scan signal line 205b on the substrate 10 is located on a side away from the orth projection of the i-th second scan signal line 203c on the substrate 10. The (ij)th first down scan signal line 205b includes a fourth lower gate 2054 of the initialization transistor T4.

[0117] The first initialization signal line 205c is located at a side of the (ij)th first down scan signal line 205b, where the orth projection of the first down scan signal line 205b on the substrate 10 is away from the i-th first down scan signal line 205a. The first initialization signal line 205c is used to transmit a first initialization signal VI1.

[0118] like Fig.6D As shown, the second semiconductor layer 207 includes a second semiconductor pattern 207a. The second semiconductor pattern 207a extends along the first direction. The second semiconductor pattern 207a includes a third active pattern 2073 of the compensation transistor T3 and a fourth active pattern 2074 of the initialization transistor T4. The second semiconductor pattern 207a overlaps with the third lower gate 2053 of the i-th first lower scan signal line 205a, and the second semiconductor pattern 207a also overlaps with the fourth lower gate 2054 of the (ij)-th first lower scan signal line 205b. The portion of the second semiconductor pattern 207a overlapping with the i-th second scan signal line 203c and the portion of the i-th second scan signal line 203c overlapping with the second semiconductor pattern 207a are two electrode plates of the second capacitor C2, respectively.

[0119] like Fig. 6EAs shown, the third conductive layer 209 includes an i-th first upper scan signal line 209a and an (ij)-th first upper scan signal line 209b, and the i-th first upper scan signal line 209a and the (ij)-th first upper scan signal line 209b both extend along the second direction. The i-th first upper scan signal line 209a is partially overlapped with the i-th first lower scan signal line 205a, and the (ij)-th first upper scan signal line 209b is partially overlapped with the (ij)-th first lower scan signal line 205b.

[0120] like Fig. 6F As shown, the display panel 100 includes a first contact hole H1, a second contact hole H2, a third contact hole H3, a fourth contact hole H4, a fifth contact hole H5, a sixth contact hole H6, a seventh contact hole H7, an eighth contact hole H8, a ninth contact hole H9, a tenth contact hole H10, an eleventh contact hole H11, a twelfth contact hole H12 and a thirteenth contact hole H13.

[0121] A first contact hole H1 penetrating the fifth insulating layer 210 , the fourth insulating layer 208 , the third insulating layer 206 , the second insulating layer 204 and the first insulating layer 202 connects the second initialization signal line 211 a and the third vertical portion 201 f to connect the first electrode of the reset transistor T7 to the second initialization signal line 211 a .

[0122] A second contact hole H2 penetrating the fifth insulating layer 210 , the fourth insulating layer 208 , the third insulating layer 206 , the second insulating layer 204 and the first insulating layer 202 connects the first lead 211 b and the first vertical portion 201 b to connect the second electrode of the data writing transistor T2 to the first lead 211 b hereinafter.

[0123] The third contact hole H3 penetrating the fifth insulating layer 210 , the fourth insulating layer 208 , and the third insulating layer 206 connects the (ij)th first upper scan signal line 209 b and the (ij)th first lower scan signal line 205 b .

[0124] The fourth contact hole H4 penetrating the fifth insulating layer 210 , the fourth insulating layer 208 , and the third insulating layer 206 connects the first initialization signal line 205 c and a third lead line 211 d hereinafter.

[0125] The fifth contact hole H5 penetrating the fifth insulating layer 210, the fourth insulating layer 208, the third insulating layer 206, the second insulating layer 204 and the first insulating layer 202 connects the fourth lead 211e below and the third horizontal portion 201g, so that the fourth lead 211e below is connected to the first light emission control transistor T5.

[0126] The sixth contact hole H6 penetrating the fifth insulating layer 210, the fourth insulating layer 208, the third insulating layer 206, the second insulating layer 204 and the first insulating layer 202 connects the fifth lead 211f below to the second horizontal portion 201e, so that the fifth lead 211f below is connected to the second light emission control transistor T6.

[0127] The seventh contact hole H7 penetrating the fifth insulating layer 210 , the fourth insulating layer 208 , the third insulating layer 206 , the second insulating layer 204 and the first insulating layer 202 connects the sixth lead 211g below with the first horizontal portion 201c , so that the sixth lead 211g below is connected to the first electrode of the driving transistor T1 .

[0128] The eighth contact hole H8 penetrating the fifth insulating layer 210, the fourth insulating layer 208, the third insulating layer 206 and the second insulating layer 204 is connected to the electrode plate opening 2051a, and one end of the seventh lead 211h described below is connected to the first gate 2031 through the eighth contact hole H8 and the electrode plate opening 2051a.

[0129] The ninth contact hole H9 penetrating the fifth insulating layer 210 , the fourth insulating layer 208 , and the third insulating layer 206 connects a fourth lead line and the electrode plate 2051 described below.

[0130] The tenth contact hole H10 penetrating the fifth insulating layer 210 and the fourth insulating layer 208 connects the seventh wiring 211h and the second semiconductor pattern 207a below so that the first gate electrode 2031 of the driving transistor T1 is connected to the first electrode of the compensation transistor T3 and the second electrode of the initialization transistor T4.

[0131] The eleventh contact hole H11 penetrating the fifth insulating layer 210 and the fourth insulating layer 208 connects the sixth lead 211g below and the second semiconductor pattern 207a to connect the first electrode of the driving transistor T1 with the second electrode of the compensation transistor T3, that is, the sixth lead 211g below bridges the first electrode of the driving transistor T1 and the second electrode of the compensation transistor T3.

[0132] The twelfth contact hole H12 penetrating the fifth insulating layer 210 and the fourth insulating layer 208 connects the third lead 211d and the second semiconductor pattern 207a below so that the third lead 211d bridges the first initialization signal line 205c and the first electrode of the initialization transistor T4.

[0133] The thirteenth contact hole H13 penetrating the fifth insulating layer 210 connects the second lead line 211c and the (ij)th first upper scan signal line 209b hereinafter.

[0134] like Figure 6GAs shown, the fourth conductive layer 211 includes a second initialization signal line 211a, a first lead 211b, a second lead 211c, a third lead 211d, a fourth lead 211e, a fifth lead 211f, a sixth lead 211g and a seventh lead 211h.

[0135] The second initialization signal line 211 a is connected to the third vertical portion 201 f through the first contact hole H1 , so that the first electrode of the reset transistor T7 is connected to the second initialization signal line 211 a .

[0136] The first lead 211 b is connected to the first vertical portion 201 b through the second contact hole H2 , so that the second electrode of the data writing transistor T2 is connected to the first lead 211 b .

[0137] The second lead line 211c is connected to the (ij)th first upper scan signal line 209b through the thirteenth contact hole H13.

[0138] The third lead 211d is connected to the first initialization signal line 205c through the fourth contact hole H4 and is connected to the second semiconductor pattern 207a through the twelfth contact hole H12, so that the third lead 211d bridges the first initialization signal line 205c and the first electrode of the initialization transistor T4.

[0139] The fourth lead 211e is connected to the third horizontal portion 201g through the fifth contact hole H5 and is connected to the electrode plate 2051 through the ninth contact hole H9, so that the fourth lead 211e is connected to both the first light emission control transistor T5 and the electrode plate 2051.

[0140] The fifth lead 211f is connected to the second horizontal portion 201e through the sixth contact hole H6, so that the fifth lead 211f is connected to the second light emission control transistor T6.

[0141] The sixth lead 211g is connected to the first horizontal portion 201c through the seventh contact hole H7 and is connected to the second semiconductor pattern 207a through the eleventh contact hole H11 so that the sixth lead 211g bridges the first electrode of the driving transistor T1 and the second electrode of the compensation transistor T3.

[0142] One end of the seventh lead 211h is connected to the first gate 2031 through the eighth contact hole H8 and the electrode plate opening 2051a, and the other end of the seventh lead 211h is connected to the second semiconductor pattern 207a through the tenth contact hole H10, so that the first gate 2031 of the driving transistor T1 is connected to the first electrode of the compensation transistor T3 and the second electrode of the initialization transistor T4.

[0143] The display panel 100 further includes fourteenth, fifteenth, sixteenth, and seventeenth contact holes H14, H15, H16, and H17 penetrating the sixth insulating layer 212.

[0144] like Figure 6H As shown, the fifth conductive layer 213 includes a data line d, a first power signal line VDD, an eighth lead line 213a and a ninth lead line 213b.

[0145] The data line d is connected to the first lead line 211 b through the fourteenth contact hole H14 , so that the data line d is connected to the second electrode of the data writing transistor T2 through the first lead line 211 b .

[0146] The first power signal line VDD is connected to the fourth lead 211 e through the sixteenth contact hole H16 , so that the first light emission control transistor T5 and the electrode plate 2051 are both connected to the first power signal line VDD.

[0147] The eighth lead line 213a is connected to the second lead line 211c through the fifteenth contact hole H15, so that the eighth lead line 213a is connected to the (ij)th first upper scan signal line 209b.

[0148] The ninth lead 213 b is connected to the fifth lead 211 f through the seventeenth contact hole H17 , so that the ninth lead 213 b is connected to the second light emission control transistor T6 .

[0149] The display panel 100 further includes a sixteenth contact hole H16. The sixteenth contact hole H16 penetrates the seventh insulating layer 214. The sixteenth contact hole H16 is disposed corresponding to the eighth lead line 213a.

[0150] like Fig.6I As shown, the sixth conductive layer 215 includes a plurality of first scanning level transmission lines L, the plurality of first scanning level transmission lines L include an ith first scanning level transmission line L(i), and the ith first scanning level transmission line L(i) is connected to the eighth lead 213a through the sixteenth contact hole H16, so that the ith first scanning level transmission line L(i) is connected to the (ij)th first upper scanning signal line 209b, thereby connecting the ith first scanning level transmission line L to the fourth upper gate 2094 of the initialization transistor T4 of the ith pixel, that is, the ith first scanning level transmission line L is connected to the gate of the initialization transistor T4 of the ith pixel.

[0151] Combination Figure 6A-Figure 6I It can be seen that at least part of the plurality of first scan level transmission lines L overlaps with the pixel circuits of the plurality of pixels. For example, at least part of the plurality of first scan level transmission lines L overlaps with the first pixel circuit 101 of the display pixel P, and / or at least part of the plurality of first scan level transmission lines L overlaps with the second pixel circuit of the redundant pixel DP.

[0152] Specifically, multiple first scan level lines L may overlap with the first pixel circuit 101 of the display pixel P; or, multiple first scan level lines L may overlap with the second pixel circuit of the redundant pixel DP; or, part of the multiple first scan level lines L overlap with the first pixel circuit 101 of the display pixel P, and another part of the multiple first scan level lines L overlap with the second pixel circuit of the redundant pixel DP; or, part of the multiple first scan level lines L overlap with the second pixel circuit of the redundant pixel DP, and another part of the multiple first scan level lines L is located between the redundant pixel DP and the gate drive circuit 30.

[0153] Please refer again Figure 3 and Figure 4 The display panel 100 further includes a plurality of second scanning level transmission lines W and a plurality of light emission control transmission lines EL. The gate driving circuit 30 further includes n-level second gate driving units B arranged side by side along the first direction and n-level light emission control units C arranged side by side along the first direction.

[0154] The n-stage second gate driving unit B includes an i-th second gate driving unit B(i) for outputting an i-th second scanning signal PScan(i), where i is greater than or equal to 1 and less than or equal to n. A plurality of second scanning level transmission lines W extend along the first direction, each second scanning level transmission line W is connected to a second gate driving unit B, and the plurality of second scanning level transmission lines W include an i-th second scanning level transmission line Wi, the i-th second scanning level transmission line Wi is electrically connected to the i-th second gate driving unit B(i) through an i-th second horizontal line Hi extending along the second direction, and the i-th second scanning level transmission line Wi is connected to both the pixels in the i-th row and the pixels in the (i+1)-th row, so that both the pixels in the i-th row and the pixels in the (i+1)-th row receive the i-th second scanning signal PScan(i).

[0155] Specifically, the gate of the data write transistor T2 of the i-th pixel located in the i-th row and the gate of the reset transistor T7 of the (i+1)-th pixel located in the (i+1)-th row are both connected to the i-th second scanning level transmission line Wi to output the i-th second scanning signal PScan(i) to the gate of the data write transistor T2 of the i-th pixel and the gate of the reset transistor T7 of the (i+1)-th pixel.

[0156] It should be noted that since each second scanning level transmission line W only needs to be connected to two adjacent rows of pixels and the space spanned by each second scanning level transmission line W in the first direction is relatively small, the risk of short circuit with other wiring lines extending in the second direction when multiple second scanning level transmission lines W extend in the first direction is relatively small, and multiple second scanning level transmission lines W can use independent wiring space.

[0157] The n-level light emitting control unit C includes an i-level light emitting control unit C(i) for outputting an i-level light emitting control signal. A plurality of light emitting control transmission lines EL extend along the second direction, each light emitting control transmission line EL is connected to a light emitting control unit C and a row of pixels, and the plurality of light emitting control transmission lines EL include an i-th light emitting control transmission line ELi, the i-th light emitting control transmission line ELi is electrically connected to the i-level light emitting control unit C(i), and the i-th light emitting control transmission line ELi is connected to the pixels of the i-th row to output the i-th light emitting control signal to the pixels of the i-th row.

[0158] Specifically, the i-th light-emitting control transmission line ELi is electrically connected to the gate of the first light-emitting control transistor T5 of the i-th pixel and the gate of the second light-emitting control transistor T6 of the i-th pixel, so that the gate of the first light-emitting control transistor T5 and the gate of the second light-emitting control transistor T6 of the i-th pixel are both connected to the i-th light-emitting control signal.

[0159] The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technical personnel in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, characterized in that: The display panel has a display area and a peripheral area outside the display area, and the display panel includes: a gate driving circuit, located in the peripheral area, the gate driving circuit comprising n stages of first gate driving units arranged side by side along a first direction, the n stages of the first gate driving units comprising an i-th stage of first gate driving units, the i-th stage of first gate driving units being used to output an i-th first scanning signal, wherein i is a positive integer less than or equal to n, and n is an integer greater than or equal to 3; n rows of pixels are arranged side by side along the first direction, the n rows of pixels are arranged in m columns along a second direction intersecting the first direction, the n rows of pixels include an i-th pixel located in the i-th row and an (i+j)-th pixel located in the (i+j)-th row, j is an integer greater than or equal to 2, (i+j) is less than or equal to n, and m is an integer greater than or equal to 1; and A plurality of first scanning level transmission lines extend along the first direction, the plurality of first scanning level transmission lines include an i-th first scanning level transmission line, the i-th first scanning level transmission line is electrically connected to the i-th first gate driving unit via an i-th first horizontal line Si extending along the second direction, the i-th first scanning level transmission line is electrically connected to both the i-th pixel and the (i+j)-th pixel, and at least part of the plurality of first scanning level transmission lines overlaps with the pixels.

2. The display panel according to claim 1, characterized in that: The n rows of pixels include a plurality of display pixels disposed in the display area, and at least a portion of the plurality of first scanning level transmission lines overlaps with the display pixels.

3. The display panel according to claim 1 or 2, characterized in that: The n rows of pixels include a plurality of redundant pixels disposed in the peripheral area, and at least a portion of the plurality of first scanning level transmission lines overlaps with the redundant pixels.

4. The display panel according to claim 1, characterized in that: The display panel further includes: a plurality of data lines extending along the first direction, at least part of the plurality of data lines being located in the display area; and A connecting line, wherein the connecting line and the data line are located in different film layers, and one connecting line comprises: a first connection line, the first connection line is located in the display area, the first connection line extends along the second direction and is connected to the data line located in the display area; and The second connection line is connected to the first connection line, and the second connection line extends along the first direction and extends from the display area to the peripheral area.

5. The display panel according to claim 4, characterized in that: The data lines, the first connection lines and the second connection lines are respectively located in three different film layers, the first scanning level transmission lines and the second connection lines are located in the same film layer, and the first scanning level transmission lines and the second connection lines are insulated from each other.

6. The display panel according to claim 5, characterized in that: The n rows of pixels include a plurality of display pixels located in the display area, the display pixels include an anode located in the display area, the film layer where the second connecting line is located is located between the film layer where the anode is located and the film layer where the data line is located, and the film layer where the data line is located is located between the film layer where the second connecting line is located and the film layer where the first connecting line is located.

7. The display panel according to claim 4, characterized in that: In the second direction, the plurality of first scanning level transmission lines are located on one side of the plurality of second connecting lines, or the plurality of first scanning level transmission lines are located on two opposite sides of the plurality of second connecting lines.

8. The display panel according to claim 1, characterized in that: Each of the pixels comprises a pixel circuit, and each of the pixel circuits comprises: Driver transistor; a compensation transistor, wherein a first electrode and a second electrode of the compensation transistor are connected between the gate electrode and the first electrode of the driving transistor; and an initialization transistor, wherein a first electrode of the initialization transistor is connected to a first initialization signal, and a second electrode of the initialization transistor is connected to a gate of the driving transistor; Wherein, the gate of the compensation transistor of the i-th pixel and the gate of the initialization transistor of the (i+j)-th pixel are both connected to the i-th first scanning stage transmission line.

9. The display panel according to claim 8, characterized in that: The gate driving circuit further includes n-stage second gate driving units arranged side by side along the first direction, the n-stage second gate driving units including an i-th stage second gate driving unit for outputting an i-th second scanning signal; The display panel further includes a plurality of second scanning level transmission lines, the plurality of second scanning level transmission lines include an i-th second scanning level transmission line, and the i-th second scanning level transmission line is electrically connected to the i-th second gate driving unit; Each pixel circuit also includes: a data writing transistor, wherein a first electrode of the data writing transistor is connected to a second electrode of the driving transistor, and a second electrode of the data writing transistor is connected to a data signal; and A reset transistor, wherein a first electrode of the reset transistor is connected to a second initialization signal, and a second electrode of the reset transistor is connected to a first electrode of the drive transistor; The n rows of pixels also include the (i+1)th pixel located in the (i+1)th row; The gate of the data writing transistor of the i-th pixel and the gate of the reset transistor of the (i+1)-th pixel are connected to the i-th second scanning stage transmission line.

10. The display panel according to claim 9, characterized in that: The gate driving circuit further includes n-stage light emitting control units arranged side by side along the first direction, wherein the n-stage light emitting control units include an i-th stage light emitting control unit for outputting an i-th light emitting control signal; Each of the pixel circuits further comprises: a first light emission control transistor, wherein a first electrode and a second electrode of the first light emission control transistor are connected between a first power supply signal and a second electrode of the driving transistor; and a second light emitting control transistor, wherein a first electrode and a second electrode of the second light emitting control transistor are connected between the first electrode of the driving transistor and a second power supply signal; Among them, the gate of the first light emitting control transistor of the i-th pixel and the gate of the second light emitting control transistor of the i-th pixel are both connected to the i-th light emitting control signal.

Images