Nitride epitaxial wafer, method of manufacturing the same, and semiconductor device

Abstract

The application discloses a nitride epitaxial wafer, a preparation method thereof and a semiconductor device. The nitride epitaxial wafer comprises a substrate, a nitride buffer layer arranged on the substrate, and a nitride epitaxial layer arranged on the nitride buffer layer, wherein the nitride epitaxial layer comprises a roughening regulation layer and at least one nitride process layer; the roughening regulation layer is formed by alternately stacking a nitride regulation growth layer and a nitride regulation interruption layer; the nitride regulation interruption layer is used for interrupting the continuity of two adjacent nitride regulation growth layers; in the thickness direction of the nitride epitaxial wafer, the roughening regulation layer is arranged above the nitride process layer, or below the nitride process layer, or between two nitride process layers. The nitride epitaxial wafer is used for separating a nitride surface roughening process from a crystal quality process control, so as to meet different epitaxial technical requirements.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a nitride epitaxial wafer, its preparation method, and a semiconductor device. Background Technology

[0002] As a third-generation semiconductor material, GaN (gallium nitride) has the characteristics of high bandgap, high critical breakdown electric field, high carrier saturation migration velocity, high thermal conductivity and direct bandgap, and has great application prospects in the fields of high temperature, high frequency, high power microelectronic devices and high performance optoelectronic devices.

[0003] Whether a nitride semiconductor material has a smooth surface with low roughness is an indicator of its performance. However, high-roughness surface roughening technology is often used in optoelectronic devices to improve light extraction efficiency and quantum dot growth. Generally, chemical wet etching and mask dry etching methods are used, but both have some drawbacks. These roughening methods often damage the surface states of nitride and the electrical properties of the device.

[0004] Recently, in-situ growth technology of insertion layers has been widely used, such as in-situ growth of insertion layers before and after nitride nucleation layers or roughening layers to improve the quality of nitride crystals, and in-situ growth of insertion layers in quantum well light-emitting layers to form quantum dots.

[0005] Currently, some intercalation layer processes mainly focus on improving the quality of nitride crystals. However, this process also affects the surface roughness of nitrides. The requirements for crystal quality and surface roughness are different in different nitride semiconductor devices. For example, when nitride materials are used as stress relief layers in quantum well light-emitting layers, low surface roughness is required according to process requirements, and the crystal quality of the nitride material needs to be appropriately reduced. This allows the use of nitride materials with low surface roughness to achieve quantum well light-emitting layers with high interface characteristics. At the same time, the high dislocation density in low-quality nitride materials can be used to relieve the stress of nitride materials. In addition, there are also nitride material templates with high nitride surface roughness and relatively high crystal quality required by the process to improve the light extraction efficiency of light-emitting devices.

[0006] Therefore, there is an urgent need to develop a new epitaxial growth process for nitride surface roughness, so that the surface roughness of nitrides can be adjusted to meet different epitaxial technology requirements. Summary of the Invention

[0007] The purpose of this invention is to provide a nitride epitaxial wafer, its preparation method, and a semiconductor device, which separates the surface roughening process of nitrides from the crystal quality process control, thereby meeting different epitaxial technology requirements.

[0008] The objective of this invention is achieved through the following technical solution:

[0009] A nitride epitaxial wafer, comprising:

[0010] Substrate;

[0011] A nitride buffer layer disposed on the substrate;

[0012] A nitride epitaxial layer is disposed on the nitride buffer layer. The nitride epitaxial layer includes a roughening control layer and at least one nitride process layer. The roughening control layer consists of alternating layers of nitride-controlled growth layers and nitride-controlled interruption layers. The nitride-controlled interruption layer is used to interrupt the continuity between two adjacent nitride-controlled growth layers.

[0013] In the thickness direction of the nitride epitaxial wafer, the roughening control layer is disposed above the nitride process layer, below the nitride process layer, or between two nitride process layers.

[0014] Preferably, the nitride buffer layer, the nitride process layer, and the nitride controlled growth layer are each Al a Ga b In 1-a-b N, 1≥a≥0, 1≥b≥0, 1≥1-ab≥0.

[0015] Preferably, the nitride process layer and the nitride controlled growth layer are the same or different.

[0016] Preferably, the nitride-regulated interruption layer is Si. y M 1-y N x , where 1≥x≥0, 1≥y≥0, and M is selected from one of Ge, Mg, Al, In, Sn, B, S, O, and C.

[0017] Preferably, the nitride-regulated interruption layer is SiN. x .

[0018] Preferably, the thickness of the nitride buffer layer is 0.01-4 μm, the thickness of the nitride epitaxial layer is 0.05-20 μm, the thickness of each nitride process layer is 5-1000 nm, the thickness of each nitride controlled growth layer is 5-1000 nm, and the thickness of each nitride controlled interruption layer is 1-1000 nm; the roughening control layer comprises 5-50 alternately stacked nitride controlled growth layers and 5-50 nitride controlled interruption layers.

[0019] Preferably, the surface roughness of the nitride epitaxial layer is 0.7-13 nm.

[0020] A method for preparing a nitride epitaxial wafer, comprising:

[0021] Step S1: Provide a substrate;

[0022] Step S2: Grow a nitride buffer layer on the substrate;

[0023] Step S3: A nitride epitaxial layer is formed on the nitride buffer layer. The nitride epitaxial layer includes a roughening control layer and at least one nitride process layer. The roughening control layer consists of alternating layers of nitride-controlled growth layers and nitride-controlled interruption layers. The material of the nitride-controlled interruption layer is different from that of the nitride-controlled growth layers. The nitride-controlled interruption layer is used to interrupt the continuity of two adjacent nitride-controlled growth layers. In the thickness direction of the nitride epitaxial wafer, the roughening control layer is disposed above the nitride process layer, below the nitride process layer, or between two nitride process layers.

[0024] Preferably, step S3 includes:

[0025] Step S31: Grow at least one nitride process layer;

[0026] Step S32: Growth of nitride-regulated growth layer;

[0027] Step S33: Interrupt the growth of the controlled growth layer and grow a nitride-controlled interruption layer;

[0028] Step S34: Repeat steps S32 and S33, alternatingly stacking nitride-regulated growth layers and nitride-regulated interruption layers to form a coarsening regulation layer;

[0029] Steps S32 to S34 may be performed before step S31, or after step S31, or between two steps S31.

[0030] Preferably, steps S32 and S33 are repeated 5-50 times.

[0031] Preferably, the process time ratio between growing the nitride-controlled growth layer in step S32 and growing the nitride-controlled interruption layer in step S33 is 0.5-25.

[0032] A semiconductor device comprising the nitride epitaxial wafer described in any of the preceding claims.

[0033] Compared with the prior art, the beneficial effects of the present invention include at least the following:

[0034] This invention obtains nitride epitaxial layers with different surface roughnesses by setting a roughening control layer comprising alternating layers of nitride-controlled growth and nitride-controlled interruption layers, and by controlling the positional relationship between the roughening control layer and the nitride process layer. For example, when the nitride process layer is located below the roughening control layer, the surface roughness of the nitride epitaxial wafer is larger; when the nitride process layer is located on both sides of the roughening control layer, the surface roughness of the nitride epitaxial wafer is reduced; and when the nitride process layer is located above the roughening control layer, the surface roughness of the nitride epitaxial wafer is minimized.

[0035] Furthermore, the surface roughness of the nitride epitaxial layer can be further altered by controlling the process time ratio between growing the nitride-regulated growth layer in step S32 and growing the nitride-regulated interrupted layer in step S33. Within the selected process time ratio range, increasing the process time ratio reduces the surface roughness of the nitride epitaxial layer; outside the selected range, changing the process time ratio has little effect on the surface roughness. Therefore, by changing the process time ratio between growing the nitride-regulated growth layer in step S32 and growing the nitride-regulated interrupted layer in step S33, different surface roughnesses can be obtained to meet different epitaxial growth requirements. Attached Figure Description

[0036] Figure 1 This is a schematic diagram of the structure of a nitride epitaxial wafer in which the roughening control layer is disposed above the nitride process layer according to an embodiment of the present invention;

[0037] Figure 2 This is a schematic diagram of the structure of a nitride epitaxial wafer in which the roughening control layer is disposed below the nitride process layer according to an embodiment of the present invention;

[0038] Figure 3 This is a schematic diagram of the structure of a nitride epitaxial wafer in which the roughening control layer is disposed between two nitride process layers, according to an embodiment of the present invention.

[0039] Figure 4 These are optical microscope images of the nitride epitaxial wafers obtained in Example 1 of this invention;

[0040] Figure 5 These are optical microscope images of the nitride epitaxial wafers obtained in Example 2 of this invention;

[0041] Figure 6 These are optical microscope images of the nitride epitaxial wafers obtained in Example 3 of this invention;

[0042] Figure 7 These are optical microscope images of the nitride epitaxial wafers obtained in Example 4 of this invention;

[0043] Figure 8This is a schematic diagram showing the process time ratio and surface roughness of the nitride growth layer and the nitride interruption layer in embodiments 7-12 of the present invention.

[0044] In the figure: 1. Substrate; 2. Nitride buffer layer; 3. Nitride epitaxial layer; 4. Roughening control layer; 5. Nitride process layer; 6. Nitride control interruption layer; 7. Nitride control growth layer. Detailed Implementation

[0045] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided to make the invention more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore repeated descriptions of them will be omitted.

[0046] The terms used to express position and direction in this invention are illustrated with reference to the accompanying drawings, but changes can be made as needed, and all such changes are included within the scope of protection of this invention.

[0047] The present invention provides a nitride epitaxial wafer, comprising a substrate 1, a nitride buffer layer 2, and a nitride epitaxial layer 3.

[0048] like Figures 1 to 3 As shown, substrate 1 can be a sapphire substrate, SiC substrate, or Si substrate. Nitride buffer layer 2 is disposed on substrate 1, and nitride epitaxial layer 3 is disposed on nitride buffer layer 2. Nitride epitaxial layer 3 includes roughening control layer 4 and at least one nitride process layer 5. Roughening control layer 4 consists of alternating layers of nitride controlled growth layer 7 and nitride controlled interruption layer 6. Nitride controlled interruption layer 6 is used to interrupt the continuity of two adjacent nitride controlled growth layers 7. In the thickness direction of nitride epitaxial wafer, roughening control layer 4 is disposed above nitride process layer 5, below nitride process layer 5, or between two nitride process layers 5. This invention achieves nitride epitaxial layers 3 with varying surface roughness by configuring a roughening control layer 4 comprising alternating layers of nitride-controlled growth 7 and nitride-controlled interruption layers 6, and by controlling the positional relationship between the roughening control layer 4 and the nitride process layer 5. The surface roughness of the nitride epitaxial layer can be adjusted as needed within the range of 0.7-13 nm, thus meeting different epitaxial technology requirements. Specifically, when the nitride process layer 5 is positioned below the roughening control layer 4, the surface roughness of the nitride epitaxial wafer is relatively large; when the nitride process layer 5 is positioned on both sides of the roughening control layer 4, the surface roughness of the nitride epitaxial wafer is reduced; and when the nitride process layer 5 is positioned above the roughening control layer 4, the surface roughness of the nitride epitaxial wafer is minimal.

[0049] As a further embodiment of the above embodiments, the nitride buffer layer 2, the nitride process layer 5, and the nitride controlled growth layer 7 are each Al a Ga b In 1-a-b N, 1≥a≥0, 1≥b≥0, 1≥1-ab≥0, where a and b can be 0.2, 0.5, or 0.7 respectively. As an example, the nitride buffer layer 2, the nitride process layer 5, and the nitride controlled growth layer 7 are each one or more combinations of GaN, AlN, InN, AlGaN, InGaN, AlInN, and AlInGaN. The nitride process layer 5 and the nitride controlled growth layer 7 may be the same or different. Selecting nitride buffer layer 2, nitride process layer 5, and nitride controlled growth layer 7 of different materials can meet various epitaxial growth needs.

[0050] The material of the nitride-controlled interruption layer 6 is preferably different from that of the nitride-controlled growth layer 7, thereby interrupting the continuity between two adjacent nitride-controlled growth layers 7. As a further embodiment of the above example, the nitride-controlled interruption layer 6 is made of Si. y M 1-y N x Where 1 ≥ x ≥ 0, 1 ≥ y ≥ 0, and x and y can be 0.2, 0.5, or 0.7 respectively, and M is selected from one of Ge, Mg, Al, In, Sn, B, S, O, and C. When M is selected from Ge, Mg, Al, In, or Sn, whose atomic radii are greater than Si, it can compensate for the difference in atomic radii between Si and N. x The introduction of a controlled interruption layer reduces the lattice size of the nitride epitaxial layer, enabling lattice-matched nitride process layer growth and improving the crystal quality of the nitride epitaxial layer. This nitride epitaxial layer can then be used as a template to further achieve high-quality nitride epitaxial layer growth. When M is selected from B, S, O, and C, whose atomic radii are smaller than Si, it can enhance the growth of SiN. x By controlling the introduction of the interrupted layer to shrink the lattice of the nitride epitaxial layer, the growth of nitride process layers with large lattice differences can be achieved, reducing the crystal quality of the nitride epitaxial layer. This nitride epitaxial layer can then be used as a template to continue growing low-stress nitride epitaxial layers, meeting the needs of different epitaxial growth.

[0051] Nitride-regulated interruption layer 6 is further preferably SiN x SiN x The growth process of the nitride-controlled interrupted layer 6 is mature and can significantly reduce costs.

[0052] As a further embodiment of the above embodiments, the thickness of the nitride buffer layer 2 is 0.01-4 μm, the thickness of the nitride epitaxial layer 3 is 0.05-20 μm, the thickness of each nitride process layer 5 is 5-1000 nm, the thickness of each nitride controlled growth layer 7 is 5-1000 nm, and the thickness of each nitride controlled interruption layer 6 is 1-1000 nm.

[0053] The coarsening control layer 4 comprises 5-50 alternating layers of nitride-controlled growth layers 7 and 5-50 layers of nitride-controlled interruption layers 6, the number of which is, for example, 10, 20, 30 or 40.

[0054] The present invention also provides a semiconductor device comprising a nitride epitaxial wafer according to any of the above claims, wherein the semiconductor device is, for example, an LED device, a HEMT device, etc.

[0055] The present invention also provides a method for preparing a nitride epitaxial wafer, comprising: steps S1-S3.

[0056] Step S1: Provide substrate 1.

[0057] Step S2: Grow a nitride buffer layer 2 on substrate 1.

[0058] Step S3: Grow a nitride epitaxial layer 3 on the nitride buffer layer 2. The nitride epitaxial layer 3 includes a roughening control layer 4 and at least one nitride process layer 5. The roughening control layer 4 consists of alternating layers of nitride-controlled growth layer 7 and nitride-controlled interruption layer 6. Preferably, the material of the nitride-controlled interruption layer 6 is different from that of the nitride-controlled growth layer 7.

[0059] The nitride regulation interruption layer 6 is used to interrupt the continuity of two adjacent nitride regulation growth layers 7; in the thickness direction of the nitride epitaxial wafer, the roughening regulation layer 4 is disposed above the nitride process layer 5, or below the nitride process layer 5, or between two nitride process layers 5.

[0060] By controlling the positional relationship between the roughening control layer 4 and the nitride process layer 5, nitride epitaxial layers 3 with different surface roughness can be obtained. The surface roughness of the nitride epitaxial layer can be adjusted as needed within the range of 0.7-13nm, thereby meeting different epitaxial technology requirements.

[0061] As a further implementation of the above embodiments, step S3 includes:

[0062] Step S31: Grow at least one nitride process layer 5.

[0063] Step S32: Growth of nitride-regulated growth layer 7.

[0064] Step S33: Interrupt the growth of the controlled growth layer 7 and grow the nitride-controlled interruption layer 6.

[0065] Step S34: Repeat steps S32 and S33, alternatingly stacking nitride-regulated growth layer 7 and nitride-regulated interruption layer 6 to form coarsening regulation layer 4.

[0066] Specifically, steps S32 to S34 are performed before step S31, in which the roughening control layer 4 is disposed below the nitride process layer 5 in the thickness direction of the nitride epitaxial wafer; or steps S32 to S34 are performed after step S31, in which the roughening control layer 4 is disposed above the nitride process layer 5 in the thickness direction of the nitride epitaxial wafer; or steps S32 to S34 are performed between two steps S31, thereby disposing the roughening control layer 4 between the two nitride process layers 5.

[0067] As a further implementation of the above embodiment, steps S32 and S33 are repeated 5-50 times to obtain coarsening control layers 4 of different thicknesses.

[0068] As a further implementation of the above embodiments, the process time ratio for growing the nitride-controlled growth layer 7 in step S32 and growing the nitride-controlled interruption layer 6 in step S33 is 0.5-25. By controlling the above process time ratio, the surface roughness of the nitride epitaxial layer can be further changed. Within this process time ratio range, increasing the process time ratio can reduce the surface roughness of the nitride epitaxial wafer; outside this process time ratio range, changing the process time ratio does not significantly change the surface roughness of the nitride epitaxial wafer. Therefore, by changing the process time ratio for growing the nitride-controlled growth layer 7 in step S32 and growing the nitride-controlled interruption layer 6 in step S33, different surface roughnesses can be obtained to meet different epitaxial growth requirements.

[0069] Example 1:

[0070] Taking the growth of a GaN epitaxial layer on a 4-inch sapphire substrate 1 using MOCVD epitaxial growth equipment as an example, the technical solution of this embodiment is described. The nitride epitaxial wafer manufacturing process includes at least the following steps:

[0071] S1: Provides a sapphire substrate 1;

[0072] S2: A GaN buffer layer with a thickness of 2.5 μm is grown on a sapphire substrate 1 at a temperature of 1125 °C.

[0073] S3: On the GaN buffer layer, a GaN epitaxial layer with a thickness of 2.5 μm is grown at a temperature of 1095 °C. The formation of the GaN epitaxial layer includes the following steps:

[0074] S31: GaN process layer with a growth thickness of 1.5 μm;

[0075] S32: GaN control growth layer with a thickness of 10nm, growth time 60s;

[0076] S33: Interrupt the growth of the GaN control layer to form a 5nm thick SiN layer. x Adjust the interrupt layer; interrupt time is 60 seconds.

[0077] S34: Repeat steps S32 and S33 100 times to form coarsening control layer 4;

[0078] The final steps S31, S32, S33 and S34 form a 2.5 μm GaN epitaxial layer.

[0079] Specifically, in Example 1, the layers from top to bottom along the thickness direction of the nitride epitaxial wafer are: roughening control layer 4, GaN process layer, GaN buffer layer, and substrate 1.

[0080] Example 2:

[0081] Taking the growth of a GaN epitaxial layer on a 4-inch sapphire substrate 1 using MOCVD epitaxial growth equipment as an example, the technical solution of this embodiment is described. The nitride epitaxial wafer manufacturing process includes at least the following steps:

[0082] S1: Provides a sapphire substrate 1;

[0083] S2: A GaN buffer layer with a thickness of 2.5 μm is grown on a sapphire substrate 1 at a temperature of 1125 °C.

[0084] S3: On the GaN buffer layer, a GaN epitaxial layer with a thickness of 2.5 μm is grown at a temperature of 1095 °C. The formation of the GaN epitaxial layer includes the following steps:

[0085] S31: GaN process layer with a growth thickness of 1 μm;

[0086] S32: GaN control growth layer with a thickness of 10nm, growth time 60s;

[0087] S33: Interrupt the growth of the GaN control layer to form a 5nm thick SiN layer. x Adjust the interrupt layer; interrupt time is 60 seconds.

[0088] S34: Repeat steps S5 and S6 100 times to form coarsening control layer 4;

[0089] S35: A GaN process layer with a growth thickness of 0.5 μm;

[0090] The final steps S31, S32, S33, S34 and S35 form a 2.5 μm GaN epitaxial layer.

[0091] Specifically, in Example 2, the layers from top to bottom along the thickness direction of the nitride epitaxial wafer are a GaN process layer, a roughening control layer 4, a GaN process layer, a GaN buffer layer, and a substrate 1.

[0092] Example 3

[0093] Taking the growth of a GaN epitaxial layer on a 4-inch sapphire substrate 1 using MOCVD epitaxial growth equipment as an example, the technical solution of this embodiment is described. The nitride epitaxial wafer manufacturing process includes at least the following steps:

[0094] S1: Provides a sapphire substrate 1;

[0095] S2: A GaN buffer layer with a thickness of 2.5 μm is grown on a sapphire substrate 1 at a temperature of 1125 °C.

[0096] S3: On the GaN buffer layer, a GaN epitaxial layer with a thickness of 2.5 μm is grown at a temperature of 1095 °C. The formation of the GaN epitaxial layer includes the following steps:

[0097] S31: GaN process layer with a growth thickness of 0.5 μm;

[0098] S32: GaN control growth layer with a thickness of 10nm, growth time 60s;

[0099] S33: Interrupt the growth of the GaN control layer to form a 5nm thick SiN layer. x Adjust the interrupt layer; interrupt time is 60 seconds.

[0100] S34: Repeat steps S5 and S6 100 times to form coarsening control layer 4;

[0101] S35: GaN process layer with a growth thickness of 1 μm;

[0102] The final steps S31, S32, S33, S34 and S35 form a 2.5 μm GaN epitaxial layer.

[0103] Specifically, in Example 3, the layers from top to bottom along the thickness direction of the nitride epitaxial wafer are a GaN process layer, a roughening control layer 4, a GaN process layer, a GaN buffer layer, and a substrate 1.

[0104] Example 4:

[0105] Taking the growth of a GaN epitaxial layer on a 4-inch sapphire substrate 1 using MOCVD epitaxial growth equipment as an example, the technical solution of this embodiment is described. The nitride epitaxial wafer manufacturing process includes at least the following steps:

[0106] S1: Provides a sapphire substrate 1;

[0107] S2: A GaN buffer layer with a thickness of 2.5 μm is grown on a sapphire substrate 1 at a temperature of 1125 °C.

[0108] S3: On the GaN buffer layer, a GaN epitaxial layer with a thickness of 2.5 μm is grown at a temperature of 1095 °C. The formation of the GaN epitaxial layer includes the following steps:

[0109] S31: GaN control growth layer with a thickness of 10nm, growth time 60s;

[0110] S32: Interrupt the growth of the GaN control layer to form a 5nm thick SiN layer. x Adjust the interrupt layer; interrupt time is 60 seconds.

[0111] S33: Repeat steps S4 and S5 100 times to form coarsening control layer 4;

[0112] S34: A GaN process layer with a growth thickness of 1.5 μm;

[0113] The final steps S31, S32, S33 and S34 form a 2.5 μm GaN epitaxial layer.

[0114] Specifically, in Example 3, the layers from top to bottom along the thickness direction of the nitride epitaxial wafer are a GaN process layer, a roughening control layer 4, a GaN buffer layer, and a substrate 1.

[0115] Example 5:

[0116] Taking the growth of an AlGaN epitaxial layer on a 4-inch sapphire substrate 1 using MOCVD epitaxial growth equipment as an example, the technical solution of this embodiment is described. The nitride epitaxial wafer manufacturing process includes at least the following steps:

[0117] S1: Provides a sapphire substrate;

[0118] S2: An AlGaN buffer layer with a thickness of 2.5 μm is grown on a sapphire substrate at a temperature of 1095 °C.

[0119] S3: An AlGaN epitaxial layer with a thickness of 3 μm is grown on the AlGaN buffer layer at a temperature of 1135℃, including:

[0120] S31: An AlGaN process layer with a growth thickness of 1.5 μm;

[0121] S32: An AlGaN controllable growth layer with a thickness of 15nm was grown, with a growth time of 60s;

[0122] S33: Interrupt the growth of the nitride control layer to form SiN x Adjust the interrupt layer; interrupt time is 40 seconds.

[0123] S34: Repeat steps S32 and S33 100 times to form a coarsening control layer; the final steps S31, S32, S33 and S34 form a 3μm AlGaN nitride epitaxial layer.

[0124] Example 6:

[0125] Taking the growth of an AlGaN epitaxial layer on a 4-inch sapphire substrate 1 using MOCVD epitaxial growth equipment as an example, the technical solution of this embodiment is described. The nitride epitaxial wafer manufacturing process includes at least the following steps:

[0126] S1: Provides a sapphire substrate;

[0127] S2: An AlGaN buffer layer with a thickness of 2.5 μm is grown on a sapphire substrate at a temperature of 1095 °C.

[0128] S3: An AlGaN epitaxial layer with a thickness of 3 μm is grown on the AlGaN buffer layer at a temperature of 1135℃, including:

[0129] S31: AlGaN process layer with a growth thickness of 1μm;

[0130] S32: An AlGaN controllable growth layer with a thickness of 15nm was grown, with a growth time of 60s;

[0131] S33: Interrupt the growth of the nitride control layer to form SiN x Adjust the interrupt layer; interrupt time is 40 seconds.

[0132] S34: Repeat steps S32 and S33 100 times to form a coarsening control layer;

[0133] S35: An AlGaN process layer with a growth thickness of 0.5 μm;

[0134] The final steps S31, S32, S33, S34 and S35 form a 3 μm AlGaN nitride epitaxial layer.

[0135] Based on the above experimental data, we can conclude that:

[0136] While keeping other parameters constant, growing the GaN process layer above or below the roughening control layer 4, or dividing the GaN control growth layer into two parts to enclose the roughening control layer 4, can change the surface roughness of the GaN epitaxial layer.

[0137] The surface roughness of the GaN epitaxial layers obtained in Examples 1-4 was measured using AFM. The surface roughnesses of the GaN epitaxial layers obtained by the above preparation method were 10.88 nm, 6.95 nm, 4.75 nm, and 1.02 nm, respectively. Under the same magnification, the surfaces of the nitride epitaxial wafers in Examples 1-4 were observed using an optical microscope. The optical microscope images of Examples 1-4 are shown below. Figure 4-7 As shown, from Figure 4-7 It can be seen that the surface roughness of the nitride epitaxial wafer gradually decreases. The test results from Examples 1-4 show that when the GaN process layer is located below the roughening control layer 4, the surface roughness of the nitride epitaxial wafer is relatively large; compared to having the GaN process layer located below the roughening control layer 4, the surface roughness of the nitride epitaxial wafer decreases when the GaN process layer is located on both sides of the roughening control layer 4; compared to having the GaN process layer located below the roughening control layer 4 and on both sides of the roughening control layer 4, the surface roughness of the nitride epitaxial wafer is minimized when all the GaN process layers are located above the roughening control layer 4.

[0138] Therefore, by changing the positional relationship between the roughening control layer 4 and the GaN process layer, GaN epitaxial layers with different surface roughness can be obtained, while the crystal quality of Examples 1, 2, 3 and 4 is basically the same.

[0139] The surface roughness of the AlGaN epitaxial layers obtained in Examples 5-6 was measured using AFM. The surface roughnesses of the AlGaN epitaxial layers were 5.32 nm and 2.92 nm, respectively. It can be seen that when the AlGaN process layer is entirely disposed above the roughening control layer 4, compared to when the AlGaN process layer is disposed on both sides of the roughening control layer 4, the surface roughness of the nitride epitaxial wafer decreases. Similarly, by changing the positional relationship between the roughening control layer 4 and the AlGaN process layer, AlGaN epitaxial layers with different surface roughnesses can be obtained.

[0140] Example 7:

[0141] The preparation process of Example 7 is basically the same as that of Example 1, except that step S33 is different.

[0142] Specifically, while keeping other parameters constant, S33: interrupt the growth of the GaN control growth layer to form a SiMgN control interruption layer with a thickness of 5nm, with an interruption time of 60s.

[0143] Tests revealed that the nitride epitaxial layers obtained in Examples 7 and 1 had considerable surface roughness. However, X-ray diffraction (XRD) analysis showed that the half-widths (WHMs) of the (002) and (102) planes in Examples 1 and 7 decreased from 279 arsec and 310 arsec to 195 arsec and 225 arsec, respectively. This indicates that by controlling the Mg atomic radius of the interrupted layer to be larger than that of Si, the surface roughness of SiN can be compensated. x The introduction of the interrupted layer reduces the lattice size of the nitride epitaxial layer, enabling the growth of lattice-matched nitride process layers and improving the crystal quality of the nitride epitaxial layer. This nitride epitaxial layer can then be used as a template to continue growing high-quality nitride epitaxial layers.

[0144] Example 8:

[0145] The preparation process of Example 8 is basically the same as that of Example 1, except that step S33 is different.

[0146] Specifically, while keeping other parameters constant, S33: interrupts the growth of the GaN control growth layer to form a SiON control interruption layer with a thickness of 5nm, with an interruption time of 60s.

[0147] Tests revealed that the nitride epitaxial layers obtained in Examples 8 and 1 had comparable surface roughness. However, X-ray diffraction (XRD) analysis showed that the half-widths (WHMs) of the (002) and (102) planes in Examples 1 and 8 increased from 279 arsec and 310 arsec to 310 arsec and 425 arsec, respectively. This indicates that by controlling the O atom radius of the interrupted layer to be smaller than that of Si, the SiN layer can be strengthened. x The introduction of the interrupted layer shrinks the lattice of the nitride epitaxial layer, enabling the growth of nitride process layers with large lattice differences, reducing the crystal quality of the nitride epitaxial layer, and allowing the growth of low-stress nitride epitaxial layers to be achieved using this nitride epitaxial layer as a template.

[0148] Examples 9-14:

[0149] The preparation processes of Examples 9-14 are basically the same as those of Example 1, except that the process time ratios of the nitride-regulated growth layer 7 in step S32 and the nitride-regulated interruption layer 6 in step S33 are different. While keeping other parameters unchanged in Example 1, the process time ratios of the nitride-regulated growth layer 7 and the nitride-regulated interruption layer 6 are set to 0.5, 5, 10, 15, 20, and 25 respectively.

[0150] This invention achieves nitride epitaxial layers 3 with different surface roughnesses by setting periodically alternating nitride-controlled growth layers 7 and nitride-controlled interruption layers 6, and by controlling the positional relationship between the nitride-controlled growth layers 7, nitride-controlled interruption layers 6, and nitride process layers 5. For example... Figure 8 As shown, the surface roughness of the nitride epitaxial layer 3 can also be changed by controlling the process time ratio. It should be noted that the preferred process time ratio between the nitride-controlled growth layer 7 and the nitride-controlled interruption layer 6 is 0.5-25. When the process time ratio is too small, i.e., less than 0.5, the resulting nitride epitaxial layer 3 has a large surface roughness, greater than 13 nm. The surface roughness of the resulting nitride epitaxial layer 3 decreases further with the process time ratio, but the surface roughness remains essentially unchanged. Conversely, when the process time ratio is too large, i.e., greater than 25, the resulting nitride epitaxial layer 3 has a small surface roughness, less than 0.7 nm. The surface roughness remains essentially unchanged with the process time ratio increasing further. The above method of controlling surface roughness by controlling the process time ratio expands the epitaxial growth window for surface roughening of the nitride epitaxial layer 3, compared to current SiN... x While the intercalation layer process improves the quality of nitride crystals, it also affects the surface roughness of nitrides. This invention separates the nitride surface roughening process from the crystal quality process control, thus meeting the needs of different epitaxial technologies.

[0151] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the invention without departing from the principles and spirit of the invention, and all such changes should fall within the protection scope of the claims of the present invention.

Claims

1. A method for preparing a nitride epitaxial wafer, characterized in that, include: Step S1: Provide a substrate; Step S2: Grow a nitride buffer layer on the substrate; Step S3: Form a nitride epitaxial layer on the nitride buffer layer. The nitride epitaxial layer includes a roughening control layer and at least one nitride process layer. The roughening control layer consists of alternating layers of nitride-controlled growth layers and nitride-controlled interruption layers. The nitride-controlled interruption layer is used to interrupt the continuity of two adjacent nitride-controlled growth layers. In the thickness direction of the nitride epitaxial wafer, the roughening control layer is disposed above the nitride process layer, below the nitride process layer, or between two nitride process layers. Step S3 includes: Step S31: Grow at least one nitride process layer; Step S32: Growth of nitride-regulated growth layer; Step S33: Interrupt the growth of the controlled growth layer and grow a nitride-controlled interruption layer; Step S34: Repeat steps S32 and S33, alternatingly stacking nitride-regulated growth layers and nitride-regulated interruption layers to form a coarsening regulation layer; Steps S32 to S34 may be performed before step S31, or after step S31, or between two steps S31. The process time ratio between growing the nitride-regulated growth layer in step S32 and growing the nitride-regulated interruption layer in step S33 is 0.5-25. The nitride buffer layer, nitride process layer, and nitride controlled growth layer are each Al a Ga b In 1-a-b N, 1≥a≥0, 1≥b≥0, 1≥1-ab≥0; The nitride-regulated interruption layer is Si. y M 1-y N x Where 1≥x≥0, 1≥y≥0, and M is selected from one of Ge, Mg, Al, In, Sn, B, S, O, and C; The surface roughness of the nitride epitaxial layer is 0.7-13 nm.

2. The method for preparing a nitride epitaxial wafer according to claim 1, characterized in that, The number of times steps S32 and S33 are repeated is 5-50 times.

3. The method for preparing a nitride epitaxial wafer according to claim 1, characterized in that, The nitride-regulated interruption layer is SiN. x .

4. The method for preparing a nitride epitaxial wafer according to claim 1, characterized in that, The thickness of the nitride buffer layer is 0.01-4 μm, the thickness of the nitride epitaxial layer is 0.05-20 μm, the thickness of each nitride process layer is 5-1000 nm, the thickness of each nitride controlled growth layer is 5-1000 nm, and the thickness of each nitride controlled interruption layer is 1-1000 nm. The coarsening control layer comprises 5-50 alternately stacked nitride-controlled growth layers and 5-50 nitride-controlled interruption layers.

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