Vertical light-emitting chip and preparation method thereof

Abstract

The present invention relates to a vertical light-emitting chip and its preparation method, comprising: growing a dissociation layer on a sapphire substrate; growing a dielectric layer on the dissociation layer, forming an array of conical protrusions on the surface of the dielectric layer away from the dissociation layer; covering the conical protrusion array with a buffer layer, with the surface of the buffer layer away from the conical protrusion array being flat; sequentially growing a light-emitting functional layer and a conductive functional layer on the buffer layer; and irradiating the dissociation layer with a laser to peel off the sapphire substrate. Through the above method, the dislocation density of the light-emitting functional layer on the flat sapphire substrate in the vertical light-emitting chip can be reduced, resulting in a high-quality light-emitting functional layer. The vertical light-emitting chip also has an internal quantum efficiency increase of 5%-20%, a light extraction efficiency improvement of 1%-5%, a reduction in reverse leakage current, and an L70 lifetime extension of more than 10%.

Description

Technical Field

[0001] The present invention relates to the technical field of vertical light-emitting chip manufacturing, and in particular to a vertical light-emitting chip and a preparation method thereof. Background Art

[0002] Compared to face-mount and flip-chip LEDs, vertical LED chips offer significant advantages in high-power lighting due to their structural characteristics, including greater lateral current expansion, improved heat dissipation, the ability to withstand higher operating currents, and higher light output efficiency. However, advancements in display, smart wearable, and lighting applications are driving the need for smaller and thinner chips, posing greater challenges for vertical LED chips and placing higher demands on their performance.

[0003] For optoelectronic components, dislocations and defects within the material largely determine the overall device performance. Vertical GaN-based LEDs are all grown epitaxially on sapphire substrates. Due to lattice mismatch, growing GaN epitaxially directly on flat sapphire substrates results in a high dislocation density, which increases epitaxial defects, non-radiative recombination, and reduced internal quantum efficiency, impacting the lifespan of vertical LED chips. Patterning on sapphire substrates, as with flip-chip and face-mount LED chips, improves the quality of the epitaxial layer. However, the subsequent laser lift-off process can easily lead to incomplete or even impossible sapphire substrate lift-off, preventing the full benefits of the vertical structure from being realized.

[0004] Therefore, for vertical LED chips, how to solve the defects in the existing technology is an urgent problem to be solved. Summary of the Invention

[0005] Based on this, the present invention provides a vertical light-emitting chip and a preparation method thereof, which can grow high-quality gallium nitride-based epitaxy on a sapphire flat substrate for vertical LED chip manufacturing.

[0006] The present invention provides a method for preparing a vertical light-emitting chip, comprising the following steps:

[0007] growing a dissociated layer on a sapphire substrate;

[0008] growing a dielectric layer on the dissociation layer, and forming an array of conical protrusions on a surface of the dielectric layer away from the dissociation layer;

[0009] A buffer layer is covered on the conical protrusion array, wherein the surface of the buffer layer away from the conical protrusion array is flat;

[0010] Growing a light-emitting functional layer and a conductive functional layer in sequence on the buffer layer;

[0011] The laser is irradiated onto the dissociation layer, and the sapphire substrate is peeled off.

[0012] As a preferred embodiment of the above, the formation of a conical protrusion array on the surface of the dielectric layer away from the dissociation layer includes:

[0013] forming an array mask pattern on the surface of the dielectric layer;

[0014] Then, a reactive ion etching process or an inductively coupled plasma process is used to remove the dielectric material not covered by the mask, and the obtained conical protrusions in the conical protrusion array are in the micron level.

[0015] As a preferred embodiment of the above embodiment, a single mask pattern in the array of mask patterns includes a circle or a regular polygon, and a size of a single mask pattern in the array of mask patterns is ≤3 μm.

[0016] As a preferred embodiment of the above embodiment, the step of covering the tapered protrusion array with a buffer layer includes:

[0017] forming a first buffer layer on the surface of the cone-shaped protrusion array, wherein the shape of the first buffer layer is the same as that of the cone-shaped protrusion array;

[0018] A second buffer layer is filled in the gaps between the first buffer layers. The second buffer layer fills the gaps between the conical protrusions in the first buffer layer, and the surface of the second buffer layer away from the first buffer layer is flat.

[0019] As a preferred embodiment of the above embodiment, the first buffer layer and the second buffer layer both include at least one material selected from the group consisting of aluminum nitride, gallium nitride, and indium gallium nitride.

[0020] As a preferred embodiment of the above, forming a first buffer layer on the surface of the cone-shaped protrusion array includes:

[0021] A first buffer layer with a thickness of 0.3-1 μm is formed by a physical sputtering process.

[0022] As a preferred embodiment of the above embodiment, the step of filling the gaps between the first buffer layers with a second buffer layer includes:

[0023] A second buffer layer with a thickness of 2-10 μm is formed by a chemical vapor deposition process.

[0024] As a preferred embodiment of the above embodiment, undoped gallium nitride with a thickness of 1-3 μm is grown at low temperature by a chemical vapor deposition process.

[0025] The present invention also provides a vertical light-emitting chip, which is manufactured by any of the above-mentioned methods for manufacturing a vertical light-emitting chip.

[0026] As a preferred embodiment of the above embodiment, the vertical light-emitting chip includes a light extraction layer, a light-emitting functional layer and a conductive functional layer stacked in sequence, and the surface of the light extraction layer away from the light-emitting functional layer is provided with a conical protrusion array, and the conical protrusions in the conical protrusion array are in the micron level.

[0027] The beneficial effect of the present invention is to provide a vertical light-emitting chip and a preparation method thereof. The preparation method forms a dissociation layer, a dielectric layer and a buffer layer in sequence before growing a light-emitting functional layer (GaN-based epitaxy) on a sapphire flat substrate, and forms a conical protrusion array on the side of the dielectric layer away from the dissociation layer, thereby changing the growth of the gallium nitride-based light-emitting epitaxial material from longitudinal to lateral, reducing the dislocation density of the gallium nitride-based light-emitting epitaxial material, improving the growth quality of the light-emitting functional layer, and reducing the non-radiative recombination of the active region. The quantum efficiency of the vertical light-emitting chip can be increased by 5%-20%, and the reverse leakage current can be reduced, and the L70 life can be extended by more than 10%; in addition, the preparation method of the present invention has a good laser stripping effect, and the conical protrusion array increases the scattering of the light-emitting surface of the formed vertical light-emitting chip, and the light extraction efficiency can be improved by 1%-5%. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 Schematic diagram of the process of preparing a vertical light-emitting chip according to an embodiment of the present invention;

[0029] Figure 2-Figure 6 This is a structural schematic diagram corresponding to the diagram of the preparation method according to an embodiment of the present invention;

[0030] Figure 7 A schematic diagram of a vertical light-emitting chip structure provided by an embodiment of the present invention;

[0031] The meanings of the reference numerals in the accompanying drawings are:

[0032] 100-vertical light-emitting chip; 1-sapphire substrate; 2-dissociation layer; 3-dielectric layer; 4-conical protrusion array; 41-conical protrusion; 5-buffer layer; 51-first buffer layer; 52-second buffer layer; 6-light-emitting functional layer; 7-conductive functional layer; 8-bonding layer; 9-substrate. DETAILED DESCRIPTION

[0033] To facilitate understanding of the present invention, the present invention will be described more fully below with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the accompanying drawings. However, the present invention may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0034] It should be noted that when an element is referred to as being “fixed to” another element, it may be directly on the other element or there may be an intermediate element. When an element is referred to as being “connected to” another element, it may be directly connected to the other element or there may be an intermediate element.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used in this specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0036] like Figures 1 to 6 As shown in FIG, it is a schematic flow chart of a method for preparing a vertical light-emitting chip according to an embodiment of the present invention. The preparation method here is mainly for GaN-based vertical light-emitting chips, and specifically includes the following steps:

[0037] Step S100, growing a dissociation layer 2 on a sapphire substrate 1;

[0038] Step S200 , growing a dielectric layer 3 on the dissociation layer 2 , and forming a conical protrusion array 4 on a surface of the dielectric layer 3 away from the dissociation layer 2 ;

[0039] Step S300, covering the conical protrusion array 4 with a buffer layer, wherein the surface of the buffer layer away from the conical protrusion array 4 is flat;

[0040] Step S400 , sequentially growing a light-emitting functional layer 6 and a conductive functional layer 7 on the buffer layer;

[0041] In step S500 , laser is irradiated onto the dissociation layer 2 , and the sapphire substrate 1 is peeled off.

[0042] The sapphire substrate 1 in the embodiment of the present invention is a flat sapphire substrate, that is, the surface of the sapphire substrate 1 is flat.

[0043] The dissociation layer 2 in step S100 is intended to facilitate subsequent laser lift-off of the sapphire substrate 1. Optionally, the dissociation layer 2 is made of a material that can absorb the laser emission wavelength; preferably, the dissociation layer 2 is a GaN substrate. One possible implementation involves low-temperature growth of undoped gallium nitride on a common flat sapphire substrate via vapor deposition. Specifically, MOCVD equipment is used to grow the undoped gallium nitride at a low temperature of 600-850°C, forming a gallium nitride-based dissociation layer 2 with a thickness of 1-3 μm.

[0044] The formation of dielectric layer 3 in step S200 specifically includes first cleaning the surface of dissociation layer 2 formed in step S100, and then depositing a dielectric material on the surface of the undoped gallium nitride-based dissociation layer 2 using CVD deposition or physical sputtering to form a dielectric layer 3 with a thickness of 2 μm. Optional dielectric materials include, but are not limited to, SiO2, Al2O3, and AlN. Preferably, SiO2 is used for ease of subsequent processing.

[0045] The formation of the conical protrusion array 4 in step S200 specifically includes step S210, making an array mask pattern on the surface of the dielectric layer 3; step S220, then using a reactive ion etching process or an inductively coupled plasma process to remove the dielectric material not covered by the mask, and the conical protrusions 41 in the obtained conical protrusion array 4 are at the micron level.

[0046] For the conical protrusion array 4, an array mask pattern can be produced on the surface of the dielectric layer 3 through a photolithography process. A single mask pattern in the array mask pattern includes but is not limited to regular shapes such as circles or regular polygons. Regular polygons include regular shapes such as squares and regular hexagons. Optionally, the size of a single mask pattern is not greater than 3 μm. Then, an RIE or ICP process is used to remove the dielectric material not covered by the mask, so that the dielectric material is etched to form a plurality of cones that are wide at the bottom and narrow at the top, thereby obtaining a conical protrusion array 4 on one surface of the dielectric layer 3 (away from the dissociation layer 2).

[0047] The buffer layer in step S300 further includes a first buffer layer 51 and a second buffer layer 52 sequentially disposed on the dielectric layer 3. Specifically, the first buffer layer 51 is formed on the surface of the tapered protrusion array 4, and the shape of the first buffer layer 51 is the same as that of the tapered protrusion array 4; the second buffer layer 52 is filled in the gaps between the first buffer layer 51, and the second buffer layer 52 fills the gaps between the tapered protrusions 41 in the first buffer layer 51. The surface of the second buffer layer 52 away from the first buffer layer 51 is flat. The morphology of the second buffer layer 52 formed on the side adjacent to the first buffer layer 51 is also a tapered protrusion array composed of a plurality of micron-scale tapered protrusions that are narrow at the top and wide at the bottom.

[0048] Optionally, both the first buffer layer 51 and the second buffer layer 52 are made of at least one of aluminum nitride, gallium nitride, or indium gallium nitride. For example, for the first buffer layer 51, the mask material remaining on the substrate surface in step S200 is cleaned and removed, and aluminum nitride is deposited on the surface of the cone-shaped protrusion array of the dielectric layer 3 using physical sputtering to obtain an aluminum nitride film with a thickness of 0.3-1 μm, which serves as the first buffer layer 51. The aluminum nitride film formed is also in the shape of a cone-shaped protrusion array. For the second buffer layer 52, aluminum nitride is grown at a high temperature of 900-1200°C using an MOCVD device until the micro-conical protrusion array formed by the first buffer layer 51 is completely covered and the gaps between the cone protrusions in the micro-conical protrusion array are filled, forming a second buffer layer 52 with a thickness of 2-10 μm, so that the surface of the second buffer layer 52 away from the first buffer layer 51 is flat.

[0049] In step S400, after the above steps are completed, the growth of the light-emitting functional layer 6, such as the N-type layer, MQW, and P-type layer, and the growth of other conductive functional layers 7 (current expansion layer, metal reflection layer, etc.) that are beneficial to current expansion and improving recombination efficiency are sequentially completed according to the conventional light-emitting functional layer 6 growth process (epitaxial growth process). The light-emitting functional layer 6 here mainly refers to the gallium nitride-based epitaxial layer, and the chip segment process is subsequently completed according to the vertical chip process.

[0050] In step S500, after the chip segment is completed according to the above steps, the chip can also undergo a series of processes such as electrode bonding and bottom filling colloid. Finally, using the laser stripping process, the laser penetrates the sapphire substrate 1 and irradiates the dissociation layer 2. The dissociation layer 2 absorbs the laser energy and decomposes, and the sapphire substrate 1 with poor thermal conductivity is peeled off.

[0051] In a method for fabricating a vertical light-emitting chip according to an embodiment of the present invention, a dissociation layer 2 and a dielectric layer 3 composite film are sequentially grown on a flat sapphire substrate for a vertical LED chip. An array of conical protrusions 4 is formed on the side of the dielectric layer 3 facing away from the dissociation layer 2. A buffer layer is then used to cover and fill the conical protrusion array 4. A gallium nitride-based light-emitting epitaxial layer and a conductive functional layer 7 are then grown on the buffer layer. Finally, the vertical LED chip is obtained by laser lift-off of the sapphire substrate 1. In the vertical LED chip obtained by this method, the growth of the gallium nitride-based light-emitting epitaxial material changes from longitudinal to lateral orientation, effectively reducing the dislocation density of the gallium nitride-based light-emitting epitaxial material, improving the quality of epitaxial growth, and minimizing non-radiative recombination in the active region. Furthermore, the internal quantum efficiency can be increased by 5%-20%, reverse leakage current can be reduced, and the L70 lifetime can be extended by more than 10%. After laser lift-off, the array structure of micron-scale conical protrusions 41 in the dielectric layer 3 increases the scattering of the light-emitting surface of the resulting vertical light-emitting chip, improving the light extraction efficiency by 1%-5%.

[0052] See also Figure 7The present invention also provides a vertical light-emitting chip 100, manufactured using the above method. The obtained vertical light-emitting chip 100 comprises a light extraction layer, a light-emitting functional layer 6, a conductive functional layer 7, a bonding layer 8, and a substrate 9, stacked in sequence. The substrate 9 may be a silicon substrate on which a driving circuit may be arranged; the bonding layer 8 may be a metal conductive layer for connecting the driving circuit and the chip's electrodes; the light-emitting functional layer 6 may be a gallium nitride-based epitaxial layer comprising an N-type layer, an MQW layer, and a P-type layer; the conductive functional layer 7 may include, but is not limited to, a current spreading layer and a metal reflective layer; the light extraction layer is the second buffer layer 52 described above; the light extraction layer has a conical protrusion array on the side away from the light-emitting functional layer 6. The conical protrusion array is formed by the conical protrusion array 4 of the dielectric layer 3 and includes a plurality of conical protrusions, each narrow at the top and wide at the bottom, and each conical protrusion is micrometer-sized; the material of the light extraction layer includes, but is not limited to, at least one of aluminum nitride, gallium nitride, or indium gallium nitride. The wider shape below the conical protrusion includes but is not limited to regular shapes such as circles or regular polygons. Regular polygons include regular shapes such as squares and regular hexagons. In the vertical light-emitting chip 100 of the embodiment of the present invention, the gallium nitride-based epitaxial material has a low dislocation density and high epitaxial quality, and the non-radiative recombination in the active region is reduced. In addition, the internal quantum efficiency is improved, the reverse leakage current is reduced, and the L70 life is extended. The surface of the micron-scale conical protrusion array of the light extraction layer increases light scattering, and the light extraction efficiency is increased. The vertical light-emitting chip 100 of the embodiment of the present invention can be used in high-efficiency, high-power light-emitting devices, such as car lights and display devices. The display device can be applied to backlight modules and direct displays.

[0053] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0054] The above embodiments merely represent preferred embodiments of the present invention. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make various modifications and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.

Claims

1. A method for preparing a vertical light-emitting chip, characterized in that: The following steps are involved: growing a dissociated layer on a sapphire substrate; growing a dielectric layer on the dissociation layer, and forming an array of conical protrusions on a surface of the dielectric layer away from the dissociation layer; A buffer layer is covered on the conical protrusion array, wherein the surface of the buffer layer away from the conical protrusion array is flat, wherein the covering of the buffer layer on the conical protrusion array includes: forming a first buffer layer on the surface of the conical protrusion array, the shape of the first buffer layer is the same as the shape of the conical protrusion array, the first buffer layer is formed by physical sputtering, the thickness of the first buffer layer is 0.3 to 1 micron, the first buffer layer is in direct contact with the dissociation layer, and the dissociation layer can absorb the emission wavelength of the laser; filling the gaps between the first buffer layers with a second buffer layer, the second buffer layer filling the gaps between the conical protrusions in the first buffer layer and the surface of the second buffer layer away from the first buffer layer is flat; Growing a light-emitting functional layer and a conductive functional layer in sequence on the buffer layer; The laser is irradiated onto the dissociation layer, the sapphire substrate is peeled off, and the first buffer layer is removed.

2. The method for preparing a vertical light-emitting chip according to claim 1, wherein: The method of forming a conical protrusion array on a surface of the dielectric layer away from the dissociation layer comprises: forming an array mask pattern on the surface of the dielectric layer; Then, a reactive ion etching process or an inductively coupled plasma process is used to remove the dielectric material not covered by the mask, and the obtained conical protrusions in the conical protrusion array are in the micron level.

3. The method for preparing a vertical light-emitting chip according to claim 2, wherein: A single mask pattern in the array of mask patterns includes a circle or a regular polygon, and a size of a single mask pattern in the array of mask patterns is ≤3 μm.

4. The method for preparing a vertical light-emitting chip according to claim 1, wherein: The first buffer layer and the second buffer layer each include at least one material selected from the group consisting of aluminum nitride, gallium nitride, and indium gallium nitride.

5. The method for preparing a vertical light-emitting chip according to claim 1, wherein: Filling the gaps between the first buffer layers with a second buffer layer comprises: A second buffer layer with a thickness of 2-10 μm is formed by a chemical vapor deposition process.

6. The method for preparing a vertical light-emitting chip according to claim 1, wherein: Undoped GaN with a thickness of 1-3 μm is grown at low temperature by chemical vapor deposition.

Images