A vector quantizer applied to DAC mismatch error suppression

Abstract

A vector quantizer applied to DAC mismatch error suppression includes a Sigma-Delta modulator, a DEM circuit, and a multi-bit DAC. The Sigma-Delta modulator receives an input signal u(t), and the output signal v[n] of the Sigma-Delta modulator is sent to the DEM circuit. The DEM circuit includes a vector filter and a vector sorter connected in sequence. The vector sorter is connected to a comparator for LSB output and a comparator array based on element enabling. The comparator array based on element enabling includes N comparators, and the output of each comparator controls the corresponding DAC element to work or not to work. The output signal of the DEM circuit is input into the multi-bit DAC, and the multi-bit DAC outputs a vector quantization signal r(t). The present invention can improve the mismatch error suppression effect in application scenarios of low-order low-bit, low-order multi-bit, and high-order multi-bit, and save hardware overhead.

Description

Technical Field

[0001] The present invention belongs to the field of analog integrated circuit design, and relates to a vector quantizer applied to DAC mismatch error suppression. Background Art

[0002] For multi-bit DACs (digital-to-analog converters) applied to oversampling ADCs (analog-to-digital converters) or Nyquist ADCs, element mismatches inevitably exist in the actual production process, resulting in high-order harmonics and elevated noise floors in the baseband. Researchers have used the DEM (Digital Elevation Model) method to suppress this non-linearity and have published several circuit structures.

[0003] Some scholars have proposed vector quantizers based on a full sorting structure. Although the quantization is accurate, the hardware area overhead is very large. Subsequently, other scholars have proposed vector quantizers based on an adder tree structure. Although the hardware area overhead is reduced compared to the vector quantizer structure based on the full sorting structure, it cannot be extended to application scenarios of low-order low-bit, low-order multi-bit, and high-order multi-bit, and the improvement results of the signal-to-noise ratio (SNR) have great limitations. Summary of the Invention

[0004] The purpose of the present invention is to overcome the problems that existing DEMs have limitations in the mismatch shaping order and the number of sorting elements, and to provide a vector quantizer applied to DAC mismatch error suppression. By designing a new architecture, the improvement of the mismatch error suppression effect is achieved in application scenarios of low-order low-bit, low-order multi-bit, and high-order multi-bit.

[0005] To achieve the above purpose, the present invention has the following technical solutions:

[0006] A vector quantizer applied to DAC mismatch error suppression includes a Sigma-Delta modulator, a DEM circuit, and a multi-bit DAC. The Sigma-Delta modulator receives an input signal u(t), and the output signal v[n] of the Sigma-Delta modulator is sent to the DEM circuit. The DEM circuit includes a vector filter and a vector sorter connected in sequence. The vector sorter is connected to a comparator for LSB output and a comparator array based on element enabling. The output signal of the vector filter is The positive input terminal of the comparator for LSB output is the sum of W1 to W N / 2 and the negative input terminal is the sum of W (N / 2+1) to W N ; the comparator array based on element enabling includes a total of N comparators. The output of each comparator controls the operation or non-operation of the corresponding DAC element, and the output signal is The output signal of the DEM circuit is input into the multi-bit DAC, and the multi-bit DAC outputs a vector quantization signal r(t).

[0007] As a preferred embodiment of the vector quantizer of the present invention, the multi-bit DAC outputs a vector quantization signal r(t) as a negative feedback signal and is jointly input into the Sigma-Delta modulator together with the input signal u(t).

[0008] As a preferred embodiment of the vector quantizer of the present invention, the number of unit elements of the multi-bit DAC is N, the vector filter has a total of N scalar paths, and the vector sorter feeds back the output signal to the vector filter in the form of positive feedback, and the signal and are both N-dimensional vectors.

[0009] As a preferred embodiment of the vector quantizer of the present invention, the vector filter is any cascaded feed-forward structure or cascaded feedback structure with an order of not less than 1.

[0010] As a preferred embodiment of the vector quantizer of the present invention, the Sigma-Delta modulator is a discrete-time structure or a continuous-time structure.

[0011] As a preferred embodiment of the vector quantizer of the present invention, the DEM circuit satisfies the following expression at any time t = nT, where n is any integer and T is the DAC sampling period:

[0012]

[0013] In the formula, sv i [n] represents the enable signal of the i-th DAC unit, v[n] is the output of the sigma-delta modulator, and N is the number of unit elements of the DAC.

[0014] As a preferred embodiment of the vector quantizer of the present invention, the positive output terminal of the 1 comparator for LSB output is used to form P1 to P N / 2 of the LSB, and the negative output terminal is used to form P (N / 2+1) to P N of the LSB, is the output signal of the vector sorter as the signal after merging the MSBs and LSBs.

[0015] As a preferred embodiment of the vector quantizer of the present invention, 2 vector sorters are provided, P1 to PN / 2 The high-order bits of q1 to q of N are determined by the output signal of the first vector sorter; P of N / 2+1 ~P N The high-order bits of q of N / 2+1 ~q N are determined by the output signal of the second vector sorter.

[0016] As a preferred embodiment of the vector quantizer of the present invention, the logic circuit structures of the first vector sorter and the second vector sorter are the same.

[0017] As a preferred embodiment of the vector quantizer of the present invention, each signal component p of i , 1≤i≤N, is formed by arranging the high-order bit MSBs generated by the vector sorter and the output bit of a comparator for LSB output in a binary manner from high to low.

[0018] Compared with the prior art, the present invention has at least the following beneficial effects:

[0019] Instead of setting the LSBs output by the vector sorter as the multi-bit outputs of multiple comparators, the LSBs are set as the single-bit form output by a single comparator, and the remaining high-order bits are all generated by the vector sorter. Compared with the vector quantizer based on the full sorting structure, the vector quantizer of the present invention can reduce the hardware area by more than 50%; at the same time, compared with the vector quantizer based on the adder tree structure, the number of comparators in the vector quantizer of the present invention does not increase with the increase of the DAC bit number, saving the hardware cost and significantly improving the hardware efficiency; compared with the vector quantizer based on the adder tree structure, the vector quantizer of the present invention can improve the mismatch shaping effect in the case of low-order and few bits; compared with the vector quantizer based on the adder tree structure, the vector quantizer of the present invention can significantly improve the mismatch shaping effect in the case of low-order and many bits; compared with the vector quantizer based on the adder tree structure, the vector quantizer of the present invention can greatly improve the mismatch shaping effect in the case of high-order and many bits, and eliminate the step noise floor effect that appears in the vector quantizer based on the adder tree structure. Brief Description of the Drawings

[0020] Figure 1 is a schematic structural diagram of the vector quantizer applied to DAC mismatch error suppression according to an embodiment of the present invention;

[0021] Figure 2 is a comparison diagram of the simulation results of the DAC output spectrum between the present invention and the adder tree structure under low-order and few bits;

[0022] Figure 3 Comparison graph of the simulation results of the present invention and the adder tree structure regarding the DAC output spectrum at low-order high bits;

[0023] Figure 4 Comparison graph of the simulation results of the present invention and the adder tree structure regarding the DAC output spectrum at high-order high bits. Specific implementation manners

[0024] The present invention will be further described in detail below with reference to the accompanying drawings.

[0025] See Figure 1 , a vector quantizer applied to DAC mismatch error suppression proposed by an embodiment of the present invention includes a Sigma-Delta modulator, a DEM circuit, and a multi-bit DAC, breaking through the limitations of the vector quantizer based on the adder tree structure in terms of mismatch shaping order and the number of DAC elements. By using the vector quantizer architecture proposed by the embodiment of the present invention, a significant improvement in the mismatch error suppression effect can be achieved in the application scenario; moreover, compared with the vector quantizer based on the full sorting structure, the vector quantizer of the present invention can achieve a 50% hardware saving; compared with the vector quantizer based on the adder tree structure, the number of comparators in the present invention does not increase with the increase of the DAC bit number, further saving the hardware overhead.

[0026] As Figure 1 shown, the signal u(t) is input into the Sigma-Delta modulator, and the output v[n] of the Sigma-Delta modulator is sent to the DEM circuit. The DEM circuit includes a vector filter and a vector sorter connected in sequence. The output signal of the vector filter is sorted by the vector sorter and then output as the signal fed back to the vector filter in a positive feedback manner. Specifically, the vector sorter is connected to 1 comparator for LSB output and a comparator array based on element enabling. The output signal of the vector filter is The positive input terminal of the 1 comparator for LSB output is the sum of W1 to W N / 2 in and the negative input terminal is (N / 2+1) the sum of W N to W in; the comparator array based on element enabling includes a total of N comparators, and the output of each comparator controls the corresponding DAC element to work or not to work. The output signal is The output signal

[0027] Further, in a possible implementation, the multi-bit DAC outputs a vector quantization signal r(t) which, as a negative feedback signal, is jointly input into the Sigma-Delta modulator with the input signal u(t). The number of unit elements of the multi-bit DAC is N, the vector filter has a total of N scalar channels, and the vector sorter feeds back the output signal to the vector filter in the form of positive feedback. The signals and are both N-dimensional vectors. The vector filter is of any cascaded feed-forward structure or cascaded feedback structure with an order not less than 1. The Sigma-Delta modulator is of a discrete-time structure or a continuous-time structure.

[0028] The DEM circuit satisfies the following expression at any time t = nT, where n is any integer and T is the DAC sampling period:

[0029]

[0030] In the formula, sv i [n] represents the enable signal of the i-th DAC unit, v[n] is the output of the sigma-delta modulator, and N is the number of unit elements of the DAC.

[0031] In a possible implementation, the positive output terminal of the 1 comparator for LSB output is used to form 's P1 to P N / 2 's LSB, and the negative output terminal is used to form 's P (N / 2+1) to P N 's LSB. is the output signal of the vector sorter as the signal after merging the MSBs and LSBs. There are 2 vector sorters. 's P1 to P N / 2 's high-order bits are determined by the output signal 's q1 to q N ; 's P N / 2+1 to P N 's high-order bits are determined by the output signal 's q N / 2+1 to q N . The logical circuit structures of the first vector sorter and the second vector sorter are the same. Each signal component p of i , where 1 ≤ i ≤ N, is formed by arranging the high-order bits MSBs generated by the vector sorter and the output bits of 1 comparator for LSB output in the binary order from high to low. ​

[0032] The working principle and effects of the vector quantizer of the present invention will be described below in conjunction with specific embodiments.

[0033] First, each output component of the vector sorter of the present invention q of i (1 ≤ i ≤ N) will contribute to p of i (1 ≤ i ≤ N), that is, the most significant bits, namely MSBs; the output of the LSB output comparator will contribute to p of i (1 ≤ i ≤ N), that is, the least significant bits, namely LSBs. It should be noted that regardless of the value of N, all MSBs except LSBs of the present invention are determined by the vector sorter. Therefore, on the one hand, the present invention eliminates the noise step problem that the vector quantization noise caused by the adder tree structure increases with the increase of N. On the other hand, compared with the full sorting structure, by using the vector segmentation technology of the present invention, 50% of the hardware overhead can be saved; compared with the vector quantizer based on the adder tree structure, the number of comparators in the present invention does not increase with the increase of the DAC bit number, further saving the hardware overhead and significantly improving the hardware efficiency.

[0034] Refer to Figure 2 , set the order of the Sigma-Delta modulator to 3, the DAC has N = 16 elements, the oversampling rate is 100, and the order of the vector loop filter = 2, Figure 2 shows the simulation diagram of the vector quantizer of the present invention and the adder tree structure regarding the DAC output spectrum. It can be seen that due to the insufficient quantization of the adder tree structure, a relatively high noise floor is generated in the low-frequency domain of the spectrum diagram, reducing the signal-to-noise ratio (SNR) of the system; the simulation results show that the SNR of the adder tree structure is 114.1 dB, while using the vector quantizer structure of the present invention, the SNR can be increased to 120.7 dB.

[0035] Refer to Figure 3 , set the order of the Sigma-Delta modulator to 3, the DAC has N = 32 elements, the oversampling rate is 100, and the order of the vector loop filter = 2, Figure 3Shows the simulation diagrams of the vector quantizer of the present invention and the adder tree structure with respect to the DAC output spectrum. It can be seen that due to the more serious insufficient quantization of the adder tree structure, a higher noise floor is generated in the low-frequency domain in the spectrum diagram compared to N = 16, further reducing the signal-to-noise ratio (SNR) of the system; the simulation results show that the SNR of the adder tree structure is 109.5 dB, however, using the vector quantizer structure of the present invention, the SNR can be increased to 124.8 dB; it can be seen that compared with the adder tree structure, when the order of the vector filter remains unchanged in the vector quantizer of the present invention, the suppression effect of the mismatch error is significantly improved as N increases.

[0036] See Figure 4 , set the order of the Sigma-Delta modulator to 4, the number of elements of the DAC is N = 32, the oversampling rate is 100, and the order of the vector loop filter = 3. Figure 4 Shows the simulation diagrams of the vector quantizer of the present invention and the adder tree structure with respect to the DAC output spectrum. It can be seen that due to the more serious insufficient quantization of the adder tree structure, the elevation of the noise floor has significantly extended from the low frequency to the high frequency. At high frequencies, the spectrum of the adder tree structure even appears in a stepped shape. The influence of this stepped noise floor will bring two disadvantages: 1) At high frequencies, there is no improvement in the mismatch shaping ability within the frequency band corresponding to the stepped noise floor, which will limit the application of the DEM based on the adder tree structure in low OSR scenarios; 2) The stepped noise floor that appears at high frequencies will greatly increase the noise floor at low frequencies, thereby further reducing the suppression of the mismatch error by the adder tree structure and reducing the signal-to-noise ratio (SNR) of the system. See Figure 4 , the simulation results show that the SNR of the adder tree structure is only 116.7 dB, far lower than the SNR of 139.4 dB achieved by using the vector quantizer structure of the present invention; it can be seen that compared with the adder tree structure, when the number of DAC elements remains unchanged in the vector quantizer of the present invention, the suppression effect of the mismatch error will be greatly improved as the order of the vector filter increases.

[0037] A vector quantizer applied to DAC mismatch error suppression according to the present invention. Compared with the vector quantizer based on the full sorting structure and the vector quantizer based on the adder tree structure, the present invention has three important improvements: 1) Compared with the vector quantizer based on the full sorting structure, the vector quantizer of the present invention can reduce the hardware area by more than 50%; compared with the vector quantizer based on the adder tree structure, the number of comparators in the present invention does not increase with the increase of the DAC bit number, further saving the hardware overhead and significantly improving the hardware efficiency; 2) Compared with the vector quantizer based on the adder tree structure, the vector quantizer of the present invention can achieve an improved mismatch shaping effect in the case of low order and few bits; 3) Compared with the vector quantizer based on the adder tree structure, the vector quantizer of the present invention can achieve a significant improvement in the mismatch shaping effect in the case of low order and many bits; 3) Compared with the vector quantizer based on the adder tree structure, the present invention can achieve a great improvement in the mismatch shaping effect in the case of high order and many bits, and eliminate the step noise floor effect that appears in the vector quantizer based on the adder tree structure.

[0038] The above embodiments are only used to illustrate the technical solutions of the present application, and are not intended to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A vector quantizer applied to DAC mismatch error suppression, characterized in that Including a Sigma-Delta modulator, a DEM circuit, and a multi-bit DAC, the Sigma-Delta modulator receives an input signal , the output signal v[n] of the Sigma-Delta modulator is sent to the DEM circuit. The DEM circuit includes a vector filter and a vector sorter connected in sequence. The vector sorter is connected to a comparator for LSB output and a comparator array based on element enabling. The output signal of the vector filter is , the positive input terminal of the comparator for LSB output is the sum of W1 to W N / 2 , and the negative input terminal is the sum of W (N / 2+1) to W N ; the comparator array based on element enabling contains a total of N comparators. The output of each comparator controls the corresponding DAC element to work or not work, and the output signal is ; the output signal of the DEM circuit is input into the multi-bit DAC, and the multi-bit DAC outputs a vector quantization signal ; the positive output terminal of the comparator for LSB output is used to form the LSBs of P1 to P of N / 2 , and the negative output terminal is used to form the LSBs of P to P (N / 2+1) to P N ; is the output signal of the vector sorter as the signal after merging MSBs and LSBs; there are 2 vector sorters. The high-order bits of P1 to P N / 2 of are determined by the output signal of the first vector sorter to ; The high-order bits of P N / 2+1 to P N of are determined by the output signal of the second vector sorter to ; the logic circuit structures of the first vector sorter and the second vector sorter are the same; each signal component of , where 1 ≤ i ≤ N, is formed by arranging the high-order bit MSBs generated by the vector sorter and the output bit of a comparator for LSB output in a binary manner from high to low.

2. The vector quantizer applied to DAC mismatch error suppression according to claim 1, characterized in that, The multi-bit DAC outputs a vector quantization signal which, as a negative feedback signal, and the input signal are jointly input into the Sigma-Delta modulator.

3. The vector quantizer applied to DAC mismatch error suppression according to claim 1, characterized in that, The number of unit elements of the multi-bit DAC is N, the vector filter has a total of N scalar paths, and the vector sorter feeds back the output signal back to the vector filter in the form of positive feedback, and the signal and are both N-dimensional vectors.

4. The vector quantizer applied to DAC mismatch error suppression according to claim 1, characterized in that The vector filter described above is of any cascade feedforward structure or cascade feedback structure with an order not less than 1.

5. The vector quantizer applied to DAC mismatch error suppression according to claim 1, characterized in that The Sigma-Delta modulator described above is of a discrete-time structure or a continuous-time structure.

6. The vector quantizer applied to DAC mismatch error suppression according to claim 1, characterized in that, The DEM circuit at any moment t = nT , n is any integer, T is the DAC sampling period, and all satisfy the following expression: In the formula, represents the enable signal of the i th DAC unit, is the output of the Sigma-Delta modulator, N is the number of unit elements of the DAC.

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