Information processing apparatus and driving method thereof

Abstract

Two analog resistance variable elements (101) and (102) in a form where a resistance component (R1) is connected in parallel with a capacitance component (C1), and a resistance component (R2) is connected in parallel with a capacitance component (C2) through an upper electrode, a lower electrode, and an oxide layer provided between the upper electrode and the lower electrode are connected in series, so that existing analog resistance variable elements can be directly utilized. In addition, for an analog resistance element in a form where a resistance component is connected in parallel with a capacitance component, a parallel circuit having a resistance component and a capacitance component can be connected. By applying a voltage to this circuit system, the resistance value can be changed. During the process of reducing the resistance to a low value, the influence of the capacitance components (C1) and (C2) appears, and the voltage is reduced by distributing the voltage according to the ratio of the capacitances, thereby suppressing a sharp decrease in the resistance.

Description

Technical Field

[0001] The present invention relates to an information processing apparatus and a driving method thereof. In particular, it relates to a brain-type information processing apparatus using an analog resistance change element and a driving method of the brain-type information processing apparatus. Background Art

[0002] IoT (Internet of Things) technology is applied to various fields, and the amount of data flowing into the Internet is acceleratingly increasing. As a result, the power consumption in all processes such as information collection, accumulation, circulation, analysis, and control has increased significantly.

[0003] In the case where a CPU accesses a memory for arithmetic processing as in a conventional computer, since the data transfer speed is slow, it is impossible to suppress the increase in power consumption. In recent neural computers (brain-type information processing apparatuses, brain-type circuits), through in-memory computing obtained by integrating a processor and a memory, superparallel computing can be performed, and by mimicking information processing in the brain, the computing efficiency can be increased and the power consumption can be reduced.

[0004] In brain-type information processing, for example, a nerve cell is modeled as a multi-input single-output element, and the input pattern is separated on a separation plane by pattern recognition of a perceptron. In a brain-type information processing apparatus, for example, an analog resistance change element is used in a perceptron, and an array structure formed by cross-connecting word lines and bit lines is used. The analog resistance change element is also called a memristor, RAND (Resistive Analog Neuro Device).

[0005] The analog resistance change element has a resistive switching effect in which the current value changes nonlinearly by applying a voltage to an insulating oxide film, and the resistance value changes analogously by a redox reaction induced by the current. For the analog resistance change element, since the I (current)-V (voltage) curve has a hysteresis characteristic, nonvolatile resistance change can be used as a memory.

[0006] As a technology related to the analog resistance change element, for example, a rectifying element is disclosed in which a titanium oxide layer is sandwiched between electrodes, and the rectifying characteristic can be reversed by applying a reverse electric signal having a magnitude exceeding a critical inversion power in opposite directions between the electrodes (for example, refer to Patent Document 1 below).

[0007] In addition, the following technology is disclosed: a non-volatile pseudo-memcapacitor (NPM) that connects a series capacitor Cs to the inherent parallel capacitor Cp of a memristor, thereby temporally controlling conductivity and reducing the power consumption of a circuit (for example, refer to Non-Patent Document 1 below).

[0008] In addition, the following technology is disclosed: a memcapacitor that sets an upper electrode by alternately arranging a plurality of second dielectric layers and a plurality of variable resistance portions in a form erected on a first dielectric layer on a lower electrode, thereby improving the operation processing speed and the number of rewrite times (for example, refer to Patent Document 2 below).

[0009] Prior Art Documents

[0010] Patent Documents

[0011] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2009-135461

[0012] Patent Document 2: Japanese Unexamined Patent Application Publication No. 2018-49887

[0013] Non-Technical Documents

[0014] Non-Patent Document 1: Zhongrui Wang, et al. 23 others, "Capacitive neural network with neuro-transistors", [online], August 10, 2018, nature communications, [searched on February 6, 2020], URL <URL: https: / / www.nature.com / articles / s41467-018-05677-5> Summary of the Invention

[0015] Technical Problem

[0016] However, in the technologies disclosed in Patent Document 1 and Non-Patent Document 1 described above, in the DC I-V curve, a sharp resistance change occurs during the low-resistance (Set) process compared to the high-resistance (Reset) process. In particular, a sharp (digital) resistance change occurs during the low-resistance process in the hysteresis characteristic. It is speculated that this is the case where the voltage applied to the high-resistance element is mostly continuously applied to perform the low-resistance process at high speed, so it is difficult to obtain a desired arbitrary resistance value.

[0017] In addition, in the technology disclosed in the above-mentioned Patent Document 2, a structure is adopted in which a plurality of second dielectric layers and a plurality of variable resistance portions are alternately and separately arranged in the in-plane direction (different positions when viewed from above) of the element. Therefore, it is impossible to reduce the longitudinal size, and it is difficult to miniaturize the element (miniaturization), and further, it is difficult to achieve three-dimensional structuring of the element in the lateral, longitudinal, and height directions.

[0018] Conventionally, in order to obtain an arbitrary resistance value with a sharp resistance change characteristic, a method using the current compliance function of a measuring device and a method using a transistor and controlling the amount of current with a gate voltage have been considered. However, in the method using the current compliance function, a measuring device is always used, which is not practical. In addition, in the method using a transistor, whether the transistors are arranged two-dimensionally or three-dimensionally, an increased amount of space for the transistors is required, and the process becomes complicated and the cost becomes high. Therefore, such a method is not desirable.

[0019] In an analog resistance change element used in a brain-type information processing device, a means for suppressing a sharp resistance change during the low-resistance state (Set) process is desired. Regarding the analog resistance change element, the suppression of the sharp resistance change characteristic during the low-resistance state (Set) process becomes a smooth resistance change achieved by removing noise of the resistance change component, and high speed and low power consumption of the product-sum circuit can be expected.

[0020] In addition, currently, due to the sharp resistance change generated during the low-resistance state (Set) process, the resistance change characteristic during the low-resistance state (Set) process and the resistance change characteristic during the high-resistance state (Reset) process are asymmetric. In the case where the analog resistance change element is used in the product-sum circuit (artificial intelligence, deep learning or inference, machine learning, etc.) of the brain-type information processing device, if the resistance change characteristic during the low-resistance state (Set) process and the resistance change characteristic during the high-resistance state (Reset) process can be made symmetric, an improvement in the symmetry of the storage operation and the forgetting operation of the product-sum circuit can be expected.

[0021] In order to solve the above problems, an object of the present invention is to obtain an information processing device and a driving method of the information processing device that can suppress a sharp resistance change and miniaturize an arbitrary resistance value with a simple structure.

[0022] Technical Solution

[0023] In order to solve the above problems, the information processing device of the present invention is characterized by having: an analog resistance change element composed of a pair of electrodes and an oxide layer provided between the pair of electrodes; and a parallel circuit having a resistance component and a capacitance component, the parallel circuit being connected in series with the analog resistance change element.

[0024] In addition, it is configured with the following features: as the parallel circuit, an analog resistor change element having a capacitance component is used, and by connecting a pair of the analog resistor change elements in series with each other, the analog resistor change element is used as an element whose resistance value can be freely changed.

[0025] In addition, it is configured with the following features: the electrode is composed of an upper electrode and a lower electrode, and through the upper electrode, the lower electrode, and the oxide layer provided between the upper electrode and the lower electrode, an analog resistor change element in a form where a resistance component and a capacitance component are connected in parallel is formed. The lower electrodes of two of the analog resistor change elements are connected to each other, and by applying a voltage to the circuit system from the upper electrode of one of the analog resistor change elements to the upper electrode of the other analog resistor change element, the resistance value can be changed.

[0026] In addition, it is configured with the following features: as the oxide layer, a plurality of layers having different resistivities are laminated.

[0027] In addition, it is configured with the following features: the resistivity of one of the plurality of oxide layers is less than 1000 mOhm cm, and the resistivity of the other is 1000 mOhm cm or more.

[0028] In addition, it is configured with the following features: adjacent pairs of the lower electrodes among a plurality of the analog resistor change elements provided at different planar positions on the substrate are connected to each other.

[0029] In addition, it is configured with the following features: at one planar position on the substrate, as the analog resistor change element, the lower electrode, the oxide layer, the intermediate electrode, the oxide layer, and the upper electrode are laminated in sequence from the lower layer.

[0030] In addition, the driving method of the information processing device of the present invention is characterized in that in an information processing device having an analog resistor change element composed of a pair of electrodes and an oxide layer provided between the pair of electrodes, a parallel circuit having a resistance component and a capacitance component is connected in series with the analog resistor change element, and the resistance value is changed by voltage application.

[0031] In addition, it is configured with the following features: as the parallel circuit, an analog resistor change element having a capacitance component is used, and by connecting a pair of the analog resistor change elements in series with each other, the analog resistor change element is used as an element whose resistance value can be freely changed.

[0032] As described above, an analog resistor element configured in a form where a resistance component and a capacitance component are connected in parallel directly connects a parallel circuit having a resistance component and a capacitance component, or directly connects another analog resistor element. For example, between a pair of analog resistor elements, in a state where no resistance change occurs (before the resistance change starts), the voltage is divided at a ratio of the resistance components R1 and R2. During a period of rapid resistance change, the influence of the capacitance components C1 and C2 of the two analog resistor elements appears and the voltage is divided according to the capacitance ratio. As a result, although most of the voltage is usually applied to the element in the high-resistance state, the voltage decreases during rapid low-resistance conversion, thereby suppressing a sharp decrease in resistance.

[0033] Technical effects

[0034] According to the present invention, an effect is achieved in which a sharp resistance change can be suppressed, and an arbitrary resistance value can be miniaturized with a simple structure. Description of the drawings

[0035] Figure 1 It is a diagram showing an equivalent circuit of the information processing apparatus according to the embodiment.

[0036] Figure 2 It is a diagram showing a structural example of the RAND according to the embodiment. (One)

[0037] Figure 3 It is a diagram showing a structural example of the RAND according to the embodiment. (Two)

[0038] Figure 4 It is a graph for explaining the I-V characteristics of RAND1 + RAND2 according to the embodiment.

[0039] Figure 5 It is a graph showing the I-V characteristics during repeated measurement of RAND1 + RAND2 according to the embodiment.

[0040] Figure 6 It is a graph for explaining the I-V characteristics of RAND1 + RAND2 according to the embodiment.

[0041] Figure 7 It is a graph for explaining the I-V characteristics in the case where the applied voltage of RAND1 + RAND2 according to the embodiment is changed.

[0042] Figure 8 It is a top view of RAND1 + RAND2 according to the embodiment.

[0043] Figure 9 It is to connect Figure 8 The cross-sectional view taken along the line connecting points A to J of

[0044] Figure 10A It is a cross-sectional view showing the manufacturing process of the analog resistance change element of the embodiment. (Part 1)

[0045] Figure 10B It is a cross-sectional view showing the manufacturing process of the analog resistance change element of the embodiment. (Part 2)

[0046] Figure 10C It is a cross-sectional view showing the manufacturing process of the analog resistance change element of the embodiment. (Part 3)

[0047] Figure 10D It is a cross-sectional view showing the manufacturing process of the analog resistance change element of the embodiment. (Part 4)

[0048] Figure 11 It shows Figure 9 a cross-sectional TEM image of the enlarged oxide layer part shown

[0049] Figure 12 It is a chart for explaining an example of setting the resistivity of multiple oxide layers of the embodiment.

[0050] Figure 13 It is a chart for explaining an example of the composition analysis of the oxide layer of the embodiment.

[0051] Figure 14 It is a figure showing a cross-sectional TEM image when x is 2.5 in the oxide layer of the embodiment.

[0052] Symbol Explanation

[0053] 100 Analog resistance change element (RAND1+RAND2, RAND)

[0054] 101 RAND1

[0055] 102 RAND2

[0056] 201 Upper electrode (TE1, TE2)

[0057] 202 Lower electrode (BE1, BE2, BE)

[0058] 203 Oxide layer (MO, MO1, MO2)

[0059] 800 Si substrate

[0060] 801 ME

[0061] 805 Insulating film

[0062] 811, 812 TiN layer

[0063] R1, R2 Resistance components

[0064] Capacitor components C1 and C2 Detailed implementation mode

[0065] Figure 1 FIG. is an equivalent circuit diagram of an information processing apparatus showing an embodiment. The information processing apparatus of the embodiment includes the analog resistance change element 100 (RAND, memristor element) of the above-described brain-type information processing apparatus, and is, for example, a structure in which two RANDs (RAND1, RAND2) of the same structure are connected in series via a connection point ME.

[0066] In addition, it may be a form in which a resistance component and a capacitor component are connected in parallel to an analog resistance element, and a structure directly connecting a parallel circuit having a resistance component and a capacitor component. That is, a structure in which an analog resistance change element is connected in series with a parallel circuit can be adopted. The analog resistance change element is composed of a pair of electrodes and an oxide layer provided between the pair of electrodes, and the parallel circuit has a resistance component and a capacitor component. In addition, a structure in which an analog resistance change element having a capacitor component is used as a parallel circuit and a pair of analog resistance change elements are connected in series with each other can also be adopted.

[0067] In Figure 1 In the structural example of, RAND1 has a characteristic in which a resistance component R1 and a capacitor component C1 are connected in parallel. RAND2 also has a characteristic in which a resistance component R2 and a capacitor component C2 are connected in parallel.

[0068] The RAND (RAND1 + RAND2) 100 of the embodiment connects RAND1 (101) and RAND2 (102) of the same structure in series. The RAND 100 of this structure reduces the voltage applied to the RAND during the above-described low-resistance state (Set), and suppresses the sharp resistance change characteristic.

[0069] In Figure 1 In the RAND 100 of the structure of, although the voltage is distributed at a ratio of the resistance components R1 and R2 in a state where no resistance change occurs, during a period in which a resistance change occurs at high speed, the influence of the capacitor components C1 and C2 appears and the voltage is distributed according to the ratio of the capacitances. When the resistance change is slow, the ratio of the voltages applied to RAND1 and RAND2 is V1:V2 = R1:R2, and when the resistance change is fast, the ratio of the voltages applied to RAND1 and RAND2 is V1:V2 = 1 / C1:1 / C2, which will be described in detail later.

[0070] For example, RAND1 functions as an element whose resistance value changes by applying a voltage, and RAND2 functions as a capacitor.

[0071] Accordingly, although most of the normal voltage is applied to the elements in the high-resistance state, the voltage decreases during the rapid low-resistance transition, and a sharp resistance decrease can be suppressed. In addition, by suppressing such a sharp resistance decrease during the low-resistance transition, the resistance change characteristics during the low-resistance transition (Set) can be made symmetric with those during the high-resistance transition (Reset).

[0072] Figure 2 , Figure 3 FIGS. are diagrams respectively showing structural examples of the RANDs of the embodiments. RAND1 (101) and RAND2 (102) each have a structure in which an insulating oxide layer is sandwiched between electrodes.

[0073] In Figure 2 example, for example, the upper electrode (TE) 201 and the lower electrode (BE) 202 are each titanium nitride TiN, and the oxide layer (MO) 203 is TaOx (tantalum oxide).

[0074] The oxide layer (MO) 203 has one or more than two layers. In Figure 2 example, MO 203 is composed of two layers, MO1 (TaOx-L) 203-1 and MO2 (TaOx-H) 203-2. TaOx-L and TaOx-H are Ta oxide films with different resistivities, and the resistivity is TaOx-L < TaOx-H.

[0075] By forming the oxide layer (MO) 203 with layers of multiple resistivities, more desirable resistance change characteristics can be obtained. The element size of one RAND (one oxide layer MO 203 portion) is 100 nm.

[0076] The resistance change in one RAND, for example, RAND1 (101), is based on a current-induced redox reaction. The conductance of the RAND increases during the low-resistance transition (Set) and decreases during the high-resistance transition (Reset).

[0077] For example, if a positive voltage is applied to the lower electrode (BE) 202, oxygen ions move and oxidize within the oxide layer MO 203, thereby forming a high-resistance layer, and the conductance increases in the entire RAND (101).

[0078] In the embodiment, as Figure 2As shown, the lower electrodes (BE) 202 of two RAND1 (101) and RAND2 (102) are connected to each other by wiring or the like. Moreover, a voltage (Drive) is applied to the upper electrode (TE1) 201 of RAND1 (101), and the upper electrode (TE2) 201 of RAND2 (102) is grounded (GND). Hereinafter, the circuit system formed by directly connecting two RAND1 (101) and RAND2 (102) is referred to as RAND1+RAND2.

[0079] Such a circuit system of RAND1+RAND2 can also be adopted. Figure 3 The structure shown. Regarding Figure 3 the structural example, it is a structure formed by laminating RAND1 (101) on top of RAND2 (102) shown in Figure 2 . In Figure 3 the structure, a single electrode is shared for Figure 2 the lower electrode (BE1) 202 of RAND1 (101) and the lower electrode (BE2) 202 of RAND2 (102) shown.

[0080] If the stacked structure shown in Figure 2 is described using the symbols described in Figure 3 , then from the bottom layer upwards, there are stacked in sequence the upper electrode (TE2) 201 of RAND2 (102), the oxide layer (MO) 203 (MO1 (203-1), MO2 (203-2)), the lower electrode (BE2) of RAND2 (102) (equivalent to the lower electrode (BE1) 202 of RAND1 (101)), the oxide layer (MO) 203 of RAND1 (101) (MO2 (203-2), MO1 (203-1)), and the upper electrode (TE1) 201 of RAND1 (101).

[0081] According to Figure 2 the structure, using the existing RAND configuration structure, RAND1+RAND2 can be formed simply by connecting the lower electrodes BE1 (202) and BE2 (202) of RAND1 and RAND2 to each other using a wiring material and / or a wiring pattern. In addition, according to Figure 3 the structure, the structure of RAND1+RAND2 (100) can be formed in the space of one RAND, and it can be arranged in approximately half the space compared to Figure 2 .

[0082] (I-V characteristics)

[0083] Next, regarding the simulated resistive change element 100 (RAND1+RAND2) of the embodiment, various electrical characteristic evaluation results using a semiconductor parameter analyzer will be described.

[0084] Figure 4 This is a diagram illustrating the I-V characteristics of RAND1+RAND2 in the embodiment. Figure 4 In (b), the I-V characteristics of RAND1+RAND2 in the embodiment are shown. Figure 4 In (a), the I-V characteristics of a single RAND (RAND1) are shown for comparison. The horizontal axis of the diagram is voltage V, and the vertical axis is current I.

[0085] As Figure 4 shown in (a), in the case of a single RAND1, for example, by using TiN for the electrodes TE and BE, it is possible to suppress a sharp increase in resistance during the Reset process shown by the dashed line in the figure. However, a sharp increase in resistance occurs during the Set process shown by the solid line in the figure (the portion marked 400x). Figure 4 In the example of (a), a sharp increase in resistance occurs sharply in the vertical direction in the figure near +1V. To suppress this sharp increase in resistance, it is necessary to use a current limit CC (Current Compliance) to control the resistance value. Conventionally, for example, as described above, a detector and / or a transistor are used separately for CC.

[0086] In contrast, in the case of RAND1+RAND2 as in the embodiment, as Figure 4 shown in (b), the resistance change during the Set process becomes slow, and by adjusting the applied voltage range, it is possible to achieve low resistance without using CC.

[0087] Figure 5 This is a diagram showing the I-V characteristics of RAND1+RAND2 in the embodiment during repeated measurements. The states of Set and Reset for 100 cycles each for RAND1+RAND2 are shown. Although there are deviations in the characteristics in the voltage V direction during the Reset process and the Set process shown in (b), Figure 4 during the repeated driving shown in Figure 5 it shows characteristics similar to the hysteresis characteristics of Set and Reset shown in (b) of Figure 4 . That is, during repeated driving, the state where the resistance change during the Set process becomes slow is also shown, similar to (b) of Figure 4 .

[0088] Figure 6 This is a diagram illustrating the I-V characteristics of RAND1+RAND2 in the embodiment. Figure 6In (a), the I-V characteristics are shown for comparison when a load resistor R3 (3 kΩ) on the wiring structure is connected in series to one RAND (RAND1) monomer. Figure 6 In (b), the I-V characteristics of RAND1+RAND2 of the embodiment are shown, and the resistance component R2 is 1 kΩ. In Figure 6 In (a) and (b) above, similarly to the above, the Reset process is represented by a dashed line and the Set process is represented by a solid line.

[0089] As Figure 6 shown in (a), it can be seen that when the resistor body connected in series to one RAND1 is the load resistor R3 on the wiring structure, the sharp increase in resistance during the Set process cannot be suppressed. In contrast, as Figure 6 shown in (b), it can be seen that by connecting the resistor of the capacitor structure of the RAND2 part to RAND1, the sharp increase in resistance during the Set process can be suppressed.

[0090] Figure 7 is a diagram for explaining the I-V characteristics when the applied voltage of RAND1+RAND2 of the embodiment is changed. Figure 7 In (a), the I-V characteristics are shown for RAND1+RAND2 when the maximum value of the applied voltage is changed in 50 mV steps. Both the Set process (solid line) and the Reset process (dashed line) show the state of resistance change simulated according to the voltage application conditions. Here, especially during the Set process, although multiple characteristic lines are shown corresponding to the change in the maximum value of the applied voltage, the sharp increase in resistance is suppressed in any of the characteristic lines.

[0091] Next, Figure 7 In (b), the I-V characteristics are shown when Set (Set1 to Set3) is performed three times with the maximum value of the applied voltage set to +1.5 V, +1.7 V, and +1.8 V. Figure 7 In (c), it shows Figure 7 the resistance change of each element of RAND1 and RAND2 during the three Sets in (b). As Figure 7 shown in (b), during the Set process (solid line), three characteristic lines (Set-1, Set-2, Set-3) are shown corresponding to the change in the maximum value of the applied voltage, but the decrease in resistance is slow with respect to the voltage in any of the characteristic lines, and the simulation characteristics are improved. In addition, it is shown that the characteristics of the Set process are symmetric with respect to 0 V compared to the characteristics of the Reset process.

[0092] In addition, if we observe Figure 7Regarding the change in the resistance value of each of RAND1 and RAND2 shown in (c), the change in the resistance value occurs only in RAND1, and the resistance value of RAND2 does not change. Therefore, it is speculated that the simulated characteristics during the observed low-resistance process (Set process) are not characteristics caused by competitive resistance value changes due to connecting RAND1 and RAND2 in reverse (equivalent to Figure 2 , Figure 3 ). In addition, when a load resistor with the same resistance value as RAND2 is connected to a single RAND, the low-resistance state becomes abrupt. Based on these results, it gives an indication that there are other factors contributing to the simulated characteristics besides the resistance value of the element.

[0093] Using Figure 1 's equivalent circuit, the resistance change of the RAND1 + RAND2 structure of such an embodiment is explained. For example, during the low-resistance process (Set process), a pulse with a width of +1.5V and 200 nsec is continuously supplied to RAND1 + RAND2, and during the high-resistance process (Reset process), a pulse with a width of -1.5V and 200 nsec is continuously supplied to RAND1 + RAND2.

[0094] Since the Set process is fast, considering the case of alternating current with ω > 0, it becomes I = V / Z, V TE1 -V ME = I×Z1, V ME -V TE2 = I×Z 2 . Z is the impedance of RAND1 and RAND2, and it becomes Z1 = 1 / ((1 / R 1 ) + jωC 1 ), Z 2 = 1 / ((1 / R 2 ) + jωC 2 )(jω is the differential operator). Thus, the voltage ratio of the two RAND1 and RAND2 is (V TE1 -V ME ) / (V ME -V TE2 ) = Z 1 / Z 2 = (1 / ((1 / R 1 ) + jωC 1 ))) / (1 / ((1 / R 2 ) + jωC 2 )) = ((1 / R 2 + jωC 2 )) / ((1 / R 1 ) + jωC 1 ).

[0095] When RAND1 is in the HRS (High Resistance State) and RAND2 is in the LRS (Low Resistance State), before the start of Set, ω = 0 and R 1 >>R 2 . At this time, it becomes V TE1 -V ME =>>V ME -V TE2 , and a voltage is applied to RAND1 in the HRS.

[0096] If Set starts, it approaches the case of ω → ∞. If the structures of RAND1 and RAND2 are the same and C 1 =C 2 , then during the Set process, it becomes V TE1 -V ME =V ME -V TE2 , and the voltage applied to RAND1 during Set decreases, suppressing a sharp resistance change. During high-speed response, in order to reduce (V TE1 -V ME ) / (V ME -V TE2 ), it is necessary to reduce C 2 / C 1 , so if C 2 is made less than C 1 , the voltage assigned to RAND1 decreases.

[0097] As described above, in DC operation (slow resistance change), since V TE 1-V ME : V ME -V TE2 =R 1 : R 2 , so if R 1 >R 2 , then V TE1 -V ME >V ME -V TE2 . Additionally, in high-speed operation (fast resistance change), since V TE1 -V ME : V ME -V TE2 = (1 / C 1 ): (1 / C 2 ), so if R 1 >R 2 and C 1 =C 2 , then V TE1-V ME =V ME -V TE2 Thus, although most of the normal voltage is allocated to the elements in the high-resistance state, the voltage decreases during low-resistance conversion at high speed, and a sharp decrease in resistance can be suppressed.

[0098] (Example)

[0099] Next, a structural example of the analog resistance change element will be described using Figures 8 to 1 0. Figure 8 is a top view of RAND1+RAND2 of the embodiment, Figure 9 is a cross-sectional view taken along the line connecting points A to J of Figure 8 . These Figure 8 , Figure 9 correspond to Figure 2 a specific structural example of the schematic diagram.

[0100] In the top view of Figure 8 , for the analog resistance change element 100, RAND1 (101) and RAND2 (102) are arranged adjacent to each other on the Si substrate 800. A Drive voltage is applied to TE1 (201) of RAND1 (101).

[0101] An oxide layer (MO) 203 is provided between TE1 (201) and BE1 (202) of RAND1 (101). The MO 203 of RAND1 (101) is located at Figure 8 the position between point B and point C of

[0102] An oxide layer (MO) 203 is provided between BE2 (202) and TE2 (201) of RAND2 (102). The MO203 of RAND2 (102) is located at Figure 8 the position between point H and point I of

[0103] In Figure 9 the cross-sectional view, when the layer structure of RAND1 (101) is described, BE1 (202) of RAND1 (101) is provided on the Si substrate 800. On this BE1 (202), Figure 2 two layers of MO1 (TaOx-L) 203-1 and MO2 (TaOx-H) 203-2 with different resistivities shown in 2)insulating films 805 such as this cover TE1, BE1, and MO.

[0104] Figure 9 The two-layer MOs 203-1 and 203-2 shown have a recess at point C and are joined to BE1 (202). For example, the recess (in the direction from point B to point C) is 100 nm. Additionally, TE1 (201) has a TiN layer 811 that forms a layer on MO203-1 between points B and C, and a TiN layer 812 that forms a layer between points B and A and is connected to TE1 (201). TiN layer 812 has a recess at point B and is connected to TiN layer 811.

[0105] In addition, BE1 (202) is led out to the front position at point D through a substantially V-shaped TiN layer 813 and is connected to ME (801) at point E.

[0106] The layer stacking structure on the RAND2 (102) side is configured symmetrically with respect to RAND1 (101) with ME (801) as the center.

[0107] Thus, as Figure 9 shown, two RAND1s (101) and RAND2s (102) form a circuit system from point A to point J. It should be noted that one existing RAND is equivalent to RAND1, and the RAND1 + RAND2 (100) of the embodiment can be simply manufactured by arranging ME801 between the existing RANDs disposed on the Si substrate 800 and connecting them.

[0108] (Manufacturing method of analog resistive change element)

[0109] Figures 10A to 10D is a cross-sectional view showing the manufacturing process of the analog resistive change element of the embodiment. In these figures, although the RAND1 (101) part of the left half is shown for ease of understanding, the right half of RAND2 (102) can be formed simultaneously with RAND1 (101) in a symmetric shape. Figure 9 First, as shown in (a) of

[0110] First, as Figure 10A shown, a TiN film is formed as the lower electrode (BE1) 202 on the silicon substrate 800 with a thermal oxide film. The TiN film can be formed, for example, using a Ti target and by means of Ar / N 2It is formed by reactive sputtering of a gas. In addition, it can also be formed by sputtering using a TiN ceramic target, chemical vapor deposition (CVD: Chemical Vapor Deposition), or atomic layer deposition (ALD: atomic layer deposition). The lower electrode (BE1) 202 is not limited to TiN, and TaN, W, Pt, Ir can also be used.

[0111] Next, as shown in Figure 10A (b) of, the lower electrode (BE1) 202 is patterned by photolithography and reactive ion etching. Next, as shown in Figure 10A (c) of, for example, by CVD and using an insulating film 805a of SiO 2 to cover the entire front surface of the pattern including the lower electrode (BE1) 202.

[0112] Next, as shown in (d) of 10B, on the insulating film (SiO 2 ) 805a on the lower electrode (BE1) 202, a hole structure 1000 that becomes an element is formed. The hole structure 1000 can be formed by photolithography and etching of the insulating film 805a.

[0113] Next, as shown in Figure 10B (e) of, two layers of MO1 (203-1) and MO2 (203-2) with different resistivities are formed as an oxide layer (MO) 203 on the insulating film 805a on which the hole structure 1000 is formed, and an upper electrode layer 811 that becomes a part of the upper electrode (TE1) is formed thereon.

[0114] Next, as shown in Figure 10B (f) of, the oxide layer (MO) 203 and the upper electrode layer 811 are patterned by photolithography and reactive ion etching.

[0115] Next, as shown in Figure 10C (g) of, an insulating film 805b of SiO 2 is used to cover the entire front surface of the oxide layer (MO) 203 and the upper electrode layer 811.

[0116] Next, as shown in Figure 10C (h) of, the insulating film 805b is etched so that it has a depth reaching the upper electrode layer 811 at a part (site A) of the upper electrode layer 811 and a depth reaching the lower electrode (BE1) 202 at a part (site B) of the lower electrode (BE1) 202 with respect to the insulating film 805b. After that, an upper electrode layer (for example, TiN) 1010 is formed.

[0117] Next, as shown inFigure 10C As shown in (i) of FIG. 1, the wiring layer of the upper electrode layer 1010 is patterned by photolithography and reactive ion etching. As a result, the upper electrode layer 1010 is divided. On the A side, a TiN layer 812 that becomes part of the upper electrode (TE1) is formed, and on the B side, a TiN layer 813 that becomes part of the connection point (ME) 801 is formed.

[0118] Next, as Figure 10D shown in (j) of FIG. 1, the entire front surface including the TiN layers 812 and 813 is covered with an insulating film 805c of SiO 2 .

[0119] Next, as Figure 10D shown in (k) of FIG. 1, a contact electrode that becomes part of the upper electrode (TE1) is formed in contact with the TiN layer 812 portion, and a contact electrode that becomes part of the ME (801) is formed in contact with the TiN layer 813 portion. These contact electrodes 201 and 801 (ME) can be formed of a mixture of Au and Ti, or Al, etc.

[0120] Through the above processes, one side of the RAND1 (101) can be formed. As Figure 9 shown in FIG. 1, the RAND2 (102) is symmetrically arranged with respect to the RAND1 (101) with the ME (801) portion as the center. In the above respective processes, the RAND1 (101) and the RAND2 (102) can be formed simultaneously on the Si substrate 800. The formed RAND1 (101) and RAND2 (102) have a structure in which the lower electrodes BE1 and BE2 (202) are connected to each other at the ME (801) portion.

[0121] Figure 11 FIG. 1 is a diagram showing a cross-sectional TEM image obtained by magnifying a portion of the oxide layer shown in Figure 9 FIG. 1. The image shows a captured image of a transmission electron microscope TEM (Transmission Electron Microscope), and is a magnified state of the oxide layer (203) at points C and H in Figure 8 , Figure 9 FIG. 1. Two layers of MO1 (TaOx-L) 203-1 and MO2 (TaOx-H) 203-2 are stacked as the oxide layer (MO) 203 on the TiN layer corresponding to BE1 and BE2 (202).

[0122] The oxide layer (MO) 203 can be appropriately selected to obtain a desired resistance value, for example, 20 nm to 40 nm. A TiN layer corresponding to TE1 and TE2 (201) is stacked on the MO 203, and an insulating film 805 (SiO 2), and a carbon film (C film) for protection.

[0123] (Resistivity of the oxide layer MO)

[0124] When the analog resistance change element 100 is joined and formed with the lower electrode BE (202) in the above-described hole structure 1000, for the oxide layer (MO) 203, the resistivity of the Ta oxide film on the lower electrode (BE) 202 side is set to be large.

[0125] On the other hand, in the structure of the oxide layer (MO) 203 that does not have the hole structure 1000, for example Figure 2 , Figure 3 In the structure described, the oxide layer (MO) 203 has the same area at the interface between the upper electrode TE (201) and the lower electrode (BE) 202.

[0126] Figure 12 It is a graph for explaining a setting example of the resistivity of a plurality of oxide layers in the embodiment. The horizontal axis represents SCCM, the vertical axis represents the resistivity of each layer of TaOx, and a measurement example when the RF power is set to 100 W is shown. Figure 14 The oxide layer (TaOx-L) with a low resistivity in Figure 12 is set to x < 2 according to Figure 2 , Figure 3 In the structure of the oxide layer (MO) 203 that does not have the hole structure 1000 described in Figure 14 According to the description of

[0127] Figure 13 It is a graph for explaining an example of the composition analysis of the oxide layer in the embodiment. Figure 13 In (a) of Figure 13 The horizontal axis represents SCCM (Standard Cubic Centimeters per Minute: standard cubic centimeters per minute), and the vertical axis represents the tantalum (Ta) concentration and the oxygen O (Oxygen) concentration.

[0128] According to Figure 13In the compositional analysis shown, the higher the resistivity of the oxide layer (MO) 203, the greater the tendency for x of TaOx to become larger, and the film thickness can be made thinner. For example, for the oxide layer (TaOx-L) with a high resistivity among MO1 (203-1) and MO2 (203-2), the film thickness can be set to 20 to 40 nm when x of TaOx is 2 or more and 2.2 or less, and when x of TaOx exceeds 2.2, the film thickness can be set to 3 to 10 nm. On the other hand, x of TaOx of the oxide layer (TaOx-H) with a high resistivity is less than 2.

[0129] Figure 14 FIG. shows a cross-sectional TEM image when x of the oxide layer in the embodiment is 2.5. Thus, even when x of TaOx exceeds 2.2, if the oxide layer MO1 = Ta 2 O 5 (x = 2.5) and the oxide layer MO2 = TaOx (x < 2), the resistivity also satisfies MO1 > MO2.

[0130] After deposition based on the above reactive sputtering, the oxide layer (MO) 203 is exposed to an oxygen atmosphere. For example, the Si substrate 800 is exposed to the atmosphere for a predetermined time or more. In addition to this, an annealing process of heating the substrate to 100 to 300 °C can also be performed in a state assisted by radicals generated by applying RF power to argon containing oxygen. In addition, for the oxide layer (MO) 203, as long as x is set to be greater than 2 on the side with more oxygen among MO1 (203-1) and MO2 (203-2).

[0131] In the above structural example, the pair of electrodes TE (201) and BE (202) are made of TiN, and the oxide layer (MO) 203 is made of TaOx, but it is not limited thereto. For example, the electrodes TE and BE can be appropriately selected from metals such as Pt, Au, Cu, TiAlN, TaN, W, Ir, and Ru. Regarding the oxide layer MO, in addition to TiOx, dielectrics such as HfOx, AlOx, SiOx, WOx, and ZrOx and their compounds, or oxides and / or oxynitrides of the electrodes can also be selected.

[0132] As described above, according to the present embodiment, it is characterized in that it has: an analog resistance change element composed of a pair of electrodes and an oxide layer provided between the pair of electrodes; and a parallel circuit having a resistance component and a capacitance component, and the parallel circuit is connected in series to the analog resistance change element. Thus, in the Set process (low-resistance process), by distributing the voltage according to the ratio of the capacitance, the voltage is reduced, and a sharp decrease in resistance can be suppressed.

[0133] In addition, it is set to have the following characteristics: as the parallel circuit, an analog resistance change element having a capacitance component is used, and by connecting a pair of the analog resistance change elements in series with each other, the analog resistance change element is used as an element whose resistance value can be freely changed. Thus, it is possible to simply manufacture using an existing analog resistance change element, and it is possible to obtain desired resistance change characteristics. It should be noted that the capacitance of the resistance change element having a capacitance component may be a fixed capacitance or may adopt an electrically variable structure.

[0134] In addition, the following structure may also be adopted: the electrode is composed of an upper electrode and a lower electrode, and an analog resistance change element in the form of a parallel connection of a resistance component and a capacitance component is formed by the upper electrode, the lower electrode, and an oxide layer provided between the upper electrode and the lower electrode. The lower electrodes of the two analog resistance change elements are connected to each other, and by applying a voltage to the circuit system from the upper electrode of one analog resistance change element to the upper electrode of the other analog resistance change element, the resistance value can be changed. Thus, an arbitrary resistance value can be obtained for each set of analog resistance change elements among a plurality of memristors on the substrate.

[0135] In addition, the following structure may also be adopted: as the oxide layer, a plurality of layers having different resistivities are laminated. In addition, it can be set that the resistivity of one of the plurality of oxide layers is less than 1000 mOhm cm, and the resistivity of the other is 1000 mOhm cm or more. By providing a plurality of oxide layers having different resistivities, desired resistance change characteristics can be obtained.

[0136] In addition, it can be configured such that adjacent pairs of lower electrodes among a plurality of analog resistance change elements provided at different planar positions on the substrate are connected to each other. For example, in a structure of existing memristors in which a plurality of RANDs are arranged adjacent to each other on the substrate, as shown in RAND1 + RAND2, adjacent pairs of RANDs can be connected in series. Any RAND among the plurality of RANDs constituting the memristor on the substrate can be used as a memristor element (analog resistance change element) having the structure of RAND1 + RAND2 described in the embodiment, and an arbitrary resistance value can be obtained for each set of RAND1 + RAND2.

[0137] In addition, the following structure may also be adopted: at one planar position on the substrate, as the analog resistance change element, a lower electrode, the oxide layer, an intermediate electrode, the oxide layer, and an upper electrode are laminated in this order from the lower layer. Thus, a set of structures composed of a pair of analog resistance change elements can be arranged at one planar position on the substrate, and the analog resistance change elements can be arranged on the substrate with high efficiency.

[0138] Therefore, according to this embodiment, it is possible to suppress a sharp resistance decrease during low-resistance formation, and thus, in the Set process, it is possible to easily obtain an arbitrary resistance value. In addition, it can be configured such that for an analog resistance element in a form where a resistance component and a capacitance component are connected in parallel, a parallel circuit having a resistance component and a capacitance component is directly connected, or another analog resistance element is directly connected. Therefore, in either structure, the structure is simple and can be easily manufactured. In particular, in a structure where two resistance variable elements are connected in series, it can be simply manufactured using existing resistance variable elements.

[0139] In addition, according to this embodiment, the analog resistance element has a structure in which an oxide layer is sandwiched between a pair of electrodes, and when observed in the stacking direction, it has a simple structure formed by simply stacking the respective layers. As a result, the height can be reduced, the entire element can be miniaturized (miniaturized), and furthermore, three-dimensional structuring of the element can be easily performed. Three-dimensional structuring is, for example, a structure formed by stacking and structuring the Figure 2 structure as Figure 3 shown. According to the embodiment, the structure of each analog resistance element can be miniaturized, so that even in the case of three-dimensional structuring, the size of the entire element can be suppressed to be small.

[0140] Moreover, by suppressing a sharp resistance change during the low-resistance formation process of the analog resistance variable element used in the brain-type information processing device, a smooth resistance change is achieved by removing noise based on the resistance change component, and high-speed operation and low power consumption of the product-sum circuit can be realized. Furthermore, by suppressing the sharp resistance change during the low-resistance formation process, the resistance change characteristics during the low-resistance formation process can be made symmetric with the resistance change characteristics during the high-resistance formation process. By using the analog resistance variable element for the product-sum circuit (artificial intelligence, deep learning or inference, machine learning, etc.) of the brain-type information processing device, the symmetry between the storage operation and the forgetting operation of the product-sum circuit can be improved.

[0141] Industrial Applicability

[0142] The present invention can use the structure of an existing memristor as a memcapacitor element and is useful by applying it to the technology related to brain-type information processing devices.

Claims

1. An information processing device, characterized in that, it has: a resistive random access memory (RRAM) cell, which is composed of a pair of electrodes and an oxide layer disposed between the pair of electrodes; a parallel circuit, which is a resistive random access memory (RRAM) cell having a capacitive component, by connecting the pair of resistive random access memory (RRAM) cells in series with each other, the resistive random access memory (RRAM) cell is used as a component capable of freely changing its resistance value, as the oxide layer, it is formed by laminating a plurality of layers having different resistivities.

2. The information processing device according to claim 1, characterized in that, the electrode is composed of an upper electrode and a lower electrode, one resistive random access memory (RRAM) cell in which a resistance component and a capacitive component are connected in parallel is formed by the upper electrode, the lower electrode, and the oxide layer disposed between the upper electrode and the lower electrode, the lower electrodes of the two resistive random access memory (RRAM) cells are connected to each other, and by applying a voltage to the circuit system from the upper electrode of one resistive random access memory (RRAM) cell to the upper electrode of the other resistive random access memory (RRAM) cell, the resistance value can be changed.

3. The information processing device according to claim 1, characterized in that, the resistivity of one of the plurality of oxide layers is less than 1000 mΩ·cm, and the resistivity of the other is 1000 mΩ·cm or more.

4. The information processing device according to any one of claims 1 to 3, characterized in that, adjacent pairs of the lower electrodes among the plurality of resistive random access memory (RRAM) cells disposed at different planar positions on the substrate are connected to each other.

5. The information processing device according to any one of claims 1 to 3, characterized in that, at one planar position on the substrate, as the resistive random access memory (RRAM) cell, the lower electrode, the oxide layer, the intermediate electrode, the oxide layer, and the upper electrode are laminated in sequence from the lower layer.

6. A driving method for an information processing device, characterized in that, in an information processing device having a resistive random access memory (RRAM) cell composed of a pair of electrodes and an oxide layer disposed between the pair of electrodes, a parallel circuit, which is a resistive random access memory (RRAM) cell having a capacitive component, is connected in series with the resistive random access memory (RRAM) cell, by connecting the pair of resistive random access memory (RRAM) cells in series with each other, the resistive random access memory (RRAM) cell is used as a component capable of freely changing its resistance value, as the oxide layer, it is formed by laminating a plurality of layers having different resistivities.

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