A high frequency signal processing circuit and method for position sensitive detector

Abstract

The present invention discloses a high-frequency signal processing circuit and method for a position sensitive detector, which belongs to the technical field of weak signal conversion and detection; a weak high-frequency optical signal is converted into a weak high-frequency current signal through a PSD working circuit, the current signal is converted into a voltage signal through a transimpedance amplifier circuit, the voltage signal is amplified again through the secondary amplifier circuit, and finally the position change of the optical signal on the x-axis and y-axis of the PSD is obtained through the addition and subtraction circuit. The present invention has the advantages of simple circuit structure and little interference of the output result by the amplification accuracy of the operational amplifier and ground noise. Through experimental testing, the output signal stability of the present invention is good, and the circuit processing result also has high accuracy.

Description

Technical Field

[0001] The invention belongs to the technical field of weak signal conversion and detection, and in particular relates to a high-frequency signal processing circuit and method for a position sensitive detector. Background Art

[0002] MEMS (micro-electromechanical systems) technology is another technology field that has a significant impact on science, technology and social development after microelectronics. It has the advantages of intelligence, miniaturization, integration, low cost and high efficiency. MEMS sensors and actuators have important application value in biomedicine, environment, industry, chemistry and other fields. MEMS micromachining technology reduces the size of traditional mechanical sensors to micrometers or even sub-micrometers. Among various microstructure sensors, microcantilever sensors are the most widely used. Compared with traditional sensors, microcantilever sensors are smaller in size, more sensitive and efficient, and more robust, fast in response and easy to use.

[0003] Resonant microcantilever beams occupy an important position in the field of sensing, so it is necessary to study the vibration characteristics of microcantilever beams and read out the change in the vibration frequency of microcantilever beams. Due to the small size and easy damage of microcantilever beams, the traditional contact vibration measurement method cannot be used. A commonly used non-contact vibration detection method for microcantilever beams is the optical detection method. The optical method includes optical interference method and optical lever method. The optical lever method is also called the beam deflection method. It directly irradiates the surface of the microcantilever beam with laser, and uses a photodetector to receive the reflected light of the microcantilever beam to sense the vibration information of the microcantilever beam. This method has a simple structure, is easy to use, and has a resolution comparable to that of the interference method. Since it was proposed by Meyer in 1988, it has made great progress and is widely used in the measurement of dynamic or static working modes of microcantilever beams.

[0004] Position sensitive detector (PSD) is a photoelectric sensor that can directly convert the light spot position signal acting on the photosensitive surface into an electrical signal representing continuous position change. It has the characteristics of high sensitivity, high resolution, fast response speed, etc. With the development of non-contact detection technology, PSD has been more and more widely used in automation control, laser positioning, instrumentation, etc. in recent years.

[0005] The test of micro-cantilever sensors requires the collection of vibration signals of different modes, but the current PSD signal processing circuit cannot effectively detect high-frequency signals, and this high-frequency current signal is very weak and is often submerged in the circuit noise. Summary of the invention

[0006] In view of the deficiencies in the prior art, the present invention designs a high-frequency signal processing circuit and method for a position sensitive detector.

[0007] A high-frequency signal processing circuit for a position sensitive detector (PSD), comprising: a PSD working circuit, a transimpedance amplifier circuit, a secondary voltage amplifier circuit and an addition and subtraction circuit; the addition and subtraction circuit comprises an addition circuit and a subtraction circuit;

[0008] Among them, the PSD working circuit, the transimpedance amplifier circuit, the secondary voltage amplifier circuit and the addition and subtraction circuit are connected in sequence;

[0009] The PSD working circuit includes a position sensitive detector PSD and a 5V reference voltage source circuit. The function of the 5V reference voltage source circuit is to provide a 5V working power supply to the position sensitive detector. The 5V reference voltage source circuit includes a first capacitor C5, a second capacitor C6 and an operational amplifier U1; the input end of the amplifier U1 is connected to a power supply VDD, the first capacitor C5 is connected to the power supply VDD and the ground GND, the second capacitor C6 is connected to the output end of the operational amplifier U1 and the ground GND, and the power supply end of the sensitive detector PSD is connected to the output end of the operational amplifier U1; wherein the power supply VDD is a common power supply for the entire signal processing circuit, and the ground GND is also common to the entire signal processing circuit;

[0010] The transimpedance amplifier circuit includes a transimpedance amplifier U3, a first resistor RL1, a second resistor RL2, a third resistor RL3, a fourth resistor RL4, a third capacitor CL2, a fourth capacitor CL3, a fifth capacitor CL6, a sixth capacitor CL7, a seventh capacitor CL5, an eighth capacitor C3, a ninth capacitor CL9, and a tenth capacitor C1; the four inverting input terminals INA-, INB-, INC-, and IND- of the transimpedance amplifier U3 are respectively connected to the current output terminals I1, I2, I3, and I4 of the position sensitive detector PSD. The inverting input terminal INA- of the transimpedance amplifier U3 is connected to the output terminal OUTA of the transimpedance amplifier U3 through the first resistor RL1 and the third capacitor CL2, and the INB-, INC-, and IND- of the transimpedance amplifier U3 are also connected to the output terminals OUTB, OUTC, and OUTD of the transimpedance amplifier U3 through the above method; the seventh capacitor CL5 and the eighth capacitor C3 are respectively connected to the ground GND, the power supply VDD, and the power supply terminal V+ of the transimpedance amplifier, and the ninth capacitor CL9 and the tenth capacitor C1 are respectively connected to the ground GND, the power supply VSS, and the power supply terminal V- of the transimpedance amplifier; the power supply VSS is shared by the entire circuit;

[0011] The secondary voltage amplifier circuit includes a voltage amplifier U2, a fifth resistor R2, a sixth resistor R3, a seventh resistor R6, an eighth resistor R8, a ninth resistor R4, a tenth resistor R1, an eleventh resistor R7, a twelfth resistor R5, an eleventh capacitor CL1, a twelfth capacitor CL4, a thirteenth capacitor CL12, a fourteenth capacitor CL13, a fifteenth capacitor CL14, and a sixteenth capacitor CL15; the voltage amplifier U2 can meet the requirements of converting and amplifying four current signals at the same time, and can be divided into four amplifiers U2A, U2B, U2C, and U2D with the same functions, the inverting input terminal INA- of the voltage amplifier U2A is connected to the output terminal OUTA of the transimpedance amplifier U3 in the transimpedance amplifier circuit through the fifth resistor R2, the inverting input terminal INA- of U2A is connected to the output terminal OUTA of U2A through the sixth resistor R3 and the thirteenth capacitor CL12, and the positive input terminal INA+ of the voltage amplifier U2A is connected to the ground GND. The eleventh capacitor CL1 and the twelfth capacitor CL4 are energy storage capacitors of the circuit. The reverse input terminal INB- of the voltage amplifier U2B is connected to the output terminal OUTB of the transimpedance amplifier U3 through the seventh resistor R6. The reverse input terminal INB- of the voltage amplifier U2B is connected to the output terminal OUTB of U2B through the eighth resistor R8 and the fourteenth capacitor CL13. The positive input terminal INB+ of the voltage amplifier U2B is connected to the ground GND. The reverse input terminal INC- of the voltage amplifier U2C is connected to the output terminal OUTD of the transimpedance amplifier U3 through the ninth resistor R4. The reverse input terminal INC- of the voltage amplifier U2C is connected to the output terminal OUTC of U2C through the tenth resistor R1 and the fifteenth capacitor CL14. The positive input terminal INC+ of the voltage amplifier U2C is connected to the ground GND. The reverse input terminal IND- of the voltage amplifier U2D is connected to the output terminal OUTC of the transimpedance amplifier U3 through the eleventh resistor R7, the inverting input terminal IND- of the voltage amplifier U2D is connected to the output terminal OUTD of U2D through the twelfth resistor R5 and the sixteenth capacitor CL15, and the positive input terminal IND+ of the voltage amplifier U2D is connected to the ground GND.

[0012] The subtraction circuit is used to realize the position conversion formula (I2+I3)-(I1+I4) and (I2+I4)-(I1+I3), including an operational amplifier U4, a thirteenth resistor R14, a fourteenth resistor R18, a fifteenth resistor R22, a sixteenth resistor R27, a seventeenth resistor R23, an eighteenth resistor R11, a seventeenth capacitor CL16, a nineteenth capacitor CL10, a twentieth capacitor CL11, a nineteenth resistor R15, a twentieth resistor R19, a twenty-first resistor R21, a twenty-second resistor R28, a twenty-third resistor R26, a twenty-fourth resistor R12, and a twenty-first capacitor CL17. The voltage amplifier U4 is a four-way operational amplifier, which can be divided into U4A, U4B, U4C, and U4D, and includes four inverting input terminals: INA-, INB-, INC-, and IND-, four non-inverting input terminals: INA+, INB+, INC+, and IND+, and four output terminals OUTA, OUTB, OUTC, and OUTD. The implementation of (I2+I3)-(I1+I4) includes operational amplifier U4A, thirteenth resistor R14, fourteenth resistor R18, fifteenth resistor R22, sixteenth resistor R27, seventeenth resistor R23, eighteenth resistor R11, seventeenth capacitor CL16, nineteenth capacitor CL10, twentieth capacitor CL11; the nineteenth capacitor CL10 and the twentieth capacitor CL11 are energy storage capacitors of the circuit to prevent the noise carried by the power supply from interfering with the circuit. The inverting input terminal of U4A is connected to the output terminals OUTA and OUTC of the voltage amplifier U2 through the thirteenth resistor R18 and the fourteenth resistor R14, respectively. The non-inverting input terminal of U4A is connected to the output terminals OUTD and OUTB of the voltage amplifier U2 through the fifteenth resistor R22 and the sixteenth resistor R27, respectively. The inverting input terminal of U4A is connected to the output terminal through the eighteenth resistor R11 and the seventeenth capacitor CL16, and the seventeenth resistor R23 is connected to the non-inverting input terminal of U4A and the ground respectively; the implementation of (I2+I4)-(I1+I3) includes an operational amplifier U4B, a nineteenth resistor R15, a twentieth resistor R19, a twenty-first resistor R21, a twenty-second resistor R28, a twenty-third resistor R26, a twenty-fourth resistor R12, and a twenty-first capacitor CL17, wherein the inverting input terminal of U4B is connected to the output terminals OUTA and OUTB of the voltage amplifier U2 through the nineteenth resistor R15 and the twentieth resistor R19, respectively, the non-inverting input terminal of U4B is connected to the output terminals OUTD and OUTC of the voltage amplifier U2 through the twenty-first resistor R21 and the twenty-second resistor R28, the inverting input terminal of U4B is connected to the output terminal through the twenty-fourth resistor R12 and the twenty-first capacitor CL17, and the twenty-third resistor R26 is connected to the non-inverting input terminal of U4B and ground, respectively;

[0013] The adding circuit is used to realize the position conversion formula I1+I2+I3+I4, including an operational amplifier U4C, an operational amplifier U4D, a twenty-fifth resistor R13, a twenty-sixth resistor R16, a twenty-seventh resistor R20, a twenty-eighth resistor R24, a twenty-ninth resistor R30, a thirtieth resistor R9, a thirty-first resistor R32, a thirty-second resistor R29, a thirty-third resistor R31, a twenty-second capacitor CL18, and a twenty-third capacitor CL19, wherein the inverting input terminal of U4C is respectively connected through the twenty-fifth resistor R13, the twenty-sixth resistor R16, the twenty-seventh resistor R20, the twenty-eighth resistor R24, the twenty-ninth resistor R30, the thirtieth resistor R9, the thirty-first resistor R32, the thirty-second resistor R29, the thirty-third resistor R31, the twenty-second capacitor CL18, and the twenty-third capacitor CL19. Resistor R16, the twenty-seventh resistor R20, and the twenty-eighth resistor R24 ​​are connected to OUTA, OUTD, OUTB, and OUTC of U2, and the inverting input terminal of U4C is connected to the output terminal through the 30th resistor R9 and the 22nd capacitor CL18; the inverting output terminal of U4D is connected to the output terminal of U4C through the thirty-first resistor R32, and is connected to the output terminal of U4D through the thirty-third resistor R31 and the twenty-third capacitor CL19; the twenty-ninth resistor R30 and the thirty-second resistor R29 are respectively connected to the non-inverting input terminals of U4C and U4D and ground.

[0014] A high-frequency signal processing method for a position sensitive detector is implemented based on the high-frequency signal processing circuit for a position sensitive detector, and specifically includes the following:

[0015] Step 1: First, the operational amplifier in the entire circuit is powered by external power supplies VDD, VSS and GND, and the power supply voltage is converted into a 5V reference voltage through a 5V reference voltage source circuit, and then a reverse bias voltage is provided for the Cathode pin of the position sensitive detector PSD;

[0016] Step 2: The position sensitive detector PSD converts the light signal directly incident on the PSD surface into a current signal through the position conversion formula:

[0017]

[0018]

[0019] The accurate position coordinates of the coordinate system formed by the four pins of PSD in the X and Y directions are obtained; four weak current signals I1, I2, I3 and I4 are output to the transimpedance amplifier circuit; where Lx is the length of the working area in the X direction; Ly is the length of the working area in the Y direction;

[0020] Step 3: The four output currents I1, I2, I3 and I4 of the position sensitive detector are each converted into a voltage signal through a transimpedance amplifier circuit;

[0021] The gain-bandwidth product, feedback resistor, and feedback capacitor parameters of the transimpedance amplifier U3 are designed to ensure that high-frequency signals pass through the circuit without being cut off; the final combined cutoff frequency of the PSD and transimpedance amplifier circuit is calculated as follows:

[0022]

[0023] Where GBP is the gain bandwidth product of the operational amplifier, Cs is the source capacitance, and R F is the feedback resistor;

[0024] Step 4: After the voltage signal is amplified by the transimpedance amplifier circuit, the output voltage signal amplitude still does not meet the actual test requirements and needs to be amplified twice. The secondary voltage amplifier circuit adopts an inverting amplifier design. The inverting amplifier converts the negative voltage output by the transimpedance amplifier circuit into a positive voltage and realizes any multiple gain at the same time.

[0025] Step 5: According to the position calculation formula in step 1, addition and subtraction operations are required. The subtraction circuit completes the operation of the numerator of the position calculation formula. In order to solve the relationship between the addition and subtraction input and output, it is necessary to perform equivalent processing. The operation circuit design of (I2+I4)-(I1+I3) is the same as that of (I2+I3)-(I1+I4);

[0026] Step 5.1: Subtraction circuit operation;

[0027] Step 5.1.1: The equivalent circuit of (I2+I3)-(I1+I4) is equivalent to the in-phase addition circuit, and its input-output relationship is:

[0028]

[0029] The (I2+I3)-(I1+I4) equivalent circuit is equivalent to an inverting addition circuit, and its input-output relationship is:

[0030]

[0031] Therefore, according to the superposition theorem, we can get:

[0032]

[0033] Because R 11 =R 22 =R 27 =R 14 =R 18 ,so:

[0034] u out =(U2+U3)-(U1+U4)

[0035] Wherein, U1, U2, U3, and U4 are the output results of the PSD output currents I1, I2, I3, and I4 after passing through the transimpedance amplifier circuit and the secondary voltage amplifier circuit;

[0036] Step 5.1.2: The equivalent circuit of (I2+I4)-(I1+I3) is equivalent to the in-phase addition circuit, and its input-output relationship is:

[0037]

[0038] The (I2+I4)-(I1+I3) equivalent circuit is equivalent to an inverting addition circuit, and its input-output relationship is:

[0039]

[0040] Therefore, according to the superposition theorem, we can get:

[0041]

[0042] Because R 12 =R 21 =R 28 =R 15 =R 19 ,so:

[0043] u out =(U2+U4)-(U1+U3)

[0044] Step 5.2: Addition circuit operation;

[0045] The adding circuit is responsible for summing the four output currents to obtain the denominator of the position calculation formula. The summing circuit adopts an inverting adding circuit design;

[0046] According to the virtual conclusion:

[0047]

[0048] According to the virtual short, we can know that: - =u + =0, so

[0049]

[0050] Because R9=R 13 =R 16 =R 20 =R 24 ,so:

[0051] u outc =-(U1+U2+U3+U4)

[0052] The summation result of the addition circuit composed of U4C is inverted, so the inverting operational amplifier circuit composed of U4D is used to perform an inversion, and the final summation result of the addition circuit is u out =(U1+U2+U3+U4);

[0053] Step 6: Upload the calculation results of the addition and subtraction circuit to the host computer for processing using the average periodogram method and Fourier transform, and then obtain the final result of the position conversion formula to obtain the position information in two directions.

[0054] Beneficial technical effects of the present invention:

[0055] The present invention provides a high-frequency measurement circuit for PSD, which is used to accurately detect the technical problem of the high-frequency weak current change of the sensor. The circuit has the advantages of simple circuit structure and little interference of the output result by the amplification accuracy of the operational amplifier and ground noise. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] Figure 1 It is a schematic diagram of the principle of PSD signal processing of the present invention.

[0057] Figure 2 They are the working surface and back surface of the position sensitive detector of the present invention, wherein Figure a is the working surface of the position sensitive detector, and Figure b is the back surface of the position sensitive detector. In Figure b, ①Anode X1 represents the output current I1 of PSD, ②③④⑦⑨NC represents no effect, ⑤Anode Y1 represents the output current I3 of PSD, ⑥Anode X2 represents the output current I2 of PSD, ⑧Cathode represents the working reverse bias voltage of PSD is 5V, and ⑩Anode Y2 represents the output current I4 of PSD.

[0058] Figure 3 is the bandwidth of the transimpedance amplifier circuit in the embodiment of the present invention.

[0059] Figure 4 This is a 5V reference voltage source circuit according to an embodiment of the present invention.

[0060] Figure 5 It is a transimpedance amplifier circuit and a secondary voltage amplifier circuit according to an embodiment of the present invention.

[0061] Figure 6 It is a realization circuit of the subtraction circuit (I2+I3)-(I1+I4) in the embodiment of the present invention.

[0062] Figure 7 It is the implementation circuit of the subtraction circuit (I2+I4)-(I1+I3) in the embodiment of the present invention.

[0063] Figure 8 This is an adding circuit according to an embodiment of the present invention.

[0064] Fig. 9 It is the (I2+I3)-(I1+I4) subtraction equivalent circuit of the present invention. Figure a is an equivalent in-phase addition circuit, and Figure b is an equivalent inverting addition circuit.

[0065] Fig.10 It is the (I2+I4)-(I1+I3) subtraction equivalent circuit of the present invention. Figure a is an equivalent in-phase addition circuit, and Figure b is an equivalent inverting addition circuit.

[0066] Fig.11 It is the test result of PSD circuit stability experiment. DETAILED DESCRIPTION

[0067] The present invention is described in detail below in conjunction with specific embodiments. The following embodiments will help those skilled in the art to further understand the present invention, but do not limit the present invention in any form. It should be pointed out that for those of ordinary skill in the art, several changes and improvements can be made without departing from the concept of the present invention. These all fall within the scope of protection of the present invention. The present invention provides a high-frequency weak current change measurement circuit, including: a PSD working circuit, a transimpedance amplifier circuit, a secondary voltage amplifier circuit and an addition and subtraction circuit, such as Figure 1 shown.

[0068] Figure 1 The circuit block diagram shown represents the entire PSD signal processing process. The PSD outputs four weak current signals, which are amplified and converted into voltage signals through the transimpedance amplifier circuit. The voltage signal is further amplified through the secondary voltage amplifier circuit, and then the numerator and denominator of the position formula in the two directions are obtained through the addition and subtraction circuit and the summation circuit. Finally, the X direction, Y direction and SUM signals are output, and then the software is used for division to obtain the position information in the two directions.

[0069] A high-frequency signal processing circuit for a position sensitive detector (PSD), comprising: a PSD working circuit, a transimpedance amplifier circuit, a secondary voltage amplifier circuit and an addition and subtraction circuit; the addition and subtraction circuit comprises an addition circuit and a subtraction circuit;

[0070] Among them, the PSD working circuit, the transimpedance amplifier circuit, the secondary voltage amplifier circuit and the addition and subtraction circuit are connected in sequence;

[0071] The PSD working circuit includes a position sensitive detector PSD and a 5V reference voltage source circuit. The function of the 5V reference voltage source circuit is to provide a 5V working power supply to the position sensitive detector. The 5V reference voltage source circuit includes a first capacitor C5, a second capacitor C6 and an operational amplifier U1. Figure 4As shown; the input end of the amplifier U1 is connected to the power supply VDD, the first capacitor C5 is connected to the power supply VDD and the ground GND, the second capacitor C6 is connected to the output end of the operational amplifier U1 and the ground GND, and the power supply end of the sensitive detector PSD is connected to the output end of the operational amplifier U1; wherein the power supply VDD is a common power supply for the entire signal processing circuit, and the ground GND is also a common power supply for the entire signal processing circuit;

[0072] The transimpedance amplifier circuit has two functions: the first function is to convert the output current signal of the PSD into a voltage signal; the second function is to amplify the input signal. It includes a transimpedance amplifier U3, a first resistor RL1, a second resistor RL2, a third resistor RL3, a fourth resistor RL4, a third capacitor CL2, a fourth capacitor CL3, a fifth capacitor CL6, a sixth capacitor CL7, a seventh capacitor CL5, an eighth capacitor C3, a ninth capacitor CL9, and a tenth capacitor C1. Figure 5 As shown; the four inverting input terminals INA-, INB-, INC-, and IND- of the transimpedance amplifier U3 are respectively connected to the current output terminals I1, I2, I3, and I4 of the position sensitive detector PSD. The inverting input terminal INA- of the transimpedance amplifier U3 is connected to the output terminal OUTA of the transimpedance amplifier U3 through the first resistor RL1 and the third capacitor CL2, and the INB-, INC-, and IND- of the transimpedance amplifier U3 are also connected to the output terminals OUTB, OUTC, and OUTD of the transimpedance amplifier U3 through the above method; the seventh capacitor CL5 and the eighth capacitor C3 are respectively connected to the ground GND, the power supply VDD, and the power supply terminal V+ of the transimpedance amplifier, and the ninth capacitor CL9 and the tenth capacitor C1 are respectively connected to the ground GND, the power supply VSS, and the power supply terminal V- of the transimpedance amplifier; the power supply VSS is shared by the entire circuit;

[0073] The function of the secondary voltage amplifier circuit is to invert and continue to amplify the voltage output by the transimpedance amplifier circuit, including a voltage amplifier U2, a fifth resistor R2, a sixth resistor R3, a seventh resistor R6, an eighth resistor R8, a ninth resistor R4, a tenth resistor R1, an eleventh resistor R7, a twelfth resistor R5, an eleventh capacitor CL1, a twelfth capacitor CL4, a thirteenth capacitor CL12, a fourteenth capacitor CL13, a fifteenth capacitor CL14, and a sixteenth capacitor CL15. Figure 5As shown; the voltage amplifier U2 can meet the requirements of converting and amplifying four current signals at the same time, and can be split into four amplifiers U2A, U2B, U2C, and U2D with the same function. The reverse input terminal INA- of the voltage amplifier U2A is connected to the output terminal OUTA of the transimpedance amplifier U3 in the transimpedance amplifier circuit through the fifth resistor R2, and the inverting input terminal INA- of U2A is connected to the output terminal OUTA of U2A through the sixth resistor R3 and the thirteenth capacitor CL12, and the positive input terminal INA+ of the voltage amplifier U2A is connected to the ground GND. The eleventh capacitor CL1 and the twelfth capacitor CL4 are energy storage capacitors of the circuit, and their function is to filter out the high-frequency noise generated by the device, cut off its path for propagation through the power supply circuit, and prevent the noise carried by the power supply from interfering with the circuit. The reverse input terminal INB- of the voltage amplifier U2B is connected to the output terminal OUTB of the transimpedance amplifier U3 through the seventh resistor R6, the inverting input terminal INB- of the voltage amplifier U2B is connected to the output terminal OUTB of U2B through the eighth resistor R8 and the fourteenth capacitor CL13, and the positive input terminal INB+ of the voltage amplifier U2B is connected to the ground GND. The reverse input terminal INC- of the voltage amplifier U2C is connected to the output terminal OUTD of the transimpedance amplifier U3 through the ninth resistor R4, the inverting input terminal INC- of the voltage amplifier U2C is connected to the output terminal OUTC of U2C through the tenth resistor R1 and the fifteenth capacitor CL14, and the positive input terminal INC+ of the voltage amplifier U2C is connected to the ground GND. The reverse input terminal IND- of the voltage amplifier U2D is connected to the output terminal OUTC of the transimpedance amplifier U3 through the eleventh resistor R7, the inverting input terminal IND- of the voltage amplifier U2D is connected to the output terminal OUTD of U2D through the twelfth resistor R5 and the sixteenth capacitor CL15, and the positive input terminal IND+ of the voltage amplifier U2D is connected to the ground GND.

[0074] The subtraction circuit is used to realize the position conversion formula (I2+I3)-(I1+I4) and (I2+I4)-(I1+I3), including an operational amplifier U4, a thirteenth resistor R14, a fourteenth resistor R18, a fifteenth resistor R22, a sixteenth resistor R27, a seventeenth resistor R23, an eighteenth resistor R11, a seventeenth capacitor CL16, a nineteenth capacitor CL10, a twentieth capacitor CL11, a nineteenth resistor R15, a twentieth resistor R19, a twenty-first resistor R21, a twenty-second resistor R28, a twenty-third resistor R26, a twenty-fourth resistor R12, and a twenty-first capacitor CL17. The voltage amplifier U4 is a four-way operational amplifier, which can be divided into U4A, U4B, U4C, and U4D, and includes four inverting input terminals: INA-, INB-, INC-, and IND-, four non-inverting input terminals: INA+, INB+, INC+, and IND+, and four output terminals OUTA, OUTB, OUTC, and OUTD. The implementation of (I2+I3)-(I1+I4) includes an operational amplifier U4A, a thirteenth resistor R14, a fourteenth resistor R18, a fifteenth resistor R22, a sixteenth resistor R27, a seventeenth resistor R23, an eighteenth resistor R11, a seventeenth capacitor CL16, a nineteenth capacitor CL10, and a twentieth capacitor CL11, as shown in FIG. Figure 6 As shown; the nineteenth capacitor CL10 and the twentieth capacitor CL11 are energy storage capacitors of the circuit to prevent the noise carried by the power supply from interfering with the circuit. The inverting input terminal of U4A is connected to the output terminals OUTA and OUTC of the voltage amplifier U2 through the thirteenth resistor R18 and the fourteenth resistor R14 respectively, and the non-inverting input terminal of U4A is connected to the output terminals OUTD and OUTB of the voltage amplifier U2 through the fifteenth resistor R22 and the sixteenth resistor R27 respectively. The inverting input terminal of U4A is connected to the output terminal through the eighteenth resistor R11 and the seventeenth capacitor CL16, and the seventeenth resistor R23 is connected to the non-inverting input terminal of U4A and the ground respectively; the implementation of (I2+I4)-(I1+I3) includes the operational amplifier U4B, the nineteenth resistor R15, the twentieth resistor R19, the twenty-first resistor R21, the twenty-second resistor R28, the twenty-third resistor R26, the twenty-fourth resistor R12, and the twenty-first capacitor CL17, as shown Figure 7 As shown, the inverting input terminal of U4B is connected to the output terminals OUTA and OUTB of the voltage amplifier U2 through the nineteenth resistor R15 and the twentieth resistor R19 respectively, the non-inverting input terminal of U4B is connected to the output terminals OUTD and OUTC of the voltage amplifier U2 through the twenty-first resistor R21 and the twenty-second resistor R28 respectively, the inverting input terminal of U4B is connected to the output terminal through the twenty-fourth resistor R12 and the twenty-first capacitor CL17, and the twenty-third resistor R26 is connected to the non-inverting input terminal of U4B and the ground respectively;

[0075] The adding circuit is used to realize the position conversion formula I1+I2+I3+I4, including an operational amplifier U4C, an operational amplifier U4D, a twenty-fifth resistor R13, a twenty-sixth resistor R16, a twenty-seventh resistor R20, a twenty-eighth resistor R24, a twenty-ninth resistor R30, a thirtieth resistor R9, a thirty-first resistor R32, a thirty-second resistor R29, a thirty-third resistor R31, a twenty-second capacitor CL18, and a twenty-third capacitor CL19, such as Figure 8 As shown, the inverting input terminal of U4C is connected to OUTA, OUTD, OUTB, and OUTC of U2 through the twenty-fifth resistor R13, the twenty-sixth resistor R16, the twenty-seventh resistor R20, and the twenty-eighth resistor R24 ​​respectively, and the inverting input terminal of U4C is connected to the output terminal through the thirtieth resistor R9 and the twenty-second capacitor CL18; the inverting output terminal of U4D is connected to the output terminal of U4C through the thirty-first resistor R32, and is connected to the output terminal of U4D through the thirty-third resistor R31 and the twenty-third capacitor CL19; the twenty-ninth resistor R30 and the thirty-second resistor R29 are respectively connected to the non-inverting input terminals of U4C and U4D and ground.

[0076] A high-frequency signal processing method for a position sensitive detector is implemented based on the high-frequency signal processing circuit for a position sensitive detector, and specifically includes the following:

[0077] Step 1: First, the operational amplifier in the entire circuit is powered by external power supplies VDD, VSS and GND, and the power supply voltage is converted into a 5V reference voltage through a 5V reference voltage source circuit, and then a reverse bias voltage is provided for the Cathode pin of the position sensitive detector PSD;

[0078] The position sensitive detector (PSD) is a photoelectric sensor that directly converts the light spot position signal acting on the photosensitive surface into an electrical signal representing the continuous position change. It has the characteristics of high sensitivity, high resolution, fast response speed, wide spectral response range, and very small dark current. It can meet the needs of high-speed vibration testing of micro cantilever beams.

[0079] Step 2: The position sensitive detector PSD converts the light signal directly incident on the PSD surface into a current signal through the position conversion formula:

[0080]

[0081]

[0082] The accurate position coordinates of the coordinate system formed by the four pins of PSD in the X and Y directions are obtained; four weak current signals I1, I2, I3 and I4 are output to the transimpedance amplifier circuit; where Lx is the length of the working area in the X direction; Ly is the length of the working area in the Y direction;

[0083] The PSD described is a four-sided two-dimensional PSD improved from Hamamatsu S5991-01. Figure 2 As shown, the PSD has a wide spectral response range, very small dark current, and fast response speed, which can meet the needs of high-speed vibration testing of micro-cantilever beams and has high position resolution.

[0084] Step 3: The transimpedance amplifier circuit mainly performs two functions. Function one is to convert the output current signal of the sensor into a voltage signal, and function two is to amplify the input signal. To process the weak current signal output by the PSD and ensure that the signal is not distorted after amplification, it is usually necessary to convert the current signal into a voltage signal, and the voltage signal is more conducive to the post-processing of the signal and is not easily affected by external interference. The four output currents I1, I2, I3 and I4 of the position sensitive detector are each converted into voltage signals through a transimpedance amplifier circuit;

[0085] The amplifiers U2, U3, and U4 all use OPA4354, which is a precision quad operational amplifier with low bias current. Its voltage noise and bandwidth noise are very low. It is powered by a positive and negative 7.5V dual power supply, which can meet the needs of converting and amplifying four current signals at the same time. Each amplifier can be divided into 4 operational amplifiers with the same functions, which are divided into U2A, U2B, U2C, U2D, U3A, U3B, U3C, U3D, U4A, U4B, U4C, and U4D for the convenience of description. The amplifier U1 uses REF02, which is a +5V precision reference voltage source.

[0086] The resistance values ​​of the resistors RL1, RL2, RL3, RL4, R2, R4, R6, R7, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, R21, R22, R23, R28, R28, R31, and R32 are all 10K; the resistance values ​​of R3, R8, R1, and R5 are 100K.

[0087] The gain-bandwidth product, feedback resistor, and feedback capacitor parameters of the transimpedance amplifier U3 are designed to ensure that the high-frequency signal passes through the circuit without being cut off. The bandwidth of the transimpedance amplifier circuit is directly related to the gain. The present invention is used for high-frequency micro-cantilever beam signal acquisition, so the circuit needs to have a higher bandwidth. The final combined cutoff frequency of the PSD and the transimpedance amplifier circuit is calculated as follows:

[0088]

[0089] Where GBP is the gain bandwidth product of the operational amplifier, Cs is the source capacitance, and R F is the feedback resistor;

[0090] In order to process the weak current signal output by the PSD and ensure that the signal is not distorted after amplification, it is usually necessary to convert the current signal into a voltage signal. The voltage signal is more conducive to the post-processing of the signal and is not easily affected by external interference. The transimpedance amplifier circuit is mostly used as the front-end amplifier of the optical sensor. The transimpedance amplifier circuit is generally designed using a low-noise operational amplifier. The operational amplifier should be selected reasonably. Generally, an operational amplifier with high input impedance and low bias current should be selected. First of all, the JFET type should be selected. JFET type operational amplifiers generally have extremely high impedance and low bias current characteristics. This system combines performance and cost requirements and finally selects the OPA4354 chip as the operational amplifier of the transimpedance amplifier circuit.

[0091] The cutoff frequency of the transimpedance amplifier will affect the bandwidth of the entire PSD processing circuit, and thus affect whether it can collect high-frequency signal conversion. OPA4354 has a gain-bandwidth product of 100MHZ, and the common-mode and differential-mode input capacitances are both 2pF. The junction capacitance of the PSD is 500pF. The feedback resistors RL1, RL2, RL3, and RL4 are all 20K, and the feedback capacitors CL2, CL3, CL6, and CL7 are 9pF. The -3dB closed-loop bandwidth of the transimpedance amplifier circuit is calculated to be 1.247MHz, which is the same as the simulation results of the LTspice software. The simulation results are shown in Figure 3 As shown, the quality factor Q is 0.707, the circuit is of Butterworth type, and the maximum bandwidth can be achieved.

[0092] Step 4: After the voltage signal is amplified by the transimpedance amplifier circuit, the amplitude of the output voltage signal still does not meet the actual test requirements and needs to be amplified twice. The secondary voltage amplifier circuit adopts an inverting amplifier design. The inverting amplifier converts the negative voltage output by the transimpedance amplifier circuit into a positive voltage and achieves any multiple gain at the same time; it can effectively suppress common-mode interference. The gain multiple of the secondary voltage amplifier circuit is not easy to be too large. Excessive gain will cause the final output voltage to be too large, exceeding the acquisition voltage range of the data equipment.

[0093] Step 5: According to the position calculation formula in step 1, addition and subtraction operations are required. The subtraction circuit completes the operation of the numerator part of the position calculation formula. The implementation of (I2+I3)-(I1+I4) is as follows: Figure 6 As shown, in order to solve the relationship between addition and subtraction input and output, it is necessary to perform equivalent processing. The equivalent circuit is as follows Fig. 9As shown. The operational circuit design of (I2+I4)-(I1+I3) is the same as that of (I2+I3)-(I1+I4). The equivalent circuit is as follows: Fig.10 As shown;

[0094] Step 5.1.1: The equivalent circuit of (I2+I3)-(I1+I4) is equivalent to the in-phase addition circuit, and its input-output relationship is:

[0095]

[0096] The (I2+I3)-(I1+I4) equivalent circuit is equivalent to an inverting addition circuit, and its input-output relationship is:

[0097]

[0098] Therefore, according to the superposition theorem, we can get:

[0099]

[0100] Because R 11 =R 22 =R 27 =R 14 =R 18 ,so:

[0101] u out =(U2+U3)-(U1+U4)

[0102] Wherein, U1, U2, U3, and U4 are the output results of the PSD output currents I1, I2, I3, and I4 after passing through the transimpedance amplifier circuit and the secondary voltage amplifier circuit;

[0103] Step 5.1.2: The equivalent circuit of (I2+I4)-(I1+I3) is equivalent to the in-phase addition circuit, and its input-output relationship is:

[0104]

[0105] The (I2+I4)-(I1+I3) equivalent circuit is equivalent to an inverting addition circuit, and its input-output relationship is:

[0106]

[0107] Therefore, according to the superposition theorem, we can get:

[0108]

[0109] Because R 12 =R 21 =R 28 =R 15 =R 19 ,so:

[0110] u out =(U2+U4)-(U1+U3)

[0111] Step 5.2: Addition circuit operation;

[0112] The adding circuit is responsible for summing the four output currents to obtain the denominator of the position calculation formula. The summing circuit adopts an inverting adding circuit design; its structure is as follows: Figure 8 shown.

[0113] According to the virtual conclusion:

[0114]

[0115] According to the virtual short, we can know that: - =u + =0, so

[0116]

[0117] Because R9=R 13 =R 16 =R 20 =R 24 ,so:

[0118] u outc =-(U1+U2+U3+U4)

[0119] The summation result of the addition circuit composed of U4C is inverted, so the inverting operational amplifier circuit composed of U4D is used to perform an inversion, and the final summation result of the addition circuit is u out =(U1+U2+U3+U4);

[0120] Step 6: Upload the calculation results of the addition and subtraction circuit to the host computer for processing using the average periodogram method and Fourier transform, and then obtain the final result of the position conversion formula to obtain the position information in two directions.

[0121] The multi-order modal experimental results of the micro-cantilever beam obtained by the circuit processing are compared with the non-viscous theory, and the relative error is between 0.24% and 7.73%. Compared with the viscous theory, the relative error is between 0.04% and 4.18%, which effectively verifies the accuracy of the circuit processing. By testing the stability of PSD within 1 minute, such as Fig.11 As shown, the sampling frequency is set to 2KHz, and a total of 120,000 sampling points are obtained. The output only varies between ±1.678μm, and the PSD output signal has good stability.

Claims

1. A high-frequency signal processing circuit for a position sensitive detector (PSD), characterized in that: include: PSD working circuit, transimpedance amplifier circuit, secondary voltage amplifier circuit and addition and subtraction circuit; the addition and subtraction circuit includes an addition circuit and a subtraction circuit; Among them, the PSD working circuit, the transimpedance amplifier circuit, the secondary voltage amplifier circuit and the addition and subtraction circuit are connected in sequence; The PSD working circuit includes a position sensitive detector PSD and a 5V reference voltage source circuit. The function of the 5V reference voltage source circuit is to provide a 5V working power supply to the position sensitive detector. The 5V reference voltage source circuit includes a first capacitor C5, a second capacitor C6 and an operational amplifier U1; the input end of the amplifier U1 is connected to a power supply VDD, the first capacitor C5 is connected to the power supply VDD and the ground GND, the second capacitor C6 is connected to the output end of the operational amplifier U1 and the ground GND, and the power supply end of the sensitive detector PSD is connected to the output end of the operational amplifier U1; wherein the power supply VDD is a common power supply for the entire signal processing circuit, and the ground GND is also common to the entire signal processing circuit; The transimpedance amplifier circuit includes a transimpedance amplifier U3, a first resistor RL1, a second resistor RL2, a third resistor RL3, a fourth resistor RL4, a third capacitor CL2, a fourth capacitor CL3, a fifth capacitor CL6, a sixth capacitor CL7, a seventh capacitor CL5, an eighth capacitor C3, a ninth capacitor CL9, and a tenth capacitor C1; the four inverting input terminals INA-, INB-, INC-, and IND- of the transimpedance amplifier U3 are respectively connected to the current output terminals I1, I2, I3, and I4 of the position sensitive detector PSD; the ... The terminal INA- is connected to the output terminal OUTA of the transimpedance amplifier U3 through the first resistor RL1 and the third capacitor CL2, and the INB-, INC-, and IND- of the transimpedance amplifier U3 are also connected to the output terminals OUTB, OUTC, and OUTD of the transimpedance amplifier U3 through the above method; the seventh capacitor CL5 and the eighth capacitor C3 are respectively connected to the ground GND, the power supply VDD, and the power supply terminal V+ of the transimpedance amplifier, and the ninth capacitor CL9 and the tenth capacitor C1 are respectively connected to the ground GND, the power supply VSS, and the power supply terminal V- of the transimpedance amplifier; the power supply VSS is shared by the entire circuit.

2. A high-frequency signal processing circuit for a position sensitive detector (PSD) according to claim 1, characterized in that: The secondary voltage amplifier circuit includes a voltage amplifier U2, a fifth resistor R2, a sixth resistor R3, a seventh resistor R6, an eighth resistor R8, a ninth resistor R4, a tenth resistor R1, an eleventh resistor R7, a twelfth resistor R5, an eleventh capacitor CL1, a twelfth capacitor CL4, a thirteenth capacitor CL12, a fourteenth capacitor CL13, a fifteenth capacitor CL14, and a sixteenth capacitor CL15; the voltage amplifier U2 can meet the requirements of converting and amplifying four current signals at the same time, and can be split into four amplifiers U with the same function. 2A, U2B, U2C, U2D, the reverse input terminal INA- of the voltage amplifier U2A is connected to the output terminal OUTA of the transimpedance amplifier U3 in the transimpedance amplifier circuit through the fifth resistor R2, the inverting input terminal INA- of U2A is connected to the output terminal OUTA of U2A through the sixth resistor R3 and the thirteenth capacitor CL12, the positive input terminal INA+ of the voltage amplifier U2A is connected to the ground GND; the eleventh capacitor CL1 and the twelfth capacitor CL4 are energy storage capacitors of the circuit, the reverse input terminal INA- of the voltage amplifier U2B ... The input terminal INB- is connected to the output terminal OUTB of the transimpedance amplifier U3 through the seventh resistor R6, the inverting input terminal INB- of the voltage amplifier U2B is connected to the output terminal OUTB of U2B through the eighth resistor R8 and the fourteenth capacitor CL13, and the positive input terminal INB+ of the voltage amplifier U2B is connected to the ground GND; the inverting input terminal INC- of the voltage amplifier U2C is connected to the output terminal OUTD of the transimpedance amplifier U3 through the ninth resistor R4, the inverting input terminal INC- of the voltage amplifier U2C is connected to the output terminal OUTC of U2C through the tenth resistor R1 and the fifteenth capacitor CL14, and the positive input terminal INC+ of the voltage amplifier U2C is connected to the ground GND; the inverting input terminal IND- of the voltage amplifier U2D is connected to the output terminal OUTC of the transimpedance amplifier U3 through the eleventh resistor R7, the inverting input terminal IND- of the voltage amplifier U2D is connected to the output terminal OUTD of U2D through the twelfth resistor R5 and the sixteenth capacitor CL15, and the positive input terminal IND+ of the voltage amplifier U2D is connected to the ground GND.

3. A high-frequency signal processing circuit for a position sensitive detector (PSD) according to claim 1, characterized in that: The subtraction circuit is used to realize the position conversion formula (I2+I3)-(I1+I4) and (I2+I4)-(I1+I3), including an operational amplifier U4, a thirteenth resistor R14, a fourteenth resistor R18, a fifteenth resistor R22, a sixteenth resistor R27, a seventeenth resistor R23, an eighteenth resistor R11, a seventeenth capacitor CL16, a nineteenth capacitor CL10, a twentieth capacitor CL11, a nineteenth resistor R15, a twentieth resistor R19, a twenty-first resistor R21, a twenty-second resistor R28, a twenty-third resistor R26, a twenty-fourth resistor R12, and a twenty-first capacitor CL17. The voltage amplifier U4 is a four-way operational amplifier, which can be disassembled. It is divided into U4A, U4B, U4C, and U4D, including four inverting input terminals: INA-, INB-, INC-, and IND-, four non-inverting input terminals: INA+, INB+, INC+, and IND+, and four output terminals OUTA, OUTB, OUTC, and OUTD; the implementation of (I2+I3)-(I1+I4) includes an operational amplifier U4A, a thirteenth resistor R14, a fourteenth resistor R18, a fifteenth resistor R22, a sixteenth resistor R27, a seventeenth resistor R23, an eighteenth resistor R11, a seventeenth capacitor CL16, a nineteenth capacitor CL10, and a twentieth capacitor CL11; the nineteenth capacitor CL10 and the twentieth capacitor CL11 are The energy storage capacitor of the circuit prevents the noise carried by the power supply from interfering with the circuit; the inverting input terminal of U4A is connected to the output terminals OUTA and OUTC of the voltage amplifier U2 through the thirteenth resistor R18 and the fourteenth resistor R14 respectively, the non-inverting input terminal of U4A is connected to the output terminals OUTD and OUTB of the voltage amplifier U2 through the fifteenth resistor R22 and the sixteenth resistor R27 respectively, the inverting input terminal of U4A is connected to the output terminal through the eighteenth resistor R11 and the seventeenth capacitor CL16, and the seventeenth resistor R23 is connected to the non-inverting input terminal of U4A and the ground respectively; the implementation of (I2+I4)-(I1+I3) includes the operational amplifier U4B, the nineteenth resistor R15, the second The twenty-first resistor R19, the twenty-first resistor R21, the twenty-second resistor R28, the twenty-third resistor R26, the twenty-fourth resistor R12, and the twenty-first capacitor CL17, wherein the inverting input terminal of U4B is connected to the output terminals OUTA and OUTB of the voltage amplifier U2 through the nineteenth resistor R15 and the twentieth resistor R19 respectively, the non-inverting input terminal of U4B is connected to the output terminals OUTD and OUTC of the voltage amplifier U2 through the twenty-first resistor R21 and the twenty-second resistor R28 respectively, the inverting input terminal of U4B is connected to the output terminal through the twenty-fourth resistor R12 and the twenty-first capacitor CL17, and the twenty-third resistor R26 is connected to the non-inverting input terminal of U4B and ground respectively.

4. A high-frequency signal processing circuit for a position sensitive detector (PSD) according to claim 1, characterized in that: The adding circuit is used to realize the position conversion formula I1+I2+I3+I4, including an operational amplifier U4C, an operational amplifier U4D, a twenty-fifth resistor R13, a twenty-sixth resistor R16, a twenty-seventh resistor R20, a twenty-eighth resistor R24, a twenty-ninth resistor R30, a thirtieth resistor R9, a thirty-first resistor R32, a thirty-second resistor R29, a thirty-third resistor R31, a twenty-second capacitor CL18, and a twenty-third capacitor CL19, wherein the inverting input terminal of U4C is respectively connected through the twenty-fifth resistor R13, the twenty-sixth resistor R16, the twenty-seventh resistor R20, the twenty-eighth resistor R24, the twenty-ninth resistor R30, the thirtieth resistor R9, the thirty-first resistor R32, the thirty-second resistor R29, the thirty-third resistor R31, the twenty-second capacitor CL18, and the twenty-third capacitor CL19. Resistor R16, the twenty-seventh resistor R20, and the twenty-eighth resistor R24 ​​are connected to OUTA, OUTD, OUTB, and OUTC of U2, and the inverting input terminal of U4C is connected to the output terminal through the 30th resistor R9 and the 22nd capacitor CL18; the inverting output terminal of U4D is connected to the output terminal of U4C through the thirty-first resistor R32, and is connected to the output terminal of U4D through the thirty-third resistor R31 and the twenty-third capacitor CL19; the twenty-ninth resistor R30 and the thirty-second resistor R29 are respectively connected to the non-inverting input terminals of U4C and U4D and ground.

5. A high-frequency signal processing method for a position sensitive detector, implemented based on the high-frequency signal processing circuit for a position sensitive detector of claim 1, characterized in that: Specifically include the following: Step 1: First, the operational amplifier in the entire circuit is powered by external power supplies VDD, VSS and GND, and the power supply voltage is converted into a 5V reference voltage through a 5V reference voltage source circuit, and then a reverse bias voltage is provided for the Cathode pin of the position sensitive detector PSD; Step 2: The position sensitive detector PSD converts the light signal directly incident on the PSD surface into a current signal through the position conversion formula: The accurate position coordinates of the coordinate system formed by the four pins of PSD in the X and Y directions are obtained; four weak current signals I1, I2, I3 and I4 are output to the transimpedance amplifier circuit; where Lx is the length of the working area in the X direction; Ly is the length of the working area in the Y direction; Step 3: The four output currents I1, I2, I3 and I4 of the position sensitive detector are each converted into a voltage signal through a transimpedance amplifier circuit; The gain-bandwidth product, feedback resistor, and feedback capacitor parameters of the transimpedance amplifier U3 are designed to ensure that high-frequency signals pass through the circuit without being cut off; the final combined cutoff frequency of the PSD and transimpedance amplifier circuit is calculated as follows: Where GBP is the gain bandwidth product of the operational amplifier, Cs is the source capacitance, and R F is the feedback resistor; Step 4: After the voltage signal is amplified by the transimpedance amplifier circuit, the output voltage signal amplitude still does not meet the actual test requirements and needs to be amplified twice. The secondary voltage amplifier circuit adopts an inverting amplifier design. The inverting amplifier converts the negative voltage output by the transimpedance amplifier circuit into a positive voltage and realizes any multiple gain at the same time. Step 5: According to the position calculation formula in step 1, addition and subtraction operations are required. The subtraction circuit completes the operation of the numerator of the position calculation formula. In order to solve the relationship between the addition and subtraction input and output, it is necessary to perform equivalent processing. The operation circuit design of (I2+I4)-(I1+I3) is the same as that of (I2+I3)-(I1+I4); Step 6: Upload the calculation results of the addition and subtraction circuit to the host computer for processing using the average periodogram method and Fourier transform, and then obtain the final result of the position conversion formula to obtain the position information in two directions.

6. A high frequency signal processing method for a position sensitive detector according to claim 5, characterized in that: Step 5 is as follows: Step 5.1: Subtraction circuit operation; Step 5.1.1: The equivalent circuit of (I2+I3)-(I1+I4) is equivalent to the in-phase addition circuit, and its input-output relationship is: The (I2+I3)-(I1+I4) equivalent circuit is equivalent to an inverting addition circuit, and its input-output relationship is: Therefore, according to the superposition theorem, we can get: Because R 11 =R 22 =R 27 =R 14 =R 18 ,so: u out =(U2+U3)-(U1+U4) Wherein, U1, U2, U3, and U4 are the output results of the PSD output currents I1, I2, I3, and I4 after passing through the transimpedance amplifier circuit and the secondary voltage amplifier circuit; Step 5.1.2: The equivalent circuit of (I2+I4)-(I1+I3) is equivalent to the in-phase addition circuit, and its input-output relationship is: The (I2+I4)-(I1+I3) equivalent circuit is equivalent to an inverting addition circuit, and its input-output relationship is: Therefore, according to the superposition theorem, we can get: Because R 12 =R 21 =R 28 =R 15 =R 19 ,so: u out =(U2+U4)-(U1+U3) Step 5.2: Addition circuit operation; The adding circuit is responsible for summing the four output currents to obtain the denominator of the position calculation formula. The summing circuit adopts an inverting adding circuit design; According to the virtual judgment: According to the virtual short, we can know that: - =u + =0, so Because R9=R 13 =R 16 =R 20 =R 24 ,so: u outc =-(U1+U2+U3+U4) The summation result of the addition circuit composed of U4C is inverted, so the inverting operational amplifier circuit composed of U4D is used to perform an inversion, and the final summation result of the addition circuit is u out =(U1+U2+U3+U4).

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