Drive circuit and electronic device
By introducing a combination of pull-up and pull-down circuits into the driving circuit, and utilizing P-type and N-type transistors and inverters, the problem of insufficient driving speed under high voltage technology is solved, and the driving performance of the memristor array is improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- TSINGHUA UNIVERSITY
- Filing Date
- 2022-06-28
- Publication Date
- 2026-05-12
AI Technical Summary
Existing drive circuits struggle to achieve sufficient drive speed within a limited area under high-voltage processes, especially for the read/write operation voltage requirements of memristor arrays, leading to a decline in memory performance.
It adopts a combination structure of pull-up and pull-down circuits, including P-type and N-type transistors and inverters, and improves driving performance by controlling the switching on and off of transistors through selection signals.
It improves the driving performance at low operating voltages and, to some extent, enhances the driving performance at high operating voltages, thereby strengthening the memory's driving capability.
Smart Images
Figure CN115223622B_ABST
Abstract
Description
Technical Field
[0001] Embodiments of this disclosure relate to a drive circuit and electronic device. Background Technology
[0002] High-voltage processes refer to CMOS (Complementary Metal Oxide Semiconductor) processes provided by semiconductor wafer foundries that can withstand higher operating voltages. In this type of process, transistors used as drivers can withstand higher operating voltages (e.g., typically 8V or 32V), but also have longer minimum gate lengths and higher transistor threshold voltages. For memristor arrays, the read operating voltage is generally lower (approximately 1V applied to the word line and <0.5V applied to the bit line), while the write operating voltage is generally higher (approximately 1.5V to 3V applied to the word line and approximately 1.5V to 2.5V applied to the bit line). Summary of the Invention
[0003] At least one embodiment of this disclosure provides a driving circuit including a pull-up circuit and a pull-down circuit. The pull-up circuit is disposed between a pull-up power supply voltage terminal and an output terminal, and is configured to receive a first selection signal and use the voltage of the pull-up power supply voltage terminal to pull up the voltage of the output terminal. The pull-down circuit is disposed between a pull-down power supply voltage terminal and an output terminal, and is configured to receive a second selection signal and use the voltage of the pull-down power supply voltage terminal to pull down the voltage of the output terminal. The pull-up circuit includes a first P-type transistor, a second N-type transistor, and a first inverter. The source of the first P-type transistor and the drain of the second N-type transistor are connected to each other and connected to the pull-up power supply voltage terminal. The drain of the first P-type transistor and the source of the second N-type transistor are connected to each other and connected to the output terminal. One of the gates of the first P-type transistor and the second N-type transistor receives the first selection signal, and the other of the gates of the first P-type transistor and the second N-type transistor receives the first selection signal via the first inverter.
[0004] For example, in the driving circuit provided in at least one embodiment of this disclosure, the pull-down circuit includes a third N-type transistor, the gate of the third N-type transistor receives a second selection signal, the drain of the third N-type transistor is connected to the output terminal, and the source of the third N-type transistor is connected to the pull-down power supply voltage terminal.
[0005] For example, in the driving circuit provided in at least one embodiment of this disclosure, the first selection signal and the second selection signal are the same selection signal.
[0006] For example, in the driving circuit provided in at least one embodiment of this disclosure, a pull-up circuit is connected to a first node to receive a first selection signal, a pull-down circuit is connected to the first node to receive a second selection signal, the gate of a first P-type transistor receives the first selection signal, and the gate of a second N-type transistor receives the first selection signal from a first inverter.
[0007] For example, at least one embodiment of the present disclosure provides a driving circuit that further includes a second inverter disposed between the first node and the selection signal providing terminal, and configured to receive an initial selection signal from the selection signal providing terminal and provide a first selection signal that is inverted from the initial selection signal.
[0008] For example, in the driving circuit provided in at least one embodiment of this disclosure, the channel width of the second N-type transistor and the channel width of the third N-type transistor are 1 / 2 to 1 / 3 of the channel width of the first P-type transistor.
[0009] For example, in the driving circuit provided in at least one embodiment of this disclosure, the first P-type transistor is a PMOS transistor, the second N-type transistor is an NMOS transistor, and the third N-type transistor is an NMOS transistor.
[0010] At least one embodiment of this disclosure also provides an electronic device including a driving circuit provided in at least one embodiment of this disclosure.
[0011] For example, at least one embodiment of the electronic device provided in this disclosure further includes: a memristor array, including a plurality of memristor units arranged in an array and a plurality of operation lines for operating the plurality of memristor units, the plurality of operation lines including a first operation line connected to the output terminal of a drive circuit; and an operation line selection circuit configured to receive an operation line address signal and output a first selection signal and a second selection signal to the drive circuit.
[0012] For example, in an electronic device provided in at least one embodiment of this disclosure, the operating lines are word lines, bit lines, or source lines of a memristor array.
[0013] For example, in an electronic device provided in at least one embodiment of this disclosure, a pull-up circuit and a pull-down circuit are respectively connected to an operation line selection circuit, and the operation line selection circuit provides a first control signal and a second control signal for controlling the pull-up circuit and the pull-down circuit respectively.
[0014] For example, in an electronic device provided in at least one embodiment of this disclosure, a pull-up circuit is connected to a first node to receive a first selection signal, a pull-down circuit is connected to the first node to receive a second selection signal, the first selection signal and the second selection signal are the same selection signal, an operation line selection circuit provides a selection signal that is simultaneously the first selection signal and the second selection signal to the first node, the gate of a first P-type transistor receives the first selection signal, and the gate of a second N-type transistor receives the first selection signal by a first inverter.
[0015] For example, in an electronic device provided in at least one embodiment of this disclosure, the driving circuit further includes a second inverter disposed between the first node and the operation line selection circuit, and configured to receive an initial selection signal from the operation line selection circuit and provide a first selection signal that is inverse of the initial selection signal. Attached Figure Description
[0016] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.
[0017] Figure 1 A schematic diagram of the circuit structure of a driving circuit is shown;
[0018] Figure 2 A schematic diagram of the circuit structure of a driving circuit provided in at least one embodiment of the present disclosure is shown;
[0019] Figure 3 A schematic diagram of the circuit structure of another driving circuit provided in at least one embodiment of the present disclosure is shown;
[0020] Figure 4 A schematic diagram of the circuit structure of another driving circuit provided in at least one embodiment of the present disclosure is shown;
[0021] Figure 5 A schematic diagram of the circuit structure of another driving circuit provided in at least one embodiment of the present disclosure is shown;
[0022] Figure 6 A schematic block diagram of an electronic device provided in at least one embodiment of the present disclosure is shown;
[0023] Figure 7 A schematic structure of a memristor array is shown;
[0024] Figure 8 A schematic diagram of an electronic device according to at least one embodiment of the present disclosure is shown. Detailed Implementation
[0025] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.
[0026] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.
[0027] Figure 1 A schematic diagram of a driving circuit for a memory array is shown.
[0028] like Figure 1As shown, the driving circuit includes a PMOS transistor S1 and an NMOS transistor S2. The source of PMOS transistor S1 is connected to a first signal terminal N1, and the source of NMOS transistor S2 is connected to a second signal terminal N2. An operating voltage (Vpp) is applied to the first signal terminal N1, and a common voltage (Vss) is applied to the second signal terminal N2. The drain of PMOS transistor S1 is connected to the drain of NMOS transistor S2. The gate of PMOS transistor S1 is connected to a first control signal terminal C1, and the gate of NMOS transistor S2 is connected to a second control signal terminal C2. For example, this driving circuit is used for word lines in a memory array, i.e., controlling the on / off state of the channel region of the switching transistor in a memory cell (not shown) connected to a word line (WL). The operating voltage (Vpp) is greater than the threshold voltage of the switching transistor in the memory cell, and the common voltage (Vss) is less than the threshold voltage of the switching transistor in the memory cell. The common voltage (Vss) is grounded or connected to a negative voltage. The first control signal terminal C1 and the second control signal terminal C2 are connected (not shown). The first control signal terminal C1 and the second control signal terminal C2 control the PMOS transistor S1 and the NMOS transistor S2. When C1 is low, the PMOS transistor S1 pulls up the word line, and the voltage output by the word line is the operating voltage, thereby controlling the channel region of the memory cell to open. When C2 is high, the NMOS transistor S2 pulls down the word line, and the voltage output by the word line is the common voltage, thereby controlling the channel region of the switching transistor of the memory cell to close.
[0029] and Figure 1 Similarly, in current driver circuit structures, PMOS transistors are typically used to pull up the voltage of the operation lines (word lines, bit lines, or source lines) to the operating voltage. PMOS transistors have a relatively high threshold voltage. When the operating voltage is low, the substrate modulation effect further increases the threshold voltage, causing the PMOS transistor to operate in the saturation region with high internal resistance, weakening its driving capability and reducing memory speed. If the operating voltage is lower than the threshold voltage of the PMOS transistor, it will be cut off and unable to perform the driving function. For example, in memristor memory, the read operation voltage is generally low (approximately 1V applied to the word line and less than 0.5V applied to the bit line), while the write operation voltage is generally high (approximately 1.5V to 3V applied to the word line and approximately 1.5V to 2.5V applied to the bit line). If the current driver circuit structure is used, the high threshold voltage of the transistor and the long minimum gate length make it difficult to achieve sufficient driving speed within a limited area, which significantly affects the performance of memristor-based memory.
[0030] At least one embodiment of this disclosure provides a driving circuit including a pull-up circuit and a pull-down circuit. The pull-up circuit is disposed between a pull-up power supply voltage terminal and an output terminal, and is configured to receive a first selection signal and use the voltage of the pull-up power supply voltage terminal to pull up the voltage of the output terminal. The pull-down circuit is disposed between a pull-down power supply voltage terminal and an output terminal, and is configured to receive a second selection signal and use the voltage of the pull-down power supply voltage terminal to pull down the voltage of the output terminal. The pull-up circuit includes a first P-type transistor, a second N-type transistor, and a first inverter. The source of the first P-type transistor and the drain of the second N-type transistor are connected to each other and connected to the pull-up power supply voltage terminal. The drain of the first P-type transistor and the source of the second N-type transistor are connected to each other and connected to the output terminal. One of the gates of the first P-type transistor and the second N-type transistor receives the first selection signal, and the other of the gates of the first P-type transistor and the second N-type transistor receives the first selection signal via the first inverter.
[0031] In the driving circuit provided in the above embodiments of this disclosure, the pull-up circuit includes a P-type transistor and an N-type transistor, which greatly improves the driving performance for low operating voltages and also improves the driving performance for higher operating voltages.
[0032] At least one embodiment of this disclosure also provides an electronic device including the above-described driving circuit.
[0033] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings, but this disclosure is not limited to these specific embodiments.
[0034] Figure 2 A schematic diagram of the circuit structure of a driving circuit 200 provided in at least one embodiment of the present disclosure is shown.
[0035] like Figure 2As shown, the driving circuit 200 includes a pull-up circuit 201 and a pull-down circuit 202. The pull-up circuit 201 is disposed between the pull-up power supply voltage terminal VOP and the output terminal OUT, and is configured to receive a first selection signal C1 and use the voltage of the pull-up power supply voltage terminal VOP to pull up the voltage of the output terminal OUT. The pull-down circuit 202 is disposed between the pull-down power supply voltage terminal VSS and the output terminal OUT, and is configured to receive a second selection signal C2 and use the voltage of the pull-down power supply voltage terminal VSS to pull down the voltage of the output terminal OUT. The pull-up circuit 201 includes a first P-type transistor XP0, a second N-type transistor XN1, and a first inverter X1. The source of the first P-type transistor XP0 and the drain of the second N-type transistor XN1 are connected to each other and to the pull-up power supply voltage terminal VOP. The drain of the first P-type transistor XP0 and the source of the second N-type transistor XN1 are connected to each other and to the output terminal OUT. The gate of the first P-type transistor XP0 receives a first selection signal C1, and the gate of the second N-type transistor XN1 receives the first selection signal C1 via the first inverter X1.
[0036] For example, in this embodiment, the pull-down circuit 202 includes a third N-type transistor XN0, the gate of the third N-type transistor XN0 receives the second selection signal C2, the drain of the third N-type transistor XN0 is connected to the output terminal OUT, and the source of the third N-type transistor XN0 is connected to the pull-down power supply voltage terminal VSS.
[0037] For example, in this embodiment, the channel width of the second N-type transistor XN1 and the channel width of the third N-type transistor XN0 are 1 / 2 to 1 / 3 of the channel width of the first P-type transistor XP0. In this embodiment, the distance between the two ends of the channel region along the source-drain current direction is the length of the channel region, and the distance between the two ends of the channel region in the direction perpendicular to the source-drain current direction is the width of the channel region.
[0038] For example, in this embodiment, the first P-type transistor XP0 can be a PMOS transistor or an HVPMOS transistor, the second N-type transistor XN1 can be an NMOS transistor or an HVNMOS transistor, and the third N-type transistor XN0 can be an NMOS transistor or an HVNMOS transistor. Both HVPMOS and HVNMOS transistors are high-voltage transistors; for example, a high-voltage transistor refers to a transistor with a high breakdown voltage (e.g., approximately greater than 50V) and a high frequency.
[0039] For example, in this embodiment, the pull-down power supply voltage terminal VSS is grounded or connected to a negative voltage. A first selection signal C1 controls the first P-type transistor XP0 and the second N-type transistor XN1, and a second selection signal C2 controls the third N-type transistor XN0. When both the first selection signal C1 and the second selection signal C2 are low, the channel region of the first P-type transistor XP0 is turned on, the channel region of the second N-type transistor XN1 is turned on, and the channel region of the third N-type transistor XN0 is turned off. The voltage at the output terminal OUT is the voltage at the pull-up power supply voltage terminal VOP. When both the first selection signal C1 and the second selection signal C2 are high, the channel region of the first P-type transistor XP0 is turned off, the channel region of the second N-type transistor XN1 is turned off, and the channel region of the third N-type transistor XN0 is turned on. The voltage at the output terminal OUT is the voltage at the pull-down power supply voltage terminal VSS.
[0040] For the lower pull-up power supply voltage VOP, the second N-type transistor XN1 is primarily responsible for conduction. Since N-type transistors have a stronger ability to conduct low voltages, the above-described drive circuit structure significantly improves the driving performance for lower pull-up power supply voltages. For the higher pull-up power supply voltage VOP, since the output voltage OUT is initially low, the N-type transistor has a stronger driving capability than the P-type transistor in this stage. Therefore, it helps in the process of starting to pull up the output voltage OUT, and the above-described drive circuit structure improves the driving performance for higher pull-up power supply voltages VOP.
[0041] Figure 3 A schematic diagram of the circuit structure of another driving circuit 300 provided in at least one embodiment of the present disclosure is shown.
[0042] like Figure 3 As shown, the driving circuit 300 includes a pull-up circuit 301 and a pull-down circuit 302. For example, the circuit components of the driving circuit 300 may be the same as those of the driving circuit 200 or different. In this embodiment, the gate of the second N-type transistor XN1 receives the first selection signal C1, and the gate of the first P-type transistor XP0 receives the first selection signal C1 via the first inverter X1. The other connection relationships of the circuit components of the driving circuit 300 are the same as those of the driving circuit 200, and will not be described again here.
[0043] For example, in this embodiment, the first selection signal C1 controls the first P-type transistor XP0 and the second N-type transistor XN1, and the second selection signal C2 controls the third N-type transistor XN0. When the first selection signal C1 is high and the second selection signal C2 is low, the channel region of the first P-type transistor XP0 is turned on, the channel region of the second N-type transistor XN1 is turned on, and the channel region of the third N-type transistor XN0 is turned off, and the voltage at the output terminal OUT is the voltage at the pull-up power supply voltage terminal VOP. When the first selection signal C1 is low and the second selection signal C2 is high, the channel region of the first P-type transistor XP0 is turned off, the channel region of the second N-type transistor XN1 is turned off, and the channel region of the third N-type transistor XN0 is turned on, and the voltage at the output terminal OUT is the voltage at the pull-down power supply voltage terminal VSS.
[0044] Technical effects of drive circuit 300 Figure 2 The driving circuit 200 shown has the same technical effect, and will not be described again here.
[0045] Figure 4 A schematic diagram of the circuit structure of another driving circuit 400 provided in at least one embodiment of the present disclosure is shown.
[0046] like Figure 4 As shown, the drive circuit 400 has a pull-up circuit 401 and a pull-down circuit 402. For example, the circuit components of the drive circuit 400 may be the same as or different from the circuit components of the drive circuit 200 and the drive circuit 300.
[0047] For example, in this embodiment, pull-up circuit 401 is connected to the first node N1 to receive the first selection signal C1, pull-down circuit 402 is connected to the first node N1 to receive the second selection signal C2, and the other connection relationships of the circuit components of drive circuit 400 are the same as those of the circuit components of drive circuit 200, and will not be described again here.
[0048] Figure 4 The driving circuit shown is Figure 2 and Figure 3 Compared to the driving circuits shown, in driving circuit 200 and driving circuit 300, the first selection signal C1 and the second selection signal C2 are different selection signals, while in this embodiment, the first selection signal C1 and the second selection signal C2 are the same selection signal.
[0049] For example, in this embodiment, the first selection signal C1 (i.e., the second selection signal C2) controls the first P-type transistor XP0, the second N-type transistor XN1, and the third N-type transistor XN0. When the first selection signal C1 (second selection signal C2) is low, the channel region of the first P-type transistor XP0 is turned on, the channel region of the second N-type transistor XN1 is turned on, and the channel region of the third N-type transistor XN0 is turned off, and the voltage at the output terminal OUT is the voltage at the pull-up power supply voltage terminal VOP. When the first selection signal C1 (second selection signal C2) is high, the channel region of the first P-type transistor XP0 is turned off, the channel region of the second N-type transistor XN1 is turned off, and the channel region of the third N-type transistor XN0 is turned on, and the voltage at the output terminal OUT is the voltage at the pull-down power supply voltage terminal VSS.
[0050] Technical effects of drive circuit 400 Figure 2 The driving circuit 200 shown has the same technical effect, and will not be described again here.
[0051] Figure 5 A schematic diagram of the circuit structure of another driving circuit 500 provided in at least one embodiment of the present disclosure is shown.
[0052] like Figure 5 As shown, the driving circuit 500 includes a pull-up circuit 501 and a pull-down circuit 502. For example, the circuit structure composed of the pull-up circuit 501 and the pull-down circuit 502 is the same as the circuit structure composed of the pull-up circuit 401 and the pull-down circuit 402.
[0053] For example, in this embodiment, pull-up circuit 501 is connected to the first node N1 to receive a first selection signal C1, and pull-down circuit 502 is connected to the first node N1 to receive a second selection signal C2. The first selection signal C1 and the second selection signal C2 are the same selection signal. The driving circuit 500 also includes a second inverter X0, which is disposed between the first node N1 and the selection signal providing terminal N2, and configured to receive an initial selection signal from the selection signal providing terminal N2 and provide a first selection signal C1 that is inverted from the initial selection signal.
[0054] For example, in this embodiment, the first selection signal C1 controls the first P-type transistor XP0, the second N-type transistor XN1, and the third N-type transistor XN0. When the initial selection signal is high, the first selection signal C1 is low, the channel region of the first P-type transistor XP0 is turned on, the channel region of the second N-type transistor XN1 is turned on, and the channel region of the third N-type transistor XN0 is turned off. The voltage at the output terminal OUT is the voltage of the pull-up power supply voltage terminal VOP. When the initial selection signal is low, the first selection signal C1 is high, the channel region of the first P-type transistor XP0 is turned off, the channel region of the second N-type transistor XN1 is turned off, and the channel region of the third N-type transistor XN0 is turned on. The voltage at the output terminal OUT is the voltage of the pull-down power supply voltage terminal VSS.
[0055] The technical effects of the 500 drive circuit Figure 2 The driving circuit 200 shown has the same technical effect, and will not be described again here.
[0056] Figure 6 A schematic block diagram of an electronic device 600 provided in at least one embodiment of the present disclosure is shown.
[0057] like Figure 6 As shown, the electronic device 600 includes a drive circuit 601, a memristor array 602, and an operation line selection circuit 603.
[0058] For example, the drive circuit 601 can be the drive circuit 200, drive circuit 300, drive circuit 400 or drive circuit 500 mentioned above.
[0059] The memristor array 602 includes multiple memristor cells arranged in an array and multiple operating lines for operating the multiple memristor cells.
[0060] Figure 7 A schematic structure of a memristor array is shown, which, for example, consists of multiple memristor cells arranged in an M x N array, where M and N are both positive integers. Each memristor cell includes a switching element and one or more memristors. Figure 7 In the middle, WL <1> WL <2> ...WL <m>These represent the word lines for the first, second, ..., Mth rows, respectively. The control electrode (e.g., the gate of a transistor) of the switching element in the memristor cell circuit of each row is connected to the corresponding word line of that row; BL <1> BL <2> BL <n>These represent the bit lines of the first, second, ..., Nth columns, respectively. The memristor in the memristor cell circuit of each column is connected to the corresponding bit line of that column; SL <1> SL <2> ……SL <m>These represent the source lines of the first row, second row, ..., Mth row, respectively. The source of the transistor in each row's memristor cell circuit is connected to the corresponding source line of that row. For example, according to Kirchhoff's laws, by setting the state (e.g., resistance value) of the memristor cells and applying corresponding word line signals and bit line signals to the word line and bit line, the above-mentioned memristor array can perform multiply-accumulate calculations in parallel. The embodiments of this disclosure do not limit the implementation method or structure (e.g., 1T1R, 2T2R) of the memristor (cell). This memristor array can be used, for example, for signal processing, multiply-accumulate operations, etc., and the embodiments of this disclosure do not limit this use.
[0061] For example, in some embodiments, the operating lines are word lines, bit lines, or source lines of a memristor array. That is, the driving circuit of the embodiments of this disclosure is used to drive word lines, bit lines, or source lines.
[0062] The operation line selection circuit 603 is configured to receive the operation line address signal and output a first selection signal and a second selection signal to the drive circuit 601. The embodiments of this disclosure do not specifically limit the specific structure and implementation of the operation line selection circuit 603; for example, it can be implemented using analog / digital circuits.
[0063] For example, the electronic device 600 may be implemented using hardware, software, firmware, and any feasible combination thereof, without limitation herein.
[0064] The technical effects of the electronic device 600 and Figures 2-5 The driving circuit shown has the same technical effect, so it will not be described again here.
[0065] Figure 8 A schematic diagram of an electronic device according to at least one embodiment of the present disclosure is shown.
[0066] like Figure 8 As shown, the electronic device includes a drive circuit, a memristor array, and an operation line selection circuit. The structure of the memristor array is as follows: Figure 7 As shown, the memristor array has multiple operating lines, including a first operating line, which is connected to the output of the drive circuit.
[0067] For example, in this embodiment, the operation lines are word lines, and the word line selection circuit receives the word line address signal and outputs a selection signal WLEN for X word lines. <x-1:0>To the drive circuit, the X word lines WL of the memristor array <x-1:0>Connected to the output of the driver circuit, the driver circuit controls the on / off state of the channel region in the memristor cell connected to the word line. In this embodiment, the voltage at the pull-up power supply voltage terminal VOP of the driver circuit is greater than the threshold voltage value of the memristor cell, and the voltage at the pull-down power supply voltage terminal VSS is less than the threshold voltage value of the memristor cell.
[0068] For example, in the drive circuit is Figure 2 or Figure 3 In the case of the driving circuit shown, the pull-up circuit and the pull-down circuit are respectively connected to the operation line selection circuit, and the operation line selection circuit provides a first control signal and a second control signal to control the pull-up circuit and the pull-down circuit respectively.
[0069] For example, in the drive circuit is Figure 4 In the case of the driving circuit shown, the pull-up circuit is connected to the first node to receive the first selection signal, and the pull-down circuit is connected to the first node to receive the second selection signal. The first selection signal and the second selection signal are the same selection signal. The operation line selection circuit provides a selection signal to the first node that is simultaneously the first selection signal and the second selection signal.
[0070] For example, in the drive circuit is Figure 5 In the case of the driving circuit shown, the driving circuit includes a second inverter disposed between the first node and the operation line selection circuit, and configured to receive an initial selection signal from the operation line selection circuit and provide a first selection signal that is inverted from the initial selection signal.
[0071] exist Figure 8 In China, with Figure 5 The driving circuit shown is an example. The word line selection circuit receives the word line address and outputs a selection signal WLEN for X word lines. <x-1:0>The output of the drive circuit is connected to the X word line of the memristor array via the selection signal supply terminal. When the voltage at the output of the drive circuit is pulled up to the voltage of the pull-up power supply terminal VOP, the memristor cell connected to the drive circuit is turned on. When the voltage at the output of the drive circuit is pulled down to the voltage of the pull-down power supply terminal VSS, the memristor cell connected to the drive circuit is turned off.
[0072] The following points need to be explained:
[0073] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.
[0074] (2) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.
[0075] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. The scope of protection of this disclosure should be determined by the scope of protection of the claims. < / m> < / n> < / m>
Claims
1. A driving circuit, comprising a pull-up circuit and a pull-down circuit, in, The pull-up circuit is located between the pull-up power supply voltage terminal and the output terminal, and is configured to receive a first selection signal and use the voltage of the pull-up power supply voltage terminal to pull up the voltage of the output terminal. The pull-down circuit is located between the pull-down power supply voltage terminal and the output terminal, and is configured to receive a second selection signal and use the voltage of the pull-down power supply voltage terminal to pull down the voltage of the output terminal. The pull-up circuit includes a first P-type transistor, a second N-type transistor, and a first inverter. The source of the first P-type transistor and the drain of the second N-type transistor are connected to each other and to the pull-up power supply voltage terminal. The drain of the first P-type transistor is connected to the source of the second N-type transistor and is also connected to the output terminal. One of the gates of the first P-type transistor and the second N-type transistor receives the first selection signal, and the other of the gates of the first P-type transistor and the second N-type transistor receives the first selection signal via the first inverter.
2. The driving circuit according to claim 1, wherein, The pull-down circuit includes a third N-type transistor. The gate of the third N-type transistor receives the second selection signal, the drain of the third N-type transistor is connected to the output terminal, and the source of the third N-type transistor is connected to the pull-down power supply voltage terminal.
3. The driving circuit according to claim 1 or 2, wherein, The first selection signal and the second selection signal are the same selection signal.
4. The driving circuit according to claim 3, wherein, The pull-up circuit is connected to the first node to receive the first selection signal, and the pull-down circuit is connected to the first node to receive the second selection signal, wherein the gate of the first P-type transistor receives the first selection signal, and the gate of the second N-type transistor receives the first selection signal from the first inverter.
5. The driving circuit according to claim 4 further includes a second inverter, wherein, The second inverter is disposed between the first node and the selection signal providing terminal, and is configured to receive an initial selection signal from the selection signal providing terminal and provide a first selection signal that is inverted from the initial selection signal.
6. The driving circuit according to claim 2, wherein, The channel width of the second N-type transistor and the channel width of the third N-type transistor are 1 / 2 to 1 / 3 of the channel width of the first P-type transistor.
7. The driving circuit according to claim 2, wherein, The first P-type transistor is a PMOS transistor, the second N-type transistor is an NMOS transistor, and the third N-type transistor is an NMOS transistor.
8. An electronic device comprising the driving circuit of claim 1.
9. The electronic device according to claim 8, further comprising: A memristor array includes multiple memristor cells arranged in an array and multiple operation lines for operating the multiple memristor cells, wherein the multiple operation lines include a first operation line connected to the output terminal of the driving circuit; and The operation line selection circuit is configured to receive the operation line address signal and output the first selection signal and the second selection signal to the drive circuit.
10. The electronic device according to claim 9, wherein, The operation lines are word lines, bit lines, or source lines of the memristor array.
11. The electronic device according to claim 9, wherein, The pull-up circuit and the pull-down circuit are respectively connected to the operation line selection circuit, and the operation line selection circuit provides the first selection signal and the second selection signal to control the pull-up circuit and the pull-down circuit respectively.
12. The electronic device according to claim 9, wherein, The pull-up circuit is connected to the first node to receive the first selection signal, and the pull-down circuit is connected to the first node to receive the second selection signal. The first selection signal and the second selection signal are the same selection signal. The operation line selection circuit provides a selection signal to the first node, which serves as both the first selection signal and the second selection signal. The gate of the first P-type transistor receives the first selection signal, and the gate of the second N-type transistor receives the first selection signal from the first inverter.
13. The electronic device according to claim 12, wherein, The driving circuit further includes a second inverter, which is disposed between the first node and the operation line selection circuit and configured to receive an initial selection signal from the operation line selection circuit and provide a first selection signal that is inverted from the initial selection signal.