Method and apparatus for reducing fast charge loss in memory cells with dual verification

Abstract

This application relates to double verification for reducing fast charge loss in memory cells. A memory device includes a memory array of memory cells. A page buffer is used to apply a first voltage or a second voltage higher than the first voltage to a bit line during a program verify operation. Control logic, operatively coupled with the page buffer, is used to perform operations including causing a plurality of memory cells to program with a first program pulse, measuring threshold voltages of the memory cells, forming a threshold voltage distribution from the measured threshold voltages, classifying a first subset of the memory cells as having a faster fast charge loss than a second subset of the memory cells based on the threshold voltage distribution, and causing the page buffer to apply the second voltage to the bit line during a program verify operation performed on any of the first subset of memory cells in response to the classifying.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure generally relate to memory sub-systems and, more specifically, to dual verification for reducing fast charge loss in memory cells. BACKGROUND

[0002] A memory sub-system can include one or more memory devices that store data. The memory devices can be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize a memory sub-system to store data at and retrieve data from the memory devices. SUMMARY

[0003] In one aspect, the present application relates to a memory device comprising: a memory array comprising memory cells; a page buffer coupled to a bit line of the memory array, wherein the page buffer is to apply one of a first voltage or a second voltage higher than the first voltage to the bit line during a program verify operation performed on the memory cells; and control logic operatively coupled with the page buffer, the control logic to perform operations comprising: causing a plurality of memory cells to program with a first program pulse; measuring a threshold voltage of each of the plurality of memory cells; forming a threshold voltage distribution from the measured threshold voltages; classifying, based on the threshold voltage distribution, a first subset of the plurality of memory cells as having a faster fast charge loss than a second subset of the plurality of memory cells; and causing, in response to the classifying, the page buffer to apply the second voltage to the bit line during a program verify operation performed on any of the first subset of the plurality of memory cells.

[0004] In another aspect, the application relates to an apparatus comprising: a page buffer coupled to a bit line of a memory array of memory cells, wherein the page buffer comprises: a first transistor path for applying a first voltage on the bit line during a first program verify operation performed on a first subset of a plurality of memory cells of the memory array; and a second transistor path coupled in parallel with the first transistor path, the second transistor path applying a second voltage higher than the first voltage to the bit line during a second program verify operation performed on a second subset of the plurality of memory cells; and control logic operatively coupled with the page buffer, the control logic performing operations comprising: causing the plurality of memory cells to program with a first program pulse; measuring a threshold voltage of each of the plurality of memory cells; forming a threshold voltage distribution from the measured threshold voltages; classifying, based on the threshold voltage distribution, the second subset of the plurality of memory cells as having a faster fast charge loss than a fast charge loss of the first subset of the plurality of memory cells; and in response to the classifying, triggering the second transistor path to apply the second voltage to the bit line during the second program verify performed on the second subset of the plurality of memory cells.

[0005] In another aspect, the application relates to a method of operating an apparatus comprising: a page buffer coupled to a bit line of a memory array of memory cells, the page buffer applying one of a first voltage or a second voltage higher than the first voltage during a program verify operation performed on the memory cells; and control logic coupled with the page buffer, wherein the method of operating the apparatus comprises: causing, by the control logic, a plurality of memory cells to program with a first program pulse; causing, by the control logic, a threshold voltage to be measured at each of the plurality of memory cells; forming, by the control logic, a threshold voltage distribution from the measured threshold voltages; classifying, by the control logic, a first subset of the plurality of memory cells as having a faster fast charge loss than a fast charge loss of a second subset of the plurality of memory cells based on the threshold voltage distribution; and in response to the classifying, causing, by the control logic, the page buffer to apply the second voltage to the bit line during a program verify operation performed on any of the first subset of the plurality of memory cells. BRIEF DESCRIPTION OF DRAWINGS

[0006] The present disclosure will be more fully understood from the following detailed description, taken in connection with the accompanying drawings, in which:

[0007] Figure 1A An example computing system including a memory sub-system is described in accordance with some embodiments.

[0008] Figure 1B Block diagram of a memory device in communication with a memory sub-system controller of a memory sub-system according to an embodiment.

[0009] Figures 2A to 2C Schematic diagram of a portion of a memory cell array in a memory of the type described as usable with reference Figure 1B to embodiments.

[0010] Figure 3 Block schematic diagram of a portion of a memory cell array in a memory of the type described as usable with reference Figure 1B to embodiments.

[0011] Figure 4 Conceptual depiction of a threshold voltage distribution of a plurality of memory cells of a memory array according to an embodiment.

[0012] Figures 5A to 5B Conceptual depiction of a threshold voltage distribution of a plurality of memory cells at different stages after programming for use with various embodiments.

[0013] Figure 6 Set of graphs illustrating the effect of the speed of fast charge loss after a programmed memory cell on a threshold voltage distribution of a set of memory cells according to an embodiment.

[0014] Figure 7A Graph illustrating a single bit line voltage value and a word line voltage value used to perform a program verify operation on memory cells of a memory array according to an embodiment.

[0015] Figure 7B Graph of threshold voltage distributions of two subsets of memory cells programmed at about the same time and a shift in corresponding program verify voltage values after about one second according to an exemplary embodiment.

[0016] Figure 8 Schematic diagram of a page buffer configured to apply two different program verify voltage levels to a bit line during program verify operations of two subsets of memory cells according to an embodiment.

[0017] Figure 9A Graph illustrating two bit line voltage values proposed for a dual verify operation and a word line voltage value usable for a dual verify operation according to an embodiment.

[0018] Figure 9B Graph of a threshold voltage distribution and a natural contraction of the threshold voltage distribution after about one second as a result of applying two bit line voltage values while performing program verify operations on two subsets of memory cells according to an embodiment.

[0019] Figure 10 For a schematic diagram of a page buffer according to another embodiment, the page buffer is configured to apply two different program verify voltage levels to bit lines during program verify operations of two subsets of memory cells.

[0020] Figure 11 For a flowchart of an example method according to some embodiments employing the disclosed page buffer to apply two different program verify voltage levels to bit lines during program verify operations performed on two subsets of memory cells.

[0021] Figure 12 For a block diagram of an example computer system in which embodiments of the disclosure can operate. DETAILED DESCRIPTION

[0022] Embodiments of the disclosure are directed to a dual verify for reducing fast charge loss in memory cells. A memory sub-system can be a storage device, a memory module, or a hybrid of a storage device and a memory module. Examples of storage devices and memory modules are described below in connection with Figure 1A A host system can utilize a memory sub-system including one or more components, such as a memory device that stores data. The host system can provide data to be stored at the memory sub-system and can request data to be retrieved from the memory sub-system.

[0023] A memory device can be a non-volatile memory device. One example of a non-volatile memory device is a NAND memory device. Other examples of non-volatile memory devices are described below in connection with Figure 1A A non-volatile memory device is a package of one or more dies. Each die can include one or more planes. The planes can be grouped into logical units (LUNs). For some types of non-volatile memory devices (e.g., NAND devices), each plane includes a group of physical blocks. Each block includes a group of pages. Each page includes a group of memory cells (“cells”). A cell is an electronic circuit that stores information. Depending on the cell type, a cell can store one or more bits of binary information and has various logical states related to the number of bits being stored. The logical states can be represented by binary values (e.g., “0” and “1”) or combinations of such values.

[0024] A memory device can be composed of bits arranged in a two-dimensional or three-dimensional grid, also referred to as a memory array. Memory cells are fabricated onto a silicon die in an array of columns (also referred to below as bit lines) and rows (also referred to below as word lines). A word line can refer to one or more rows of memory cells of a memory device that are used with one or more bit lines to generate an address for each of the memory cells. The intersection of a bit line and a word line constitutes an address of a memory cell.

[0025] Various access operations can be performed on the memory cells. For example, data can be written to the memory cells, read from the memory cells, and erased from the memory cells. The memory cells can be grouped into units of writing, e.g., pages. For some types of memory devices, a page is the minimum unit of writing. A word line can have multiple pages on the same word line grouped into sub-blocks. Typically, one sub-block is accessed at any given time. Although each sub-block has its own set of select gates coupled to bit lines, the sub-blocks share a common page buffer or sense amplifier.

[0026] In certain memory systems, charge loss occurs within the memory cells, where the threshold voltage (Vt) of the memory cells can shift away from the originally programmed level, making it more difficult to determine the logic state of the memory cell. Quick charge loss (QCL) is the amount of charge loss that is measurable in the threshold voltage, i.e., that is lost from the memory cell shortly after it has been programmed, e.g., within a second or a few seconds. Some memory cells have more traps within the poly channel grain boundaries. Depending on the pre-programmed state of the traps, these traps tend to either trap or release electrons. Memory cells that trap more electrons cause the cell Vt to appear higher, resulting in faster programming speed, e.g., lower program time (“tprog”). Memory cells that release more electrons cause the cell Vt to appear lower, resulting in slower programming speed, e.g., higher tprog. Thus, although two memory cells are programmed at about the same time, the memory cells can experience different amounts of QCL. Furthermore, a cell that exhibits faster QCL shows a larger shift in the threshold voltage distribution than a cell that has slower QCL. Ideally, QCL would be the same in all memory cells, such that the shift in the threshold voltage distribution is predictable, but the structural reality of trapping and releasing electrons, which is somewhat unpredictable, must be compensated for in some way. Additionally, as technology scales, where the cell volume size is decreasing, each additional electron trapped or released will have a greater impact on QCL in advanced memory devices.

[0027] In these memory systems, an increase in charge loss, whether fast charge loss or slow charge loss, also tends to reduce the read window budget (RWB) between the adjacent threshold voltage distributions of the logic states. As various RWBs decrease, the memory device can exhibit a higher bit error rate when reading out discrete logic states from the memory cells, for example, making it more difficult to detect local minima between adjacent threshold voltage distributions. In certain memory systems, when iteratively programming each memory cell using a programming method known as incremental step programming path (ISPP), compensation for the corresponding decrease in different QCL rates and RWBs is improved by shrinking the programming step. This ISPP programming employs a number of sequential programming pulses with intermediate program verify operations, where the programming is locked after exceeding a program verify (PV) voltage. While making the ISPP-based programming step more frequent can compensate for the decreased RWB, using additional programming steps also decreases performance while increasing programming time.

[0028] Aspects of the present disclosure address the above and other deficiencies by modifying a page buffer that is capable of programming (e.g., writing to) and reading data from a memory cell. The modification to the page buffer can enable two different program verify voltages (e.g., a first voltage and a second voltage that is higher than the first voltage) to be applied to a bit line (coupled to the memory cell) during program verify operations performed on two different subsets of memory cells. More specifically, the page buffer can apply the first voltage to the bit line during program verify operations performed on a first subset of memory cells that are classified as having slow QCL, and the second voltage to a second subset of memory cells that are classified as having fast QCL during program verify operations performed on the second subset of memory cells. Thus, the second subset of memory cells can be classified as "fast" compared to the programming speed of the first subset of memory cells. Using two different PV voltage levels can enable standardization of the threshold voltage distributions between the two different subsets of memory cells that differ in QCL rate. In this way, each of the second subset of memory cells, if properly compensated and programmed, will exhibit faster QCL and leave with substantially the same threshold voltage distribution as each of the first subset of memory cells that have slower QCL. It should be noted that the term "slower" can be considered as normal QCL rate for QCL, but of course is slower compared to "fast" QCL rate.

[0029] In these embodiments, the control logic of the local media controller can direct the disclosed processes by causing memory cells (e.g., of a memory array) to be programmed with a first program pulse. The control logic can further cause threshold voltages to be read for each of the memory cells, and form a threshold voltage distribution from the measured threshold voltages. The control logic can then classify a first subset of the plurality of memory cells as having a faster fast charge loss than a second subset of the plurality of memory cells based on the threshold voltage distribution. The control logic can cause a page buffer to apply a second voltage to a bit line during a program verify operation performed on any of the first subset of memory cells in response to the classification. In this way, the control logic can classify the second subset of memory cells as slow QCL cells and the first subset of memory cells as fast QCL cells for the purpose of applying a first PV voltage level and a second PV voltage level, respectively, when performing program verify operations. Later read operations of the first and second subsets of memory cells can be performed without separating read (or sense) voltage levels.

[0030] Accordingly, advantages of systems and methods implemented in accordance with some embodiments of the present disclosure include, but are not limited to, an efficient and effective way to compensate for different fast charge losses between memory cells programmed at about the same point in time. Such compensation is performed at a lower total program time (tprog) compared to other ISPP-related solutions, with similar (or increased) reduction in overall bit error rate due to the compensation. Other advantages will be apparent to those skilled in the art of hardware design and associated algorithms for QCL compensation within a memory subsystem discussed below.

[0031] Figure 1A An example computing system 100 including a memory subsystem 110 is illustrated in accordance with some embodiments of the present disclosure. The memory subsystem 110 can include media, such as one or more volatile memory devices (e.g., memory devices 140), one or more non-volatile memory devices (e.g., memory devices 130), or a combination of such media or memory devices.

[0032] The memory subsystem 110 can be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded Multi-Media Controllers (eMMC) drives, Universal Flash Storage (UFS) drives, Secure Digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0033] The computing system 100 can be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, a car, or other transportation vehicle), an Internet of Things (IoT) enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or such computing device that includes a memory and a processing device.

[0034] The computing system 100 can include a host system 120 coupled to one or more memory sub-systems 110. In some embodiments, the host system 120 is coupled to different types of memory sub-systems 110. Figure 1A One example of a host system 120 coupled to one memory sub-system 110 is illustrated. As used herein, “coupled to” or “coupled with” generally refers to a connection between components that can be an indirect communicative connection or direct communicative connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0035] The host system 120 can include a processor chipset and a software stack executed by the processor chipset. The processor chipset can include one or more cores, one or more caches, a memory controller (e.g., NVDIMM controller), and a storage protocol controller (e.g., PCIe controller, SATA controller). The host system 120 uses the memory sub-system 110, for example, to write data to and read data from the memory sub-system 110.

[0036] The host system 120 can be coupled to the memory sub-system 110 via a physical host interface. Examples of a physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), a Double Data Rate (DDR) memory bus, a Small Computer System Interface (SCSI), a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM socket interface supporting Double Data Rate (DDR)), etc. The physical host interface can be used to transfer data between the host system 120 and the memory sub-system 110. When the memory sub-system 110 is coupled with the host system 120 by a physical host interface (e.g., a PCIe bus), the host system 120 can further utilize an NVM Express (NVMe) interface to access components (e.g., the memory devices 130). The physical host interface can provide an interface for passing control, address, data, and other signals between the memory sub-system 110 and the host system 120. Figure 1AThe memory sub-system 110 is illustrated as an example. In general, the host system 120 can access multiple memory sub-systems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0037] The memory devices 130, 140 can include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., the memory device 140) can be, but are not limited to, random access memories (RAMs), such as dynamic random access memories (DRAMs) and synchronous dynamic random access memories (SDRAMs).

[0038] Some examples of non-volatile memory devices (e.g., the memory device 130) include negative-and (NAND) type flash memories and in-place write memories, such as three-dimensional cross-point (“3D cross-point”) memory devices, which are cross-point arrays of non-volatile memory cells. Cross-point arrays of non-volatile memory cells can perform bit storage based on changes in bulk resistance in conjunction with a stackable cross-gridded data access array. Additionally, in contrast to many flash-based memories, cross-point non-volatile memories can perform in-place write operations, where a non-volatile memory cell can be programmed without being previously erased. NAND type flash memories include, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0039] Each of the memory devices 130 can include one or more arrays of memory cells. One type of memory cell, for example, single-level cells (SLCs), can store one bit of data per cell. Other types of memory cells, for example, multi-level cells (MLCs), triple-level cells (TLCs), quad-level cells (QLCs), and penta-level cells (PLCs), can store multiple bits of data per cell. In some embodiments, each of the memory devices 130 can include one or more arrays of memory cells, such as SLCs, MLCs, TLCs, QLCs, PLCs, or any combination of such. In some embodiments, a particular memory device can include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, a QLC portion, or a PLC portion. The memory cells of the memory devices 130 can be grouped into pages, which can refer to logical units of the memory device used for storing data. For some types of memory (e.g., NAND), pages can be grouped to form blocks.

[0040] While a 3D cross-point array of non-volatile memory cells and non-volatile memory components of NAND type flash memory (e.g., 2D NAND, 3D NAND) are described, the memory devices 130 can be based on any other type of non-volatile memory, such as read-only memory (ROM), phase change memory (PCM), self-selecting memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive-bridge RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), or non-volatile (NOR) flash memory, or electrically erasable programmable read-only memory (EEPROM).

[0041] The memory sub-system controller 115 (or, for simplicity, the controller 115) can communicate with the memory devices 130 to perform operations such as reading data, writing data, or erasing data at the memory devices 130, among other such operations. The memory sub-system controller 115 can include hardware such as one or more integrated circuits and / or discrete components, a buffer memory, or a combination thereof. The hardware can include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory sub-system controller 115 can be a microcontroller, special purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0042] The memory sub-system controller 115 can include a processing device that includes one or more processors (e.g., the processor 117) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory sub-system controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control the operation of the memory sub-system 110, including handling communications between the memory sub-system 110 and the host system 120.

[0043] In some embodiments, the local memory 119 can include memory registers that store memory pointers, fetched data, and the like. The local memory 119 can also include read-only memory (ROM) for storing microcode. While the example memory sub-system 110 in Figure 1A While the example memory sub-system 110 has been shown to include the memory sub-system controller 115, in another embodiment of the disclosure, the memory sub-system 110 does not include the memory sub-system controller 115, but can rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory sub-system).

[0044] Generally, memory sub-system controller 115 can receive commands or operations from host system 120 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to memory devices 130. Memory sub-system controller 115 can be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error-correcting code (ECC) operations, encryption operations, caching operations, and address translations between a logical address (e.g., logical block address (LBA), name space) and a physical address (e.g., physical block address) associated with memory devices 130. Memory sub-system controller 115 can also include host interface circuitry to communicate with host system 120 via a physical host interface. The host interface circuitry can convert commands received from a host system into command instructions to access memory devices 130, as well as convert responses associated with memory devices 130 into information for host system 120.

[0045] Memory sub-system 110 can also include additional circuitry or components not illustrated. In some embodiments, memory sub-system 110 can include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoder and column decoder) that can receive an address from memory sub-system controller 115 and decode the address to access memory devices 130.

[0046] In some embodiments, memory devices 130 include a local media controller 135 that operates in conjunction with memory sub-system controller 115 to perform operations on one or more memory cells of memory devices 130. An external controller (e.g., memory sub-system controller 115) can externally manage memory devices 130 (e.g., perform media management operations on memory devices 130). In some embodiments, memory sub-system 110 is a managed memory device, which is a raw memory device 130 with control logic (e.g., local media controller 135) on-die and a controller (e.g., memory sub-system controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0047] In some embodiments, memory devices 130 include a page buffer 152 that can provide circuitry for programming data to memory cells of memory devices 130 and reading data from memory cells. Page buffer 152 can be designed to apply two different program verify voltages to bit lines used to perform program verify operations on slow QCL cells using a first voltage and fast QCL cells using a second voltage, respectively, where the second voltage is higher than the first voltage.

[0048] In these embodiments, the control logic of the local media controller 135 can be adapted to measure threshold voltage distributions of reads (or other accesses) within different groups of memory cells in order to then classify these memory cells as slow QCL cells or fast QCL cells. For example, the control logic can cause a number of memory cells of a memory array to be programmed with a first program pulse. The control logic can measure threshold voltages of these memory cells and form a threshold voltage distribution from the measured threshold voltages. The control logic can then classify a first subset of the memory cells as having a faster charge loss (QCL) than a second subset of the memory cells based on the threshold voltage distribution. The control logic can finally cause the page buffer to apply a second voltage to the bit line during program verify operations performed on any of the first subset of memory cells and a first voltage to the bit line during program verify operations performed on any of the second subset of memory cells in response to the classification.

[0049] Figure 1B A simplified block diagram of a first device in the form of a memory device 130 in communication with a second device in the form of a memory subsystem controller 115 of a memory subsystem (e.g., memory subsystem 110) in accordance with an embodiment. Some examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, mobile telephones, etc. The memory subsystem controller 115 (e.g., a controller external to the memory device 130) can be a memory controller or other external host device. Figure 1A

[0050] The memory device 130 includes an array 104 of memory cells logically arranged in rows and columns. Memory cells in a logical row are typically connected to the same access line (e.g., word line), while memory cells in a logical column are typically selectively connected to the same data line (e.g., bit line). A single access line can be associated with more than one logical row of memory cells, and a single data line can be associated with more than one logical column. The memory cells of at least a portion of the array 104 of memory cells (not shown in FIG. 1) are capable of being programmed to one of at least two target data states. Figure 1B

[0051] ​​Row decode circuitry 108 and column decode circuitry 111 are provided to decode address signals. Address signals are received and decoded to access the memory cell array 104. The memory device 130 also includes input / output (I / O) control circuitry 112 to manage the input of commands, addresses, and data to the memory device 130 and the output of data and status information from the memory device 130. An address register 114 is in communication with the I / O control circuitry 112 and the row and column decode circuitry 108, 111 to latch address signals prior to decoding. A command register 124 is in communication with the I / O control circuitry 112 and the local media controller 135 to latch incoming commands.

[0052] The controller, e.g., the local media controller 135 internal to the memory device 130, controls access to the memory cell array 104 in response to commands and generates status information for the external memory sub-system controller 115, i.e., the local media controller 135 is configured to perform access operations, e.g., read, program, and / or erase operations, on the memory cell array 104. The local media controller 135 is in communication with the row and column decode circuitry 108, 111 to control the row and column decode circuitry 108, 111 in response to addresses.

[0053] The local media controller 135 is also in communication with a cache register 118 and a data register 121. The cache register 118 latches incoming or outgoing data as directed by the local media controller 135 to temporarily store data while the memory cell array 104 is busy writing or reading other data, respectively. During a program operation, e.g., a write operation, data can be transferred from the cache register 118 to the data register 121 for delivery to the memory cell array 104; new data can then be latched in the cache register 118 from the I / O control circuitry 112. During a read operation, data can be transferred from the cache register 118 to the I / O control circuitry 112 for output to the memory sub-system controller 115; new data can then be transferred from the data register 121 to the cache register 118. The cache register 118 and / or the data register 121 can form, e.g., at least a portion of, a page buffer 152 of the memory device 130. The page buffer 152 can further include sensing devices, e.g., sense amplifiers, to sense data states of memory cells of the memory cell array 104, e.g., by sensing a state of a data line connected to the memory cells. A status register 122 can be in communication with the I / O control circuitry 112 and the local memory controller 135 to latch status information for output to the memory sub-system controller 115.

[0054] The memory device 130 receives control signals at the memory sub-system controller 115 from the local media controller 135 via a control link 132. For example, the control signals can include a chip enable signal CE#, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WE#, a read enable signal RE#, and a write protect signal WP#. Additional or alternative control signals (not shown) can be further received via the control link 132, depending on the nature of the memory device 130. In one embodiment, the memory device 130 receives command signals (which represent commands), address signals (which represent addresses), and data signals (which represent data) from the memory sub-system controller 115 via a multiplexed input / output (I / O) bus 134, and outputs data to the memory sub-system controller 115 via the I / O bus 134.

[0055] For example, a command can be received via input / output (I / O) pins [7:0] of the I / O bus 134 at the I / O control circuitry 112, and can then be written into the command register 124. An address can be received via input / output (I / O) pins [7:0] of the I / O bus 134 at the I / O control circuitry 112, and can then be written into the address register 114. Data can be received via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices at the I / O control circuitry 112, and can then be written into the cache register 118. The data can then be written into the data register 121 for programming the memory cell array 104.

[0056] In an embodiment, the cache register 118 can be omitted, and data can be written directly into the data register 121. Data can also be output via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices. While reference can be made to I / O pins, these can include any electrically conductive node that enables electrical connection to the memory device 130 by an external device (e.g., the memory sub-system controller 115), such as a commonly used electrically conductive pad or electrically conductive bump.

[0057] Those skilled in the art will appreciate that additional circuitry and signals can be provided, and that the Figure 1B memory device 130 has been simplified Figure 1B It is recognized that the functionality described with reference to the various block components can not necessarily be separated in accordance with the different components or component portions of an integrated circuit device. For example, a single component or component portion of an integrated circuit device can be adapted to perform the functionality of multiple block components described. Figure 1Bof more than one block component of the integrated circuit device. Alternatively, one or more components or component portions of the integrated circuit device can be combined to perform Figure 1B the functionality of a single block component of the integrated circuit device. Additionally, although specific I / O pins are described in terms of popular convention for receiving and outputting various signals, it should be noted that other combinations of I / O pins (or other I / O node structures) or other numbers of I / O pins (or other I / O node structures) can be used in various embodiments.

[0058] Figures 2A to 2C is a portion of a memory cell array 200A (e.g., a portion of the memory cell array 104) in a memory of the type as can be used for reference Figure 1B described in accordance with embodiments. The memory array 200A includes access lines (e.g., word lines 2020-202 N ) and data lines (e.g., bit lines 2040-204 M ). The word lines 202 can be connected to global access lines (e.g., global word lines) not shown in Figure 2A For some embodiments, the memory array 200A can be formed over a semiconductor, e.g., can be conductively doped to have a conductivity type, e.g., a p-type conductivity, e.g., to form a P-well, or an n-type conductivity, e.g., to form an n-well.

[0059] The memory array 200A can be arranged in rows (each corresponding to a word line 202) and columns (each corresponding to a bit line 204). Each column can include a string of memory cells (e.g., non-volatile memory cells) connected in series, such as one of the NAND strings 2060-206 M Each NAND string 206 can be connected (e.g., selectively connected) to a common source (SRC) 216 and can include memory cells 2080-208 N The memory cells 208 can represent non-volatile memory cells for storing data. The memory cells 208 of each NAND string 206 can be connected in series between a select gate 210 (e.g., a field effect transistor), such as one of the select gates 2100-210 M (e.g., which can be a source select transistor, commonly referred to as a select gate source), and a select gate 212 (e.g., a field effect transistor), such as one of the select gates 2120-212 M (e.g., which can be a drain select transistor, commonly referred to as a select gate drain). The select gates 2100-210 M may be commonly connected to a select line 214, such as a source select line (SGS), and the select gates 2120-212M They can be connected together to select line 215, such as drain select line (SGD). Although depicted as conventional field-effect transistors, select gates 210 and 212 can utilize a structure similar to (e.g., identical to) memory cell 208. Select gates 210 and 212 can represent a plurality of select gates connected in series, wherein each select gate connected in series is configured to receive the same or independent control signal.

[0060] The source of each select gate 210 can be connected to a common source 216. The drain of each select gate 210 can be connected to a memory cell 2080 of the corresponding NAND string 206. For example, the drain of select gate 2100 can be connected to a memory cell 2080 of the corresponding NAND string 2060. Therefore, each select gate 210 can be configured to selectively connect the corresponding NAND string 206 to the common source 216. The control gate of each select gate 210 can be connected to a select line 214.

[0061] The drain of each select gate 212 can be connected to bit line 204 for the corresponding NAND string 206. For example, the drain of select gate 2120 can be connected to bit line 2040 for the corresponding NAND string 2060. The source of each select gate 212 can be connected to the memory cell 208 of the corresponding NAND string 206. N For example, the source of the select gate 2120 can be connected to the memory cell 208 of the corresponding NAND string 2060. N Therefore, each select gate 212 can be configured to selectively connect the corresponding NAND string 206 to the corresponding bit line 204. The control gate of each select gate 212 can be connected to the select line 215.

[0062] Figure 2A The memory array 200A can be a quasi-two-dimensional memory array and can have a generally planar structure, for example, in which the common source 216, NAND string 206, and bit line 204 extend in a generally parallel plane. Alternatively, Figure 2A The memory array 200A in the memory array may be a three-dimensional memory array, for example, in which the NAND string 206 may extend substantially perpendicular to the plane containing the common source 216 and the plane containing the bit line 204, the bit line being substantially parallel to the plane containing the common source 216.

[0063] A typical configuration of memory cell 208 includes a data storage structure 234 (e.g., floating gate, charge trap, etc.) that determines the data state of the memory cell (e.g., by changing a threshold voltage) and a control gate 236, such as... Figure 2AThe data storage structure 234 can include both conductive structures and dielectric structures, while the control gate 236 is typically formed of one or more conductive materials. In some cases, the memory cell 208 can further have a defined source / drain (e.g., source) 230 and a defined source / drain (e.g., drain) 232. The control gate 236 of the memory cell 208 is connected to (and in some cases formed by) the word line 202.

[0064] A column of memory cells 208 can be a NAND string 206 or a number of NAND strings 206 selectively connected to a given bit line 204. A row of memory cells 208 can be memory cells 208 commonly connected to a given word line 202. A row of memory cells 208 can include, but need not include, all of the memory cells 208 commonly connected to a given word line 202. A row of memory cells 208 can be typically divided into one or more groups of physical pages of memory cells 208, and a physical page of memory cells 208 typically includes every other memory cell 208 commonly connected to a given word line 202. For example, memory cells 208 commonly connected to a word line 202 N and selectively connected to even bit lines 204 (e.g., bit lines 2040, 2042, 2044, etc.) can be one physical page of memory cells 208 (e.g., even memory cells), while memory cells 208 commonly connected to a word line 202 N and selectively connected to odd bit lines 204 (e.g., bit lines 2041, 2043, 2045, etc.) can be another physical page of memory cells 208 (e.g., odd memory cells).

[0065] Although the bit lines 2043-2045 are not explicitly depicted in Figure 2A , it is apparent from the figure that the bit lines 204 of the memory cell array 200A can be numbered consecutively from bit line 2040 to bit line 204 M . Other groupings of memory cells 208 commonly connected to a given word line 202 can also define physical pages of memory cells 208. For certain memory devices, all of the memory cells commonly connected to a given word line can be considered a physical page of memory cells. Portions of a physical page of memory cells (which in some embodiments can still be an entire row) that are read during a single read operation or programmed during a single program operation (e.g., an upper or lower page of memory cells) can be considered a logical page of memory cells. A block of memory cells can include those memory cells configured to be erased together, such as memory cells connected to word lines 2020-202 Nall memory cells of a page (e.g., all NAND strings 206 sharing a common word line 202). Unless explicitly distinguished, a reference to a page of memory cells refers herein to memory cells of a logical page of memory cells. Although discussed in connection with NAND flash memory Figure 2A Examples, the embodiments and concepts described herein are not limited to a particular array architecture or structure, and can include other structures (e.g., SONOS, phase change, ferroelectric, etc.) and other architectures (e.g., AND array, NOR array, etc.).

[0066] Figure 2B Another diagram of a portion of a memory cell array 200B in a memory of the type as can be used in reference Figure 1B described, e.g., as part of the memory cell array 104. Figure 2B correspond to the description provided in reference to Figure 2A Figure 2B Additional details are provided of one example of a three-dimensional NAND memory array structure. The three-dimensional NAND memory array 200B can incorporate vertical structures that can include semiconductor pillars, where a portion of the pillars can act as channel regions of memory cells of NAND strings 206. The NAND strings 206 can each be selectively connected to bit lines 2040to 204 M through select transistors 212 (e.g., which can be drain select transistors, commonly referred to as select gate drains) and to common sources 216 through select transistors 210 (e.g., which can be source select transistors, commonly referred to as select gate sources). Multiple NAND strings 206 can be selectively connected to the same bit line 204. Subsets of NAND strings 206 can be connected to their respective bit lines 204 by applying a bias to select lines 2150to 215 K The select transistors 210 can be activated by applying a bias to select line 214. Each word line 202 can be connected to a plurality of rows of memory cells of the memory array 200B. Rows of memory cells commonly connected to each other through a particular sub-line 202 can be commonly referred to as a layer.

[0067] Figure 2C Another diagram of a portion of a memory cell array 200C in a memory of the type as can be used in reference Figure 1B described, e.g., as part of the memory cell array 104. Figure 2C correspond to the description provided in reference to Figure 2A The memory cell array 200C can include, as Figure 2A ​The depicted series-connected memory cell strings (e.g., NAND strings) 206, access (e.g., word) lines 202, data (e.g., bit) lines 204, select lines 214 (e.g., source select lines), select lines 215 (e.g., drain select lines), and sources 216 of the memory cell array 200A can be a portion of the memory cell array 200C, for example. The depicted series-connected memory cell strings (e.g., NAND strings) 206, access (e.g., word) lines 202, data (e.g., bit) lines 204, select lines 214 (e.g., source select lines), select lines 215 (e.g., drain select lines), and sources 216 of the memory cell array 200B can be a portion of the memory cell array 200C, for example.

[0068] Figure 2C The depicted grouping of the NAND strings 206 into memory cell blocks 250, such as memory cell blocks 2500 through 250 L , can be a portion of the memory cell array 200C, for example. The memory cell blocks 250 can be groupings of memory cells 208 that can be erased together in a single erase operation, sometimes referred to as erase blocks. Each memory cell block 250 can represent those NAND strings 206 that are generally associated with a single select line 215 (e.g., select line 2150). The sources 216 of the memory cell block 2500 can be the same sources 216 as the sources 216 of the memory cell block 250 L . The access lines 202 and select lines 214 and 215 of each memory cell block 2500 through 250 L may be generally selectively connectable to the sources 216. The access lines 202 and select lines 214 and 215 of one memory cell block 250 can not be directly connected to the access lines 202 and select lines 214 and 215 of any other memory cell block 2500 through 250 L , respectively.

[0069] The depicted bit lines 2040 through 204 M may be connected (e.g., selectively connected) to buffer portions 240 that can be a portion of the page buffer 152 of the memory device 130. The buffer portions 240 can correspond to a memory plane (e.g., a group of memory cell blocks 2500 through 250 L ). The buffer portions 240 can include sensing circuitry (which can include sense amplifiers) for sensing data values indicated on the respective bit lines 204.

[0070] Figure 3 is a block diagram of a portion of a memory cell array 300 of the type as can be used in reference Figure 1B . The memory cell array 300 is depicted as having four memory planes 350 (e.g., memory planes 3500 through 3503), each in communication with a respective buffer portion 240, which can collectively form a page buffer 352. While four memory planes 350 are depicted, other numbers of memory planes 350 can collectively be in communication with the page buffer 352. Each memory plane 350 is depicted as including L+1 memory cell blocks 250 (e.g., memory cell blocks 2500 through 250L ).

[0071] Figure 4 Conceptual depiction of threshold voltage ranges for a plurality of memory cells. Figure 4 An example of threshold voltage ranges and their distributions for a population of sixteen-level memory cells, such as QLC memory cells, is illustrated. For example, such memory cells can be programmed to have a threshold voltage (Vt) that falls within one of sixteen different threshold voltage ranges 4300 through 430 15 The width of threshold voltage range 4300 is generally greater than the remaining threshold voltage ranges 4301 through 430 15 Because the memory cells are generally all in a data state corresponding to threshold voltage range 4300, then a subset of those memory cells are subsequently programmed to have a threshold voltage in one of threshold voltage ranges 4301 through 430 15 Because programming operations are generally controlled in a more incremental manner than erase operations, these threshold voltage ranges 4301 through 430 15 may tend to have tighter distributions.

[0072] Threshold voltage ranges 4300, 4301, 4302, 4303, 4304, 4305, 4306, 4307, 4308, 4309, 430 10 , 430 11 , 430 12 , 430 13 , 430 14 , and 430 15Each can represent a respective data state, such as L0, LI, L2, L3, L4, L5, L6, L7, L8, L9, L10, LI 1, L12, L13, L14, and L15, respectively. As an example, if the threshold voltage of a memory cell is within a first threshold voltage range of the sixteen threshold voltage ranges 4300, the memory cell can store a data state L0 having a data value of logical'1111'in this case, and is commonly referred to as an erase state of the memory cell. If the threshold voltage is within a second threshold voltage range of the sixteen threshold voltage ranges 4301, the memory cell can store a data state LI having a data value of logical '0111'in this case. If the threshold voltage is within a third threshold voltage range of the sixteen threshold voltage ranges 4302, the memory cell can store a data state L2 having a data value of logical '0011'in this case, and so on. Table 1 provides one possible correspondence between data states and their corresponding logical data values. Other assignments of data states to logical data values are known or can be contemplated. As used herein, a memory cell that is held in the lowest data state (e.g., the erase state or the L0 data state) will be considered to be programmed to the lowest data state.

[0073] Data state Logical data value Data state Logical data value L0 1111 L8 1100 L1 0111 L9 0100 L2 0011 L10 0000 L3 1011 L11 1000 L4 1001 L12 1010 L5 0001 L13 0010 L6 0101 L14 0110 L7 1101 L15 1110

[0074] Table 1

[0075] Figures 5A to 5B A conceptual depiction of threshold voltage distributions for a plurality of memory cells at different stages after programming for use with embodiments. After programming, the threshold voltages of the memory cells can shift due to phenomena such as, for example, fast charge loss (QCL). QCL is a process that ejects electrons near the gate dielectric interface outward to the channel region of the memory cell, and can cause Vt shifts shortly after a program pulse. As the memory cells are passed through verify operations, the programmed threshold voltages can appear higher due to trapped charge in the gate dielectric. When the memory cells are read after the program operation has completed, the Vt of the memory cells can be lower than the Vt obtained during the program verify operations due to charge leakage from the gate dielectric out to the channel region. The threshold voltages of the memory cells can further shift due to accumulated charge loss within the age of their programmed data, such as the time period between the programmed data and the read data, referred to herein as the data age. Charge loss can also be affected by the age of the memory cells. In contrast to the data age, the memory cell age generally indicates the number of program / erase cycles that the memory cell has undergone. These various phenomena can cause the threshold voltage distributions to widen and shift over time. Various embodiments provide devices and methods that can help mitigate these issues.

[0076] Figure 5AFor a conceptual depiction of threshold voltage distributions of a plurality of memory cells at a time after a program operation (e.g., immediately after a program operation) Figure 5B For a conceptual depiction of those same threshold voltage distributions at some later time after the program operation. Figure 5A of threshold voltage distributions 530 d to 530 d+1 and Figure 5B May represent at a time when a program operation of a memory cell is complete Figure 4 of threshold voltage ranges 4300 to 430 15 of distributions.

[0077] Referring to Figure 5A At a time of program completion, adjacent threshold voltage distributions 530 are typically separated by some margin 532 (e.g., a dead space). Application of a sense voltage (e.g., a read voltage) within the margin 532 to control gates of a plurality of memory cells can be used to distinguish between memory cells of threshold voltage distribution 530 d and any lower threshold voltage distributions) from memory cells of threshold voltage distribution 530 d+1 and any higher threshold voltage distributions) can be conceived without error.

[0078] Referring to Figure 5B Adjacent threshold voltage distributions can have widened such that threshold voltage distribution 530 d and threshold voltage distribution 530 d+1 may have merged, as represented by curve 534 indicating a sum of the two adjacent threshold voltage distributions. Curve 534 can have a local minimum 536. In the event of such a merging of adjacent threshold voltage distributions, distinguishing between memory cells intended to be in threshold voltage distribution 530 d and memory cells intended to be in threshold voltage distribution 530 d+1 will typically result in some errors. For example, application of a sense voltage to control gates of a plurality of memory cells having a voltage level corresponding to local minimum 536 can be expected to result in a minimum number of memory cells having a data state other than their target (e.g., intended) data state, but some number of errors will typically be unavoidable. Application of a sense voltage higher or lower than the voltage level corresponding to local minimum 536 can be expected to result in a greater number of errors. While application of a sense voltage having a voltage level corresponding to local minimum 536 of curve 534 can result in a minimum number of errors, it can be difficult to determine at what voltage level this local minimum 536 occurs.

[0079] Figure 6A set of graphs illustrating the effect of the speed of fast charge loss after programming a set of memory cells on the threshold voltage distribution of the set of memory cells in accordance with embodiments. As illustrated, the width of any given threshold voltage (Vt) distribution is referred to as the programmed Vt sigma (PVS). When programming memory cells (e.g., via ISPP), the threshold voltage distribution can shift shortly after programming due to QCL.

[0080] After reading out or measuring the threshold voltage of a set of memory cells directly after programming, the resulting threshold voltage distribution can be plotted as illustrated in Figure 6 In some embodiments, the control logic can cause the threshold voltage distribution to be measured, for example, by measuring the upper tail of the threshold voltage distribution above an upper voltage value (Vut) and optionally also by measuring the lower tail of the threshold voltage distribution below a lower voltage value (Vlt). The values of Vut and Vlt can be programmed to the control logic, for example, the control logic within the local media controller 135.

[0081] In various embodiments, the control logic can identify a first subset of memory cells as having threshold voltages above the upper voltage value, and a second subset of memory cells as having threshold voltages below or equal to the upper voltage value. In this manner, any memory cell having a voltage threshold above the upper voltage value (Vut) can be classified as fast QCL, and any memory cell having a voltage threshold below or equal to the upper voltage value (Vut) can be classified as slow QCL. In this sense, "slow" QCL is to be understood as not being fast enough, and is not to be considered as "fast" QCL. In some embodiments, any memory cell having a threshold voltage below the lower voltage value (Vlt) can be considered the slowest QCL, thus creating a third subset of memory cells that are separately classified in further embodiments to be discussed.

[0082] In these embodiments, a first voltage can be applied to the bit line for performing program verification (PV) of slow QCL memory cells, and a second voltage higher than the first voltage can be applied to the bit line for performing PV of fast QCL memory cells. In another embodiment, a third voltage can be employed to perform program verification of the "slowest" cells, as an extension to embodiments of the invention, for example, instead of the first voltage.

[0083] Figure 7AA graph of single bit line voltage values and word line voltage values for performing program verify (PV) operations on memory cells of a memory array according to an embodiment is shown for purposes of explanation. Since the bit line voltage remains constant, program verify operations are performed on all memory cells at the same PV voltage level (e.g., 0.4 V) without needing to compensate for the ability of QCL (in advance). The PV voltage of 0.4 V is exemplary only, is intended for explanation, and can vary for different designs.

[0084] Figure 7B A graph of threshold voltage distributions for two subsets of memory cells programmed at about the same time and a shift in corresponding program verify voltage values after about one second according to an exemplary embodiment. Program verify operations are performed on the two subsets of memory cells at the same bit line voltage, as according to Figure 7A , and thus at the same PV voltage level. Because of this, the threshold voltage distributions start at about the same Vt range, e.g., above the PV voltage level. Since one of the subsets of memory cells has a faster QCL than the other subset of memory cells, after about one second (or a few seconds), the threshold voltage distribution of the fast QCL cells drops in Vt faster than the threshold voltage distribution of the slow QCL cells drops in Vt. Thus, Figures 7A to 7B together illustrate the need to compensate for QCL by applying two different PV voltage levels on the bit line.

[0085] Figure 8 A schematic diagram of a page buffer 852 according to an embodiment configured to apply two different program verify voltage levels to a bit line during program verify operations of two subsets of memory cells. For purposes of explanation only, the two subsets of memory cells are referred to as a first subset of memory cells and a second subset of memory cells located in a memory array 104 or 204A, NAND strings 206 are part of the memory array. The page buffer 852 is coupled to a particular NAND string 206 by a particular bit line 204 (e.g., BL 204), e.g., in Figure 2A is explained in more detail. Figure 8 The select transistors 210 and 212 that selectively connect the NAND string 206 to the source 216 and the bit line 204, respectively, are not shown in. While the discussion is directed to use of the page buffer 852 with the NAND string 206, other memory structures and architectures are suitable for use with the page buffer 852 in which a current path from the bit line 204 to the source 216 can be selectively created depending on the data state of the memory cell selected for sensing. Further, the transistors are illustrated as n-channel metal oxide semiconductor (NMOS) transistors to include nFETs, but in other embodiments, the transistors are p-channel metal oxide semiconductor (PMOS) transistors to include pFETs.

[0086] As part of the verify operation, page buffer 852 can verify whether the program pulse successfully changed the threshold voltage of the target memory cell to indicate its desired data state. To accomplish this, page buffer 852 includes a first transistor path (Tl) in which a first bit line (BL) clamp transistor 868 (Blclamp) is pre-charged at the gate, e.g., such that the gate of the first BL clamp transistor 868 is at a particular voltage, e.g., 1 V (for purposes of explanation only). The pre-charge voltage can be applied on a signal line 869 attached to the gate of the first BL clamp transistor 868. After the first BL clamp transistor 868 is pre-charged (e.g., the gate of the first BL clamp transistor 868 and the signal line 869 are pre-charged), the bit line 204 is pre-charged to the pre-charge gate voltage minus the value of the threshold voltage (Vth) of the first BL clamp transistor 868. In the current example, this would be 1 V minus a Vth of 0.6 V, meaning that the bit line 204 is pre-charged to 0.4 V. This 0.4 V can thus be understood as a first voltage corresponding to a first PV voltage level.

[0087] In some embodiments, to supply a selectable source of a second PV voltage level, page buffer 852 further includes a second transistor path (T2) coupled in parallel with the first transistor path. The second transistor path can include a second bit line (BL) clamp transistor 842 (Blclamp h) pre-charged to a second gate voltage that is higher than the first gate voltage. For example, the second BL clamp transistor 842 of the second transistor path can be arranged in common-source common-gate with the first BL clamp transistor 868 of the first transistor path. For purposes of explanation, the gate of the second BL clamp transistor 842 (which can include a signal line 843) is pre-charged to 1.3 V. The pre-charge voltage can be applied on the signal line 843 attached to the gate of the second BL clamp transistor 842. As a result of this pre-charge, the source of the second BL clamp transistor 842 (and the bit line 204 coupled to the source of the second BL clamp transistor 842) is also pre-charged to the gate voltage minus the value of the Vth of the second BL clamp transistor 842. In this example, this would be 1.3 V minus a Vth of 0.6 V, meaning that the source of the second BL clamp transistor 842 and the bit line 204 are pre-charged to 0.7 V. This 0.7 V can thus be understood as a second voltage corresponding to a second PV voltage level. In these embodiments, the second gate voltage is higher than the first gate voltage by the difference between the second voltage and the first voltage.

[0088] In various embodiments, the second transistor path (T2) further includes a trigger transistor 844 coupled in series with the second bit line (BL) clamp transistor 842, e.g., having a source coupled to the drain of the second BL clamp transistor 842. The drain of the trigger transistor 844 is coupled to the bit line 204 that extends through the first transistor path. In these embodiments, a latch is coupled to the gate of the trigger transistor 842. The latch 850 can store a value that indicates whether the memory cell that is to undergo a program verify operation is a fast QCL cell or a slow QCL cell compared to another memory cell. The control logic of the local media controller 135 can store this value in the latch 850. For example, in response to classifying the memory cell as a slow QCL cell, the control logic can store a logical zero ("0") in the latch 850. The latch 850 feeds the logical zero value to the gate of the trigger transistor 844, e.g., on signal line 851, thus causing the trigger transistor to remain off, and the second transistor path is inactive.

[0089] Additionally, for example, in response to classifying the memory cell as a fast QCL cell, the control logic can store a logical one ("1") in the latch 850. The latch 850 feeds the logical one value to the gate of the trigger transistor 844, e.g., on signal line 851, thus turning on the trigger transistor 844. For example, the logical one value is sufficient to be greater than the threshold voltage of the trigger transistor 844. At the same time, the control logic can cause the first BL clamp transistor 868 to turn off, e.g., send a voltage signal to signal line 869 that causes the gate-source voltage to be less than the Vth of the first BL clamp transistor 868. In this way, the second transistor path is activated while the first transistor path is deactivated.

[0090] In related embodiments, after activating one of the first transistor path or the second transistor path, the control logic turns on the transistor 848 (tc_iso) coupled to the sense amplifier 858 of the page buffer 852. For example, the control logic can send a voltage signal to signal line 849 attached to the gate of the transistor 848. In response to the transistor 848 turning on, current from the page buffer 852 can be stored in the capacitor 814 for subsequent PV operations in which the sense amplifier 858 senses the voltage level of the threshold voltage distribution in the connected memory cell. The sa_out signal from the page buffer 852 can be sent back to the control logic (of the local media controller 135) for deciding whether a program pulse (e.g., the first program pulse) successfully changed the threshold voltage of the target memory cell to indicate its desired data state.

[0091] In various embodiments, page buffer 852 also includes a third BL clamp transistor 834 (Blclamp3) and a target transistor 836 (TARGET) coupled between voltage node 846 (e.g., power supply voltage Vcc) and the first transistor path (e.g., at the drain of the first BL clamp transistor 868). Third BL clamp transistor 834 and target transistor 836 can also be pre-charged and provide current flow through page buffer 852 when performing a program verify operation. In some embodiments, control logic sends a voltage signal to the gate of target transistor 836 at a level that causes the amount of current needed to flow through third BL clamp transistor 834 and onto bit line 204.

[0092] In some embodiments, page buffer 852 can similarly be configured to apply more than two program verify voltages to compensate for more than two QCL rates or states, as previously mentioned. For example, these different QCL rates or states can cover a third subset of memory cells, e.g., that are classified with the “slowest” QCL. Thus, a third transistor path (or T3) can be a replicated version of the second transistor path (T2) and include a second latch from which the third transistor path is triggered.

[0093] Figure 9A A graph of two bit line voltage values suggested for a dual verify operation and a word line voltage value that can be used for a dual verify operation is suggested for illustration of the examples according to embodiments. In addition, for reference Figure 8 For the examples discussed, the first bit line voltage value is 0.4 V applied by the first transistor path (Tl) and used for slow QCL cells, and the second bit line voltage value is 0.7 V applied by the second transistor path (T2) for fast QCL cells. As previously discussed, fast QCL cells can be so classified based on having a higher threshold voltage distribution after being programmed by a program pulse (e.g., a first program pulse) compared to the threshold voltage distribution of slow QCL cells. The values of 0.4 V and 0.7 V, respectively, are merely illustrative, as these separate bit line voltages (e.g., different program PV levels) can have other values, e.g., 1 V and 0.7 V, or 1.1 V and 0.8 V, respectively, etc. Moreover, an additional gap in PV levels can be applied to subsequent programming of higher level voltage distributions associated with higher level logic states between two different memory cells, e.g., as would be expected in ISPPP-based programming of multiple logic states.

[0094] Figure 9BThis is a graph showing the threshold voltage distribution as a result of applying two bit line voltage values ​​when performing a programming verification operation on two subsets of memory cells, according to an embodiment, and the natural contraction of the threshold voltage distribution after approximately one second. As can be observed, the threshold voltage distribution of the slow QCL cells exceeds the first programming voltage level (PV1) after programming. Figure 9A The threshold voltage distribution of the fast QCL cell is 0.4 V. In contrast, the threshold voltage distribution of the fast QCL cell is programmed to exceed the higher programming verification (PV) voltage PV2, which is... Figure 9A The voltage level is 0.7 V. Although ISPP-based programming is performed at different PV voltage values, the two threshold voltage distributions of the two memory cells still converge to each other after about a second (or several seconds), for example, closer to the PV1 voltage level. This is due to the faster charge loss of the fast QCL cell.

[0095] Figure 10 This is a schematic diagram of a page buffer 1052 according to another embodiment, which is configured to apply two different programming verification voltage levels to bit lines during programming verification operations of two subsets of memory cells. Figure 10 Page buffer 1052 and Figure 8 Page buffer 852 has some similarities, as it has been similarly numbered. However, instead of two transistor paths, page buffer 1052 is configured to generate two different PV voltage levels, thereby performing programming verification operations via a boost sensing node.

[0096] More specifically, in an alternative embodiment, page buffer 1052 includes a sensing node 1040 coupled between bit line 204 and sensing amplifier 858. For example, sensing node 1040 may be located between transistor 848 of page buffer 1052 and sensing amplifier 858. Page buffer 1052 further includes a boost regulator 1044 that capacitively boosts the voltage of sensing node 1040 and thus changes the voltage threshold of sensing amplifier 858 from a first voltage to a second voltage. It should be remembered that the first voltage is a first programming verification voltage value (reference...). Figure 8 The page buffer 852 is described as 0.4 V) and the second voltage is a second programming verification voltage level higher than the first programming verification voltage value (reference). Figure 8 The page buffer 852 is described as 0.7 V. For example, the boost regulator 1044 can provide a small amount of current to charge the capacitor 1046 coupled between the sensing node 1040 and the boost regulator 1044 to the difference between the first voltage and the second voltage, for example, 0.3 V.

[0097] In various embodiments, page buffer 1052 includes a latch 1050 coupled to boost regulator 1044. Latch 1050 can store a value indicating whether a memory cell undergoing a program verify operation is a fast QCL cell or a slow QCL cell. Control logic of local media controller 135 can store this value in latch 1050. For example, in response to classifying a memory cell as a slow QCL cell, control logic can store a logical zero ("0") in latch 850. The logical zero value is the default input to boost regulator 1044, which therefore takes no action and page buffer 1052 performs a program verify operation at the lower PV voltage level.

[0098] Additionally, for example, in response to classifying a memory cell as a fast QCL cell, control logic can store a logical one ("1") in latch 850. Latch 1050 feeds the logical one value to boost regulator 1044, which is therefore triggered to boost the charge of capacitor 1046 by an incremental increase in voltage that, when added to the first voltage, results in a second voltage that provides the second PV voltage level. Thus, a logical value of one in latch 850 can cause boost regulator 1044 to change the voltage threshold of sense amplifier 858. Since sense amplifier 858 senses at a higher voltage, the PV verify level is effectively changed when a program verify operation is performed by page buffer 1052.

[0099] In related embodiments, after first BL clamp transistor 868 is pre-charged with third BL clamp transistor 834 and target transistor 836 (as discussed with reference to Figure 10 Control logic turns on transistor 848 (tc iso) coupled to sense amplifier 858 of page buffer 1052. For example, control logic can send a voltage signal to signal line 849 attached to the gate of transistor 848. In response to transistor 848 turning on, current from page buffer 852 can be stored in capacitor 814 for subsequent PV operations in which sense amplifier 858 senses the voltage level of the threshold voltage distribution in the connected memory cell. As a program verify operation, the output signal from page buffer 852 can be sent back to control logic (of local media controller 135) for deciding whether a program pulse (e.g., a first program pulse) successfully changed the threshold voltage of the target memory cell to indicate its desired data state.

[0100] Because the boosting performed by boost regulator 1044 can be performed quickly and the program verify operation on sense amplifier 858 can also be performed quickly, the output of page buffer 1052 can be strobed to control logic quickly. For example, where it can take page buffer about 10 ps to measure the current level in a memory cell, for the purposes of the program verify operation, it can take only about 1 ps to measure the voltage level of the threshold voltage distribution. For this reason, page buffer 1052 can optionally include additional circuitry to generate two different sense amplifier (SA) outputs for each of two subsets of memory cells, e.g., if performing program verify operations on two subsets of memory cells in quick succession, one of the two subsets is a slow QCL cell and the other of the two subsets is a fast QCL cell.

[0101] More specifically, in some embodiments, page buffer 1052 includes a first AND gate 1066 to output sense data from a first memory cell, e.g., a fast QCL cell, and receive an input that includes the output of sense amplifier 858 and latch 1050. In this way, when latch 1050 stores a logical value of one, the PV voltage level is a higher second voltage, and first AND gate 1066 outputs a second SA output (sa_out2). Page buffer 1052 can further include an inverter 1062 that receives the output of latch 1050 as an input. Page buffer 1052 can further include a second AND gate 1068 to output sense data from a second memory cell, e.g., at a first SA output (sa_outl), and receive an input that includes the output of sense amplifier 858 and inverter 1062. In this way, when latch 1050 stores a zero value, the boost regulator is not activated and inverter 1062 activates so that second AND gate 1068 outputs first SA output (sa_outl). In these embodiments, each of sa_outl and sa_out2 can be provided to control logic to enable the control logic to know the time at which each of the two different program verify levels has been satisfied by any particular cell that has been classified as slow QCL or fast QCL, respectively.

[0102] In some embodiments, page buffer 1052 can similarly be configured to apply more than two program verify voltages to compensate for more than two QCL rates or states. For example, these different QCL rates or states can cover a third subset of memory cells, e.g., that are classified as “slowest” QCL. For example, a second capacitor can be added in parallel with capacitor f 1046 that enables a second additional amount of voltage to be added to the normal PV voltage level, resulting in a third voltage for performing PV using the third voltage. If this third voltage is used for slowest QCL cells, a capacitor can be used to de-boost the PV voltage.

[0103] Figure 11 A flowchart of an example method 1100 according to some embodiments employing the disclosed page buffer to apply two different program verify voltage levels to a bit line during a program verify operation performed on a memory cell. The method 1100 can be performed by processing logic that can comprise hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method 1100 is performed by a local media controller 135 coupled to a page buffer (e.g., page buffer 152, page buffer 352, page buffer 852, or page buffer 1052) of a memory array having a memory cell. The page buffer is coupled to a bit line of the memory array. The page buffer is used to perform a program verify operation on the memory cell one at a time at one of a first voltage or a second voltage higher than the first voltage. Although shown in a particular sequence or order, unless otherwise specified, the order of the processes can be modified. Thus, the illustrated embodiments should be understood only as examples, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. Additionally, one or more processes can be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible. Figures 1A to 1B

[0104] At operation 1110, a number of memory cells are programmed. For example, the processing logic causes a number of cells of the memory array to be programmed with a first program pulse.

[0105] At operation 1120, the memory cells are read. For example, the processing logic causes a threshold voltage to be measured at each of the memory cells.

[0106] At operation 1130, a threshold voltage distribution is formed. For example, the processing logic forms a threshold voltage distribution from the read threshold voltages.

[0107] At operation 1140, the memory cells are classified. For example, the processing logic classifies a first subset of the memory cells as having a faster charge loss than a second subset of the memory cells based on the threshold voltage distribution. The classification can involve operations including measuring an upper tail position of the threshold voltage distribution above an upper limit voltage value, and identifying the first subset of the memory cells as memory cells having a threshold voltage above the upper limit voltage value.

[0108] ​At operation 1150, a program verify operation is performed. For example, the processing logic causes the page buffer to apply the second voltage to the bit line during a program verify operation performed on any of the first subset of memory cells in response to the classification. The processing logic can further cause the page buffer to apply the first voltage to the bit line during the program verify performed on the first subset of memory cells.

[0109] In reference to Figure 8 In the discussed embodiments, the processing logic can further store a logic value in a latch coupled to a gate of a trigger transistor in response to the classification to cause the trigger transistor to turn on, the trigger transistor activating a parallel transistor path that generates the second voltage for program verify. In reference to Figure 10 In the discussed embodiments, the processing logic can further store a logic value in a latch coupled to a boost regulator to cause the boost regulator to increase a voltage threshold of a sense amplifier to perform program verify at the second voltage. In these ways, the second voltage can be employed by the page buffer in addition to the first voltage to perform program verify at two different voltages.

[0110] Figure 12 An example machine, the example machine being a computer system 1200, within which a set of instructions, for causing the machine to perform any one or more of the methodologies discussed herein, can be executed. In some embodiments, the computer system 1200 can correspond to a host system (e.g., a host system 120 of FIG. 1) that includes, is coupled to, or utilizes a memory sub-system (e.g., a memory sub-system 110 of FIG. 1) or can be used to perform operations of a controller (e.g., execute an operating system to perform operations of a memory sub-system controller 115 of FIG. 1). In alternative embodiments, the machine can be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine can operate in the capacity of a server or a client machine in client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a capacity of a server or a client machine in a cloud computing infrastructure or environment. Figure 1A Figure 1A The machine can be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular telephone, a web appliance, a server, a network router, a switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein. Figure 1A

[0111] The machine can be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular telephone, a web appliance, a server, a network router, a switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0112] ​​The example computer system 1200 includes a processing device 1202, a main memory 1204 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 1210 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 1218, which communicate with each other via a bus 1230.

[0113] Processing device 1202 represents one or more general-purpose processing devices such as a microprocessor, central processing unit, or the like. More particularly, the processing device can be a complex instruction set computing (CISC) microprocessor, reduced instruction set computing (RISC) microprocessor, very long instruction word (VLIW) microprocessor, or

[0114] Data storage system 1218 can include a machine-readable storage medium 1224 (also known as computer-readable medium) on which is stored one or more sets of instructions 1228 or software embodying any one or more of the methodologies or functions described herein. Data storage system 1218 can further include the previously discussed local media controller 135 and page buffer 152. Instructions 1228 can also reside, completely or at least partially, within main memory 1204 and / or processing device 1202 during execution thereof by computer system 1200, main memory 1204 and processing device 1202 also constituting machine-readable storage media. Machine-readable storage medium 1224, data storage system 1218, and / or main memory 1204 can correspond to memory subsystem 110 of FIG. 1. Figure 1A

[0115] In one embodiment, instructions 1226 include instructions to implement a controller (e.g., controller 130 of FIG. 1) corresponding to a device (e.g., device 110 of FIG. 1) to manage access to a memory subsystem (e.g., memory subsystem 110 of FIG. 1). Figure 1A ​instructions to implement functionality of the memory sub-system controller 115). While the machine-readable storage medium 1224 is shown in an example embodiment to be a single medium, the term "machine-readable storage medium" should be taken to include a single medium or multiple media that store one or more sets of instructions. The term "machine-readable storage medium" shall also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine to perform any one or more of the methodologies of the present disclosure. The term "machine-readable storage medium" shall accordingly be taken to include, but not be limited to, solid-state memories, optical media, and magnetic media.

[0116] Some portions of the preceding detailed descriptions have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. The algorithms described herein are generally

[0117] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure can refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage systems.

[0118] The present disclosure also relates to an apparatus for performing the operations herein. This apparatus can be specially constructed for the required purposes, or it can include a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program can be stored in a computer readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0119] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general purpose systems can be used with programs in accordance with the teachings herein, or it can prove convenient to construct a more specialized apparatus to perform the method. The structure for a variety of these systems will appear as described in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages can be used to implement the teachings of the disclosure as described herein.

[0120] The present disclosure can be provided as a computer program product, or software, that can include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic devices) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form accessible by a machine (e.g., a computer). In some embodiments, a machine- readable (e.g., computer-readable) medium includes a machine (e.g., a computer) readable storage medium such as read only memory ("ROM"), random access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory devices, etc.

[0121] In the foregoing specification, embodiments of the present disclosure have been described with reference to specific embodiments thereof. It will be evident that various modifications can be made to the disclosure without departing from the broader spirit and scope of embodiments of the present disclosure as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

Claims

1. A memory device comprising: A memory array, comprising memory cells; A page buffer coupled to a bit line of the memory array, wherein the page buffer is used to apply one of a first voltage or a second voltage higher than the first voltage to the bit line during a programming verification operation performed on the memory cell; and Control logic coupled to the page buffer in an operational manner, the control logic performing operations including the following: This causes multiple memory cells to be programmed with the first programming pulse; Measure the threshold voltage of each of the plurality of memory cells; The threshold voltage distribution of the plurality of memory cells is formed based on the measured threshold voltage; Using the threshold voltage distribution, the first fast charge loss of a first subset of the plurality of memory cells is compared with the second fast charge loss of a second subset of the plurality of memory cells; Based on the comparison, it is determined that the first rapid charge loss is faster than the second rapid charge loss; and In response to the determination, the page buffer applies the second voltage to the bit line during the programming verification operation performed on any of the first subset of the plurality of memory cells until the first subset is programmed to exceed the second voltage.

2. The memory device of claim 1, wherein the operation further comprises identifying the first subset of the plurality of memory cells by means of: Measure the upper tail of the threshold voltage distribution above the upper limit voltage value; and The first subset of the plurality of memory cells is identified as memory cells having a threshold voltage higher than the upper limit voltage value.

3. The memory device of claim 1, wherein the operation further comprises causing the page buffer to apply the first voltage to the bit line during the programming verification operation performed on any of the second subset of the plurality of memory cells.

4. The memory device of claim 3, wherein the operation further comprises identifying the second subset of the plurality of memory cells by means of: Measure the upper tail of the threshold voltage distribution above the upper limit voltage value; and The second subset of the plurality of memory cells is identified as memory cells having a threshold voltage that is lower than or equal to the upper limit voltage value.

5. The memory device of claim 1, wherein the page buffer comprises: The first transistor path includes a first line BL clamp transistor precharged to a first gate voltage; and A second transistor path coupled in parallel with the first transistor path, the second transistor path including a second BL clamping transistor precharged to a second gate voltage, the second gate voltage being higher than the first gate voltage by the difference between the second voltage and the first voltage.

6. The memory device according to claim 5, wherein, The second transistor path further includes: A trigger transistor, which is coupled in series with the second BL clamping transistor; and A latch coupled to the gate of the trigger transistor, wherein the operation further includes storing a logic value in the latch in response to determining that a first subset of the plurality of memory cells has a faster charge loss than a second subset of the plurality of memory cells, the logic value causing the trigger transistor to turn on.

7. The memory device of claim 1, wherein the page buffer comprises: A sensing node, which is coupled between the bit line and the sensing amplifier; A boost regulator that capacitively boosts the voltage of the sensing node and changes the voltage threshold of the sensing amplifier from the first voltage to the second voltage; and A latch coupled to the boost regulator, wherein the operation further includes storing a logic value in the latch in response to determining that a first subset of the plurality of memory cells has a faster charge loss than a second subset of the plurality of memory cells, the logic value causing the boost regulator to change the voltage threshold.

8. The memory device according to claim 7, further comprising: A first AND gate is used to output sensing data from each of the first subset of the plurality of memory cells and to receive an input including the outputs of the sensing amplifier and the latch; An inverter that receives an input including the output of the latch; and A second AND gate is used to output sensing data from each of the second subset of the plurality of memory cells and to receive an input including the outputs of the sensing amplifier and the inverter.

9. A memory device comprising: Page buffers coupled to bit lines of a memory array of memory cells, wherein the page buffers include: A first transistor path is used to apply a first voltage to the bit line during a first programming verification operation performed on a first subset of the plurality of memory cells of the memory array; and A second transistor path coupled in parallel with the first transistor path applies a second voltage higher than the first voltage to the bit line during a second programming verification operation performed on a second subset of the plurality of memory cells; and Control logic coupled to the page buffer in an operational manner, the control logic performing operations including the following: The plurality of memory cells are programmed with a first programming pulse; Measure the threshold voltage of each of the plurality of memory cells; A threshold voltage distribution is formed based on the measured threshold voltage; Based on the threshold voltage distribution, the second subset of the plurality of memory cells is classified as having a fast charge loss that is faster than the fast charge loss of the first subset of the plurality of memory cells; and In response to the classification, the second transistor path is triggered to apply the second voltage to the bit line during the second programming verification operation performed on the second subset of the plurality of memory cells.

10. The memory device of claim 9, wherein the classification includes: Measure the upper tail of the threshold voltage distribution above the upper limit voltage value; and The second subset of the plurality of memory cells is identified as memory cells having a threshold voltage higher than the upper limit voltage value.

11. The memory device of claim 9, wherein the operation further comprises causing the page buffer to apply the first voltage to the bit line via the first transistor path during the first programming verification operation performed on the first subset of the plurality of memory cells.

12. The memory device of claim 11, wherein the operation further comprises classifying the first subset of the plurality of memory cells by means of: Measure the upper tail of the threshold voltage distribution above the upper limit voltage value; and The first subset of the plurality of memory cells is identified as memory cells having a threshold voltage that is lower than or equal to the upper limit voltage value.

13. The memory device of claim 9, wherein the first transistor path includes a first line BL clamping transistor precharged to a first gate voltage, and the second transistor path includes a second BL clamping transistor precharged to a second gate-source voltage, the second gate-source voltage being higher than the first gate voltage by the difference between the second voltage and the first voltage.

14. The memory device according to claim 13, wherein, The second transistor path further includes: A trigger transistor, which is coupled in series with the second BL clamping transistor; and A latch coupled to the gate of the trigger transistor, wherein the operation further includes storing a logic value in the latch in response to classifying a second subset of the plurality of memory cells as having a fast charge loss that is faster than that of the first subset of the plurality of memory cells, the logic value causing the trigger transistor to turn on.

15. A method of operating an apparatus, the apparatus comprising: A page buffer coupled to a bit line of a memory array of memory cells, the page buffer applying either a first voltage or a second voltage higher than the first voltage during a programming verification operation performed on the memory cells; and control logic coupled to the page buffer, wherein the method of operating the device includes: The control logic enables multiple memory cells to be programmed with a first programming pulse. The control logic enables the measurement of a threshold voltage at each of the plurality of memory cells; The control logic forms a threshold voltage distribution for the plurality of memory cells based on the measured threshold voltage. Using the threshold voltage distribution, the first fast charge loss of a first subset of the plurality of memory cells is compared with the second fast charge loss of a second subset of the plurality of memory cells; Based on the comparison, it is determined that the first rapid charge loss is faster than the second rapid charge loss; and In response to the determination, the control logic causes the page buffer to apply the second voltage to the bit line during the programming verification operation performed on any of the first subset of the plurality of memory cells until the first subset is programmed to exceed the second voltage.

16. The method of claim 15, further comprising identifying the first subset of the plurality of memory cells by: Measure the upper tail of the threshold voltage distribution above the upper limit voltage value; and The first subset of the plurality of memory cells is identified as memory cells having a threshold voltage higher than the upper limit voltage value.

17. The method of claim 15, further comprising causing the page buffer to apply the first voltage to the bit line during the programming verification operation performed on the second subset of the plurality of memory cells.

18. The method of claim 17, further comprising identifying the second subset of the plurality of memory cells by: Measure the upper tail of the threshold voltage distribution above the upper limit voltage value; and The second subset of the plurality of memory cells is identified as memory cells having a threshold voltage lower than the upper limit voltage value.

19. The method of claim 15, further comprising, in response to the determination, storing in a latch coupled to the gate of a trigger transistor a logic value that turns on the trigger transistor, the trigger transistor activating a transistor path connected in parallel with the trigger transistor and generating the second voltage for the programming verification operation.

20. The method of claim 15, further comprising storing in a latch coupled to the boost regulator a logic value that causes the boost regulator to increase the voltage threshold of the sense amplifier to perform the programming verification operation at the second voltage.

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