Method for forming semiconductor structure

Abstract

The present application provides a method for forming a semiconductor structure, the method comprising: providing a substrate, a first hard mask layer, a second hard mask layer and a patterned mandrel layer being sequentially formed on the surface of the substrate, the patterned mandrel layer comprising a plurality of first grooves exposing the second hard mask layer; forming a plurality of first isolation openings in the mandrel layer between the first grooves; forming a plurality of second isolation openings in the second hard mask layer exposed by the first grooves; forming side walls on both sides of the first grooves, the side walls not filling up the first grooves, the side walls also filling up the first isolation openings and the second isolation openings; forming a sacrificial layer in the unfilled first grooves; etching the sacrificial layer and part of the mandrel layer to form a plurality of second grooves; continuing to etch the remaining mandrel layer to form a plurality of third grooves; etching along the second grooves and the third grooves into the substrate; removing the first hard mask layer and the second hard mask layer.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for forming a semiconductor structure. Background Art

[0002] Due to the limitation of deep ultraviolet lithography (DUV), it is difficult to achieve the minimum spacing of 28 nanometers in the semiconductor back end of line (BEOL) process in the current 5 nanometer technology. Without the use of extreme ultraviolet lithography (EUV), only complex processes or a large number of masks can be used to form a 28 nanometer metal spacing. This makes the process very complicated and the cost is also high.

[0003] Therefore, it is necessary to provide more effective and reliable technical solutions to simplify the process and thus reduce costs. Summary of the invention

[0004] The present application provides a method for forming a semiconductor structure, which can simplify the process and thus reduce costs.

[0005] The present application provides a method for forming a semiconductor structure, comprising: providing a substrate, wherein a first hard mask layer, a second hard mask layer and a patterned mandrel layer are sequentially formed on the surface of the substrate, wherein the patterned mandrel layer comprises a plurality of first grooves exposing the second hard mask layer; forming a plurality of first isolation openings in the mandrel layer between the first grooves; forming a plurality of second isolation openings in the second hard mask layer exposed by the first grooves; forming side walls on both sides of the first grooves, wherein the side walls do not fill the first grooves and also fill the first isolation openings and the second isolation openings; forming a sacrificial layer in the unfilled first grooves; etching the sacrificial layer and part of the mandrel layer to form a plurality of second grooves; continuing to etch the remaining mandrel layer to form a plurality of third grooves; etching along the second grooves and the third grooves into the substrate; and removing the first hard mask layer and the second hard mask layer.

[0006] In some embodiments of the present application, the width of the first groove is greater than or equal to 42 nanometers.

[0007] In some embodiments of the present application, the width of the second groove and the third groove is less than or equal to 14 nanometers.

[0008] In some embodiments of the present application, the method for forming side walls on both sides of the first groove includes: forming a side wall material layer at the bottom and both sides of the first groove and on the surface of the mandrel layer; etching and removing the side wall material layer on the surface of the mandrel layer and the bottom of the first groove to form the side walls on both sides of the first groove.

[0009] In some embodiments of the present application, the method of etching the sacrificial layer and part of the mandrel layer to form a plurality of second grooves includes: forming a patterned second photoresist layer on the surface of the mandrel layer, the side wall, and the sacrificial layer, the patterned second photoresist layer including a plurality of second openings, and the second openings being located above part of the sacrificial layer and the side wall; using the patterned second photoresist layer as a mask, etching the mandrel layer and the sacrificial layer along the second openings to form the plurality of second grooves; and removing the patterned second photoresist layer.

[0010] In some embodiments of the present application, a width of the second opening is greater than a width of the first groove.

[0011] In some embodiments of the present application, the method of continuing to etch the remaining mandrel layer to form a plurality of third grooves includes: forming a patterned third photoresist layer in the mandrel layer, the side wall surface and the second groove, the patterned third photoresist layer including a plurality of third openings, and the third openings being located above the remaining sacrificial layer and the side wall; using the patterned third photoresist layer as a mask to etch the mandrel layer and the sacrificial layer along the third openings to form the plurality of third grooves; and removing the patterned third photoresist layer.

[0012] In some embodiments of the present application, a width of the third opening is greater than a width of the first groove.

[0013] In some embodiments of the present application, the base includes a substrate and a dielectric layer located on a surface of the substrate.

[0014] In some embodiments of the present application, the method for forming the semiconductor structure further includes: forming a metal layer in the second trench and the third trench, wherein a portion of the metal layer is isolated by the substrate.

[0015] In the method for forming a semiconductor structure described in the present application, 84-nanometer pitch photolithography technology can be used to form a minimum pitch of 28 nanometers, which can simplify the process and thus reduce costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The following drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals represent similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting, exemplary embodiments, and the drawings are only used for the purpose of illustration and description, and are not intended to limit the scope of this application. Other embodiments may also accomplish the inventive intent in this application. It should be understood that the drawings are not drawn to scale. Among them:

[0017] Figure 1 A flow chart of a method for forming a semiconductor structure according to an embodiment of the present application;

[0018] Figures 2 to 25 It is a structural schematic diagram of each step in the method for forming a semiconductor structure described in an embodiment of the present application. DETAILED DESCRIPTION

[0019] The following description provides specific application scenarios and requirements of the present application, with the purpose of enabling those skilled in the art to make and use the content in the present application. It will be apparent to those skilled in the art that various local modifications to the disclosed embodiments are apparent, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present application. Therefore, the present application is not limited to the embodiments shown, but to the widest scope consistent with the claims.

[0020] The technical solution of the present invention is described in detail below in conjunction with the embodiments and drawings.

[0021] Figure 1 The present invention is a flowchart of a method for forming a semiconductor structure according to an embodiment of the present invention.

[0022] refer to Figure 1 As shown, the method for forming the semiconductor structure described in the present application includes:

[0023] Step S110: providing a substrate, wherein a first hard mask layer, a second hard mask layer and a patterned mandrel layer are sequentially formed on a surface of the substrate, wherein the patterned mandrel layer comprises a plurality of first grooves exposing the second hard mask layer;

[0024] Step S120: forming a plurality of first isolation openings in the mandrel layer between the first grooves;

[0025] Step S130: forming a plurality of second isolation openings in the second hard mask layer exposed by the first trench;

[0026] Step S140: forming side walls on both sides of the first trench, wherein the side walls do not completely fill the first trench, but also completely fill the first partition opening and the second partition opening;

[0027] Step S150: forming a sacrificial layer in the unfilled first trench;

[0028] Step S160: etching the sacrificial layer and a portion of the mandrel layer to form a plurality of second grooves;

[0029] Step S170: continue etching the remaining mandrel layer to form a plurality of third grooves;

[0030] Step S180: etching into the substrate along the second groove and the third groove;

[0031] Step S190: removing the first hard mask layer and the second hard mask layer.

[0032] Figures 2 to 25 This is a schematic diagram of the structure of each step in the method for forming a semiconductor structure described in an embodiment of the present application. Figure 1 as well as Figures 2 to 25 The method for forming the semiconductor structure described in the present application is described in detail.

[0033] refer to Figure 2 and Figure 3 As shown, step S110, providing a substrate 100, wherein a first hard mask layer 111 and a second hard mask layer 112 and a patterned mandrel layer 120 are sequentially formed on the surface of the substrate 100, wherein the patterned mandrel layer 120 includes a plurality of first grooves 121 exposing the second hard mask layer 112. Figure 3 is a top view, Figure 2 For along Figure 3 It should be understood that due to the Figure 3 It is a top view, so the substrate 100 and the first hard mask layer 111 located underneath are covered and cannot be observed, and only the topmost patterned mandrel layer 120 and the exposed second hard mask layer 112 can be observed.

[0034] In some embodiments of the present application, the base 100 includes a substrate 101 and a dielectric layer 102 located on the surface of the substrate 101. In the embodiments of the present application, the back-end process of the semiconductor process is used as an example for explanation, and the substrate 101 includes but is not limited to a semiconductor substrate, a semiconductor substrate with active devices formed thereon, etc. The dielectric layer 102 is located on the surface of the substrate 101 and is used to form a metal layer.

[0035] In some embodiments of the present application, the material of the dielectric layer 102 is, for example, a dielectric material such as silicon oxide.

[0036] In some embodiments of the present application, the width of the first groove 121 is greater than or equal to 42 nanometers. In the method for forming the semiconductor structure described in the embodiment of the present application, 84 nanometer spacing photolithography technology is used to form a minimum spacing of 28 nanometers, thereby simplifying the process and reducing costs. The size of the structure (such as the first groove 121) formed by a single photolithography is relatively large, and a smaller structure is subsequently formed step by step through other steps. Of course, in other embodiments of the present application, the width of the first groove 121 can also be larger, that is, using a photolithography technology with a spacing greater than 84 nanometers.

[0037] In some embodiments of the present application, a method of forming the first hard mask layer 111 and the second hard mask layer 112 includes a chemical vapor deposition process or a physical vapor deposition process.

[0038] In some embodiments of the present application, the method for forming the patterned mandrel layer 120 includes: forming a mandrel layer on the surface of the second hard mask layer 112; forming a patterned first photoresist layer on the surface of the mandrel layer, the patterned first photoresist layer including a plurality of first openings; using the patterned first photoresist layer as a mask to etch the mandrel layer along the plurality of first openings to form the first grooves 121; and removing the patterned first photoresist layer.

[0039] refer to Figure 4 and Figure 5 As shown, in step S120, a plurality of first isolation openings 131 exposing the second hard mask layer 112 are formed in the mandrel layer 120 between the first trenches 121. Figure 5 is a top view, Figure 4 For along Figure 5 The cross-section diagram is made by the dotted line. It should be noted that Figure 4 The position of the first partition opening 131 is only indicated by a dotted box, which is not an actual structure. In addition, it should be understood that due to the top view, the first partition opening 131 cannot be directly observed in the top view, but the position of the first partition opening 131 can be indicated in the figure. The same is true for other subsequent opening-type structures. In the top view, the opening structure will overlap with the structure exposed by the opening structure. Sometimes the mark in the figure indicates the position of the opening structure, not the exposed structure under the opening.

[0040] The first isolating opening 131 cuts off part of the mandrel layer 120, and the position of the first isolating opening 131 is also the position where the subsequently formed metal layer is isolated. The size, position and number of the first isolating opening 131 are set according to the design of the metal layer in the back-end process, and the first isolating opening 131 in this application is only a demonstration.

[0041] In some embodiments of the present application, a method for forming the first isolation opening 131 includes wet etching or dry etching.

[0042] refer to Figure 6 and Figure 7 As shown, in step S130, a plurality of second isolation openings 132 exposing the first hard mask layer 111 are formed in the second hard mask layer 112 exposed by the first trench 121. Figure 7 is a top view, Figure 6 For along Figure 7 The cross-section is made by the dashed line.

[0043] The second isolation opening 132 cuts a portion of the second hard mask layer. The size, position and number of the second isolation opening 132 are set according to the design of the metal layer in the back-end process. The second isolation opening 132 in this application is only an example.

[0044] In some embodiments of the present application, a method for forming the second isolation opening 132 includes wet etching or dry etching.

[0045] refer to Figure 8 and Fig. 9 As shown, in step S140, sidewalls 140 are formed on both sides of the first trench 121. The sidewalls 140 do not fill up the first trench 121, but also fill up the first partition opening 131 and the second partition opening 132. Fig. 9 is a top view, Figure 8 For along Fig. 9 The cross-section is made by the dashed line.

[0046] In some embodiments of the present application, the method for forming the sidewalls 140 on both sides of the first trench 121 includes: forming a sidewall material layer at the bottom and both sides of the first trench 121, in the first isolation opening 131 and the second isolation opening 132, and on the surface of the mandrel layer 120; etching and removing the sidewall material layer on the surface of the mandrel layer 120 and the bottom of the first trench 121, and forming the sidewalls 140 on both sides of the first trench 121. When etching the sidewall material layer, the second hard mask layer 112 is used as an etching stop layer, so that the part of the sidewall material layer in the first isolation opening 131 and the second isolation opening 132 below the top surface of the second hard mask layer 112 will not be etched, so that the sidewalls 140 can fill the first isolation opening 131 and the second isolation opening 132.

[0047] In some embodiments of the present application, the material of the sidewall spacer 140 includes titanium oxide, silicon carbide, silicon carbonitride, silicon nitride or silicon oxide.

[0048] In some embodiments of the present application, the method of forming the sidewall material layer may include low-pressure chemical vapor deposition formed by chemical vapor deposition, physical vapor deposition, atomic layer deposition, etc., laser ablation deposition, and selective epitaxial growth process, etc.

[0049] In some embodiments of the present application, a method of etching the spacer material layer includes wet etching or dry etching.

[0050] refer to Fig.10 and Fig.11 As shown, in step S150, a sacrificial layer 150 is formed in the unfilled first trench 121. Fig.11 is a top view, Fig.10 For along Fig.11 The cross-section is made by the dashed line.

[0051] In some embodiments of the present application, the method of forming the sacrificial layer 150 includes a tiger's nest vapor deposition process or a physical vapor deposition process, etc.

[0052] In some embodiments of the present application, the material of the sacrificial layer 150 is the same as that of the mandrel layer 120. The function of the sacrificial layer 150 is to fill the first groove 121, so that the surface of the wafer is flat, which is convenient for the photolithography process. The sacrificial layer 150 will be removed when the mandrel layer 120 is etched in the subsequent process, so the material of the sacrificial layer 150 can be the same or similar to that of the mandrel layer 120, so as to be etched at the same time.

[0053] refer to Figures 12 to 15 As shown, in step S160 , a portion of the sacrificial layer 150 and a portion of the mandrel layer 120 are etched to form a plurality of second grooves 122 .

[0054] refer to Fig.12 and Fig.13 As shown, a patterned second photoresist layer 160 is formed on the surface of the mandrel layer 120, the sidewall 140, and the sacrificial layer 150, and the patterned second photoresist layer 160 includes a plurality of second openings, and the second openings are located above a portion of the sacrificial layer 150 and the sidewall 140. Fig.13 is a top view, Fig.12 For along Fig.13 The cross-section is made by the dashed line.

[0055] In some embodiments of the present application, the width of the second opening is greater than the width of the first groove. The embodiment of the present application uses a photolithography process with a pitch greater than or equal to 84 nanometers, so the width of the second opening in the patterned second photoresist layer 160 is relatively large.

[0056] refer to Fig.14 and Fig.15As shown, the mandrel layer 120 and the sacrificial layer 150 are etched along the second opening using the patterned second photoresist layer 160 as a mask to form the plurality of second grooves 122; and the patterned second photoresist layer 160 is removed. Fig.15 is a top view, Fig.14 For along Fig.15 The cross-section is made by the dashed line.

[0057] Although a photolithography process with a pitch of 84 nanometers or more is used to form a larger second opening, the sidewall 140 below the second opening will not be etched, and only the sacrificial layer 150 and the mandrel layer 120 will be etched, thereby forming a smaller second groove 122.

[0058] In some embodiments of the present application, the width of the second trench 122 is less than or equal to 14 nanometers.

[0059] refer to Figures 16 to 19 As shown, in step S170 , the remaining mandrel layer 120 is continuously etched to form a plurality of third trenches 123 .

[0060] refer to Fig.16 and Fig.17 As shown, a patterned third photoresist layer 161 is formed in the mandrel layer 120, the surface of the sidewall 140 and the second groove 122, and the patterned third photoresist layer 161 includes a plurality of third openings, and the third openings are located above the remaining sacrificial layer 150 and the sidewall 140. Fig.17 is a top view, Fig.16 For along Fig.17 The cross-section is made by the dashed line.

[0061] In some embodiments of the present application, the width of the third opening is greater than the width of the first groove. The present application embodiment uses a photolithography process with a pitch greater than or equal to 84 nanometers, so the width of the third opening in the patterned third photoresist layer 161 is relatively large.

[0062] refer to Fig.18 and Fig.19 As shown, the mandrel layer 120 and the sacrificial layer 150 are etched along the third opening using the patterned third photoresist layer 161 as a mask to form the plurality of third grooves 123; and the patterned third photoresist layer 161 is removed. Fig.19 is a top view, Fig.18 For along Fig.19 The cross-section is made by the dashed line.

[0063] Although the third opening is larger by using a photolithography process with a pitch greater than or equal to 84 nanometers, the sidewall 140 below the third opening will not be etched, and only the sacrificial layer 150 and the mandrel layer 120 will be etched, thereby forming a smaller third trench 123.

[0064] In some embodiments of the present application, the width of the third trench 123 is less than or equal to 14 nanometers.

[0065] In the method for forming a semiconductor structure described in an embodiment of the present application, a large-size pitch lithography process (a lithography process with a pitch greater than or equal to 84 nanometers) is used. Through multiple photolithography operations, the sidewalls are used as barriers during each photolithography operation, so that a plurality of small-size second grooves and third grooves (with a width less than or equal to 14 nanometers) can be formed.

[0066] refer to Fig. 20 and Fig.21 As shown, in step S180, etching is performed along the second groove 122 and the third groove 133 into the substrate 100, specifically, etching is performed until the substrate 101 is exposed. Fig.21 is a top view, Fig. 20 For along Fig.21 The cross-section is made by the dashed line.

[0067] In some embodiments of the present application, a method of etching along the second groove 122 into the substrate 100 includes wet etching or dry etching.

[0068] refer to Figure 22 to Figure 25 As shown, step S190: removing the first hard mask layer 111 and the second hard mask layer 112.

[0069] refer to Fig. 22 and Fig.23 As shown, the sidewall spacer 140, the mandrel layer 120, and the second hard mask layer 112 are removed. Fig.23 is a top view, Fig. 22 For along Fig.23 The cross-section is made by the dashed line.

[0070] refer to Fig.24 and Fig.25 As shown, a metal layer 170 is formed in the second groove 122 and the third groove 123, wherein a portion of the metal layer 170 is isolated by the substrate 100. Fig.25 is a top view, Fig.24 For along Fig.25 The cross-section is made by the dashed line.

[0071] In some embodiments of the present application, the method for forming the metal layer 170 includes: forming a metal material layer on the substrate 100 that completely covers the substrate 100 and the first hard mask layer 111; using a chemical mechanical polishing process to polish the first hard mask layer 111 and the metal material layer until the substrate 100 is exposed to form the metal layer 170, specifically, exposing the dielectric layer 102 in the substrate 100.

[0072] In the method for forming a semiconductor structure described in the present application, 84-nanometer pitch photolithography technology can be used to form a minimum pitch of 28 nanometers, which can simplify the process and thus reduce costs.

[0073] In summary, after reading the contents of this application, those skilled in the art will appreciate that the aforementioned application contents may be presented only in an exemplary manner and may not be restrictive. Although not explicitly stated herein, those skilled in the art will appreciate that this application is intended to encompass various reasonable changes, improvements and modifications to the embodiments. These changes, improvements and modifications are within the spirit and scope of the exemplary embodiments of this application.

[0074] It should be understood that the term "and / or" used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or intermediate elements may also be present.

[0075] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, the term "directly" means that there are no intervening elements. It should also be understood that the terms "comprising," "containing," "including," or "comprising," when used in this application document, indicate the presence of the recited features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0076] It should also be understood that although the terms first, second, third, etc. can be used to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the teachings of the present application, the first element in some embodiments can be referred to as the second element in other embodiments. The same reference numerals or the same reference signs represent the same elements throughout the specification.

[0077] In addition, the present specification describes exemplary embodiments by reference to idealized exemplary cross-sectional views and / or plan views and / or stereograms. Therefore, differences from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are foreseeable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but should include deviations in shapes caused by, for example, manufacturing. For example, an etched region shown as a rectangle will typically have circular or curved features. Therefore, the region shown in the figure is schematic in nature, and its shape is not intended to illustrate the actual shape of the region of the device nor to limit the scope of the exemplary embodiments.

Claims

1. A method for forming a semiconductor structure, It is characterized in that include: Providing a substrate, wherein a first hard mask layer, a second hard mask layer and a patterned mandrel layer are sequentially formed on a surface of the substrate, wherein the patterned mandrel layer comprises a plurality of first grooves exposing the second hard mask layer; forming a plurality of first isolation openings in the mandrel layer between the first grooves; forming a plurality of second isolation openings in the second hard mask layer exposed by the first trench; Forming side walls on both sides of the first groove, wherein the side walls do not fill up the first groove, and the side walls also fill up the first partition opening and the second partition opening; forming a sacrificial layer in the unfilled first trench; Etching the sacrificial layer and a portion of the mandrel layer to form a plurality of second grooves; Continue etching the remaining mandrel layer to form a plurality of third grooves, wherein the width of the first groove is greater than the width of the second groove and the third groove; Etching into the substrate along the second trench and the third trench; The first hard mask layer and the second hard mask layer are removed.

2. The method for forming a semiconductor structure according to claim 1, It is characterized in that The width of the first groove is greater than or equal to 42 nanometers.

3. The method for forming a semiconductor structure according to claim 1, It is characterized in that The width of the second groove and the third groove is less than or equal to 14 nanometers.

4. The method for forming a semiconductor structure according to claim 1, It is characterized in that The method of forming sidewalls on both sides of the first trench comprises: forming a spacer material layer at the bottom and both sides of the first trench and on the surface of the mandrel layer; The sidewall material layer on the surface of the mandrel layer and the bottom of the first trench is removed by etching to form the sidewalls on both sides of the first trench.

5. The method for forming a semiconductor structure according to claim 1, It is characterized in that The method of etching the sacrificial layer and a portion of the mandrel layer to form a plurality of second grooves comprises: Forming a patterned second photoresist layer on the surface of the mandrel layer, the sidewall, and the sacrificial layer, wherein the patterned second photoresist layer includes a plurality of second openings, and the second openings are located above a portion of the sacrificial layer and the sidewall; Using the patterned second photoresist layer as a mask, etching the mandrel layer and the sacrificial layer along the second opening to form the plurality of second grooves; The patterned second photoresist layer is removed.

6. The method for forming a semiconductor structure according to claim 5, It is characterized in that The width of the second opening is greater than the width of the first groove.

7. The method for forming a semiconductor structure according to claim 5, It is characterized in that The method of continuing to etch the remaining mandrel layer to form a plurality of third trenches includes: forming a patterned third photoresist layer in the mandrel layer, the sidewall surface and the second groove, wherein the patterned third photoresist layer comprises a plurality of third openings, and the third openings are located above the remaining sacrificial layer and the sidewall; Using the patterned third photoresist layer as a mask, etching the mandrel layer and the sacrificial layer along the third opening to form the plurality of third grooves; The patterned third photoresist layer is removed.

8. The method for forming a semiconductor structure according to claim 7, It is characterized in that A width of the third opening is greater than a width of the first trench.

9. The method for forming a semiconductor structure according to claim 1, It is characterized in that The base comprises a substrate and a dielectric layer located on the surface of the substrate.

10. The method for forming a semiconductor structure according to claim 1, It is characterized in that Also includes: A metal layer is formed in the second trench and the third trench, wherein a portion of the metal layer is isolated by the substrate.

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