Determination Method, Device, Equipment and Storage Medium for Misalignment of Wafer Test Mapping Diagram

Abstract

The present invention relates to a method, apparatus, device, and storage medium for determining misalignment of a wafer test map. The method includes: obtaining a first position of a marked die in the wafer test map; obtaining a plurality of second positions in the wafer test map corresponding to the first position after making multiple preset-distance overall movements along multiple directions in the wafer test map, and respectively determining the first pass rates of the dice located at the plurality of second positions; determining the misalignment situation between the wafer test map and the wafer according to the first pass rates; wherein the wafer test map is a layout map that maps the positions of all dice on the wafer and provides a basis for the movement of the test head. The method for determining misalignment of the wafer test map in the embodiments of the present application can determine the misalignment situation between the wafer test map and the wafer, is not easily missed in inspection, and has low labor costs.

Description

Technical Field

[0001] The present invention relates to the technical field of wafer testing, and particularly to a method, apparatus, device, and storage medium for determining misalignment of a wafer test map. Background Art

[0002] After a wafer is fabricated, the dies (or chips) on the wafer need to be tested to reject unqualified dies and package qualified dies. This test is also called chip probing (CP), which is used to detect the electrical performance and circuit functions of each die. During chip probing, the test probe (Prober) performs sequential movement tests according to the chip probing recipe map (CP Recipe Map). The chip probing recipe map maps all the wafer positions in the physical wafer, so it can also be called a wafer test map. The wafer test map of each wafer establishes the connection between the two based on the reference die at the edge of the physical wafer. However, due to the limited image recognition accuracy of the test probe, there will be a misalignment (map shift) of the wafer test map relative to the physical wafer, resulting in incorrect test results. Although the misalignment of the wafer test map relative to the physical wafer can be detected by the human eye, it is easy to miss detections and the labor cost is high. Summary of the Invention

[0003] In view of this, an embodiment of the present application provides a method for determining misalignment of a wafer test map to solve at least one problem in the background art.

[0004] To achieve the above object, the technical solution of the present application is realized as follows:

[0005] In a first aspect, an embodiment of the present application provides a method for determining misalignment of a wafer test map, the method including:

[0006] Obtaining a first position of a marked die in the wafer test map;

[0007] Obtaining a plurality of second positions in the wafer test map corresponding to the first position after making multiple preset distances of overall movement along multiple directions in the wafer test map, and respectively determining the first qualification rates of the dies located at the plurality of second positions;

[0008] Determining the misalignment situation between the wafer test map and the wafer according to the first qualification rate; wherein, the wafer test map is a layout map that provides a basis for the movement of the test head and maps all die positions on the wafer.

[0009] Optionally, obtaining multiple second positions in the wafer test map corresponding to the first position after making multiple overall movements of a preset distance in multiple directions in the wafer test map includes:

[0010] Obtaining multiple second positions in the wafer test map corresponding to the first position after making multiple overall movements of a preset distance in the first direction, second direction, third direction, and fourth direction in the wafer test map respectively; wherein, the first direction and the second direction are opposite, the third direction and the fourth direction are opposite, and the first direction and the third direction are perpendicular.

[0011] Optionally, the preset distance of each movement is equal to the pitch between two adjacent die in the direction of the current overall movement in the wafer test map.

[0012] Optionally, the number of movements in any direction during the multiple overall movements of the preset distance is less than or equal to half of the number of die covered by one wafer exposure.

[0013] Optionally, the respectively determining the first pass rate of the die located at multiple second positions includes:

[0014] For each second position, obtaining the test results of the multiple die located at the second position, and determining the first pass rate according to the number of qualified die and the total number of die in the test results.

[0015] Optionally, the determining the misalignment between the wafer test map and the wafer according to the first pass rate includes:

[0016] If any first pass rate is less than the second pass rate of one half, there is a misalignment between the wafer test map and the wafer;

[0017] Or, if any first pass rate is less than a preset value, there is a misalignment between the wafer test map and the wafer; the second pass rate is the pass rate of all die of the currently tested wafer.

[0018] Optionally, the obtaining the first position of the marked die in the wafer test map includes:

[0019] Scanning the wafer test map;

[0020] Obtaining the coordinates of the marked die in the wafer test map in the wafer test map.

[0021] In a second aspect, a device for determining misalignment of a wafer test map is provided in this embodiment, and the device includes:

[0022] An acquisition module, configured to acquire a first position of a marked die in a wafer test mapping diagram;

[0023] A first determination module, configured to acquire multiple second positions in the wafer test mapping diagram corresponding to the first position after making multiple preset-distance overall movements along multiple directions in the wafer test mapping diagram, and respectively determine first qualification rates of the dies located at the multiple second positions;

[0024] A second determination module, configured to determine a misalignment situation between the wafer test mapping diagram and the wafer according to the first qualification rates.

[0025] In a third aspect, an apparatus is provided in this embodiment. The apparatus includes: a memory, a communication bus, and a processor, where:

[0026] The memory is configured to store a program for determining the misalignment of the wafer test mapping diagram;

[0027] The communication bus is configured to implement connection communication between the memory and the processor;

[0028] The processor is configured to execute the program for determining the misalignment of the wafer test mapping diagram to implement the steps of any of the methods described above.

[0029] In a fourth aspect, a computer-readable storage medium is provided in this embodiment. An executable program is stored on the computer-readable storage medium, and when the executable program is executed by a processor, the steps of any of the methods described above are implemented.

[0030] A method for determining the misalignment of a wafer test mapping diagram provided in an embodiment of the present application includes: acquiring a first position of a marked die in the wafer test mapping diagram; acquiring multiple second positions in the wafer test mapping diagram corresponding to the first position after making multiple preset-distance overall movements along multiple directions in the wafer test mapping diagram, and respectively determining first qualification rates of the dies located at the multiple second positions; and determining a misalignment situation between the wafer test mapping diagram and the wafer according to the first qualification rates. The method for determining the misalignment of the wafer test mapping diagram in the embodiment of the present application can determine the misalignment situation between the wafer test mapping diagram and the wafer by acquiring the test qualification rates corresponding to multiple positions after making multiple preset-distance overall movements of the marked die along multiple directions in the wafer test mapping diagram. In this way, the method for determining the misalignment of the wafer test mapping diagram in the embodiment of the present application can determine the misalignment situation between the wafer test mapping diagram and the wafer, is not prone to missed inspections, and has low labor costs.

[0031] Additional aspects and advantages of the present application will be given in part in the following description, become apparent in part from the following description, or be understood through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The drawings described herein are provided to further understand the present application and form a part of the present application. The schematic embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation to the present application. In the drawings:

[0033] Figure 1 is a schematic flowchart of a method for determining misalignment of a wafer test map provided by an embodiment of the present application;

[0034] Figure 2 is a schematic diagram of a wafer test map without misalignment in the method for determining misalignment of a wafer test map provided by an embodiment of the present application;

[0035] Figure 3 is a schematic diagram of a wafer test map with misalignment in the method for determining misalignment of a wafer test map provided by an embodiment of the present application;

[0036] Figure 4 is a schematic structural diagram of a device for determining misalignment of a wafer test map provided by an embodiment of the present application;

[0037] Figure 5 is a schematic diagram of a device in the method for determining misalignment of a wafer test map provided by an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0038] The exemplary embodiments disclosed in the present application will be described in more detail below with reference to the drawings. Although the exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided so that the present application can be more thoroughly understood and the scope of the present application can be fully conveyed to those skilled in the art.

[0039] In the following description, numerous specific details are given to provide a more thorough understanding of the present application. However, it will be apparent to one of ordinary skill in the art that the present application can be practiced without one or more of these details. In other instances, some well-known technical features are not described in order to avoid confusion with the present application; that is, not all features of the actual embodiments are described here, and the well-known functions and structures are not described in detail.

[0040] To thoroughly understand the present application, detailed steps and detailed structures will be presented in the following description to explain the technical solutions of the present application. The preferred embodiments of the present application are described in detail below. However, in addition to these detailed descriptions, the present application can have other embodiments.

[0041] In view of the technical problems in the related art, an embodiment of the present application provides a method for determining misalignment of a wafer test mapping diagram. The method can be implemented by the test equipment in the middle test. The test equipment in the middle test needs to install corresponding software, or can also be implemented by other similar computers, such as Figure 1 As shown, the method includes:

[0042] Step 101: Obtain the first position of the marked die in the wafer test mapping diagram;

[0043] Step 102: Obtain multiple second positions in the wafer test mapping diagram corresponding to the first position after making multiple preset-distance overall movements along multiple directions in the wafer test mapping diagram, and respectively determine the first pass rates of the dice located at the multiple second positions;

[0044] Step 103: Determine the misalignment situation between the wafer test mapping diagram and the wafer according to the first pass rate.

[0045] Here, the wafer test mapping diagram is a layout diagram that maps the positions of all dice on the wafer and provides a basis for the movement of the test head. That is, the wafer test mapping diagram is a virtual middle-test movement diagram generated by the test equipment in the middle test according to the wafer to be tested. After generation, the wafer test mapping diagram is relatively independent of the physical wafer and does not change during the test process. The marked die is an abnormal die on the wafer identified before the test, and is marked in the wafer test mapping diagram and does not need to be tested during the test. There are generally multiple marked dice in the wafer. Therefore, the first position here can be the position of one die or the layout position of multiple dice. Correspondingly, the second position is also the same, and the multiple second positions refer to the multiple second positions in multiple directions, that is, the multiple second positions refer to the second positions in multiple directions. To distinguish it from the wafer test mapping diagram, the wafer can also be called a physical wafer, and the wafer and the physical wafer mentioned below have the same meaning. The test head here can be the test probe described above.

[0046] In the embodiments of the present application, the reason for the misalignment of the wafer test map relative to the physical wafer is as follows: Before the middle test, a wafer test map is made with the first wafer to be tested, including marking the positions of the markdice on the wafer test map. The wafer test map is generated based on the specifications of the wafer to be tested and the positions of the identified reference dice. For the wafer test map corresponding to the first wafer to be tested, since the reference dice are identified manually, there is generally no misalignment. For the subsequent wafers in the same batch, the wafer test map is automatically formed based on the first wafer test map by identifying the positions of the reference dice through the images of the test probes, which may cause misalignment (mapshift) of the wafer test map relative to the physical wafer because the accuracy of image recognition by the test probes is limited or there are errors in the wafer positioning device. According to the recognition principle of the test probes and the wafer positioning device, the misalignment distance of the wafer test map relative to the physical wafer is an integer multiple of the pitch between adjacent dice. That is, if there is misalignment between the wafer test map and the physical wafer, the position of any mapped die in the wafer test map is different from the position of the die in the physical wafer by 1 - N times the pitch between adjacent dice, where N is a positive integer.

[0047] For ease of understanding, the misalignment situation of the wafer test map will be introduced in combination with Figure 2 and Figure 3 . Figure 2 and Figure 3 are respectively schematic diagrams of the wafer test maps without misalignment and with misalignment in the method for determining the misalignment of the wafer test map provided by the embodiments of the present application. As Figure 2 shown, the outermost thick circular border is the border of the physical wafer, and the innermost thin circular border adjacent to the thick circular border is the border of the wafer test map. The gaps between the two borders are relatively uniform on the four sides of up, down, left, and right. Therefore, there is no misalignment of the wafer test map relative to the physical wafer. The position of the reference die in the figure is the black dot on the upper edge, and the coordinates are set to (0, 0). The multiple white small blocks in the figure are the position mappings of the markdice, with a square shape. During testing, they can be set to not be tested, which does not affect the accuracy of the test results.

[0048] As Figure 3As shown in the figure, the outermost thick circular border is the border of the physical wafer, and the thin circular border adjacent to the thick circular border is the border of the wafer test map. The gap between the two borders is smaller on the left side than on the right side. Even on the left side, the border of the wafer test map has touched or exceeded the border of the physical wafer. Therefore, the wafer test map is misaligned relative to the physical wafer. The reference die positions in the figure are the two black dots on the upper edge. The one on the left is the reference die defined by the wafer test map, with coordinates (0,0) in the wafer test map. The one on the right is the reference die defined by the physical wafer mapped in the wafer test map, with coordinates (1,0) in the wafer test map. That is, the positions of the two reference dice are misaligned, and the misalignment distance is the pitch between two adjacent dice. The misalignment of the positions of the two reference dice causes the entire wafer test map to be misaligned relative to the physical wafer, that is, the positions of the marked dice are also misaligned. In the figure, multiple white small blocks are the position mappings of the marked dice. Due to the misalignment, the marked dice in the physical wafer are mapped to the right end of the white small blocks in the wafer test map. However, in the wafer test map, the left end of the white small blocks is misidentified as the position of the marked dice. Therefore, during testing, the dice at the position of the right end of the white small blocks will be tested, that is, the marked dice that should not be tested are tested, while the dice that should be tested, that is, the dice at the position of the left end of the white small blocks, are not tested. Therefore, the misalignment of the wafer test map relative to the physical wafer will affect the accuracy of the test results. Therefore, it is necessary to confirm whether the wafer test map is misaligned relative to the physical wafer.

[0049] Figure 3 In it, the misalignment distance between the wafer test map and the physical wafer is the pitch between two adjacent dice. Since the dice are basically adjacent to each other, it can also be considered that the misalignment distance between the wafer test map and the physical wafer is the width of one die. Therefore, in Figure 3 In it, the positions of the marked dice in the wafer test map and the dice positions in the physical wafer are basically connected together to form a rectangular white small block, that is, two squares form a rectangle. It can be understood that the misalignment distance between the wafer test map and the physical wafer can also be 2 times, 3 times, etc. the pitch between two adjacent dice. In this way, the positions of the marked dice in the wafer test map and the dice positions in the physical wafer will not be connected together.

[0050] The principle of the method for determining the misalignment of the wafer test mapping diagram provided by the embodiments of the present application is as follows: If the wafer test mapping diagram is misaligned relative to the physical wafer, the positions of the marked die in the wafer test mapping diagram will be offset as a whole in a certain direction, that is, the positions of the marked die mapped in the wafer test mapping diagram and the positions of the marked die in the physical wafer are both misaligned. During testing, the following will occur: The marked die on the wafer are tested, while some non-marked die on the wafer are not tested. Moreover, the results of the mismeasured marked die are mostly defective, that is, the qualified rate is very low, or far less than the overall qualified rate of the wafer. And because the misalignment of the wafer test mapping diagram relative to the physical wafer is an overall offset, the distribution of the mismeasured marked die on the wafer remains unchanged. Therefore, the method for determining the misalignment of the wafer test mapping diagram can be: Find the positions of multiple die in the wafer test mapping diagram whose qualified rate is far less than the overall qualified rate of the wafer and is consistent with the distribution of the marked die. Therefore, it is possible to obtain the multiple positions after the marked die in the wafer test mapping diagram are respectively moved as a whole by a preset distance in multiple directions, and then obtain the test qualified rates at the multiple positions respectively. If the test qualified rate at any one position is far less than the overall qualified rate of the wafer, it means that the correct position of the marked die in the physical wafer is found, and it also means that the wafer test mapping diagram is misaligned relative to the physical wafer. If the test qualified rates at all positions are not far less than the overall qualified rate of the wafer, and even close to the overall qualified rate of the wafer, it means that the wafer test mapping diagram is not misaligned relative to the physical wafer.

[0051] Note: The above conclusion of no misalignment is only the conclusion drawn by the test equipment. As for whether there is actually no misalignment, it needs to be further judged by the operator or relevant technical personnel. Exemplarily, the test result shows that the wafer test mapping diagram is not misaligned relative to the physical wafer. Although the conclusion may have errors, it can be considered that the probability of actual misalignment is relatively low. For example, the probability of misalignment may be less than 1%. There are many reasons for the misjudgment of the method of the embodiments of the present application. For example, there is misalignment, but the misalignment distance is very large, resulting in the inability to find the position of the marked die even after obtaining multiple positions after moving as a whole by a preset distance multiple times. Another example is that the original test result record is incorrect, or the test equipment fails, resulting in an incorrect test result itself, etc. However, in general, the probability of these situations occurring is relatively low.

[0052] The method for determining the misalignment of the wafer test mapping diagram according to the embodiments of the present application can determine the misalignment situation between the wafer test mapping diagram and the wafer by obtaining the test qualified rates corresponding to the positions after the marked die in the wafer test mapping diagram are respectively moved as a whole by a preset distance in multiple directions. In this way, the method for determining the misalignment of the wafer test mapping diagram according to the embodiments of the present application can determine the misalignment situation between the wafer test mapping diagram and the wafer, is not prone to missed detection, and has low labor costs.

[0053] In some embodiments, in step 102, the obtaining of a plurality of second positions in the wafer test map corresponding to the overall movement of the first position along multiple directions by a preset distance respectively includes:

[0054] Obtaining a plurality of second positions in the wafer test map corresponding to the overall movement of the first position along the first direction, the second direction, the third direction, and the fourth direction by a preset distance respectively; wherein, the first direction and the second direction are opposite, the third direction and the fourth direction are opposite, and the first direction and the third direction are perpendicular.

[0055] That is, the multiple directions include the first direction, the second direction, the third direction, and the fourth direction. The relative relationship of the above four directions is: the first direction and the second direction are opposite, the third direction and the fourth direction are opposite, and the first direction and the third direction are perpendicular. Therefore, the above four directions can be considered as the X and Y directions in a plane rectangular coordinate system, that is, the four directions of the positive X direction, the negative X direction, the positive Y direction, and the negative Y direction. The setting of the above four directions is related to the direction of the misalignment between the wafer test map and the wafer. Generally speaking, the misalignment is the above four directions.

[0056] In some embodiments, in step 102, the preset distance of each movement is equal to the pitch between two adjacent die in the direction of the current overall movement in the wafer test map. As mentioned above, the misalignment distance between the wafer test map and the physical wafer is generally 1 - N times the pitch between adjacent die, where N is a positive integer. Therefore, the distance of each movement is set to the pitch between two adjacent die in the movement direction. In this way, no omission will occur during the determination process.

[0057] In some embodiments, in step 102, the number of movements in any one of the multiple overall movements by the preset distance is less than or equal to half of the number of die covered by one wafer exposure. Here, the setting of the number of movements in any one direction is determined according to the image recognition accuracy of the test probe and the positioning accuracy of the wafer positioning device, and a sufficient margin is left to ensure that there is no omission and higher efficiency. Generally, the number of die covered by one wafer exposure is related to the size of the wafer, and the misalignment distance between the wafer test map and the physical wafer is generally also related to the size of the wafer. However, in general middle test equipment, the misalignment distance between the wafer test map and the physical wafer generally does not exceed half of the number of die covered by one wafer exposure. Otherwise, it only means that the middle test equipment has failed or needs to be scrapped.

[0058] In some embodiments, in step 102, the separately determining the first pass rate of the die located at the multiple second positions includes:

[0059] For each of the second positions, obtain the test results of the multiple die located at the second position, and determine the first pass rate according to the number of qualified die and the total number of die in the test results. For example, if there are 100 marked die on the wafer, each of the second positions corresponds to a position of 100 die and there are 100 test results. If 90 of them are qualified, the first pass rate is 90%, and if 10 of them are qualified, the first pass rate is 10%.

[0060] In some embodiments, in step 103, the determining the misalignment between the wafer test map and the wafer according to the first pass rate includes:

[0061] If any of the first pass rates is less than half of the second pass rate, there is a misalignment between the wafer test map and the wafer; the second pass rate is the pass rate of all die of the currently tested wafer.

[0062] For example, if the second pass rate is 80%, and if any of the first pass rates is less than 40%, there is a misalignment between the wafer test map and the wafer.

[0063] Otherwise, if all of the first pass rates are greater than or equal to half of the second pass rate, there is no misalignment between the wafer test map and the wafer. For example, if the second pass rate is 80%, and if all of the first pass rates are greater than or equal to 40%, there is no misalignment between the wafer test map and the wafer. As described above, this is the conclusion given by the test equipment. As for whether there is actually no misalignment, it needs to be further judged by the operator or relevant technical personnel.

[0064] In some embodiments, in step 103, the determining the misalignment between the wafer test map and the wafer according to the first pass rate may also include:

[0065] If any of the first pass rates is less than a preset value, there is a misalignment between the wafer test map and the wafer.

[0066] The preset value here may be the above-mentioned second pass rate or other values. Since the pass rate of the marked die is much lower than the normal value, the preset value can be set to a fixed value of 30% or 20% to simplify the calculation process.

[0067] In some embodiments, in step 101, the obtaining the first position of the marked die in the wafer test map includes:

[0068] Scan the wafer test map;

[0069] Obtain the coordinates of the marked die in the wafer test map in the wafer test map.

[0070] The scanning here can be understood as traversing and recording in a preset order. The preset order can be from top to bottom and from left to right. When encountering the position of the corresponding marked die, record the coordinates of the position of the marked die. The coordinates here can be the coordinates of a rectangular coordinate system, that is, the horizontal axis X and the vertical axis Y. For example, the coordinate representation of the reference die described above is (0, 0), indicating that the coordinate value of the X-axis is 0 and the coordinate value of the Y-axis is 0.

[0071] The embodiment of the present application also provides a device 400 for determining the misalignment of a wafer test map, as Figure 4 shown. The device 400 includes an acquisition module 401, a first determination module 402, and a second determination module 403; wherein,

[0072] The acquisition module 401 is configured to acquire the first position of the marked die in the wafer test map.

[0073] The first determination module 402 is configured to acquire multiple second positions in the wafer test map corresponding to the first position after making multiple preset-distance overall movements along multiple directions in the wafer test map, and respectively determine the first pass rates of the dice located at the multiple second positions.

[0074] The second determination module 403 is configured to determine the misalignment situation between the wafer test map and the wafer according to the first pass rate.

[0075] In some embodiments, the first determination module 402 is specifically configured to:

[0076] Acquire multiple second positions in the wafer test map corresponding to the first position after making multiple preset-distance overall movements along the first direction, the second direction, the third direction, and the fourth direction in the wafer test map; wherein, the first direction and the second direction are opposite, the third direction and the fourth direction are opposite, and the first direction and the third direction are perpendicular.

[0077] That is, the multiple directions include the first direction, the second direction, the third direction, and the fourth direction. The relative relationship of the above four directions is: the first direction and the second direction are opposite, the third direction and the fourth direction are opposite, and the first direction and the third direction are perpendicular. Therefore, the above four directions can be considered as the X and Y directions in a rectangular coordinate system, that is, the four directions of the positive X direction, the negative X direction, the positive Y direction, and the negative Y direction.

[0078] In some embodiments, the first determination module 402 is further configured to: obtain a plurality of second positions in the wafer test mapping corresponding to the first position after the first position makes a plurality of overall movements of a preset distance along the first direction, the second direction, the third direction, and the fourth direction in the wafer test mapping. Wherein, the preset distance of each movement is equal to the pitch between two adjacent die in the direction of the current overall movement in the wafer test mapping. As described above, the misalignment distance generated by the wafer test mapping relative to the physical wafer is generally 1-N times the pitch between adjacent die, where N is a positive integer. Therefore, the distance of each movement is set to the pitch between two adjacent die in the movement direction. In this way, no omission will occur during the determination process.

[0079] In some embodiments, the first determination module 402 is further configured to: obtain a plurality of second positions in the wafer test mapping corresponding to the first position after the first position makes a plurality of overall movements of a preset distance along the first direction, the second direction, the third direction, and the fourth direction in the wafer test mapping. Wherein, the number of movements in any direction during the plurality of overall movements of the preset distance is less than or equal to half of the number of die covered by one wafer exposure. Here, the setting of the number of movements in any direction is determined according to the image recognition accuracy of the test probe and the positioning accuracy of the wafer positioning device, and a sufficient margin is left so that no omission will occur and the efficiency is higher.

[0080] In some embodiments, the first determination module 402 is further configured to:

[0081] For each of the second positions, obtain the test results of the plurality of die located at the second position, and determine the first pass rate according to the number of qualified die and the total number of die in the test results. For example, if there are 100 marked die on the wafer, each of the second positions corresponds to the positions of 100 die, and there are 100 test results. If 90 of them are qualified, the first pass rate is 90%, and if 10 of them are qualified, the first pass rate is 10%.

[0082] In some embodiments, the second determination module 403 is specifically configured to:

[0083] If any one of the first pass rates is less than one-half of the second pass rate, determine that there is a misalignment between the wafer test mapping and the wafer; the second pass rate is the pass rate of all die of the currently tested wafer.

[0084] For example, if the second pass rate is 80%, if any one of the first pass rates is less than 40%, determine that there is a misalignment between the wafer test mapping and the wafer. That is, if there is no misalignment in the wafer test mapping, any one of the first pass rates will be relatively close to 80% and will not be lower than 40%.

[0085] In some embodiments, the second determination module 403 is further configured to:

[0086] If any one of the first pass rates is less than a preset value, it is determined that there is a misalignment between the wafer test map and the wafer.

[0087] The preset value here can be the above-mentioned second pass rate or other values. Since the pass rate of the marked die is much lower than the normal value, the preset value can be set to a fixed value of 30% or 20% to simplify the calculation process.

[0088] In some embodiments, the obtaining module 401 is specifically configured to:

[0089] Scan the wafer test map;

[0090] Obtain the coordinates of the marked die in the wafer test map in the wafer test map.

[0091] Here, the scan can be understood as traversing and recording in a preset order. The preset order can be from top to bottom and from left to right. When encountering the position of the corresponding marked die, record the coordinates of the position of the marked die.

[0092] The device 400 in the embodiments of the present invention can be a device provided in a test device or an independent device connected to and communicating with the test device.

[0093] In some embodiments, the device 400 of the embodiments of the present invention can be used to execute the method for determining the misalignment of the wafer test map described in the above embodiments. Of course, it can also include modules for executing any process and / or step in the method for determining the misalignment of the wafer test map described in the above embodiments. For the sake of brevity, it will not be elaborated here.

[0094] The description of the above device embodiments is similar to the description of the above method embodiments and has similar beneficial effects to the method embodiments. For the technical details not disclosed in the device embodiments of the present invention, please refer to the description of the method embodiments of the present invention for understanding.

[0095] Each module included in the embodiments of the present invention can be implemented by a processor in a test device; of course, it can also be implemented by a logic circuit in the test device. During implementation, the processor can be a central processing unit (CPU), a microprocessor (MPU), a digital signal processor (DSP), or a field programmable gate array (FPGA), etc.

[0096] The embodiments of the present application also provide a device 500, as Figure 5 shown, the device 500 includes: a memory 501, a communication bus 502, and a processor 503, where:

[0097] The memory 501 is used to store the program for the method of determining the misalignment of the wafer test map;

[0098] The communication bus 502 is used to realize the connection and communication between the memory 501 and the processor 503;

[0099] The processor 503 is used to execute the program for the method of determining the misalignment of the wafer test map, so as to implement any one or more steps in the method of determining the misalignment of the wafer test map as described above.

[0100] Specifically, the processor 503 may be a central processing unit (CPU), a microprocessor (MPU), a digital signal processor (DSP), or a field programmable gate array (FPGA), etc.; the memory 501 may be implemented by any type of volatile or non-volatile storage device, or a combination thereof. For example, it may be a memory such as FRAM, ROM, PROM, EPROM, EEPROM, flash memory, magnetic surface memory, optical disc, mobile memory, etc., or any combination thereof.

[0101] Specifically, the device 500 further includes: an external communication interface 504, a test probe 505, and a display 506, where:

[0102] The external communication interface 504 can be used to communicate with the outside. The external terminals include a server or a client. The external communication interface 504 may include a wired interface and a wireless interface;

[0103] The test probe 505 can be used to detect the electrical performance and circuit functions of each die;

[0104] The display 506 can be used to display the wafer test map, the probe test position, and the test result.

[0105] The description of the device 500 in the above embodiment is similar to the description of the above method embodiment, and has the same beneficial effects as the method embodiment. For the technical details not disclosed in the device 500 of this embodiment, please refer to the description of the method embodiment in the present invention for understanding.

[0106] The embodiment of the present application further provides a computer-readable storage medium, on which an executable program is stored. When the executable program is executed by a processor, it implements any one or more steps in the method of determining the misalignment of the wafer test map as described above.

[0107] The computer-readable storage medium can be implemented by any type of volatile or non-volatile storage device, or a combination thereof. Among them, the non-volatile memory can be a read-only memory (ROM, Read Only Memory), programmable read-only memory (PROM, Programmable Read-Only Memory), erasable programmable read-only memory (EPROM, Erasable Programmable Read-Only Memory), electrically erasable programmable read-only memory (EEPROM, Electrically Erasable Programmable Read-Only Memory), ferromagnetic random access memory (FRAM, Ferromagnetic Random Access Memory), flash memory (Flash Memory), magnetic surface memory, optical disc, or compact disc read-only memory (CD-ROM, Compact Disc Read-Only Memory); the magnetic surface memory can be a disk memory or a tape memory. The volatile memory can be a random access memory (RAM, Random Access Memory), which is used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static random access memory (SRAM, Static Random Access Memory), synchronous static random access memory (SSRAM, Synchronous Static Random Access Memory), dynamic random access memory (DRAM, Dynamic Random Access Memory), synchronous dynamic random access memory (SDRAM, Synchronous Dynamic Random Access Memory), double data rate synchronous dynamic random access memory (DDRSDRAM, Double Data Rate Synchronous Dynamic Random Access Memory), enhanced synchronous dynamic random access memory (ESDRAM, Enhanced Synchronous Dynamic Random Access Memory), sync link dynamic random access memory (SLDRAM, SyncLink Dynamic Random Access Memory), direct rambus random access memory (DRRAM, Direct Rambus Random Access Memory).The storage media described in the embodiments of the present application are intended to include, but are not limited to, these and any other suitable types of memories.

[0108] The description of the above computer-readable storage media embodiments is similar to the description of the above method embodiments and has similar beneficial effects to the method embodiments. For the technical details not disclosed in the computer-readable storage media embodiments of this embodiment, please refer to the description of the method embodiments in the present invention for understanding.

[0109] In the embodiments of the present invention, if there are terms such as "first", "second", and "third", they are only used to distinguish similar objects and do not represent a specific order for the objects. It can be understood that "first", "second", and "third" can be interchanged in a specific order or sequence when permitted.

[0110] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present application. When used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, determine the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term "and / or" includes any and all combinations of the related listed items.

[0111] It should be understood that the term "one embodiment" or "some embodiments" mentioned throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of the present invention. Therefore, the appearances of "in one embodiment" or "in some embodiments" throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in various embodiments of the present invention, the magnitude of the serial numbers of the above processes does not mean the order of execution, and the order of execution of each process should be determined by its function and internal logic and should not constitute any limitation to the implementation process of the embodiments of the present invention. The serial numbers of the above embodiments of the present invention are only for description and do not represent the advantages or disadvantages of the embodiments.

[0112] In several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of the modules is only a logical function division. In actual implementation, there may be other division methods. For example, multiple modules or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed with each other can be through some interfaces. The indirect coupling or communication connection of devices or modules can be electrical, mechanical, or other forms.

[0113] The modules described above as separate components may or may not be physically separated. The components shown as modules may or may not be physical modules; they can be located in one place or distributed to multiple network modules; some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0114] In addition, in each embodiment of the present invention, all the functional modules can be integrated into one processing module, or each functional module can be separately used as a module, or two or more functional modules can be integrated into one module; the above integrated modules can be implemented in the form of hardware, or in the form of a combination of hardware and software functional modules.

[0115] Those of ordinary skill in the art can understand that all or part of the steps of implementing the above method embodiments can be completed by hardware related to program instructions. The foregoing program can be stored in a computer-readable storage medium. When the program is executed, it executes the steps including the above method embodiments.

[0116] Alternatively, if the above integrated modules of the present invention are implemented in the form of software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the embodiments of the present invention, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing an electronic device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the methods described in the various embodiments of the present invention. In this way, the embodiments of the present invention are not limited to any specific combination of hardware and software.

[0117] It should be understood that the above embodiments are all exemplary and do not cover all possible implementation manners included in the claims. Without departing from the scope of the present disclosure, various deformations and changes can be made on the basis of the above embodiments. Similarly, various technical features of the above embodiments can be arbitrarily combined to form additional embodiments of the present invention that may not be explicitly described. Therefore, the above embodiments only represent several implementation manners of the present invention and do not limit the protection scope of the present invention patent.

Claims

1. A method for determining the misalignment of a wafer test map, characterized in that, The method includes: Obtaining a first position of a marked die in a wafer test map; the marked die is an abnormal die with a low pass rate that is identified before testing and does not need to be tested; the first position is the position of one die or the layout position of multiple dice; Obtaining multiple second positions in the wafer test map corresponding to the first position after the first position is integrally moved a preset distance multiple times in multiple directions in the wafer test map, and respectively determining a first pass rate of the dice located at the multiple second positions; Determining a misalignment situation between the wafer test map and the wafer according to the first pass rate; wherein, the wafer test map is a layout map that maps the positions of all dice on the wafer and provides a basis for the movement of the test head.

2. The method for determining the misalignment of the wafer test mapping diagram according to claim 1, characterized in that The obtaining multiple second positions in the wafer test map corresponding to the first position after the first position is integrally moved a preset distance multiple times in multiple directions in the wafer test map includes: Obtaining multiple second positions in the wafer test map corresponding to the first position after the first position is integrally moved a preset distance multiple times in the first direction, the second direction, the third direction, and the fourth direction in the wafer test map; wherein, the first direction and the second direction are opposite, the third direction and the fourth direction are opposite, and the first direction and the third direction are perpendicular.

3. The method for determining the misalignment of the wafer test mapping diagram according to claim 1 or 2, characterized in that The preset distance of each movement is equal to the pitch between two adjacent dice in the direction of the current integral movement in the wafer test map.

4. The method for determining the misalignment of the wafer test mapping diagram according to claim 3, characterized in that, The number of movements in any direction during the multiple integral movements of the preset distance is less than or equal to half of the number of dice covered by one wafer exposure.

5. The method for determining the misalignment of the wafer test mapping diagram according to claim 1 or 2, characterized in that, The respectively determining a first pass rate of the dice located at the multiple second positions includes: For each of the second positions, obtaining the test results of the multiple dice located at the second position, and determining the first pass rate according to the number of qualified dice and the total number of dice in the test results.

6. The method for determining the misalignment of the wafer test mapping diagram according to claim 1, wherein The determining a misalignment situation between the wafer test map and the wafer according to the first pass rate includes: If any one of the first pass rates is less than half of the second pass rate, there is a misalignment between the wafer test map and the wafer; Or, if any one of the first pass rates is less than a preset value, there is a misalignment between the wafer test map and the wafer; the second pass rate is the pass rate of all dice of the currently tested wafer.

7. The method for determining the misalignment of the wafer test mapping diagram according to claim 1 or 2, characterized in that, The obtaining a first position of a marked die in a wafer test map includes: Scanning the wafer test map; Obtaining the coordinates of the marked die in the wafer test map in the wafer test map.

8. A device for determining misalignment of a wafer test mapping diagram, characterized in that, The device includes: An obtaining module, configured to obtain a first position of a marked die in a wafer test map; the marked die is an abnormal die with a low pass rate that is identified before testing and does not need to be tested; the first position is the position of one die or the layout position of multiple dice; A first determination module, configured to obtain a plurality of second positions in the wafer test map corresponding to the first position after the first position makes a plurality of preset-distance overall movements along multiple directions in the wafer test map, and respectively determine the first pass rates of the dies located at the plurality of second positions; A second determination module, configured to determine the misalignment between the wafer test map and the wafer according to the first pass rate.

9. A device, characterized in that, The device includes: a memory, a communication bus, and a processor, where: The memory is configured to store a program for determining the misalignment of the wafer test map; The communication bus is configured to implement connection communication between the memory and the processor; The processor is configured to execute the program for determining the misalignment of the wafer test map to implement the steps of the method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, An executable program is stored on the computer-readable storage medium, and when the executable program is executed by the processor, the steps of the method according to any one of claims 1 to 7 are implemented.

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