Semiconductor devices

Abstract

Provided is a semiconductor device capable of achieving high integration of semiconductor elements and reducing the inductance generated during operation. The semiconductor device of an embodiment comprises a first substrate, a second substrate, a first metal layer, a second metal layer, a first semiconductor element, a second semiconductor element, a first terminal, a second terminal, a third terminal, a first gate terminal, and a second gate terminal. The second substrate is disposed separately from the first substrate in a first direction and comprises a main wiring and a signal wiring. The main wiring comprises a first wiring layer, a second wiring layer, a third wiring layer, and a fourth wiring layer. The signal wiring comprises a first gate wiring layer disposed on a layer different from the main wiring, and a second gate wiring layer disposed on a layer different from the main wiring. The first semiconductor element is disposed on the first metal layer and comprises a first electrode, a second electrode, and a first gate electrode. The second semiconductor element is disposed on the second metal layer and comprises a third electrode, a fourth electrode, and a second gate electrode.

Description

[0001] This application claims priority based on Japanese Patent Application No. 2021-70759 (filing date: April 20, 2021), the entire contents of which are incorporated herein by reference. Technical Field

[0002] Embodiments of the present invention relate to a semiconductor device. Background Art

[0003] Conventional power modules have semiconductor elements mounted on a substrate, and electrodes of the semiconductor elements are electrically connected to circuits on the substrate via wiring such as fine metal wires.

[0004] If current flows through the wiring, inductance (Ls) is generated. The surge voltage generated at the time of cutoff is expressed by the product of the current change rate and the inductance. As the current change rate increases with the speed of switching on and off, the surge voltage increases. If the surge voltage exceeds the specified voltage, it may break down the semiconductor element, so it is required to reduce the inductance.

[0005] As an example of reducing inductance, there is a method of opposing wirings in which currents flow in opposite directions. However, when a two-dimensional circuit formed on an insulating circuit substrate is used, the inductance cancellation effect caused by the opposing currents between wirings is small. In addition, when wirings are provided on a single insulating circuit substrate, semiconductor elements cannot be integrated at a high density. Summary of the invention

[0006] Embodiments of the present invention provide a semiconductor device capable of achieving high integration of semiconductor elements and reducing inductance generated during operation.

[0007] The semiconductor device of the embodiment comprises a first substrate, a second substrate, a first metal layer, a second metal layer, a first semiconductor element, a second semiconductor element, a first terminal, a second terminal, a third terminal, a first gate terminal and a second gate terminal. The first metal layer is provided on the first substrate. The second metal layer is provided on the first substrate separately from the first metal layer. The second substrate is provided on the first substrate separately from the first substrate in the first direction and comprises a main wiring and a signal wiring. The main wiring comprises a first wiring layer electrically connected to the first metal layer, a second wiring layer electrically connected to the second metal layer, a third wiring layer provided separately from the first wiring layer and the second wiring layer, and a fourth wiring layer electrically connected to the third wiring layer. The signal wiring comprises a first gate wiring layer provided on a layer different from the main wiring in the first direction, and a second gate wiring layer provided on a layer different from the main wiring in the first direction. The first semiconductor element is provided on the first metal layer and comprises a first electrode, a second electrode and a first gate electrode. The first electrode is electrically connected to the first metal layer and is provided on the first surface of the first semiconductor element. The second electrode is electrically connected to the second wiring layer and is provided on the second surface of the first semiconductor element opposite to the first surface. The first gate electrode is electrically connected to the first gate wiring layer and is provided on the second surface of the first semiconductor element. The second semiconductor element is provided on the second metal layer and has a third electrode, a fourth electrode and a second gate electrode. The third electrode is electrically connected to the second metal layer and is provided on the first surface of the second semiconductor element. The fourth electrode is electrically connected to the fourth wiring layer and is provided on the second surface of the second semiconductor element opposite to the first surface. The second gate electrode is electrically connected to the second gate wiring layer and is provided on the second surface of the second semiconductor element. The first terminal is electrically connected to the first wiring layer. The second terminal is electrically connected to the third wiring layer. The third terminal is electrically connected to the second metal layer. The first gate terminal is electrically connected to the first gate wiring layer. The second gate terminal is electrically connected to the second gate wiring layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 (a) is a plan view of the semiconductor device 100 according to the first embodiment. Figure 1 (b) is a plan view of the semiconductor device 100 according to the first embodiment.

[0009] Figure 2 (a) is Figure 1 (b) is a cross-sectional view taken along line AA'. Figure 2 (b) is Figure 1 (b) is a cross-sectional view taken along line BB'. Figure 2 (c) is Figure 1 (b) is a cross-sectional view taken along line CC'.

[0010] Figure 3 (a) is Figure 1 (b) is a cross-sectional view taken along line DD'. Figure 3 (b) is Figure 1 (b) is a cross-sectional view taken along line EE'. Figure 3 (c) is Figure 1 (b) is a cross-sectional view taken along the line FF'. Figure 3 (d) is Figure 1 (b) is a cross-sectional view taken along line GG'.

[0011] Figure 4 This is an equivalent circuit of the semiconductor device 100 according to the first embodiment.

[0012] Figure 5 It is a cross-sectional view of a semiconductor device 101 according to a modification of the first embodiment.

[0013] Figure 6 It is a cross-sectional view of a semiconductor device 102 according to a modification of the first embodiment.

[0014] Figure 7 is a cross-sectional view of a semiconductor device 300 according to a comparative example.

[0015] Figure 8 It is a cross-sectional view of a semiconductor device 200 according to the second embodiment.

[0016] Fig. 9 It is a perspective view of the front and back surfaces of the first semiconductor element 30 and the second semiconductor element 31. DETAILED DESCRIPTION

[0017] Below, while referring to the attached Figure 1 The embodiment of the present invention will be described. In the description, common reference numerals are given to common parts in all the drawings. In addition, the dimensional ratios of the drawings are not limited to the ratios shown in the drawings. In addition, this embodiment does not limit the present invention.

[0018] [First embodiment]

[0019] (Structure of Semiconductor Device 100)

[0020] Reference Figure 1 , Figure 2 , Figure 3 and Figure 4 The detailed structure of the semiconductor device 100 according to the first embodiment will be described. Figure 1 (a) shows a top view of the semiconductor device 100 according to the first embodiment. Figure 1 (b) from Figure 1 (a) is a projection of the second substrate 12 , showing a top view of the first semiconductor element 30 and the second semiconductor element 31 .

[0021] Figure 2 (a) shows Figure 1 The cross-sectional view of the line AA' shown in (b) is as follows: Figure 2 (b) shows Figure 1 The cross-sectional view of the line BB' shown in (b) is Figure 2 (c) shows Figure 1 (b) is a cross-sectional view taken along line CC'. Figure 3 (a) shows Figure 1 The cross-sectional view of the line D-D' shown in (b) is Figure 3 (b) shows Figure 1 The cross-sectional view of the line EE' shown in (b) is Figure 3 (c) shows Figure 1 The cross-sectional view of the line F-F' shown in (b) is Figure 3 (d) shows Figure 1 (b) is a cross-sectional view taken along line GG'. Figure 4 An equivalent circuit of the semiconductor device 100 according to the first embodiment is shown.

[0022] The semiconductor device 100 according to the first embodiment is a power semiconductor module. Figure 4 As shown, this is a so-called "2in1" type module that can form a half-bridge circuit with one module.

[0023] The semiconductor device 100 includes a resin case 1, a cover 2, a first substrate 11, a second substrate 12, a first metal layer 21, a second metal layer 22, a third metal layer 23, a first semiconductor element 30, a second semiconductor element 31, a first conductor layer 41, a second conductor layer 42, a third conductor layer 43, a fourth conductor layer 44, a fifth conductor layer 45, a first gate conductor layer 46, a second gate conductor layer 47, a first terminal 51, a second terminal 52, a third terminal 53, a first gate terminal 54, a second gate terminal 55, a first source sense terminal 56, and a second source sense terminal 57.

[0024] The direction from the first substrate 11 toward the second substrate 12 is defined as the Z direction (first direction). The direction perpendicular to the Z direction is defined as the X direction (second direction), and the direction perpendicular to the X and Z directions is defined as the Y direction (third direction). Figure 1 The semiconductor device 100 shown is a top view of the XY plane. Figure 2 The semiconductor device 100 shown in (a) is a cross-sectional view taken along the XZ plane. Figure 2 (b) Figure 2 (c) and Figure 3The semiconductor device 100 shown in the figure shows a cross-sectional view of the Y-Z plane. In addition, the X direction, the Y direction, and the Z direction are expressed as an orthogonal relationship in this embodiment, but are not limited to being orthogonal, as long as they are mutually intersecting. In addition, for the convenience of explanation, the direction from the first substrate 11 toward the second substrate 12 is called "upper", and the opposite direction is called "lower".

[0025] The first substrate 11 is an insulating substrate having a first surface and a second surface. A first metal layer 21, a second metal layer 22, and a third metal layer 23 are provided on the first surface of the first substrate 11. The second surface of the first substrate 11 is connected to the heat sink 3.

[0026] The resin case 1 is erected around the first substrate 11. The resin case 1 is provided with a cover 2. In addition, the inside of the resin case 1 is filled with silicone rubber 4 as a sealing material. The resin case 1, the cover 2, the first substrate 11 and the silicone rubber 4 have the function of protecting or insulating the components in the semiconductor device 100.

[0027] The first metal layer 21, the second metal layer 22, and the third metal layer 23 are provided on the first surface of the first substrate 11 so as to be separated from each other. The second metal layer 22 is provided between the first metal layer 21 and the third metal layer 23 in the X direction. The first metal layer 21, the second metal layer 22, and the third metal layer 23 are composed of, for example, copper (Cu) plates.

[0028] The second substrate 12 is provided on the first surface side of the first substrate 11 in the Z direction and is separated from the first substrate 11. The second substrate 12 has a first wiring layer 61, a second wiring layer 62, a third wiring layer 63, a fourth wiring layer 64, a fifth wiring layer 65, a first gate wiring layer 66, a second gate wiring layer 67, a first source sensing wiring layer 68, a second source sensing wiring layer 69, a first conductive contact hole 71 (first connection portion), a second conductive contact hole 72 (second connection portion), a third conductive contact hole 73 (third connection portion), a fourth conductive contact hole 74 (fourth connection portion), a fifth conductive contact hole 75 (fifth connection portion), and a sixth conductive contact hole 76 (sixth connection portion).

[0029] The first wiring layer 61 is as follows Figure 1 (a) Figure 2 and Figure 3 As shown in (d), the first wiring layer 61 is provided on the upper part of the second substrate 12 and is located on the upper side of the first metal layer 21. The first wiring layer 61 is provided to extend in the Y direction. Figure 2 (a) and Figure 3 As shown in (d), the first conductive contact hole 71 is provided at the lower part of the second substrate 12 and is located between the first wiring layer 61 and the first metal layer 21. Figure 2 (a) and Figure 3 As shown in (d) of FIG. 1 , a plurality of wiring layers 61 and 65 are provided inside the second substrate 12 between the first wiring layer 61 and the fifth wiring layer 65 to electrically connect the first wiring layer 61 and the fifth wiring layer 65 .

[0030] The third wiring layer 63 is as follows Figure 1 (a) Figure 2 (a) Figure 3 (a) and Figure 3 As shown in (b), the third wiring layer 63 is provided on the upper part of the second substrate 12 and is located on the upper side of the second metal layer 22 and the third metal layer 23. The third wiring layer 63 is provided extending in the Y direction and is adjacent to the first wiring layer 61 in the X direction. Figure 2 (a) and Figure 3 As shown in (b), the second conductive contact hole 72 is provided at the lower part of the second substrate 12 and is located on the upper side of the second metal layer 22 and the third metal layer 23. Figure 2 As shown in (a), the second conductive contact hole 72 is provided in the second substrate 12 between the third wiring layer 63 and the fourth wiring layer 64 to electrically connect the third wiring layer 63 and the fourth wiring layer 64. In addition, although not shown in the figure, a plurality of second conductive contact holes 72 can be provided in the Y direction similarly to the first conductive contact holes 71.

[0031] The second wiring layer 62 is as follows Figure 2 (a) Figure 2 (c) and Figure 3 As shown in (c), the second wiring layer 62 is disposed at the lower portion of the second substrate 12 and is located above the first metal layer 21 and the second metal layer 22. The second wiring layer 62 is located between the fourth wiring layer 64 and the fifth wiring layer 65 in the X direction. In addition, the second wiring layer 62 is disposed separately from the first wiring layer 61 in the Z direction. Furthermore, a portion of the second wiring layer 62 is disposed in a manner opposite to a portion of the first wiring layer 61.

[0032] The first gate wiring layer 66 is as follows Figure 2 (a)~ Figure 2 As shown in (c) of FIG. 1 , the first gate wiring layer 66 is provided in a layer different from the first wiring layer 61 and the second wiring layer 62 in the Z direction. Specifically, the first gate wiring layer 66 is provided inside the second substrate 12 and extends in the Y direction.

[0033] The second gate wiring layer 67 is as follows Figure 2 (a) Figure 3 (a) and Figure 3As shown in (b), the second gate wiring layer 67 is provided in a layer different from the third wiring layer 63 and the fourth wiring layer 64 in the Z direction. Specifically, the second gate wiring layer 67 is provided inside the second substrate 12 and extends in the Y direction. In addition, inside the second substrate 12, the first gate wiring layer 66 and the second gate wiring layer 67 are adjacent to each other in the X direction.

[0034] The first source sensing wiring layer 68 is as follows Figure 2 (a)~ Figure 2 As shown in (c), the first source sense wiring layer 68 is provided in a layer different from the first wiring layer 61 and the second wiring layer 62 in the Z direction. Specifically, the first source sense wiring layer 68 is provided inside the second substrate 12 and extends in the Y direction.

[0035] The second source sensing wiring layer 69 is as follows Figure 2 (a) Figure 3 (a) and Figure 3 As shown in (b), the second source sense wiring layer 69 is provided in a layer different from the third wiring layer 63 and the fourth wiring layer 64 in the Z direction. Specifically, the second source sense wiring layer 69 is provided inside the second substrate 12 and extends in the Y direction. In addition, inside the second substrate 12, the first source sense wiring layer 68 and the second source sense wiring layer 69 are adjacent to each other in the X direction.

[0036] In addition, Figure 2 In (a), the first gate wiring layer 66 and the first source sensing wiring layer 68 are shown to be arranged between the first wiring layer 61 and the second wiring layer 62, but they can be arranged in layers different from the first wiring layer 61 and the second wiring layer 62. For example, they can be arranged in the order of the first gate wiring layer 66, the first source sensing wiring layer 68, the first wiring layer 61, and the second wiring layer 62 from the top. Similarly, in Figure 2 In (a), the second gate wiring layer 67 and the second source sense wiring layer 69 are shown to be provided between the third wiring layer 63 and the fourth wiring layer 64 , but they may be provided in a layer different from the third wiring layer 63 and the fourth wiring layer 64 .

[0037] The first wiring layer 61, the second wiring layer 62, the third wiring layer 63, the fourth wiring layer 64, and the fifth wiring layer 65 are defined as main wirings. In addition, the first gate wiring layer 66, the second gate wiring layer 67, the first source sense wiring layer 68, and the second source sense wiring layer 69 are defined as signal wirings.

[0038] The first wiring layer 61 , the second wiring layer 62 , the third wiring layer 63 , the fourth wiring layer 64 , the fifth wiring layer 65 , the first gate wiring layer 66 , the second gate wiring layer 67 , the first source sense wiring layer 68 , and the second source sense wiring layer 69 are made of, for example, Cu.

[0039] Next, the first semiconductor element 30 and the second semiconductor element 31 provided on the first metal layer 21 or the second metal layer 22 will be described. Fig. 9 The diagram shows a perspective view of the front and back surfaces of the first semiconductor element 30 and the second semiconductor element 31 .

[0040] The first semiconductor element 30 is provided between the first metal layer 21 and the second substrate 12. The first semiconductor element 30 is, for example, a vertical MOSFET, and a first drain electrode 32 (first electrode) is formed on the lower surface (first surface P1) in the Z direction, and a first source electrode 33 (second electrode) and a first gate electrode 34 are formed on the upper surface (second surface P2). The first drain electrode 32 is electrically connected to the first metal layer 21. A first conductor layer 41 is provided on the first source electrode 33, and the first source electrode 33 is electrically connected to the second wiring layer 62 via the first conductor layer 41. In addition, since the second wiring layer 62 is electrically connected to the first source sensing wiring layer 68 via the fifth conductive contact hole 75, the first source electrode 33 and the first source sensing wiring layer 68 are electrically connected. The first gate conductor layer 46 is provided on the first gate electrode 34, and the first gate electrode 34 and the first gate wiring layer 66 are connected via the first gate conductor layer 46 and the third conductive contact hole 73. That is, the first gate conductor layer 46 and the third conductive contact hole 73 are electrically connected.

[0041] The second semiconductor element 31 is provided between the second metal layer 22 and the second substrate 12. Similar to the first semiconductor element 30, the second semiconductor element 31 is, for example, a vertical MOSFET, and a second drain electrode 35 (third electrode) is formed on the lower surface (first surface S1) in the Z direction, and a second source electrode 36 (fourth electrode) and a second gate electrode 37 are formed on the upper surface (second surface S2). The second drain electrode 35 is electrically connected to the second metal layer 22. A second conductor layer 42 is provided on the second source electrode 36, and the second source electrode 36 is electrically connected to the fourth wiring layer 64 via the second conductor layer 42. In addition, since the fourth wiring layer 64 is electrically connected to the second source sensing wiring layer 69 via the sixth conductive contact hole 76, the second source electrode 36 and the second source sensing wiring layer 69 are electrically connected. The second gate conductor layer 47 is provided on the second gate electrode 37, and the second gate electrode 37 and the second gate wiring layer 67 are connected via the second gate conductor layer 47 and the fourth conductive contact hole 74. That is, the second gate conductor layer 47 and the fourth conductive contact hole 74 are electrically connected.

[0042] The first semiconductor element 30 and the second semiconductor element 31 are made of, for example, silicon (Si), silicon carbide (SiC), gallium nitride (GaN), or the like.

[0043] The third conductor layer 43 is provided between the second wiring layer 62 and the second metal layer 22, and electrically connects the second wiring layer 62 to the second metal layer 22. That is, the first source electrode 33 of the first semiconductor element 30 is electrically connected to the second source electrode 36 of the second semiconductor element 31 via the second wiring layer 62, the third conductor layer 43, and the second metal layer 22. In addition, the height of the third conductor layer 43 in the Z direction is substantially equal to the height between the first drain electrode (first electrode) 32 of the first semiconductor element 30 described later and the boundary between the first conductor layer 41 and the second wiring layer 62.

[0044] The fourth conductor layer 44 is provided between the first metal layer 21 and the fifth wiring layer 65, and electrically connects the first metal layer 21 and the fifth wiring layer 65. In addition, the fifth wiring layer 65 is provided at the lower portion of the second substrate 12. In addition, as described above, the first wiring layer 61 and the fifth wiring layer 65 are electrically connected via the first conductive contact hole 71. That is, the first wiring layer 61 and the first metal layer 21 are electrically connected via the first conductive contact hole 71, the fifth wiring layer 65, and the fourth conductor layer 44. The fifth conductor layer 45 is provided between the third metal layer 23 and the fourth wiring layer 64.

[0045] The fifth conductor layer 45 is provided between the third wiring layer 63 and the fourth wiring layer 64 and electrically connects the third metal layer 23 and the fourth wiring layer 64. That is, the third metal layer 23 and the second source electrode 36 of the second semiconductor element 31 are electrically connected.

[0046] The first metal layer 21 to the third metal layer 23, the first wiring layer 61 to the fifth wiring layer 65, the first gate wiring layer 66, the second gate wiring layer 67, the first source sensing wiring layer 68, and the second source sensing wiring layer 69 extend in the Y direction. Figure 1 to Figure 3 , it is shown that the first semiconductor element 30, the second semiconductor element 31, the first to fifth conductor layers 41 to 45, the first gate conductor layer 46, the second gate conductor layer 47, and the first to sixth conductive contact holes 71 to 76 are each provided with eight in the Y direction.

[0047] Each electrode and each metal layer, each electrode and each conductor layer, and each conductor layer and each wiring layer are connected using, for example, solder (not shown).

[0048] One end of the P power terminal 51 (first terminal) is exposed outside the resin case 1, and the other end is electrically connected to the first wiring layer 61. One end of the N power terminal 52 (second terminal) is exposed outside the resin case 1, and the other end is electrically connected to the third wiring layer 63. One end of the AC output terminal 53 (third terminal) is exposed outside the resin case 1, and the other end is electrically connected to the second metal layer 22.

[0049] One end of the first gate terminal 54 is exposed outside the resin case 1, and the other end is electrically connected to the first gate wiring layer 66. One end of the second gate terminal 55 is exposed outside the resin case 1, and the other end is electrically connected to the second gate wiring layer 67. One end of the first source sense terminal 56 is exposed outside the resin case 1, and the other end is electrically connected to the first source sense wiring layer 68. One end of the second source sense terminal 57 is exposed outside the resin case 1, and the other end is electrically connected to the second source sense wiring layer 69. The first source sense terminal 56 and the second source sense terminal 57 are source potentials, which serve as a reference when applying voltage to the first gate electrode 34 and the second gate electrode 37.

[0050] In addition, passive elements may be connected to the first gate wiring layer 66 and the second gate wiring layer 67. The passive elements are, for example, resistors and capacitors, and are provided for the purpose of suppressing noise of the gate voltage.

[0051] Figure 5 1 is a cross-sectional view of a semiconductor device 101 according to a modification of the first embodiment. As in the semiconductor device 101, a sixth conductor layer 81 may be provided between the first drain electrode 32 and the first metal layer 21, and a seventh conductor layer 82 may be provided between the second drain electrode 35 and the second metal layer 22. The semiconductor device 100 and the semiconductor device 101 have the same structure except for this.

[0052] Figure 6 FIG. 2 is a cross-sectional view of a semiconductor device 102 according to a modified example of the first embodiment. Figure 6 As shown in FIG. 1 , the first semiconductor element 30 can be sealed by resin 83. Similarly, the second semiconductor element 31 can also be sealed by resin 83. Resin 83 is, for example, epoxy resin. Figure 6 , a structure in which the inside of the resin 83 (the first semiconductor element 30 and the second semiconductor element 31 ) can be seen through a part of the resin 83 is shown.

[0053] (Operation of Semiconductor Device 100)

[0054] The operation of the semiconductor device 100 will be described.

[0055] The current input from the P power terminal 51 flows through the first wiring layer 61 in the X direction and the Y direction and reaches the first conductive contact hole 71. Then, the current sequentially passes through the first conductive contact hole 71, the fifth wiring layer 65, the fourth conductor layer 44, and the first metal layer 21 and reaches the drain electrode of the first semiconductor element 30. When the voltage of the first gate electrode 34 is equal to or higher than the threshold value, the current flows through the first semiconductor element 30 in the longitudinal direction (Z direction), sequentially passes through the first source electrode 33 and the first conductor layer 41 and reaches the second wiring layer 62. The current passes through the second wiring layer 62 in the X direction, flows through the third conductor layer 43 and the second metal layer 22, and reaches the AC output terminal 53. At this time, the direction of the current flowing in the X direction in the first wiring layer 61 is opposite to the direction of the current flowing in the X direction in the second wiring layer 62.

[0056] When the voltage of the second gate electrode 37 is equal to or higher than the threshold value, the current reaching the AC output terminal 53 passes through the second metal layer 22, the second drain electrode 35, the second source electrode 36, and the second conductor layer 42 in sequence, and flows through the fourth wiring layer 64 in the X direction. Then, the current passes through the second conductive contact hole 72, passes through the third wiring layer 63 in the X direction and the Y direction, and is output from the N power terminal 52. At this time, the direction of the current flowing in the fourth wiring layer 64 in the X direction is opposite to the direction of the current flowing in the third wiring layer 63 in the X direction.

[0057] (Effects of the First Embodiment)

[0058] The effects of the semiconductor device 100 according to the first embodiment will be described using a semiconductor device 300 according to a comparative example. Figure 7 1 is a cross-sectional view of a semiconductor device 300 according to a comparative example. The same components as those of the semiconductor device 100 according to the first embodiment are denoted by the same reference numerals.

[0059] The structure of the semiconductor device 300 of the comparative example is described. The semiconductor device 300 is different from the semiconductor device 100 of the first embodiment in that the third wiring layer 63, the first gate wiring layer 66, and the second gate wiring layer 67 are provided on the first substrate 11 instead of the second substrate 12. Furthermore, the first source electrode 33 and the second metal layer 22, the first gate electrode 34 and the first gate wiring layer 66, the second source electrode 36 and the third wiring layer 63, and the second gate electrode 37 and the second gate wiring layer 67 are connected by a metal thin wire 90, for example, using solder.

[0060] The semiconductor device 300 according to the comparative example requires a region on the first substrate 11 where the third wiring layer 63 , the first gate wiring layer 66 , and the second gate wiring layer 67 are provided.

[0061] In addition, for the semiconductor device 300 of the comparative example, since the electrodes and wiring layers of the first semiconductor element 30 and the second semiconductor element 31 are connected by metal fine wires 90, respectively, the effect of using the opposing current between the wiring layers to cancel the inductance (Ls) is small. In addition, since the metal fine wires 90 are thin, the inductance (Ls) generated in the metal fine wires 90 is large. The surge voltage generated when the semiconductor device is turned off is represented by the product of the current change rate and the inductance. Since the current change rate increases with the high speed of switching on and off, the surge voltage increases. If the surge voltage exceeds the specified voltage, the semiconductor element may be broken down.

[0062] On the other hand, the semiconductor device 100 according to the first embodiment has the second substrate 12 disposed on the upper side of the first substrate 11, and the main wiring and the signal wiring are disposed on the second substrate 12. Therefore, compared with the comparative example in which a part of the main wiring layer and the signal wiring layer are disposed on the first substrate 11, the area in which the semiconductor element can be mounted is increased on the first substrate 11. That is, the semiconductor device 100 according to the first embodiment can increase the current that can flow per unit area compared with the semiconductor device 300 according to the comparative example.

[0063] In addition, as described above, the direction of the current flowing in the X direction in the first wiring layer 61 is opposite to the direction of the current flowing in the X direction in the second wiring layer 62. Similarly, the direction of the current flowing in the X direction in the fourth wiring layer 64 is opposite to the direction of the current flowing in the X direction in the third wiring layer 63. The first wiring layer 61 and the second wiring layer 62 are arranged opposite to each other in the Z direction. In addition, the third wiring layer 63 and the fourth wiring layer 64 are arranged opposite to each other in the Z direction. Therefore, the inductance (Ls) generated when the semiconductor device 100 according to the first embodiment is operated is offset by the opposite current in the opposite direction. As a result, the semiconductor device 100 can reduce the surge voltage when turning on and off, and can suppress the breakdown of the semiconductor element.

[0064] Furthermore, the bonding interface between the second wiring layer 62 and the first conductor layer 41 , the bonding interface between the second wiring layer 62 and the third conductor layer 43 , the bonding interface between the fourth wiring layer 64 and the second conductor layer 42 , and the bonding interface between the fifth wiring layer 65 and the fourth conductor layer 44 are located on the same XY plane. Therefore, when the first drain electrode 32 and the first metal layer 21, the first source electrode 33 and the first conductor layer 41 and the second wiring layer 62, the first gate conductor layer 46 and the first gate electrode 34 and the third conductive contact hole 73, the second drain electrode 35 and the second conductor layer 42, the second source electrode 36 and the second conductor layer 42 and the fourth wiring layer 64, the second gate conductor layer 47 and the second gate electrode 37 and the fourth conductive contact hole 74, the third conductor layer 43 and the second metal layer 22 and the second wiring layer 62, the fourth conductor layer 44 and the first metal layer 21 and the fifth wiring layer 65, and the fifth conductor layer 45 and the third metal layer 23 and the fourth wiring layer 64 are connected using solder or the like, they can be connected simultaneously using a reflow oven. Therefore, the semiconductor device 100 can reduce the number of manufacturing steps compared to the semiconductor device 300 in which the metal fine wires 90 are connected one by one by solder or the like when connecting the electrodes and wirings of the first semiconductor element 30 and the second semiconductor element 31 by the metal fine wires 90 .

[0065] Furthermore, the semiconductor device 100 according to the present embodiment includes the third metal layer 23 and the fifth conductor layer 45. By providing the third metal layer 23 and the fifth conductor layer 45, the heat generated when the semiconductor device 100 is turned on can be more efficiently discharged. In addition, by providing the third metal layer 23 and the fifth conductor layer 45, the current distribution when the semiconductor device 100 is turned on can be made uniform. However, the semiconductor device 100 can be implemented even without providing the third metal layer 23 and the fifth conductor layer 45.

[0066] [Second embodiment]

[0067] (Structure of Semiconductor Device 200)

[0068] Reference Figure 8 A semiconductor device 200 according to the second embodiment will be described. Figure 8 It is a cross-sectional view of a semiconductor device 200 according to the second embodiment. Figure 8 The cross-section shown is equivalent to Figure 1 The cross-sectional position of line AA' in (b).

[0069] The semiconductor device 200 according to the second embodiment is different from the semiconductor device 100 according to the first embodiment in that a shielding layer 84 is provided on the second substrate 12. More specifically, the shielding layer 84 is provided between the main wiring (the first wiring layer 61, the second wiring layer 62, the third wiring layer 63, the fourth wiring layer 64, and the fifth wiring layer 65) and the signal wiring (the first gate wiring layer 66, the second gate wiring layer 67, the first source sensing wiring layer 68, and the second source sensing wiring layer 69). The shielding layer 84 is made of copper, for example, and is set to a floating potential. The description of the points that overlap with the semiconductor device 100 according to the first embodiment is omitted.

[0070] The magnitude of the current flowing through the main wiring changes with time. The change in the magnitude of the current over time generates electromagnetic noise, which affects the signal wiring.

[0071] The semiconductor device 200 according to the second embodiment has the shield layer 84 between the main wiring and the signal wiring. Therefore, the semiconductor device 200 can reduce the influence of electromagnetic noise generated by current changes in the main circuit on the signal wiring layer, thereby suppressing the occurrence of malfunction.

[0072] Several embodiments of the present invention have been described, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other forms, and various omissions, substitutions, and changes can be made without departing from the scope of the invention. These embodiments and their variations are included in the scope or spirit of the invention, and are included in the invention described in the claims and the scope of their equivalents.

Claims

1. A semiconductor device comprising: 1st substrate; A first metal layer is disposed on the first substrate; a second metal layer, separated from the first metal layer and disposed on the first substrate; a second substrate, which is provided in a first direction apart from the first substrate, and has a main wiring and a signal wiring, wherein the main wiring has a first wiring layer electrically connected to the first metal layer, a second wiring layer electrically connected to the second metal layer, a third wiring layer provided in a manner separate from the first wiring layer and the second wiring layer, and a fourth wiring layer electrically connected to the third wiring layer, and the signal wiring has a first gate wiring layer provided in a layer different from the main wiring in the first direction, and a second gate wiring layer provided in a layer different from the main wiring in the first direction; a first semiconductor element disposed on the first metal layer, comprising a first electrode electrically connected to the first metal layer and disposed on a first surface of the first semiconductor element, a second electrode electrically connected to the second wiring layer and disposed on a second surface of the first semiconductor element opposite to the first surface, and a first gate electrode electrically connected to the first gate wiring layer and disposed on the second surface of the first semiconductor element; a second semiconductor element disposed on the second metal layer, comprising a third electrode electrically connected to the second metal layer and disposed on the first surface of the second semiconductor element, a fourth electrode electrically connected to the fourth wiring layer and disposed on the second surface of the second semiconductor element opposite to the first surface, and a second gate electrode electrically connected to the second gate wiring layer and disposed on the second surface of the second semiconductor element; a first terminal electrically connected to the first wiring layer; a second terminal electrically connected to the third wiring layer; a third terminal electrically connected to the second metal layer; a first gate terminal electrically connected to the first gate wiring layer; as well as a second gate terminal electrically connected to the second gate wiring layer, The signal wiring further includes a first source sensing wiring layer electrically connected to the second electrode, and a second source sensing wiring layer electrically connected to the fourth electrode; The semiconductor device further comprises: a first source sensing terminal electrically connected to the first source sensing wiring layer; as well as The second source sensing terminal is electrically connected to the second source sensing wiring layer.

2. The semiconductor device according to claim 1, wherein: The first gate wiring and the second gate wiring are provided inside the second substrate.

3. The semiconductor device according to claim 1 or 2, wherein: The semiconductor device further comprises: a first conductor layer provided between the second electrode and the second wiring layer; a first gate conductor layer provided between the first gate electrode and the first gate wiring layer; a second conductor layer provided between the fourth electrode and the fourth wiring layer; a second gate conductor layer provided between the second gate electrode and the second gate wiring layer; a third conductor layer, provided between the second metal layer and the second wiring layer; a fourth conductor layer electrically connected to the first wiring layer via the first connecting portion; as well as The fifth wiring layer is provided on the second substrate and between the first wiring layer and the fourth conductor layer.

4. The semiconductor device according to claim 1 or 2, wherein: The semiconductor device further comprises: a third metal layer disposed on the first substrate so as to be adjacent to the second metal layer in a second direction intersecting the first direction; as well as The fifth conductor layer is provided between the third metal layer and the fourth wiring layer.

5. The semiconductor device according to claim 1 or 2, wherein: A portion of the first wiring layer is disposed opposite to a portion of the second wiring layer in the first direction; and a portion of the third wiring layer is disposed opposite to a portion of the fourth wiring layer in the first direction.

6. The semiconductor device according to claim 1 or 2, wherein: A shielding layer is provided between the main wiring and the signal wiring.

7. The semiconductor device according to claim 1 or 2, wherein: The semiconductor device further comprises: a sixth conductor layer, disposed between the first electrode and the first metal layer; and The seventh conductor layer is provided between the third electrode and the second metal layer.

8. The semiconductor device according to claim 3, wherein: The bonding interface between the second wiring layer and the first conductor layer, the bonding interface between the second wiring layer and the third conductor layer, the bonding interface between the fourth wiring layer and the second conductor layer, and the bonding interface between the fifth wiring layer and the fourth conductor layer are located on the same plane in the second direction.

9. The semiconductor device according to claim 1 or 2, wherein: Passive elements are connected to the signal wiring.

10. The semiconductor device according to claim 1 or 2, wherein: The direction of the current flowing through the first wiring layer and the direction of the current flowing through the second wiring layer are opposite to each other in the second direction; The direction of the current flowing through the third wiring layer and the direction of the current flowing through the fourth wiring layer are opposite to each other in the second direction.

Images