Semiconductor element with barrier layer and method for producing the same

Abstract

The present disclosure provides a semiconductor element with an aluminum fluoride barrier layer and a method for manufacturing the semiconductor element. The semiconductor element has a substrate, a circuit layer disposed on the substrate, a pad layer disposed in the circuit layer and containing aluminum and copper, a first barrier layer disposed on the circuit layer and containing aluminum fluoride, and a first connecting member disposed on the first barrier layer.

Description

[0001] Cross Reference To

[0002] This application claims priority to and the benefit of U.S. Nonprovisional Application No. 17 / 234,282, filed April 19, 2021, the contents of which are incorporated herein by reference in their entirety. TECHNICAL FIELD

[0003] The present disclosure relates to a semiconductor device and a method of manufacturing the semiconductor device. In particular, the present disclosure relates to a semiconductor device having an aluminum fluoride barrier layer and a method of manufacturing the semiconductor device having the barrier layer. BACKGROUND

[0004] Semiconductor devices are used in different electronic applications, such as personal computers, cell phones, digital cameras, or other electronic devices. The size of semiconductor devices is gradually reduced to meet the increasing demand for computing power. However, during the process of reducing the size, different problems are increased, and such problems continue to increase in number and complexity. Therefore, there are still challenges in achieving improved quality, yield, performance, and reliability, as well as reducing complexity.

[0005] The above description of background art is provided merely for better understanding of the present disclosure and should not be construed as an acknowledgment or any form of suggestion that this background art is prior art to the claimed subject matter. SUMMARY

[0006] One embodiment of the present disclosure provides a semiconductor device, comprising a substrate; a circuit layer disposed on the substrate; a pad layer disposed in the circuit layer and comprising aluminum and copper; a first barrier layer disposed on the pad layer and comprising aluminum fluoride; and a first connecting member disposed on the first barrier layer.

[0007] In some embodiments, the semiconductor device further comprises a first passivation layer disposed on the circuit layer, wherein the first barrier layer is disposed in the first passivation layer.

[0008] In some embodiments, a thickness of the first passivation layer is greater than a thickness of the first barrier layer.

[0009] In some embodiments, a lower portion of the first connecting member extends into the first passivation layer and is disposed on the first barrier layer.

[0010] In some embodiments, the first barrier layer comprises zinc oxide.

[0011] In some embodiments, the semiconductor device further comprises a heat dissipation layer disposed below the substrate.

[0012] In some embodiments, the semiconductor element further comprises an attachment layer disposed between the heat dissipation layer and the substrate.

[0013] In some embodiments, the semiconductor element further comprises a buffer pad layer disposed in the circuit layer and topographically aligned with the pad layer. The buffer pad layer is disposed in a vertical plane lower than a vertical plane of the pad layer.

[0014] In some embodiments, the first barrier layer has a U-shaped cross-sectional profile.

[0015] Another embodiment of the present disclosure provides a method of fabricating a semiconductor element, comprising providing a substrate; forming a circuit layer on the substrate; forming a pad layer in the circuit layer; forming a first passivation layer on the circuit layer; forming a first opening along the first passivation layer to expose the pad layer; forming a first barrier layer on the pad layer and in the first opening; and forming a first connecting member on the first barrier layer. The pad layer comprises aluminum and copper. The first barrier layer comprises aluminum fluoride.

[0016] In some embodiments, the first barrier layer comprises zinc oxide.

[0017] In some embodiments, a content of the zinc oxide is greater than a content of the aluminum fluoride.

[0018] In some embodiments, a process temperature of the step of forming the first passivation layer is between about 350 °C and about 450 °C.

[0019] In some embodiments, a process pressure of the step of forming the first passivation layer is between about 2.0 Torr and about 2.8 Torr.

[0020] In some embodiments, the step of forming the first opening comprises argon and tetrafluoromethane as etching agents.

[0021] In some embodiments, a process temperature of the step of forming the first opening is between about 120 °C and about 160 °C.

[0022] In some embodiments, a process pressure of the step of forming the first opening is between about 0.3 Torr and about 0.4 Torr.

[0023] In some embodiments, the step of forming the first opening comprises helium and nitrogen trifluoride as etching agents.

[0024] In some embodiments, a process temperature of the step of forming the first opening is between about 80 °C and about 100 °C.

[0025] In some embodiments, a process pressure of the step of forming the first via is between about 1.2 Torr and about 1.3 Torr.

[0026] Due to the design of the semiconductor device of the present disclosure, the saturated bonding property of the aluminum fluoride can prevent the underlying liner from being corroded by various semiconductor processes, especially those containing fluorine ions. Thus, the reliability of the semiconductor device can be improved.

[0027] The foregoing has outlined rather broadly the features and technical advantages of the technology of the present disclosure so that the detailed description of the present disclosure that follows can be better understood. Additional features and advantages of the technology of the present disclosure will be described in the detailed description of the present disclosure that follows. Such features and advantages of the present disclosure can be readily employed as modifications on the described modes of practicing this disclosure. Those skilled in the art of the pertinent art will readily appreciate that other modifications can be made of the present disclosure without departing from the scope of the present disclosure defined by the claims. Such equivalent constructions and methods are intended to be within the scope of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0028] The present disclosure will become more fully understood from the detailed description and examples given below and the accompanying drawings of which:

[0029] Figures 1 to 5 is a cross-sectional schematic view illustrating semiconductor devices of an embodiment of the present disclosure.

[0030] Figure 6 is a flowchart illustrating a method of manufacturing semiconductor devices of an embodiment of the present disclosure.

[0031] Figures 7 to 11 is a cross-sectional schematic view illustrating a flow of manufacturing semiconductor devices of an embodiment of the present disclosure.

[0032] Figures 12 to 14 is a cross-sectional schematic view illustrating a flow of manufacturing semiconductor devices of another embodiment of the present disclosure.

[0033] Figures 15 to 17 is a cross-sectional schematic view illustrating a flow of manufacturing semiconductor devices of another embodiment of the present disclosure.

[0034] BRIEF DESCRIPTION OF DRAWINGS

[0035] 1A: Semiconductor device

[0036] 1B: Semiconductor device

[0037] 1C: Semiconductor device

[0038] 1D: semiconductor element

[0039] 1E: semiconductor element

[0040] 1F: semiconductor element

[0041] 101: base

[0042] 103: circuit layer

[0043] 105: device element

[0044] 107: conductive feature

[0045] 109: first passivation layer

[0046] 201: pad layer

[0047] 203: first barrier layer

[0048] 205: first connector

[0049] 301: under bump metallization

[0050] 303: buffer pad layer

[0051] 305: attachment layer

[0052] 307: heat spreading layer

[0053] 401: barrier material

[0054] OP: pad opening

[0055] OP1: first opening

[0056] R1: first recess

[0057] S11: step

[0058] S13: step

[0059] S15: step

[0060] S17: step

[0061] T1: thickness

[0062] T2: thickness

[0063] Z: direction DETAILED DESCRIPTION

[0064] The specific examples described herein illustrate aspects of the disclosure and do not represent all theties of the disclosure. Of course, these examples are merely illustrative and are not intended to limit the scope of the disclosure. For example, where a first component is described as being formed on a second component, this can include embodiments where the first and second components are formed in direct contact with each other, or where additional components are formed between the first and second components such that the first and second components do not contact each other. Additionally, the embodiments of the disclosure can refer to a number of examples using a numbering scheme, such as "first", "second", "third", etc. These numbering schemes are merely used to distinguish between like elements, and do not limit the scope of the disclosure to a particular number of elements. For example, a first element described herein could be termed a second element without departing from the scope of the disclosure.

[0065] In addition, spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0066] It will be understood that, when a component is referred to as being "on", "connected to", or "coupled to" another component, it can be directly on, connected, or coupled to the other component, or intervening components can be present. In contrast, when an element is referred to as being "directly on", "directly connected to", or "directly coupled to" another element, there are no intervening components present.

[0067] It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. Rather, these terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.

[0068] Unless otherwise indicated herein, when a term such as "same," "equal," "planar," or "coplanar" is used herein, it is not necessary that the orientation, layout, location, shape, size, amount, or other measure be an exact identical orientation, layout, location, shape, size, amount, or other measure, but it means within acceptable variation, including nearly identical orientation, layout, location, shape, size, amount, or other measure, which can occur, for example, due to manufacturing processes. The term "substantially" can be used herein to express this meaning. For example, substantially the same, substantially equal, or substantially planar can be an exact same, equal, or planar, or it can be within acceptable variation, including nearly identical, equal, or planar, which can occur, for example, due to manufacturing processes.

[0069] In the present disclosure, a semiconductor device generally means a device that can operate by utilizing semiconductor characteristics, and an electro-optic device, a light-emitting display device, a semiconductor circuit, and an electronic device are included in the range of the semiconductor device.

[0070] It should be understood that in the description of the present disclosure, above (or up) corresponds to the direction of the Z-direction arrow, and below (or down) corresponds to the opposite direction of the Z-direction arrow.

[0071] Figures 1 to 5 is a cross-sectional view schematically illustrating each semiconductor device 1A, 1B, 1C, 1D, 1E of an embodiment of the present disclosure.

[0072] Reference should be made to Figure 1The semiconductor device 1A can include a substrate 101, a circuit layer 103, a plurality of device elements 105, a plurality of conductive features 107, a first passivation layer 109, a pad layer 201, a first barrier layer 203, and a first connection 205.

[0073] Referring to Figure 1 The substrate 101 can include a bulk semiconductor substrate composed of at least one semiconductor material. For example, the bulk semiconductor can include an elemental semiconductor such as silicon or germanium, a compound semiconductor such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or other III-V compound semiconductor or II-VI compound semiconductor.

[0074] In some embodiments, the substrate 101 can include a semiconductor-on-insulator, which is composed of, from bottom to top, a handle substrate, an insulator layer, and an uppermost semiconductor material layer. The handle substrate and the uppermost semiconductor material layer include the same material as the aforementioned bulk semiconductor substrate. The insulator layer can be a crystalline or non-crystalline dielectric material such as an oxide and / or nitride. For example, the insulator layer can be a dielectric oxide such as silicon oxide. As another example, the insulator layer can be a dielectric nitride such as silicon nitride or boron nitride. As yet another example, the insulator layer can include a stack of a dielectric oxide and a dielectric nitride such as a stack of silicon oxide and silicon nitride or boron nitride in any order. The insulator layer can have a thickness between about 10 nm and about 200 nm. The insulator layer can eliminate leakage current and reduce the parasitic capacitance of the semiconductor device 1A.

[0075] Referring to Figure 1Circuitry layer 103 can be formed on substrate 101. Circuitry layer 103 can include a plurality of interlayer dielectric layers and / or a plurality of interlayer metal dielectric layers that include a plurality of device elements 105 and a plurality of conductive features 107. The device elements 105 can be transistors, such as complementary metal-oxide-semiconductor (CMOS) transistors, metal-oxide-semiconductor field-effect transistors (MOSFETs), fin field-effect-transistors (FinFETs), or combinations thereof. The conductive features 107 can include conductive plugs, conductive lines, and conductive vias, or other suitable conductive elements.

[0076] The conductive features 107 can each correspond to electrically connecting the device elements 105 to form a plurality of functional units in circuitry layer 103. In the description of the present disclosure, a functional unit generally represents a functionally relevant logic circuit that has been divided into a different unit for functional purposes. In some embodiments, the functional units can generally be highly complex circuits, such as processor cores, memory controllers, or accelerator units. In some embodiments, the complexity and functionality of a functional unit can be more complex or less complex. In the present disclosure, the circuitry layer 103 with the device elements 105 can be considered a memory.

[0077] For example, the interlayer dielectric layers and / or the interlayer metal dielectric layers can include silicon oxide, borophosphosilicate glass, undoped silicate glass, fluorosilicate glass, low-k dielectric materials, the like, or combinations thereof. The low-k dielectric materials can have a dielectric constant less than 3.0 or even less than 2.5. In some embodiments, the low-k dielectric materials can have a dielectric constant less than 2.0.

[0078] For example, the conductive features 107 can include tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitrides (e.g., titanium nitride), transition metal aluminides, or combinations thereof.

[0079] Reference is made to Figure 1The underfill 201 can be disposed in the circuit layer 103 and can be electrically coupled to a corresponding device element 105 via the corresponding conductive feature 107. The upper surface of the underfill 201 and the upper surface of the circuit layer 103 can be substantially coplanar. The underfill 201 can have a thickness between about 400 nm and about 1100 nm. In some embodiments, for example, the underfill 201 can include an aluminum-copper alloy. A small amount of copper in aluminum can improve electromigration resistance and further reduce the occurrence of aluminum hillocks on the surface of an aluminum thin film layer.

[0080] In some embodiments, for example, the underfill 201 can include pure aluminum. In some embodiments, the circuit layer 103 at the layer where the underfill 201 is disposed can include a polymeric material such as polybenzoxazole, polyimide, benzocyclobutene, solder resist film, or the like. The polymeric material, such as polyimide, has many attractive properties such as the ability to fill high aspect ratio openings, a relatively low dielectric constant (about 3.2), a simple deposition process, reduction of steps in the underlying layers, and high temperature resistance after curing. In addition, some photosensitive polymeric materials, such as photosensitive polyimide, can have all of the aforementioned properties and can be patterned like a photoresist mask and, after patterning and etching, can be left on a surface, i.e., on which the photosensitive polymeric material has been deposited, as part of a passivation layer.

[0081] It should be appreciated that the number of underfills 201 is for illustration purposes only in embodiments of the present disclosure. For example, the number of underfills 201 can be more than one.

[0082] It should be understood that the term "about" modifying the quantity of an ingredient, component described herein, or a reactant of a composition of this disclosure, means that the values can occur within an acceptable standard deviation range for the particular measurement or liquid handling procedure used to manufacture the concentrates or solutions. Furthermore, variations can occur within the acceptable standard deviation range due to inadvertent error in measuring or liquid handling procedures applied in manufacturing compositions or performing the methods or the like. In one aspect, the term "about" means within 10% of the reported numerical value. In another aspect, the term "about" means within 5% of the reported numerical value. In yet another aspect, the term "about" means within 10, 9, 8, 7, 6, 5, 4, 3, 2, or 1% of the reported numerical value.

[0083] See Figure 1 A first passivation layer 109 can be disposed on the circuit layer 103. The first passivation layer 109 can be a single layer structure or a multi-layer structure. In some embodiments, the first passivation layer 109 can include polybenzoxazole, polyimide, benzocyclobutene, solder resist film, the like, or a combination thereof. The first passivation layer 109 including a polymeric material can have the aforementioned attractive properties and description thereof is not repeated herein. In some other embodiments, the first passivation layer 109 can be a dielectric layer. The dielectric layer can include a nitride, such as silicon nitride, an oxide, such as silicon oxide, an oxynitride, such as silicon oxynitride, nitrided silicon oxide, phosphosilicate glass, borosilicate glass, boron-doped phosphosilicate glass, the like, or a combination thereof.

[0084] See Figure 1A first opening OP1 can be formed through the first passivation layer 109 to expose a portion of the pad layer 201. In some embodiments, the sidewalls of the first opening OP1 can be substantially vertical. In some embodiments, the sidewalls of the first opening OP1 can be tapered. It should be understood that in the description of the present disclosure, a surface is "substantially vertical" if it deviates from a vertical plane by no more than three times the root mean square roughness of the surface.

[0085] Referring to Figure 1 A first barrier layer 203 can be formed on the pad layer 201 and in the first passivation layer 109. The first barrier layer 203 can have a thickness Tl that is less than a thickness T2 of the first passivation layer 109. The first barrier layer 203 can include aluminum fluoride. Due to the saturating bonding properties of aluminum fluoride, it stabilizes and protects the underlying pad layer from a variety of semiconductor processes, particularly those involving fluorine ions. In some embodiments, the first barrier layer 203 can also include zinc oxide, which can increase the electronic properties of the first barrier layer 203. In some embodiments, the amount of zinc oxide can be greater than the amount of aluminum fluoride.

[0086] Referring to Figure 1 A first connecting member 205 can be formed on the first barrier layer 203. A lower portion of the first connecting member 205 can extend into the first passivation layer 109, completely fill the first opening OP1, and be formed on the first barrier layer 203. An upper portion of the first connecting member 205 can protrude from a plane that is coplanar with the upper surface of the first passivation layer 109, and the upper portion of the first connecting member 205 is formed on the lower portion of the first connecting member 205. In some embodiments, the first connecting member 205 can include a conductive material having low resistivity, such as tin, lead, silver, copper, nickel, bismuth, or alloys thereof.

[0087] In some embodiments, the first connecting member 205 can be a solder joint. The solder joint can include a material, such as tin or other suitable materials, such as silver or copper. In an embodiment where the solder joint is a tin solder joint, the fabrication technique of the solder joint can include initially forming a layer of tin to a thickness of between about 10 μm and about 100 μm via evaporation, electroplating, printing, solder transfer, or ball placement. Once the layer of tin has been formed and fills the first opening OP1 and is on the first passivation layer 109, a reflow process can be performed to shape the solder joint into the desired shape.

[0088] Referring to Figure 2, the semiconductor element IB can have a structure similar to that as described in Figure 1 In Figure 2 the same or similar elements in Figure 1 have been designated like element numbers, and repeated description thereof has been omitted. The first barrier layer 203 can be conformally disposed in the first opening OP1. In some embodiments, the first barrier layer 203 can be disposed on the pad layer 201 and on the sidewalls of the first opening OP1. In other words, the first barrier layer 203 can have a U-shaped cross-sectional profile.

[0089] Referring to Figure 3 , the semiconductor element 1C can have a structure similar to that as described in Figure 2 In Figure 3 the same or similar elements in Figure 2 have been designated like element numbers, and repeated description thereof has been omitted. The semiconductor element 1C can have an under bump metal layer 301. The under bump metal layer 301 can be conformally disposed on the first barrier layer 203 and in the first opening OP1. The under bump metal layer 301 can be a single layer structure or a stack structure of multiple layers. For example, the under bump metal layer 301 can include a first conductive layer, a second conductive layer, and a third conductive layer stacked in sequence. The first conductive layer can serve as an adhesion layer to stably attach the first connecting member 205 to the first barrier layer 203. For example, the first conductive layer can include at least one of titanium, titanium tungsten, chromium, and aluminum. The second conductive layer can serve as a barrier layer to prevent a conductive material included in the first connecting member 205 from diffusing into the pad layer 201. The second conductive layer can include at least one of copper, nickel, chromium copper, and nickel vanadium. The third conductive layer can serve as a seed layer to form the first connecting member 205 or as a wetting layer to improve the wetting properties of the first connecting member 205. The third conductive layer can include at least one of nickel, copper, and aluminum.

[0090] Referring to Figure 4 , the semiconductor element ID can have a structure similar to that as described in Figure 1 In Figure 4 the same or similar elements in Figure 1The components in the diagram are labeled with similar component numbers, and their repetitive descriptions have been omitted. Semiconductor component 1D may have a cushion layer 303. The cushion layer 303 may be disposed in circuit layer 103 and may be topographically aligned with cushion layer 201. The cushion layer 303 may be disposed on a vertical plane that is lower than a vertical plane of cushion layer 201. In some embodiments, the cushion layer 303 and cushion layer 201 may not be in contact with each other. The cushion layer 303 may be used to absorb and redistribute stresses caused by shear stress and concentrated in the underlying layers, which are due to thermal expansion mismatch of a wiring process or a bumping process, as well as general stress. For example, the cushion layer 303 may comprise a material having a coefficient of thermal expansion less than about 20 ppm / °C and a Young's modulus less than about 15 GPa. In some embodiments, the buffer layer 303 may comprise a material comprising polyimide or an epoxy-based material. The buffer layer 303 may have a thickness between approximately 500 nm and approximately 10,000 nm. Preferably, the thickness of the buffer layer 303 may be between approximately 1,000 nm and approximately 5,000 nm. The buffer layer 303 can serve as a buffer pad to reduce stress in a bumping process or a wiring process; thus, it can reduce delamination on the upper portion of the first passivation layer 109 or circuit layer 103.

[0091] Please refer to Figure 5 Semiconductor element 1E may have similar characteristics to, for example: Figure 1 The structure described. In Figure 5 The same or similar Figure 1 The components in the diagram are labeled with similar component numbers, and their repetitive descriptions have been omitted. Semiconductor component 1E may have an attachment layer 305 and a heat dissipation layer 307.

[0092] Please refer to Figure 5A heat spreading layer 307 can be disposed below the substrate 101. An attachment layer 305 can be used to attach the heat spreading layer 307 to the substrate 101. In some embodiments, the attachment layer 305 can include a die attach film, a silver paste, or the like. In some embodiments, the heat spreading layer 307 can include a composite material selected from the group consisting of silicon carbide, aluminum carbide, graphite, and the like. The heat spreading layer 307 can have a good thermal conductivity, which can be greater than about 2 W / m.K. In some embodiments, the heat spreading layer 307 can have a high thermal conductivity, which can be greater than about 100 W / m.K, and can include a metal, a metal alloy, or the like. For example, the heat spreading layer 307 can include a metal and / or a metal alloy selected from the group consisting of aluminum, copper, nickel, cobalt, and the like.

[0093] In some embodiments, the heat spreading layer 307 can include a carbon material filled with a flexible material, such as a polymer matrix. For example, the heat spreading layer 307 can generally include vertically oriented graphite and nanotubes filled with a fluoropolymer rubber matrix. The aspect ratio of the nanotubes can be between about 1 : 1 and about 1 : 100. In other examples, the heat spreading layer 307 can include graphitic carbon. In yet another example, the heat spreading layer 307 can include a pyrolytic graphite sheet. In some embodiments, the heat spreading layer 307 can have a thermal resistance of less than 0.2 °C cm / W at a thickness between about 250 μm and about 450 μm. The heat spreading layer 307 can provide additional heat spreading capability for the semiconductor element IE. 2 / Watt, which can be between about 250 μm and about 450 μm. The heat spreading layer 307 can provide additional heat spreading capability for the semiconductor element IE.

[0094] It should be understood that the terms "forming," "formed," and "form" can mean and include any method of creating, building, patterning, implanting, or depositing an element, a dopant, or a material. Examples of forming methods can include, but are not limited to, atomic layer deposition, chemical vapor deposition, physical vapor deposition, sputtering, spin coating, diffusing, depositing, growing, implantation, photolithography, dry etching, and wet etching.

[0095] It should be understood that in the description of the present disclosure, functions or steps mentioned can occur in a different order than the order described in each figure. For example, two figures that are shown in succession can actually be executed substantially concurrently, or sometimes in the reverse order, depending on the functions or steps involved.

[0096] Figure 6 is a flowchart illustrating a method of fabricating a semiconductor element 1A according to an embodiment of the present disclosure. Figures 7 to 11 is a cross-sectional view illustrating a flow of fabricating a semiconductor element 1A according to an embodiment of the present disclosure.

[0097] Referring to Figures 6 to 8 At step S11, a substrate 101 can be provided, a circuit layer 103 can be formed on the substrate 101, and a pad layer 201 can be formed in the circuit layer 103.

[0098] Referring to Figure 7 The substrate 101 and the circuit layer 103 can have structures similar to those described in Figure 1 and will not be repeated herein. The fabrication techniques of the ILDs and / or the ILMs of the circuit layer 103 can include deposition processes, such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, or the like. After the deposition processes, planarization processes can be performed to remove excess materials and provide a substantially planar surface for subsequent processing steps. During the formation of the ILDs and / or the ILMs, device elements 102 and conductive features 107 can be formed.

[0099] Referring to Figure 7 The pad opening OP can be formed in the circuit layer 103. The pad opening OP can be formed by a lithography process followed by an etching process to pattern the circuit layer 103.

[0100] In some embodiments, the etching process can be a non-isotropic dry etching process using argon and tetrafluoromethane as etchants. The etching process can have a process temperature between about 120 °C and about 160 °C. The etching process can have a process pressure between about 0.3 Torr and about 0.4 Torr. The etching process can have a process duration between about 33 seconds and about 39 seconds.

[0101] Alternatively, in some embodiments, the etching process can be a non-isotropic dry etching process using helium and nitrogen trifluoride as etchants. The etching process can have a process temperature between about 80 °C and about 100 °C. The etching process can have a process pressure between about 1.2 Torr and about 1.3 Torr. The etching process can have a process duration between about 20 seconds and about 30 seconds.

[0102] In some embodiments, a cleaning process can be performed after the aforementioned etching process. The cleaning process includes a mixture of hydrogen and argon as a remote plasma at a process temperature between about 250 °C and about 350 °C, a process pressure between about 1 Torr and about 10 Torr, and the presence of a bias energy supplied to the apparatus performing the cleaning process. The bias energy can be between about 0 W and about 200 W. The cleaning process can remove the oxide on the upper surface of the conductive feature 107 via the pad opening PO without damaging the conductive feature 107.

[0103] A passivation process can be sequentially performed on circuit layer 103 and pad openings PO. The passivation process may include immersing an intermediate semiconductor device in a precursor, such as dimethylaminotrimethylsilane, tetramethylsilane, or similar, at a process temperature between approximately 200°C and approximately 400°C. Ultraviolet energy can be used to facilitate the passivation process. The passivation process passivates the sidewalls of circuit layer 103 via pad openings PO by sealing their surface vias, thereby reducing unwanted sidewall growth that can affect the electronic performance of semiconductor device 1A during subsequent processing steps. Therefore, the performance and reliability of semiconductor device 1A can be improved.

[0104] Please refer to Figure 8 The pad 201 can be sequentially formed in the pad opening PO by sputtering, electroplating, or electroless plating. For example, when the fabrication technology of the pad 201 involves sputtering using aluminum or copper as the source material, the sputtering process temperature can be between approximately 100°C and approximately 400°C. The sputtering process pressure can be between approximately 1 mTorr and approximately 100 mTorr. After sputtering, an etching process can be performed to trim the pattern of the pad 201. The etching process can use chlorine or argon as the etchant. The chlorine etchant flow rate can be between approximately 10 sccm (standard cubic centimeters per minute) and approximately 30 sccm. The argon etchant flow rate can be between approximately 900 sccm and approximately 1100 sccm. The etching process temperature can be between approximately 50°C and approximately 200°C. The etching process pressure can be between approximately 50 mTorr and approximately 10 Torr. The etching process can take between approximately 30 seconds and approximately 200 seconds.

[0105] Please refer to Figure 6 and Figure 9 In step S13, a first passivation layer 109 may be formed on the circuit layer 103, and a first opening OP1 may be formed along the first passivation layer 109 to expose the pad layer 201.

[0106] Please refer to Figure 9For example, the fabrication technique of the first passivation layer 109 can include spin coating, lamination, deposition, or the like. The deposition can include chemical vapor deposition, such as plasma-enhanced chemical vapor deposition. A process temperature of the plasma-enhanced chemical vapor deposition can be between about 350 °C and about 450 °C. A process pressure of the plasma-enhanced chemical vapor deposition can be between about 2.0 Torr and about 2.8 Torr. A process time of the plasma-enhanced chemical vapor deposition can be between about 8 seconds and about 12 seconds.

[0107] Reference is made to Figure 9 The fabrication technique of the first opening OP1 can include a photolithography process and a subsequent etching process. In some embodiments, the etching process can be a non-isotropic dry etching process that uses argon and tetrafluoromethane as etchants. A process temperature of the etching process can be between about 120 °C and about 160 °C. A process pressure of the etching process can be between about 0.3 Torr and about 0.4 Torr. A process time of the etching process can be between about 33 seconds and about 39 seconds.

[0108] Alternatively, in some embodiments, the etching process can be a non-isotropic dry etching process that uses helium and nitrogen trifluoride as etchants. A process temperature of the etching process can be between about 80 °C and about 100 °C. A process pressure of the etching process can be between about 1.2 Torr and about 1.3 Torr. A process time of the etching process can be between about 20 seconds and about 30 seconds.

[0109] In some embodiments, after the aforementioned etching process, a cleaning process can be performed. The cleaning process includes a mixture of hydrogen and argon as a remote plasma at a process temperature between about 250 °C and about 350 °C, a process pressure between about 1 Torr and about 10 Torr, and in the presence of a bias energy supplied to the apparatus performing the cleaning process. The bias energy can be between about 0 W and about 200 W. The cleaning process can remove the oxide on the upper surface of the pad layer 201, which is derived from oxidation by oxygen in air, via the first opening OP1 without damaging the pad layer 201.

[0110] A passivation process can be performed on the first passivation layer 109 and the first opening POl in sequence. The passivation process can include immersing the intermediate semiconductor element in a precursor at a process temperature between about 200 °C to about 400 °C, where the precursor is dimethylaminotrimethylsilane, tetramethylsilane, or the like. An ultraviolet energy can be used to facilitate the passivation process. The passivation process can passivate the sidewalls of the first passivation layer 109 by sealing the surface pores thereof via the first opening POl to reduce undesired sidewall growth, which can affect the electronic performance of the semiconductor element 1A during subsequent processing steps. Accordingly, the performance and reliability of the semiconductor element 1A can be improved.

[0111] Referring to Figure 6 and Figure 10 At step S15, a first barrier layer 203 can be formed on the pad layer 201 and in the first opening OP1.

[0112] Referring to Figure 10 In some embodiments, the fabrication technique of the first barrier layer 203 can include a sputtering process. The sources of the sputtering process can include aluminum and sulfur hexafluoride or fluorine. The sulfur hexafluoride or fluorine can be decomposed in a plasma and provide a fluorine source to react with the deposited film, such as fluoride ions or fluoride radicals.

[0113] In some embodiments, the sources of the sputtering process can include zinc oxide and aluminum fluoride. The ratio of the sputtering power of the zinc oxide to the sputtering power of the aluminum fluoride can be about 100 W:75 W.

[0114] In some embodiments, the sputtering process can completely fill the first opening OP1. An etch-back process can be performed to recess the thickness of the first barrier layer 203. During the etch-back process, the etch rate ratio of the first barrier layer 203 to the first passivation layer 109 can be between about 100: 1 to about 1.05: 1, between about 15: 1 to about 2: 1, or between about 10: 1 to about 2: 1.

[0115] Referring to Figure 6 and Figure 11 At step S17, a first connector 205 can be formed on the first barrier layer 203.

[0116] Referring to Figure 11The fabrication technique of the first connecting member 205 can include a suitable process, such as evaporation, plating, ball drop, or screen printing. In some embodiments, the first connecting member 205 can be formed by a C4 process, which means controlled collapse chip connection bumps (C4).

[0117] Figures 12 to 14 is a cross-sectional schematic diagram illustrating a flow of fabricating a semiconductor device IB according to another embodiment of the present disclosure.

[0118] Referring to Figure 12 , an intermediate semiconductor device can be fabricated in a similar manner as described above with reference to Figures 7 to 9 . A barrier material 401 can be conformally formed in the first opening OP1 and on the upper surface of the first passivation layer 109. In some embodiments, the barrier material 401 can include aluminum fluoride. In some embodiments, the content of zinc oxide can be greater than the content of aluminum fluoride. In some embodiments, the fabrication technique of the barrier material 401 can include an atomic layer deposition method.

[0119] The atomic layer deposition method is a self-limiting, sequential monolayer-by- monolayer thin film growth technique based on surface reactions, which can provide atomic layer control and deposit conformal thin films of materials provided by multiple precursors onto substrates of different compositions. In the atomic layer deposition method, the precursors are separated during the reaction. The first precursor passes over the substrate, and a monolayer is created on the substrate. Any excess unreacted precursor is purged away. Then, a second precursor passes over the substrate and reacts with the first precursor to form a monolayer film on the substrate surface. This cycle is repeated to create a film of a desired thickness.

[0120] In some embodiments, the precursors can be trimethylaluminum and hydrogen fluoride from a hydrogen fluoride-pyridine solution. A process temperature of the atomic layer deposition method can be between about 75 °C and about 300 °C. A carrier gas of the atomic layer deposition method can be nitrogen, and a flow rate of the carrier gas can be between about 130 seem and about 150 seem.

[0121] Referring to Figure 13An etching process or a planarization process can be performed to remove the barrier material 401 formed on the upper surface of the first passivation layer 109, thereby forming the first barrier layer 203 having a U-shaped cross-sectional profile. When the etching process is used, the barrier material 401 formed in the first opening OP1 can be protected by a photoresist layer. The planarization process can be chemical mechanical polishing.

[0122] Referring to Figure 14 , the manufacturing technique of the first connecting member 205 can be similar to a procedure as described in Figure 11 , and the description thereof will not be repeated herein.

[0123] Figures 15 to 17 is a cross-sectional schematic view illustrating a procedure of manufacturing a semiconductor device 1F according to another embodiment of the present disclosure.

[0124] Referring to Figure 15 , an intermediate semiconductor device can be manufactured similar to a procedure as described in Figures 7 to 9 . An isotropic etching process can be performed to form a first recess R1 on the pad layer 201. The first recess R1 makes the upper surface of the pad layer 201 concave. In some embodiments, the etching rate of the pad layer 201 in the isotropic etching process can be faster than the etching rate of the first passivation layer 109 in the isotropic etching process. For example, the etching rate ratio of the pad layer 201 to the first passivation layer 109 during the isotropic etching process can be between about 100: 1 and about 1.05: 1. For another example, the etching rate ratio of the pad layer 201 to the first passivation layer 109 during the isotropic etching process can be between about 20: 1 and about 10: 1.

[0125] Referring to Figure 16 , the manufacturing technique of the layer of barrier material 401 can be similar to a procedure as described in Figure 12 , and the description thereof will not be repeated herein.

[0126] Referring to Figure 17 , the manufacturing technique of the first barrier layer 203 and the first connecting member 205 can be similar to a procedure as described in Figure 13 and Figure 14 , and the description thereof will not be repeated herein. The first recess R1 can increase the contact surface between the barrier material 401 and the pad layer 201. Thus, the contact resistance of the first barrier layer 203 can be reduced. As a result, the reliability of the semiconductor device 1F can be improved.

[0127] An embodiment of the present disclosure provides a semiconductor device, comprising: a substrate; a circuit layer disposed on the substrate; a pad layer disposed in the circuit layer and comprising aluminum and copper; a first barrier layer disposed on the pad layer and comprising aluminum fluoride; and a first connecting member disposed on the first barrier layer.

[0128] Another embodiment of the present disclosure provides a method for fabricating a semiconductor device, comprising providing a substrate; forming a circuit layer on the substrate; forming a pad layer in the circuit layer; forming a first passivation layer on the circuit layer; forming a first opening along the first passivation layer to expose the pad layer; forming a first barrier layer on the pad layer and in the first opening; and forming a first connecting member on the first barrier layer. The pad layer comprises aluminum and copper. The first barrier layer comprises aluminum fluoride.

[0129] Due to the design of the semiconductor device of the present disclosure, the saturated bonding property of the aluminum fluoride can prevent the underlying pad layer 201 from being corroded by various semiconductor processes, especially those containing fluorine ions. Thus, the reliability of the semiconductor device 1A can be improved.

[0130] While the present disclosure and its advantages have been disclosed in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the techniques described above can be implemented in different methodologies than those described above, and the methodologies described above can be implemented in other ways than those described. Moreover, any of the claims below that refer to other claims give no indication of their dependence on other claims, and should not be construed to be so dependent.

[0131] Further, the scope of the application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily understand, the disclosed implementations can be practiced with other process, machines, manufacture, compositions of matter, means, methods, or steps, analogous to those described but not previously described herein. Accordingly, the claims are intended to cover all such equivalents.

Claims

1. A semiconductor device, comprising: a substrate; a circuit layer disposed on the substrate; a pad layer disposed in the circuit layer and comprising aluminum and copper; a first barrier layer disposed on the pad layer and comprising aluminum fluoride; and a first connecting member disposed on the first barrier layer, wherein the first barrier layer comprises zinc oxide.

2. The semiconductor device of claim 1, further comprising a first passivation layer disposed on the circuit layer, wherein the first barrier layer is disposed in the first passivation layer.

3. The semiconductor device of claim 2, wherein a thickness of the first passivation layer is greater than a thickness of the first barrier layer.

4. The semiconductor device of claim 2, wherein a lower portion of the first connecting member extends into the first passivation layer and is disposed on the first barrier layer.

5. The semiconductor device of claim 3, further comprising a heat dissipation layer disposed below the substrate.

6. The semiconductor device of claim 5, further comprising an attachment layer disposed between the heat dissipation layer and the substrate.

7. The semiconductor device of claim 3, further comprising a buffer pad layer disposed in the circuit layer and topographically aligned with the pad layer, wherein the buffer pad layer is disposed at a vertical level lower than a vertical level of the pad layer.

8. The semiconductor device of claim 3, wherein the first barrier layer has a U-shaped cross-sectional profile.

9. A method of fabricating a semiconductor device, comprising: providing a substrate; forming a circuit layer on the substrate; forming a pad layer in the circuit layer, wherein the pad layer comprises aluminum and copper; forming a first passivation layer on the circuit layer; forming a first opening along the first passivation layer to expose the pad layer; forming a first barrier layer on the pad layer and in the first opening, wherein the first barrier layer comprises aluminum fluoride; and forming a first connecting member on the first barrier layer, wherein the first barrier layer comprises zinc oxide.

10. The method of fabricating a semiconductor device of claim 9, wherein a content of the zinc oxide is greater than a content of the aluminum fluoride.

11. The method of fabricating a semiconductor device of claim 9, wherein a process temperature of the step of forming the first passivation layer is between about 350 °C and about 450 °C.

12. The method of fabricating a semiconductor device of claim 11, wherein a process pressure of the step of forming the first passivation layer is between about 2.0 Torr and about 2.8 Torr.

13. The method of fabricating a semiconductor device of claim 9, wherein the step of forming the first opening comprises argon and tetrafluoromethane as etchants.

14. The method of fabricating a semiconductor device of claim 13, wherein a process temperature of the step of forming the first opening is between about 120 °C and about 160 °C.

15. The method of fabricating a semiconductor device of claim 14, wherein a process pressure of the step of forming the first opening is between about 0.3 Torr and about 0.4 Torr.

16. The method of claim 9, wherein the step of forming the first opening comprises helium gas and nitrogen trifluoride as etchants.

17. The method of claim 16, wherein the step of forming the first opening is performed at a process temperature between about 80 °C and about 100 °C.

18. The method of claim 17, wherein the step of forming the first opening is performed at a process pressure between about 1.2 Torr and about 1.3 Torr.

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