An array substrate, its fabrication method, and a display panel

Abstract

This invention discloses an array substrate, its fabrication method, and a display panel. The array substrate includes a substrate and multiple pixel driving circuits disposed on the substrate. Each pixel driving circuit includes a driving transistor and a storage capacitor. The driving transistor includes a first active portion and a first gate. The storage capacitor includes a first electrode plate and a second electrode plate disposed opposite to each other along the thickness direction of the substrate. The second electrode plate is disposed on the same layer as the first active portion and is made of semiconductor material. The second electrode plate includes at least a first portion, the orthographic projection of which onto the substrate lies within the orthographic projection of the first electrode plate onto the substrate. The first portion is made of lightly doped semiconductor material. This invention reduces the number of film layers in the array substrate, simplifying the process flow and reducing process complexity.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to an array substrate, its fabrication method, and a display panel. Background Technology

[0002] The more complex the design and fabrication process of an array substrate, the longer, more difficult, and more expensive the process becomes. Therefore, reducing the number of film layers on the array substrate while ensuring that its performance is not compromised is of great significance for simplifying the design and fabrication process and has attracted close attention from the industry. With the development of organic light-emitting diodes (OLEDs), it is necessary to develop a new type of array substrate and display panel containing it to overcome the shortcomings of existing technologies. Summary of the Invention

[0003] This application provides an array substrate, its fabrication method, and a display panel, which solves the problem of the large number of film layers in the array substrate in the prior art.

[0004] To solve the above-mentioned technical problems, one technical solution adopted in this application is: an array substrate, including a substrate and a plurality of pixel driving circuits disposed on the substrate, wherein the pixel driving circuits include:

[0005] The driving transistor includes a first active portion and a first gate;

[0006] The storage capacitor includes a first electrode plate and a second electrode plate disposed opposite to each other along the thickness direction of the substrate; the second electrode plate is disposed on the same layer as the first active part and both are made of semiconductor material;

[0007] The second electrode plate includes at least a first part, the orthographic projection of the first part on the substrate is located within the orthographic projection of the first electrode plate on the substrate; the first part is a lightly doped semiconductor material.

[0008] Optionally, the first electrode plate is made of a conductive material and is disposed on the same layer as the gate.

[0009] Optionally, the second electrode is located between the substrate and the first electrode;

[0010] Optionally, the driving transistor is a top-gate structure;

[0011] Optionally, the second electrode plate is electrically connected to the first gate.

[0012] Optionally, a drive transistor is used to generate drive current.

[0013] Optionally, the second electrode plate further includes a second part, which is disposed on one side of the first part and the orthographic projection of the second part on the substrate is outside the orthographic projection of the first electrode plate on the substrate; the second part is a heavily doped semiconductor material.

[0014] Optionally, the second part is elongated, and the long side of the second part contacts the side of the first part;

[0015] Optionally, the first active portion includes a source portion and a drain portion, and a channel portion located between the source portion and the drain portion; the source portion and the drain portion are made of heavily doped semiconductor material, and the channel portion is made of lightly doped semiconductor material.

[0016] Optionally, the pixel driving circuit further includes a first connection portion, which is disposed on the same layer as the second electrode plate and is made of semiconductor material; the first connection portion is made of heavily doped semiconductor material; one end of the first connection portion is connected to one end of the second electrode plate, and the other end is electrically connected to the first gate of the driving transistor.

[0017] Optionally, the first connecting part is electrically connected to the first portion;

[0018] Optionally, the first connecting part is electrically connected to the second part.

[0019] Optionally, the pixel driving circuit further includes a first switching transistor; the first terminal of the first switching transistor is electrically connected to the first gate of the driving transistor via the second portion;

[0020] Alternatively, the pixel driving circuit may further include a second connection portion.

[0021] The second connecting part is disposed on the same layer as the second electrode plate and both are made of semiconductor material; the second connecting part is made of heavily doped semiconductor material; one end of the second connecting part is electrically connected to one end of the second electrode plate, and the other end is electrically connected to the first electrode of the first switching transistor;

[0022] Optionally, the second connecting part is electrically connected to the first part;

[0023] Optionally, the second connecting part is electrically connected to the second part.

[0024] Optionally, the first electrode plate is made of a conductive material and is electrically connected to the first voltage signal line in the pixel driving circuit;

[0025] Optionally, the first voltage signal line is used to turn on the second plate.

[0026] Optionally, the first connecting part and the second connecting part are electrically connected to two different positions of the first part, respectively;

[0027] Optionally, the first connecting portion and the second connecting portion are electrically connected to opposite sides of the first portion, respectively; or

[0028] One of the first connecting part and the second connecting part is connected to the first part, and the other is connected to the second part. The first voltage signal line is used to put the second electrode plate in a conductive state; or

[0029] Both the first connecting part and the second connecting part are electrically connected to the second part.

[0030] Optionally, the first voltage signal line is a reference voltage signal line used to provide an initialization voltage for the first gate of the driving transistor;

[0031] Optionally, the reference voltage signal line is electrically connected to the second electrode of the first switching transistor; or

[0032] The first voltage signal line is the power supply voltage signal line, used to provide DC power supply voltage for driving transistors;

[0033] Optionally, the array substrate further includes a scanning circuit disposed on the substrate, the scanning circuit including a plurality of cascaded shift registers, and the first voltage signal line being electrically connected to the shift registers.

[0034] Optionally, the orthographic projection of the driving transistor on the substrate and the orthographic projection of the first switching transistor on the substrate are located on opposite sides of the orthographic projection of the storage capacitor on the substrate.

[0035] To solve the above-mentioned technical problems, another technical solution adopted in this application is: a method for fabricating an array substrate, comprising:

[0036] A semiconductor layer is formed on the substrate;

[0037] A first active portion, a second electrode, and a connection portion are obtained by patterning and lightly doping a semiconductor layer; the first active portion includes a source portion, a drain portion, and a channel portion.

[0038] A first insulating layer is formed covering the first active part and the second electrode plate;

[0039] A first conductive layer is formed on the side of the first insulating layer away from the substrate;

[0040] Patterning the first conductive layer yields the first gate and the first electrode.

[0041] Using the first gate and the first electrode plate as masks, the source, drain and connection portions are heavily doped.

[0042] To solve the above-mentioned technical problems, another technical solution adopted in this application is: a display panel, including any of the array substrates described above.

[0043] The beneficial effects of the embodiments of this application are as follows: This application provides an array substrate, a method for fabricating the same, and a display panel. The array substrate includes a substrate and a plurality of pixel driving circuits disposed on the substrate. The pixel driving circuits include a driving transistor and a storage capacitor. The driving transistor includes a first active portion and a first gate. The storage capacitor includes a first electrode plate and a second electrode plate disposed opposite to each other along the thickness direction of the substrate. The second electrode plate is disposed on the same layer as the first active portion and both are made of semiconductor material. The second electrode plate includes at least a first portion, the orthographic projection of which onto the substrate lies within the orthographic projection of which onto the substrate. The first portion is made of lightly doped semiconductor material. This method reduces the number of film layers in the array substrate, simplifying the process flow and reducing the complexity of the process. Attached Figure Description

[0044] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0045] Figure 1 This is a schematic diagram of the structure of the first embodiment of the array substrate provided in this application;

[0046] Figure 2 This is a schematic diagram of the structure of the second embodiment of the array substrate provided in this application;

[0047] Figure 3 This application provides a kind of... Figure 1 The corresponding structural diagram of the second electrode plate;

[0048] Figure 4 This application provides a kind of... Figure 2 The corresponding structural diagram of the second electrode plate;

[0049] Figure 5 This application provides a kind of... Figure 1 Schematic diagram of the corresponding array substrate;

[0050] Figure 6 This application provides a kind of... Figure 2 Schematic diagram of the corresponding array substrate;

[0051] Figure 7 This is a schematic diagram of the scanning circuit on the substrate of the array substrate provided in this application;

[0052] Figure 8 This is a schematic diagram of the structure of the third embodiment of the array substrate provided in this application;

[0053] Figure 9This application provides a corresponding method. Figure 1 A schematic diagram of the pixel driving circuit of the array substrate;

[0054] Figure 10 This application provides a corresponding method. Figure 9 An equivalent schematic diagram of the pixel driving circuit of the array substrate.

[0055] Figure 11 This application provides a corresponding method. Figure 2 A schematic diagram of the pixel driving circuit of the array substrate;

[0056] Figure 12 This application provides a corresponding method. Figure 11 An equivalent schematic diagram of the pixel driving circuit of the array substrate.

[0057] Figure 13 This is a schematic flowchart of a method for fabricating an array substrate provided in this application;

[0058] Figure 14 This is a schematic diagram of the patterned semiconductor layer of the array substrate provided in this application;

[0059] Figure 15 This is a schematic diagram of the patterned first conductive layer of the array substrate provided in this application;

[0060] Figure 16 This is a schematic diagram of the structure of the display panel provided in this application. Detailed Implementation

[0061] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0062] The terms "first," "second," and "third" in this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationships and movements between components in a specific orientation (as shown in the figures). If the specific orientation changes, the directional indications also change accordingly. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0063] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0064] In existing array substrate designs, the number of film layers is relatively large, and the capacitor in the pixel circuit is composed of two metal plates and an insulating layer between the two metal plates. Even if one of the metal plates of the capacitor is set in the same layer as the gate of the thin-film transistor, the design of the other metal plate still requires an extra mask. The increase in the number of masks obviously increases the process flow, process difficulty and implementation cost of the array substrate. Furthermore, the insulating layer between the two metal plates of the capacitor is too thick, resulting in an insufficient capacitance of the capacitor, which in turn is insufficient to meet the capacitance requirements of the pixel circuit.

[0065] Please see Figure 1 and Figure 2 , Figure 1 This is a schematic diagram of the structure of the first embodiment of the array substrate provided in this application. Figure 2 This is a schematic diagram of the structure of the second embodiment of the array substrate provided in this application.

[0066] See Figure 1This application provides an array substrate, including a substrate 1 and a plurality of pixel driving circuits 100 disposed on the substrate 1. Each pixel driving circuit 100 includes a driving transistor DTFT and a storage capacitor Cst. The array substrate may include a display area. The pixel driving circuits 100 may be located in the display area.

[0067] The driving transistor DTFT includes a first active portion 21 and a first gate 41. Optionally, the driving transistor DTFT is used to generate a driving current.

[0068] The storage capacitor Cst includes a first electrode 42 and a second electrode 22 disposed opposite to each other along the thickness direction of the substrate 1. The second electrode 22 is disposed on the same layer as the first active part 21 and both are made of semiconductor material, which simplifies the patterning process.

[0069] The second electrode 22 includes at least a first part 221, the orthographic projection of the first part 221 on the substrate 1 is located within the orthographic projection of the first electrode 42 on the substrate 1; the first part 221 is a lightly doped semiconductor material.

[0070] Specifically, the array substrate of this application embodiment includes, from bottom to top: a substrate 1, a semiconductor layer 2, a first insulating layer 3 (which may be a gate insulating layer), a first conductive layer 4, a second insulating layer 5, a source / drain electrode metal layer 6, a planarization layer 7, an anode layer 8, and a pixel definition layer 9. The substrate 1 can be a rigid substrate, such as a glass substrate, or a flexible substrate, such as a polyesterimide substrate, depending on the requirements. The substrate 1 can be a single-layer substrate or a multi-layer substrate. When the substrate 1 is a multi-layer substrate, an inorganic barrier layer is filled between adjacent layers. The inorganic barrier layer can be an inorganic insulating material such as silicon oxide or silicon nitride, depending on the requirements. The layer in contact between the substrate 1 and the semiconductor layer 2 is a buffer layer, which can be a material such as silicon oxide or silicon nitride, depending on the requirements. The semiconductor layer 2 is disposed on one side of the substrate 1 and can be an amorphous silicon layer, a monocrystalline silicon layer, a polycrystalline silicon layer, or a metal oxide layer, depending on the requirements. In this embodiment, the semiconductor layer 2 can be a polycrystalline silicon layer (PSI). The first insulating layer 3 is disposed on the side of the semiconductor layer 2 away from the substrate 1 and covers the patterned semiconductor layer 2. The first insulating layer 3 can be made of inorganic insulating materials such as silicon oxide or silicon nitride, and can be reasonably set as needed. The first conductive layer 4 is disposed on the side of the first insulating layer 3 away from the substrate 1. The first conductive layer 4 is made of a metal material with good conductivity, and can be reasonably set as needed. The second insulating layer 5 is disposed on the side of the first conductive layer 4 away from the substrate 1 and covers the patterned first conductive layer 4. The second insulating layer 5 can be made of inorganic insulating materials such as silicon oxide or silicon nitride, and can be reasonably set as needed. The source / drain electrode metal layer 6 is disposed on the side of the second insulating layer 5 away from the substrate 1. The source / drain electrode metal layer 6 is made of a metal material with good conductivity, and can be reasonably set as needed. The planarization layer 7 is disposed on the side of the source / drain electrode metal layer 6 away from the substrate 1. The anode layer 8 is disposed on the side of the planarization layer 7 away from the substrate 1. The pixel definition layer 9 is disposed on the side of the anode layer 8 away from the substrate 1.

[0071] Specifically, the driving transistor DTFT in this embodiment can be a top-gate structure, a bottom-gate structure, or a dual-gate structure, whichever is appropriate as needed. This embodiment provides a driving transistor DTFT with a top-gate structure, including a first active portion 21, a first gate 41, a first electrode 61, and a second electrode 62. The first active portion 21 is disposed on a semiconductor layer 2 and is obtained by patterning the semiconductor layer 2. The first gate 41 is disposed on a first conductive layer 4 and is obtained by patterning the first conductive layer 4. The first electrode 61 and the second electrode 62 are disposed on a source / drain electrode metal layer 6 and are obtained by patterning the source / drain electrode metal layer 6. The first active portion 21 includes a source portion 211 and a drain portion 212, and a channel portion 213 located between the source portion 211 and the drain portion 212. The source portion 211 and the drain portion 212 are made of heavily doped semiconductor material, and the channel portion 213 is made of lightly doped semiconductor material. The terms "lightly doped" and "heavily doped" in this embodiment are common knowledge to those skilled in the art and will not be elaborated upon here. In this embodiment, the channel portion 213 and the second electrode plate 22 have the same doping concentration. A first contact hole H1 is provided between the source portion 211 and the first electrode 61. The first contact hole H1 is obtained by patterning on the first insulating layer 3 and the second insulating layer 5. The first electrode 61 is connected to the source portion 211 through a conductive material filled in the first contact hole H1. A second contact hole H2 is provided between the drain portion 212 and the second electrode 62. The second contact hole H2 is obtained by patterning on the first insulating layer 3 and the second insulating layer 5. The second electrode 62 is connected to the drain portion 212 through a conductive material filled in the second contact hole H2.

[0072] Specifically, in this embodiment, the second electrode 22 of the storage capacitor Cst is obtained by patterning the semiconductor layer 2. Optionally, the first electrode 42 is made of a conductive material and the first voltage signal line S U Electrical connection. First voltage signal line S UThis can be used to put the second electrode 22 into a conductive state. In some specific embodiments, optionally, the second electrode 22 is located between the substrate 1 and the first electrode 42. Optionally, the second electrode 22 is electrically connected to the first gate 41. In some specific embodiments, the first electrode 42 and the first gate 41 are disposed on the same layer. This arrangement allows the first electrode 42 and the first gate 41 to be patterned on the same layer, simplifying the array substrate's fabrication process. The first gate 41 and the first electrode 42 serve as metal masks for the corresponding first active portion 21 and the second electrode 22, saving the masking process of at least one metal electrode layer commonly used on existing array substrates, reducing the fabrication difficulty and cost of the array substrate. Simultaneously, this arrangement results in a shorter distance between the first electrode 42 and the second electrode 22, leading to a larger storage capacitor Cst. In some specific embodiments, the first electrode 42 is disposed on the same layer as other metal layers, such as the first electrode 61 and the second electrode 62. The first electrode 42 serves as a metal mask, allowing the portion of the second electrode 22 other than the first portion 221 to be heavily doped.

[0073] See Figure 2 Optionally, to improve the electrical connection between the second electrode 22 and other devices, the second electrode 22 may further include a second portion 222. The second portion 222 is disposed on one side of the first portion 221, and the orthographic projection of the second portion 222 on the substrate 1 is outside the orthographic projection of the first electrode 42 on the substrate 1. The second portion 222 is made of heavily doped semiconductor material. In some specific embodiments, the second portion 222 may optionally be elongated (e.g., ...). Figure 4 (As shown). Optionally, the long side of the second part 222 contacts the side of the first part 221 to achieve electrical connection. This arrangement increases the contact area between the second part 222 and the first part 221, improving the conductivity between the second electrode plate 22 and other devices. Electrical connection with other devices can be achieved without passing through the lightly doped and low-conductivity first part 221.

[0074] Please see Figures 3-6 , Figure 3 This application provides a kind of... Figure 1 The corresponding structural diagram of the second electrode plate, Figure 4 This application provides a kind of... Figure 2 The corresponding structural diagram of the second electrode plate, Figure 5 This application provides a kind of... Figure 1 Schematic diagram of the corresponding array substrate. Figure 6 This application provides a kind of... Figure 2 A schematic diagram of the corresponding array substrate layout.

[0075] See Figure 3 and Figure 4In some specific embodiments, the pixel driving circuit 100 further includes a first connection portion 231. The first connection portion 231 and the second electrode plate 22 are disposed on the same layer and are both made of semiconductor material. The first connection portion 231 is made of heavily doped semiconductor material. The heavy doping process of the first connection portion 231 is performed with the first gate 41 and the first electrode plate 42 as masks, which reduces the process difficulty of the array substrate. One end of the first connection portion 231 is connected to one end of the second electrode plate 22, and the other end is electrically connected to the first gate 41 of the driving transistor DTFT. Optionally, the first connection portion 231 can be electrically connected to the first part 221 or to the second part 222.

[0076] In some specific embodiments, optionally, see [link to relevant documentation]. Figure 5 The diagram illustrates a pixel circuit comprising a driving transistor DTFT, a data writing transistor T1, a compensation transistor T2, a first reset transistor T3, a first light-emitting control transistor T4, a second light-emitting control transistor T5, a second reset transistor T6, and a storage capacitor Cst. The storage capacitor Cst, the first reset transistor T3, and the second reset transistor T6 are located in the upper half of the layout, with the first reset transistor T3 having a dual-gate structure. The storage capacitor Cst is located between the compensation transistor T2 and the first reset transistor T3. The data writing transistor T1 and the compensation transistor T2 are located in the middle of the layout, with the compensation transistor T2 also having a dual-gate structure. The driving transistor DTFT, the first light-emitting control transistor T4, and the second light-emitting control transistor T5 are located in the lower half of the layout.

[0077] Optionally, the orthographic projections of the driving transistor DTFT and the first switching transistor on the substrate 1 are located on opposite sides of the orthographic projections of the storage capacitor Cst on the substrate 1. By applying a conduction voltage to the first electrode 42, the resistance of the electrical connection between the driving transistor DTFT and the first switching transistor is made smaller, thus meeting the requirements.

[0078] The first switching transistor may be the first reset transistor T3, or other switching transistors that need to be connected to the driving transistor but are blocked by the second plate 22.

[0079] In this embodiment, the orthographic projection of the second electrode plate 22 of the storage capacitor Cst onto the substrate 1 is located within the orthographic projection of the first electrode plate 42 onto the substrate 1, that is, the second electrode plate 22 only includes the first part 221.

[0080] The pixel driving circuit 100 also includes a second connection portion 232; the second connection portion 232 and the second electrode plate 22 are disposed on the same layer and are both made of semiconductor material, the second connection portion 232 is made of heavily doped semiconductor material; the heavy doping process of the second connection portion 232 is performed with the first gate 41 and the first electrode plate 42 as masks, reducing the process difficulty of the array substrate. One end of the second connection portion 232 is electrically connected to one end of the second electrode plate 22, and the other end is electrically connected to the first electrode of the first switching transistor. Optionally, the second connection portion 232 can be electrically connected to the first part 221, and can also be electrically connected to the second part 222.

[0081] In some specific embodiments, the first connecting portion 231 and the second connecting portion 232 are electrically connected to two different locations of the first portion 221, respectively. Since the first portion 221 is made of a lightly doped semiconductor material, its conductivity is poor. The resistance of the first connecting portion 231 connected to the second connecting portion 232 via the lightly doped first portion 221 is relatively large. Therefore, the resistance through the first voltage signal line S... U An electrical signal is provided to the first electrode 42, which is electrically connected to it, so that the second electrode 22, which is correspondingly disposed to the first electrode 42, is in a conducting state. This allows the first gate of the driving transistor DTFT to be electrically connected to the first electrode of the first switching transistor via the first connection portion 231, the conducting first portion 221, and the second connection portion 232, with a relatively low line impedance. Optionally, in this embodiment, the first connection portion 231 and the second connection portion 232 are electrically connected to opposite sides of the first portion 221, respectively. Optionally, the first connection portion 231 and the second connection portion 232 are located on opposite sides of the first portion 221.

[0082] In some specific embodiments, optionally, one of the first connecting portion 231 and the second connecting portion 232 is connected to the first portion 221, and the other is connected to the second portion 222. In this embodiment, the first connecting portion 231 is connected to the first portion 221, and the second connecting portion 232 is connected to the second portion 222. Since the resistance of the first connecting portion 231 connected to the second connecting portion 232 via the lightly doped first portion 221 and the heavily doped second portion 222 is relatively large, the resistance through the first voltage signal line S... U An electrical signal is provided to the first electrode plate 42 that is electrically connected to it, so that the second electrode plate 22 that is corresponding to the first electrode plate 42 is in a conducting state, thereby making the heavily doped second part 222, the conducting first part 221, and the first connecting part 232 electrically connected to the first gate 41 of the driving transistor DTFT.

[0083] In some specific embodiments, both the first connecting portion 231 and the second connecting portion 232 are electrically connected to the second portion 222. Since the second portion 222 is made of heavily doped semiconductor material, it has good conductivity. The second electrode 22 achieves good electrical connection with the first gate 41 of the driving transistor DTFT and with the first electrode of the first switching transistor. Optionally, the first voltage signal line S... U The provided electrical signal can either put the first part 221 of the second plate 22 into a conducting state or into an intermediate state between the conducting and closed states, that is, ensure that the resistance of the first part 221 is not too large.

[0084] Optionally, the driving transistor DTFT can be a PMOS transistor or an NMOS transistor. The first part 221 can be an N-type doped or P-type doped semiconductor, which can be set as needed. The storage capacitor Cst has a structure similar to that of a transistor, with the first plate 42 acting as a gate of the transistor and the second plate 22 acting as an active layer of the transistor, and the first plate 42 and the second plate 22 can form a capacitor. Optionally, the driving transistor DTFT can be a PMOS transistor. Optionally, the storage capacitor Cst is similar to a PMOS transistor. Optionally, the first voltage signal line S U The DC voltage can be low to keep the second plate 22 in a conducting state. Optionally, the first voltage signal line S U The voltage is lower than the gate turn-on voltage of the first gate 41, so that the second plate 22 is in the conducting state.

[0085] Optionally, the driving transistor DTFT can be an NMOS transistor. Optionally, the storage capacitor Cst is similar to an NMOS transistor. Optionally, the first voltage signal line S... U The DC voltage can be high to keep the second plate 22 in a conducting state.

[0086] In some specific embodiments, optionally, the first voltage signal line S U A reference voltage signal line Vref can be used to provide an initialization voltage for the first gate 41 of the driving transistor DTFT and / or the light-emitting device LE. In this embodiment, the reference voltage signal line Vref is electrically connected to the first gate of the first switching transistor. The first voltage signal line S... U The reference voltage signal line Vref is applicable to various situations where the first connection part 231 and the second connection part 232 are connected to the second electrode plate 22.

[0087] In some specific embodiments, optionally, the first voltage signal line S UThe power supply voltage signal line VDD can be used to provide a DC power supply voltage to the driving transistor DTFT. In this embodiment, the pixel driving circuit 100 also includes a first light-emitting control transistor T4. The power supply voltage signal line is electrically connected to the first terminal of the first light-emitting control transistor T4, and the second terminal of the first light-emitting control transistor T4 is electrically connected to the first terminal of the driving transistor DTFT. First voltage signal line S U The power supply voltage signal line VDD is suitable for situations where both the first connection part 231 and the second connection part 232 are electrically connected to the second part 222. First voltage signal line S U The power supply voltage signal line VDD is applicable when the first terminal of the first switching transistor is electrically connected to the first gate 41 of the driving transistor DTFT via the second part 222.

[0088] In some specific embodiments, optionally, see [link to relevant documentation]. Figure 6 The pixel driving circuit 100 shown therein is... Figure 5 The difference in the pixel driving circuit 100 shown is that, in this embodiment, the second electrode plate 22 of the storage capacitor Cst further includes a second portion 222, which is disposed on one side of the first portion 221 and the orthographic projection of the second portion 222 on the substrate 1 is located outside the orthographic projection of the first electrode plate 42 on the substrate 1. Figure 5 The first plate 42 and the second plate 22 of the corresponding storage capacitor Cst have a large facing area, but the second plate 22 needs to be in a conducting state. Figure 6 The area of ​​the first plate 42 and the second plate 22 facing each other in the corresponding storage capacitor Cst is small, but it is not necessary for the second plate 22 to be in a conducting state. If... Figure 6 The second plate 22 of the corresponding storage capacitor Cst is in the conducting state, and the electrical connection between the first electrode of the first switching transistor and the first gate 41 of the driving transistor DTFT is better.

[0089] Optionally, the first terminal of the first switching transistor of the pixel driving circuit 100 is electrically connected to the first gate 41 of the driving transistor DTFT via the second portion 222. Optionally, the first voltage signal line S U The provided electrical signal can either put the first part 221 of the second plate 22 into a conducting state or into an intermediate state between the conducting and closed states, that is, ensure that the resistance of the first part 221 is not too large.

[0090] Please see Figure 7 , Figure 7 This is a schematic diagram of the scanning circuit on the substrate of the array substrate provided in this application.

[0091] Optional, see Figure 7The array substrate also includes a scanning circuit disposed on the substrate, the scanning circuit including multiple cascaded shift registers SR, and a first voltage signal line S. U Electrically connected to the shift register SR. First voltage signal line S U The voltage can be either high or low DC, matching the doping type of the second electrode 22 to enable its conduction. Multiple cascaded shift registers SR can be electrically connected to the scan signal lines, outputting scan signals sequentially to the scan signal lines (such as the first scan signal line S1, the second scan signal line S2, and the third scan signal line S3). The array substrate may also include a non-display area, where the scan circuitry can be located. Optionally, the first electrode 42 in any row of multiple pixel driving circuits 100 can be integrated into a single, relatively wide strip.

[0092] Optionally, the array substrate also includes a light-emitting control circuit disposed on the substrate, electrically connected to the light-emitting control signal line EM. The light-emitting control circuit can output the light-emitting control signal EM to the scan signal line step by step. The light-emitting control circuit can be located in a non-display area.

[0093] In some specific embodiments, the first voltage signal line S U Electrically connected to the shift register SR on the scanning circuit on substrate 1. First voltage signal line S U The electrical connection of the shift register SR on the scanning circuit on substrate 1 is suitable for various situations where the first connection part 231 and the second connection part 232 are connected to the second electrode plate 22. The shift register SR on the scanning circuit can be connected to a high-level (Vgh) signal line or a low-level (Vgl) signal line.

[0094] Please see Figure 8 , Figure 8 This is a schematic diagram of the structure of the third embodiment of the array substrate provided in this application.

[0095] See Figure 8 The array substrate provided in the third embodiment of this application differs from the array substrate in the first embodiment in that the relative positions of the first conductive layer 4 and the second insulating layer 5 are changed in this embodiment. Specifically, the first conductive layer 4 is disposed on one side of the substrate 1; the first conductive layer 4 is patterned to form a first gate 41 and a first electrode 42 on the same layer; the second insulating layer 5 is disposed on the side of the first conductive layer 4 away from the substrate 1 and covers the first gate 41 and the first electrode 42; the semiconductor layer 2 is disposed on the side of the second insulating layer 5 away from the substrate 1. These differences result in the driving transistor DTFT of this embodiment having a bottom-gate structure, and the relative positions of the first electrode 42 and the second electrode 22 of the storage capacitor Cst are changed.

[0096] Please see Figures 9-12 , Figure 9This application provides a corresponding method. Figure 1 A schematic diagram of the pixel driving circuit of the array substrate. Figure 10 This application provides a corresponding method. Figure 9 An equivalent schematic diagram of the pixel driving circuit of the array substrate. Figure 11 This application provides a corresponding method. Figure 2 A schematic diagram of the pixel driving circuit of the array substrate. Figure 12 This application provides a corresponding method. Figure 11 An equivalent schematic diagram of the pixel driving circuit of the array substrate.

[0097] The structure of the pixel driving circuit 100 in the specific embodiments of this application is not limited. See also Figures 9-12 Optionally, the pixel driving circuit 100 can be a 7T1C pixel driving circuit 100.

[0098] Optionally, a driving transistor DTFT is used to generate a driving current. Its first terminal 61 is electrically connected to the second terminal of the first light-emitting control transistor T4, its second terminal 62 is electrically connected to the first terminal of the second light-emitting control transistor T5, and its first gate 41 is electrically connected to the second plate 22 of the storage capacitor Cst.

[0099] Optionally, the pixel driving circuit 100 further includes: a data writing transistor T1, used to write the data signal on the data line Data to the first terminal 61 of the driving transistor DTFT in response to the second scan signal on the second scan signal line S2. The first terminal of the data writing transistor T1 is electrically connected to the data line, the second terminal of the data writing transistor T1 is electrically connected to the first terminal 61 of the driving transistor DTFT, and the gate of the data writing transistor T1 is electrically connected to the second scan signal line S2.

[0100] Optionally, the pixel driving circuit 100 further includes a compensation transistor T2. The compensation transistor T2 is used to write a data signal to the first gate 41 in response to the second scan signal on the second scan signal line S2, via the turned-on driving transistor DTFT and the turned-on compensation transistor T2. Optionally, the compensation transistor T2 is a dual-gate transistor, reducing leakage current to the first gate 41 via the compensation transistor T2. The first terminal of the compensation transistor T2 is electrically connected to the second terminal 62 of the driving transistor DTFT, the second terminal of the compensation transistor T2 is electrically connected to the first gate 41 of the driving transistor DTFT, and the gate of the compensation transistor T2 is electrically connected to the second scan signal line S2.

[0101] Optionally, the pixel driving circuit 100 further includes a first reset transistor T3. The first reset transistor T3 is used to write the initialization voltage on the reference voltage signal line Vref into the first gate 41 of the driving transistor DTFT in response to the first scan signal of the first scan signal line S1 for initialization. Optionally, the first reset transistor T3 is a dual-gate transistor, reducing leakage current through the first gate 41 to the first reset transistor T3. The first terminal of the first reset transistor T3 is electrically connected to the reference voltage signal line Vref, the second terminal of the first reset transistor T3 is electrically connected to the first gate 41 of the driving transistor DTFT, and the gate of the first reset transistor T3 is electrically connected to the first scan signal line S1.

[0102] Optionally, the pixel driving circuit 100 further includes a first light-emitting control transistor T4. The first terminal of the first light-emitting control transistor T4 is electrically connected to the power supply voltage signal line VDD, the second terminal of the first light-emitting control transistor T4 is electrically connected to the first terminal 61 of the driving transistor DTFT, and the gate of the first light-emitting control transistor T4 is electrically connected to the light-emitting control signal line EM.

[0103] Optionally, the pixel driving circuit 100 further includes a second light-emitting control transistor T5. The first terminal of the second light-emitting control transistor T5 is electrically connected to the second terminal 62 of the driving transistor DTFT, the second terminal of the second light-emitting control transistor T5 is electrically connected to the first terminal (e.g., the anode) of the light-emitting device LE, and the gate of the second light-emitting control transistor T5 is electrically connected to the light-emitting control signal line EM.

[0104] Optionally, the pixel driving circuit 100 further includes a second reset transistor T6. The second reset transistor T6 is used to write an initialization voltage on the reference voltage signal line Vref into the anode of the light-emitting device LE in response to the third scan signal of the third scan signal line S3, thereby initializing the light-emitting device LE. The first terminal of the second reset transistor T6 is electrically connected to the reference voltage signal line Vref, the second terminal of the second reset transistor T6 is electrically connected to the first terminal (e.g., the anode) of the light-emitting device LE, and the gate of the second reset transistor T6 is electrically connected to the third scan signal line S3.

[0105] Optionally, the storage capacitor Cst includes a first electrode 42 and a second electrode 22 disposed opposite to each other along the thickness direction of the substrate 1; the second electrode 22 and the first active portion 21 are disposed on the same layer and are both made of semiconductor material, simplifying the patterning process. The second electrode 22 includes at least a first portion 221, the orthographic projection of the first portion 221 onto the substrate 1 being located within the orthographic projection of the first electrode 42 onto the substrate 1; the first portion 221 is made of lightly doped semiconductor material. See also Figure 10 In this embodiment of the application, the storage capacitor Cst is equivalent to a short circuit in the second electrode 22 of the pixel driving circuit 100.

[0106] In some specific embodiments, the pixel circuit can also adopt a 6T1C circuit or a 6T2C circuit, which can be set appropriately according to needs.

[0107] Please see Figures 13-15 , Figure 13 This is a schematic flowchart of a method for fabricating an array substrate provided in this application. Figure 14 This is a schematic diagram of the patterned semiconductor layer of the array substrate provided in this application. Figure 15 This is a schematic diagram of the patterned first conductive layer of the array substrate provided in this application.

[0108] See Figure 13 The method for fabricating an array substrate according to a specific embodiment of this application includes:

[0109] S1. Form a semiconductor layer 2 on substrate 1;

[0110] S2, see also Figure 14 The semiconductor layer 2 is patterned and lightly doped to obtain a first active portion 21, a second electrode 22, and a connection portion; the first active portion 21 includes a source portion 211, a drain portion 212, and a channel portion 213; the connection portion includes a first connection portion 231 and / or a second connection portion 232.

[0111] S3, forming a first insulating layer 3 covering the first active part 21 and the second electrode plate 22;

[0112] S4. A first conductive layer 4 is formed on the side of the first insulating layer 3 away from the substrate 1;

[0113] S5, see also Figure 15 Patterning the first conductive layer 4 yields the first gate 41 and the first electrode 42.

[0114] S6. Using the first gate 41 and the first electrode plate 42 as masks, the source part 211, the drain part 212, and the connection part are heavily doped.

[0115] Optionally, the connecting portion includes a first connecting portion 231 and / or a second connecting portion 232.

[0116] The array substrate provided in this application embodiment can be used to fabricate the array substrate provided in the above embodiment, and has the beneficial effects provided in the above embodiment, which will not be repeated here.

[0117] Please see Figure 16 , Figure 16 This is a schematic diagram of the structure of the display panel provided in this application.

[0118] See Figure 16This application provides a display panel that includes the array substrate described in the above embodiments. The display panel can be an LED display panel or an OLED display panel. This embodiment uses an OLED display panel as an example for explanation. Optionally, the display panel includes an array substrate and an organic light-emitting layer 10, a cathode electrode 11, and an encapsulation layer 12 disposed on the array substrate.

[0119] A driving transistor DTFT is used to generate a driving current so that the organic light-emitting layer 10 emits light.

[0120] The display panel provided in this application can be applied to electronic devices such as desktop computers, laptops, personal digital assistants (PDAs), mobile phones, and televisions.

[0121] The display panel provided in this application includes the array substrate of the above embodiments. Therefore, the display panel provided in this application has the beneficial effects described in the above embodiments, which will not be repeated here.

[0122] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces, or indirect coupling or communication connection between apparatuses or units, and may be electrical, mechanical, or other forms.

[0123] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0124] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. An array substrate comprising a substrate, and a plurality of pixel drive circuits provided on the substrate, characterized by, The pixel driving circuit comprises: a driving transistor comprising a first active part and a first gate; a storage capacitor comprising a first plate and a second plate oppositely arranged along a thickness direction of the substrate; the second plate is arranged in the same layer as the first active part and is of a semiconductor material; wherein the second plate comprises at least a first part, a normal projection of the first part on the substrate is located within a normal projection of the first plate on the substrate; the first part is of a lightly doped semiconductor material; the pixel driving circuit further comprises a first connecting part arranged in the same layer as the second plate and of a semiconductor material; the first connecting part is of a heavily doped semiconductor material; one end of the first connecting part is connected with one end of the second plate, and the other end is electrically connected with the first gate of the driving transistor; the pixel driving circuit further comprises a first switch transistor and a second connecting part arranged in the same layer as the second plate and of a semiconductor material; the second connecting part is of a heavily doped semiconductor material; one end of the second connecting part is electrically connected with one end of the second plate, and the other end is electrically connected with a first electrode of the first switch transistor; the first plate is of a conductive material and is electrically connected with a first voltage signal line, the first voltage signal line is used to make the second plate in a conductive state.

2. The array substrate of claim 1, wherein, the first plate is of a conductive material and is arranged in the same layer as the first gate.

3. The array substrate of claim 2, wherein, the second plate is located between the substrate and the first plate.

4. The array substrate of claim 2, wherein, the driving transistor is of a top gate structure.

5. The array substrate of claim 2, wherein, the second plate is electrically connected with the first gate.

6. The array substrate of claim 2, wherein, the driving transistor is used to generate a driving current.

7. The array substrate of claim 1, wherein, the second plate further comprises a second part arranged on one side of the first part and a normal projection of the second part on the substrate is located outside a normal projection of the first plate on the substrate; the second part is of a heavily doped semiconductor material.

8. The array substrate of claim 7, wherein, the second part is of a long strip shape, and a long side of the second part is in contact with a side of the first part; a length of the second part in a first direction is greater than a length of the first part in the first direction, the first part and the second part are arranged along a second direction, and the first direction and the second direction intersect.

9. The array substrate of claim 7, wherein, the first active part comprises a source part and a drain part, and a channel part located between the source part and the drain part; the source part and the drain part are of a heavily doped semiconductor material, and the channel part is of a lightly doped semiconductor material.

10. The array substrate of claim 1, wherein, the first connecting part is electrically connected with the first part.

11. The array substrate of claim 7, wherein, the first connecting part is electrically connected with the second part.

12. The array substrate of claim 7, wherein, the first electrode of the first switch transistor is electrically connected with the first gate of the driving transistor through the second part.

13. The array substrate of claim 12, wherein, the second connecting part is electrically connected with the first part.

14. The array substrate of claim 12, wherein, the second connecting part is electrically connected with the second part.

15. The array substrate of claim 7, wherein, the first connecting part and the second connecting part are respectively electrically connected with two different positions of the first part.

16. The array substrate of claim 15, wherein, the first connecting part and the second connecting part are respectively electrically connected with opposite sides of the first part; or One of the first connection part and the second connection part is connected with the first part, and the other is connected with the second part, and the first voltage signal line is used to make the second plate in a conductive state; or Both the first connection part and the second connection part are electrically connected with the second part.

17. The array substrate of claim 1, wherein, The first voltage signal line is a reference voltage signal line, which is used to provide an initialization voltage for the first gate of the driving transistor.

18. The array substrate of claim 17, wherein, The reference voltage signal line is electrically connected with the second electrode of the first switch transistor, and the first switch transistor is used to write the initialization voltage on the reference voltage signal line into the first gate of the driving transistor; or The first voltage signal line is a power supply voltage signal line, which is used to provide a direct current power supply voltage for the driving transistor. Or The array substrate further comprises a scanning circuit arranged on the substrate, and the scanning circuit comprises a plurality of cascaded shift registers, and the first voltage signal line is electrically connected with the shift registers.

19. The array substrate of claim 1, wherein, The orthographic projection of the driving transistor on the substrate and the orthographic projection of the first switch transistor on the substrate are located on opposite sides of the orthographic projection of the storage capacitor on the substrate.

20. The array substrate of claim 1, wherein, The second plate of the storage capacitor in the pixel driving circuit is equivalent to a short circuit.

21. The array substrate of claim 7, wherein The pixel driving circuit further comprises a data writing transistor, the first electrode of the data writing transistor is electrically connected with a data line, and the second electrode of the data writing transistor is electrically connected with the first electrode of the driving transistor. The pixel driving circuit further comprises a compensation transistor, the first electrode of the compensation transistor is electrically connected with the second electrode of the driving transistor, and the second electrode of the compensation transistor is electrically connected with the first gate of the driving transistor.

22. The array substrate of claim 21, wherein, The second part is connected between the active layer of the compensation transistor and the active layer of the first switch transistor.

23. The array substrate of claim 21, wherein, The active layer of the compensation transistor is connected with the first connection part, and the active layer of the first switch transistor is connected with the second connection part.

24. An array substrate comprising a substrate, and a plurality of pixel driving circuits provided on the substrate, characterized in that, The pixel driving circuit comprises: a driving transistor comprising a first active part and a first gate; a storage capacitor comprising a first plate and a second plate arranged oppositely along the thickness direction of the substrate; the second plate is arranged in the same layer as the first active part and is of a semiconductor material; wherein the second plate comprises at least a first part, the orthographic projection of the first part on the substrate is located within the orthographic projection of the first plate on the substrate; and the first part is of a lightly doped semiconductor material. The second plate further comprises a second part, the second part is arranged on one side of the first part, and a projection of the second part on the substrate is located outside a projection of the first plate on the substrate; the second part is of a heavily doped semiconductor material; the second part is long-strip-shaped, and a long side of the second part is in contact with a side of the first part; a length of the second part in a first direction is greater than a length of the first part in the first direction, the first part and the second part are arranged along a second direction, and the first direction and the second direction intersect; and the second plate in the pixel driving circuit is equivalent to a short circuit.

25. The array substrate of claim 24, wherein, The first plate is of a conductive material and is electrically connected with a first voltage signal line, and the first voltage signal line is used to make the second plate in a conductive state.

26. The array substrate of claim 24, wherein, The pixel driving circuit further comprises a first switch transistor, a first electrode of the first switch transistor is electrically connected with a first gate electrode of the driving transistor through the second part; and the first switch transistor is used to write an initialization voltage on a reference voltage signal line into the first gate electrode of the driving transistor. A projection of the driving transistor on the substrate and a projection of the first switch transistor on the substrate are located on opposite sides of a projection of the storage capacitor on the substrate. The pixel driving circuit further comprises a data writing transistor, a first electrode of the data writing transistor is electrically connected with a data line, and a second electrode of the data writing transistor is electrically connected with a first electrode of the driving transistor. The pixel driving circuit further comprises a compensation transistor, a first electrode of the compensation transistor is electrically connected with a second electrode of the driving transistor, and a second electrode of the compensation transistor is electrically connected with the first gate electrode of the driving transistor. The second part is connected between an active layer of the compensation transistor and an active layer of the first switch transistor.

27. A manufacturing method for manufacturing the array substrate according to any one of claims 1 to 26, characterized by, Comprising: forming a semiconductor layer on a substrate; performing a patterning treatment and a light doping treatment on the semiconductor layer to obtain a first active part, a second plate, and a connecting part; the first active part comprises a source part, a drain part, and a channel part; forming a first insulating layer covering the first active part and the second plate; forming a first conductive layer on a side of the first insulating layer away from the substrate; patterning the first conductive layer to obtain a first gate and a first plate; performing a heavy doping treatment on the source part, the drain part, and the connecting part by taking the first gate and the first plate as a mask.

28. A display panel comprising: The array substrate of any one of claims 1-26.

Images