A clock generation circuit for generating multiple output clocks for a serializer / deserializer circuit

Abstract

A clock generation circuit for generating multiple output clocks includes: a differential circuit for receiving a single input clock signal and outputting two differential clock signals and a DC signal; a first polyphase filter for generating four clock signals orthogonal to each other from the differential clock signals; a plurality of setting buffers for setting the same DC point for the four clock signals and generating four resultant clock signals; a plurality of coupled polyphase filters for generating another four clock signals orthogonal to each other and outputting eight resultant clock signals; a phase mixer for generating eight output clock signals that are 45 degrees out of phase with each other; and a plurality of recovery buffers for setting the DC point for each of the eight clock signals and generating eight output clock signals at the same DC point.

Description

Technical Field

[0001] The present invention relates to a clock generation circuit for generating multiple clocks with multiple phases, and more particularly to a clock generation circuit that uses multiple tunable polyphase filters to generate multiple clocks with multiple phases over a wide frequency band. Background Art

[0002] A serializer / deserializer (SERDES) architecture is a circuit used for high-speed digital data transmission between integrated circuit chips. The serializer / deserializer requires many clocks with multiple phases. Conventional clock generation circuits use interpolators, phase locked loops (PLLs), and / or delay locked loops (DLLs) to generate the multiple phases. Since these clocks are often generated at different phases in the clock generation circuit, the resulting output clocks may contain duty cycle errors and skew errors. To correct this problem, conventional clock generation circuits additionally include a duty cycle correction circuit and a quadrature correction, which increases the size, cost, and complexity of the entire circuit. In addition, a delay locked loop is a closed loop circuit that requires startup and stabilization time to lock the clock at a specific frequency, thus increasing the time required to generate multiple clocks.

[0003] U.S. Patent No. 8,774,336 teaches a circuit for generating multiple-phase clocks using a polyphase filter. This circuit requires four input clocks of a single fixed frequency, which cannot be adjusted. To generate clocks of different phases, adjacent clocks are generated by the polyphase filter and sent to an interpolator to differentially generate clocks of intermediate phases. Therefore, this method of mixing clock phases is complex.

[0004] U.S. Patent No. 7,733,984 teaches a serializer / deserializer circuit using a polyphase filter network with a phase rotator circuit. The interpolator used to generate four phases of a clock causes skew errors. In addition, the polyphase filter can only operate at a fixed frequency.

[0005] U.S. Patent No. 9,350,528 teaches a serializer / deserializer circuit using a polyphase filter network, where the clocks generated by the interpolator require correction of quadrature errors.

[0006] Therefore, there is a great need for a clock generation circuit that can generate multiple clocks with multiple phases, where the clock generation circuit does not require complex circuitry, and the generated clocks have a minimum duty cycle error and a minimum skew error. Summary of the Invention

[0007] The present invention discloses a clock generation circuit using an open loop circuit, where the open loop circuit can generate multiple clocks with multiple phases from a single input clock.

[0008] One embodiment of the present invention discloses a clock generation circuit for generating multiple output clocks for a serializer / deserializer circuit, the multiple output clocks having different phase angles respectively. The clock generation circuit includes: a differential circuit for receiving a single input clock signal and outputting two differential clock signals that are 180 degrees apart from each other and a DC signal representing the DC point of the two differential clock signals; a first polyphase filter for receiving the two differential output signals and the DC signal and generating four clock signals that are orthogonal to each other; a plurality of setting buffers for receiving the four clock signals, setting a same DC point for the four clock signals, and generating four resultant clock signals; a plurality of coupled polyphase filters for receiving the four resultant clock signals, generating four other clock signals that are orthogonal to each other and have a micro skew θ with respect to one of the four resultant clock signals, and outputting eight resultant clock signals; a phase mixer for receiving the eight resultant clock signals, mixing every two adjacent phase signals, and generating an intermediate output signal to generate eight output clocks that are 45 degrees apart from each other; and a plurality of recovery buffers for receiving the eight clock signals from the phase mixer and setting a DC point for each of the eight clock signals and generating eight output clocks that are exactly 45 degrees apart from each other and all at a same DC point.

[0009] The single input clock signal is a square wave, and the clock generation circuit further includes: a single-ended to differential circuit for receiving the single input clock signal and generating two differential square waves; and a square wave to sine wave circuit for receiving the two differential square waves and converting the two differential square waves into two differential sine waves, where the two differential sine waves are output as the two differential clock signals that are 180 degrees apart from each other.

[0010] Multiple coupled polyphase filters include: a second polyphase filter for receiving the four resultant clock signals and performing internal superposition of multiple clock signals with the same phase difference to generate four clock signals with corrected amplitudes; and a third polyphase filter for receiving the four clock signals with corrected amplitudes and generating the other four mutually orthogonal clock signals; wherein the other four clock signals and the four clock signals with corrected amplitudes are output to the phase mixer as the eight resultant clock signals, the first polyphase filter, the second polyphase filter, and the third polyphase filter receive the same multiple selection codes to adjust multiple internal circuits according to the multiple frequencies of multiple input clock signals, each polyphase filter includes a first resistor bank and a second resistor bank, and the multiple selection codes select a first multiple of resistors from the first resistor bank and a second multiple of resistors from the second resistor bank to adjust the multiple polyphase filters. Description of the Drawings

[0011] Figure 1 Schematic diagram of a circuit for generating 8 clock signals with different phases using a single input clock according to an embodiment of the present invention.

[0012] Figure 2A In Figure 1 Schematic diagram of the clock phases generated between the second polyphase filter and the third polyphase filter shown.

[0013] Figure 2B In Figure 1 Schematic diagram of the clock phases generated between the third polyphase filter and the adjacent phase mixer in the circuit shown.

[0014] Figure 2C In Figure 1 Schematic diagram of the clock phases generated between the adjacent phase mixer and the AC-coupled DC restoration buffer in the circuit shown.

[0015] Figure 3 Shows Figure 1 The clock signals and internal components generated by the first polyphase filter and the AC-coupled DC restoration buffer in the circuit shown.

[0016] Figure 4 Shows Figure 1 The internal components of the second polyphase filter, the third polyphase filter, the adjacent phase mixer, and the DC restoration buffer in the circuit shown.

[0017] Figure 5 Shows Figure 1 The internal components of the single-ended to differential circuit coupled to the square wave to sine wave circuit shown.

[0018] Figure 6A Shows Figure 1 The internal components and clock phases of the first polyphase filter shown.

[0019] Figure 6B Shows Figure 1 The internal components and clock phases of the second polyphase filter shown.

[0020] Figure 6C Shows Figure 1 The internal components and clock phases of the third polyphase filter shown.

[0021] Figure 7 Schematic diagram of the first adjustable resistor bank and the second adjustable resistor bank of a polyphase filter according to an embodiment of the present invention.

[0022]

Symbol description

[0023] 100: Circuit

[0024] 105: Single-ended to differential circuit

[0025] 107: Square wave to sine wave circuit

[0026] 110: Differential circuit

[0027] 120: First passive polyphase filter

[0028] 130: AC-coupled DC setting buffer

[0029] 140: Second passive polyphase filter

[0030] 150: Third passive polyphase filter

[0031] 160: Adjacent phase mixer

[0032] 170: AC-coupled DC restoration buffer

[0033] CLK_IN: Input clock

[0034] Sinp, Sinn: Differential sine wave signal

[0035] DC: DC voltage signal

[0036] 45, 90, 135, 180, 225, 270, 315, 360: Phase Detailed implementation method

[0037] FIG. 1 is a schematic diagram of a circuit 100 that generates eight clock signals with different phases using a single input clock according to an embodiment of the present invention. As shown in FIG. 1, the circuit 100 includes a differential circuit 110, and the differential circuit 110 includes a single-ended to differential circuit 105 and a square wave to sine wave circuit 107. The differential circuit 110 receives an input clock CLK_IN, and the input clock CLK_IN is a square wave. The single-ended to differential circuit 105 generates a differential square wave signal, which is then converted by the square wave to sine wave circuit 107 into differential sine wave signals Sinp and Sinn. The differential sine wave signals and a DC voltage signal DC of the differential sine wave signals are transmitted to a first passive polyphase filter 120. In addition, a selection code R for frequency selection is also input to the first passive polyphase filter 120, and these selection codes are used to tune the resistors in the passive polyphase filter according to the frequency of the incoming signal. The first passive polyphase filter 120 generates four mutually orthogonal sine waves, each having phases of 45, 135, 225, and 315. These four sine waves have different amplitudes, that is, these four sine waves are not at the same DC level. These four sine waves are input to a plurality of AC coupled DC setting buffers 130, which set the same DC point for each sine wave by rejecting the DC level of the incoming signal.

[0038] Since there will be some orthogonality errors in these four sine waves, these four sine waves are then input to a second passive polyphase filter 140, which corrects the orthogonality errors and any amplitude mismatches. The second passive polyphase filter 140 also receives the selection code R, which is the same code as the selection code R input to the first passive polyphase filter 120. The second passive polyphase filter 140 corrects the amplitude and phase separation so that the four sine waves are output as clean signals that are exactly 90 degrees apart from each other. These clean signals are input to a third passive polyphase filter 150, which also receives the same selection code R input to the first passive polyphase filter 120 and the second passive polyphase filter 140. The third passive polyphase filter 150 generates another four signals, which are also orthogonal to each other (i.e., 90 degrees) and have intermediate phases with respect to the four input signals, so that the third passive polyphase filter 150 outputs four signals with phases of 90, 180, 270, and 360 respectively.

[0039] In addition to being input to the third passive polyphase filter 150, four sine waves with respective phases of 45, 135, 225, and 315 are also directly input to a plurality of adjacent phase mixers 160. There is an inherent delay between these four signals and the other four signals with phases of 90, 180, 270, and 360 generated by the third passive polyphase filter 150. To correct these skews, each of the plurality of adjacent phase mixers 160 generates an average clock at the output, and then these eight signals are transmitted to a plurality of AC coupled DC restoration buffers, which are respectively rail-to-rail converters to set a DC point.

[0040] The operation of the present invention in each stage will be described below. FIGS. 2A, 2B, and 2C respectively illustrate the phases of the signals output and generated from the second passive polyphase filter 140, the third passive polyphase filter 150, and the adjacent phase mixer 160. As shown in FIG. 2A, the four signals with phases of 45, 135, 225, and 315 are exactly 90 degrees apart from each other. In FIG. 2B, there is a skew between these four original signals and the other four signals with phases of 90, 180, 270, and 360. In FIG. 2C, all the signals have been offset from the original point. Thus, for example, the clock phase CK45 is not 45 degrees relative to the origin of the graph, but all the signals are 45 degrees apart from each other.

[0041] Referring to FIG. 3, it illustrates the clock signals and internal components generated by the first passive polyphase filter 120 and the plurality of AC coupled DC restoration buffers 130. Differential sine wave signals at the same DC point are input to the first passive polyphase filter 120. The first passive polyphase filter 120 includes a high-pass filter and a low-pass filter, where the high-pass filter does not allow the original DC point to pass through, and the low-pass filter allows the original DC point to pass through. Thus, as shown in the waveform diagram, there is an offset between the clock output from the high-pass filter and the clock output from the low-pass filter.

[0042] As described above, the plurality of AC coupled DC setting buffers 130 eliminate the incoming DC point of all signals by setting their own DC points for all signals. As shown in the waveform diagram, there is less offset between the clocks, but due to inherent irregularities, amplitude errors may still exist.

[0043] FIG. 4 shows the internal components of the second passive polyphase filter 140, the third passive polyphase filter 150, the adjacent phase mixer 160, and the plurality of AC-coupled DC restoration buffers 170. The second passive polyphase filter 140 is used to correct the irregularities and amplitude errors introduced by the clock signal output from the AC-coupled DC setting buffer 130. This correction is achieved by internally generating a second clock for each signal of a specific phase (i.e., 45_i, 135_i, 225_i, and 315_i) having a respective different amplitude from the original clock signal of the same phase, and then superposing the clock signal pairs of the same phase difference to offset the differences, thereby generating average output signals that are exactly 90 degrees apart from each other, as shown in FIG. 2A.

[0044] The third passive polyphase filter 150 includes the same internal components as the second passive polyphase filter 140 and is used to generate another four output clocks. As shown in FIG. 2B, the original clocks are exactly 90 degrees apart from each other, and the newly generated clocks are exactly 90 degrees apart from each other. However, the inherent delay required to generate the other four clocks results in a slight skew between the four signals of these two groups. Therefore, these eight clocks are regarded as intermediate clock signals.

[0045] The eight intermediate clock signals are input to the adjacent phase mixer 160, as shown in FIG. 4. The adjacent phase mixer 160 includes a plurality of buffer pairs. Each buffer pair receives two signals that are 45 degrees apart from each other and generates an average output signal. As shown in FIG. 4, the first buffer pair receives signals 45 and 90 and generates signal 67.5, the second buffer pair receives signals 90 and 135 and generates signal 112.5, the third buffer pair receives signals 135 and 180 and generates signal 157.5, the fourth buffer pair receives signals 180 and 225 and generates signal 202.5, the fifth buffer pair receives signals 225 and 270 and generates signal 247.5, the sixth buffer pair receives signals 270 and 315 and generates signal 292.5, the seventh buffer pair receives signals 315 and 360 and generates signal 337.5, and the eighth buffer pair receives signals 360 and 45 and generates signal 22.5. The eight resulting signals are exactly 45 degrees apart from each other. Signal 67.5 is input to a DC restoration buffer as the new clock signal 45. It should be noted that this is only for illustrative purposes, and signal 67.5 can also be used as the new clock signal 0. It should be noted that there is exactly a 45-degree phase difference between each consecutive clock signal pair, and the eight clock signals generated by the adjacent phase mixer 160 and input to the plurality of AC-coupled DC restoration buffers 170 are pure sine waves. Since the duty cycle distortion of a pure sine wave is less than that of a square wave, a pure sine wave is a better choice.

[0046] FIG. 5 shows the internal components of the differential circuit 110 including the single-ended to differential circuit 105 and the square wave to sine wave circuit 107. The single-ended to differential circuit 105 is formed by a complementary metal oxide semiconductor (CMOS) buffer and an inverter coupled to a cross-coupled inverter. The cross-coupled inverter serves as a latch to restore the duty cycle of the input clock. The square wave to sine wave circuit 107 is a second-order passive resistor-capacitor filter and generates a differential sine wave. After the sine wave circuit 107 are coupled a DC setting buffer 109 and a differential stage 111. The differential sine wave passes through a plurality of AC-coupled DC setting buffers 113, which generate a DC voltage that matches the DC voltage of the differential sine wave, and the plurality of passive polyphase filters require this DC voltage.

[0047] FIG. 6A, FIG. 6B, and FIG. 6C respectively show the internal components and clock phases of the first passive polyphase filter 120, the second passive polyphase filter 140, and the third passive polyphase filter 150. For the sake of brevity, the generation of the clock signals has been described in detail above and will not be repeated here.

[0048] FIG. 7 is a schematic diagram of a plurality of resistor banks in a passive polyphase filter according to an embodiment of the present invention. As shown in FIG. 7, the passive polyphase filter includes a first resistor bank and a second resistor bank. In each resistor bank, the resistors are in parallel, and resistor adjustment is performed by turning on one resistor from each resistor bank to form a parallel combination. Resistor selection is performed in a 1-Hot fashion, thus allowing a total of 8x4 resistor combinations. It should be noted that the present invention utilizes the generation of eight clock signals as a preferred embodiment, but the method of the present invention can also be applied to generate sixteen clock signals, etc. In this modified embodiment, each resistor bank will be modified to increase the number of resistors.

[0049] The method and circuit of the present invention can generate eight clock signals that are exactly 45 degrees apart from each other and have no skew or amplitude variation. By using passive circuits such as passive polyphase filters and passive resistor-capacitor filters, no closed-loop circuit is required and thus no signal fine-tuning is needed. Since no bias setting or startup circuit is required, the absence of the closed-loop circuit also makes the entire circuit more stable. In addition, the passive circuit operates at a very low power.

[0050] The above are only the preferred embodiments of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

Claims

1. A clock generation circuit for generating a plurality of output clocks for a serializer / deserializer circuit, the plurality of output clocks having different phase angles respectively, the clock generation circuit comprising: A differential circuit for receiving a single input clock signal and outputting two differential clock signals that are 180 degrees out of phase with each other and a DC signal representing a DC point of the two differential clock signals; A first polyphase filter for receiving the two differential output signals and the DC signal and generating four clock signals that are orthogonal to each other; A plurality of setting buffers for receiving the four clock signals, setting a same DC point for the four clock signals, and generating four resultant clock signals; A plurality of coupled polyphase filters for receiving the four resultant clock signals, generating another four clock signals that are orthogonal to each other and have a micro skew θ with respect to the four resultant clock signals, and outputting eight resultant clock signals; A phase mixer for receiving the eight resultant clock signals, mixing every two adjacent phase signals, and generating an intermediate output signal to generate eight output clocks that are 45 degrees out of phase with each other; And A plurality of recovery buffers for receiving the eight clock signals from the phase mixer and setting a DC point for each of the eight clock signals, and generating eight output clocks that are exactly 45 degrees out of phase with each other and all at a same DC point.

2. The clock generation circuit according to claim 1, wherein the single input clock signal is a square wave, and the differential circuit comprises: A single-ended to differential circuit for receiving the single input clock signal and generating two differential square waves; and A square wave to sine wave circuit for receiving the two differential square waves and converting the two differential square waves into two differential sine waves, wherein the two differential sine waves are output as the two differential clock signals that are 180 degrees out of phase with each other.

3. The clock generation circuit according to claim 1, wherein the plurality of coupled polyphase filters comprises: A second polyphase filter is configured to receive the four resultant clock signals and perform internal superposition of multiple clock signals with the same phase difference to generate four clock signals with corrected amplitudes; And A third polyphase filter for receiving the four clock signals with corrected amplitudes and generating the other four clock signals that are orthogonal to each other; Wherein the other four clock signals and the four clock signals with corrected amplitudes are output to the phase mixer as the eight resultant clock signals.

4. The clock generation circuit according to claim 3, wherein the first polyphase filter, the second polyphase filter, and the third polyphase filter receive a plurality of selection codes to adjust a plurality of internal circuits according to a plurality of frequencies of a plurality of input clock signals, wherein the first polyphase filter, the second polyphase filter, and the third polyphase filter receive the same plurality of selection codes.

5. The clock generation circuit according to claim 4, wherein each polyphase filter comprises a first resistor bank and a second resistor bank, and the plurality of selection codes select a first plurality of resistors from the first resistor bank and a second plurality of resistors from the second resistor bank to adjust the plurality of polyphase filters.

6. The clock generation circuit according to claim 1, wherein the first polyphase filter includes a plurality of low-pass filters, and the plurality of low-pass filters allow the DC point from the differential circuit to pass through, so that the four generated clock signals are all located at the DC point.

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