A level conversion circuit for resisting power supply and threshold perturbations

Abstract

The present invention discloses a level conversion circuit for resisting power supply and threshold perturbations, including an anti-interference circuit composed of MOS transistors Mn8 and Mn13, which plays a role in resisting interference from power supply ground signal fluctuations to the input and is realized by the method of commonly grounding the gate-source stage; MOS transistors Mn14 and Mp8 form an inverter used as a buffer output. MOS transistors Mp6 and Mp7 form a cross-coupled latch structure based on positive feedback. MOS transistors Mn9 and Mn12 are used as low-threshold input pair transistors. MOS transistors Mn10, Mn11 and a DAC jointly form a clamping circuit, which plays a role in clamping and protecting the drain voltages of the two input pair transistors. The present invention not only realizes the level conversion function of the traditional level conversion circuit from a digital voltage of 1.2V to an analog voltage of 3.3V, but also provides an effective solution for power supply perturbations and threshold changes of input pair transistors in a harsh environment.

Description

Technical Field

[0001] The present invention relates to the technical field of analog - to - digital conversion, and particularly to a level - conversion circuit for resisting power - supply and threshold perturbations. Background Art

[0002] In the use of mixed - signal circuits, it is often necessary to convert digital - level signals into analog - level signals. As shown in the traditional level - conversion circuit Figure 2 shown below, Figure 2 the MOS transistors are all high - threshold analog transistors with a maximum withstand voltage of 3.3V. MOS transistors Mn3 and Mn6 play a role in resisting the interference of power - supply ground - wire signal fluctuations on the input, and the method of commonly grounding the gate - source stage is adopted to achieve this. VDD2 is 3.3V, and VIN + and VIN - are the high - level and low - level signals of 1.2V and 0V generated by the circuit shown in Figure 1 shown below. When VIN + inputs a high level and VIN - inputs a low level, MOS transistor Mn5 conducts, and MOS transistor Mn4 turns off, causing node 1 to be pulled to a low level, that is, the gate voltage of MOS transistor Mp3 is low, which leads to the conduction of MOS transistor Mp3. The voltage of node 2 is gradually pulled up, reducing the conduction degree of MOS transistor Mp4, and thus pulling the level of node 1 even lower, realizing a positive - feedback adjustment mechanism. The above - described is the working mechanism of the cross - coupled latch structure based on positive feedback. Finally, the output Vout1 is a high level of 3.3V, achieving the level conversion from the digital voltage of 1.2V to the analog voltage of 3.3V.

[0003] Although the existing level - conversion circuit can achieve the function of converting the digital voltage of 1.2V to the analog voltage of 3.3V, if its external environment is relatively harsh, situations such as "power - supply perturbations and threshold changes of input pair transistors" will occur in the harsh environment, resulting in functional failure. Therefore, in a relatively harsh working environment, the traditional level - conversion circuit can no longer achieve its normal function.

[0004] The reasons for the functional failure of the traditional level - conversion circuit as shown in Figure 2 are analyzed as follows. In Figure 2 , since MOS transistors Mn4 and Mn5 are high - threshold analog transistors with a maximum withstand voltage of 3.3V, under PVT function verification, when they are in a relatively harsh environment, Figure 2 the threshold voltages of the input pair transistors MOS transistors Mn4 and Mn5 in Figure 1The VDD1 in it is 1.2V. There may also be a certain voltage fluctuation in VDD1. If the voltage of VDD1 fluctuates downward from 1.2V, when generating VIN+ finally, it will be lower than the theoretical value of the actual 1.2V. Thus, when the fluctuating high-level VIN+ is lower than the fluctuation threshold voltage of the Mn5 transistor, the MOS transistor Mn5 cannot be turned on at this time, resulting in the failure of the actual level conversion function. Summary of the Invention

[0005] In view of the above-mentioned traditional level conversion circuit, due to the influence of the harsh environment, there are situations of "power supply disturbance and input pair transistor threshold change", which further causes the problem of the failure of the actual level conversion function. The present invention proposes a level conversion circuit for resisting power supply and threshold disturbances to solve the problem of function failure caused by the influence of the external harsh environment.

[0006] The present invention is realized through the following technical solutions:

[0007] A level conversion circuit for resisting power supply and threshold disturbances includes a MOS transistor Mn9, a MOS transistor Mn12, an inverter, a cross-coupled latch circuit, and a clamping circuit. The clamping circuit is used for clamping protection of the drain voltages of the MOS transistor Mn9 and the MOS transistor Mn12, and includes a MOS transistor Mn10, a MOS transistor Mn11, and a DAC conversion module. The maximum withstand voltages of the MOS transistor Mn10 and the MOS transistor Mn11 are greater than the maximum withstand voltages of the MOS transistor Mn9 and the MOS transistor Mn12;

[0008] The gate of the MOS transistor Mn9 is used as the power supply VIN- input terminal, the gate of the MOS transistor Mn12 is used as the power supply VIN+ input terminal. The source electrodes of the MOS transistor Mn9 and the MOS transistor Mn12 are connected to GND. The drain of the MOS transistor Mn9 is connected to the source of the MOS transistor Mn10. The drain of the MOS transistor Mn12 is connected to the source of the MOS transistor Mn11. The gates of the MOS transistor Mn10 and the MOS transistor Mn11 are connected to the output signal of the DAC conversion module. The drain of the MOS transistor Mn10 is connected to the cross-coupled latch circuit. The drain of the MOS transistor Mn11 is connected to the cross-coupled latch circuit and the inverter.

[0009] Preferably, the gates of the MOS transistor Mn9 and the MOS transistor Mn12 are connected to an anti-interference circuit, and the anti-interference circuit is used to resist the interference of the power supply ground signal fluctuation to the input.

[0010] Preferably, the anti-interference circuit includes a MOS transistor Mn8 and a MOS transistor Mn13. The drains of the MOS transistor Mn8 and the MOS transistor Mn13 are respectively connected to the gates of the MOS transistor Mn9 and the MOS transistor Mn12. The source and gate of the MOS transistor Mn8 and the MOS transistor Mn13 are respectively grounded.

[0011] Preferably, the cross-coupled latch circuit includes MOS transistor Mp6 and MOS transistor Mp7;

[0012] The drains of MOS transistor Mp7 and MOS transistor Mn11 are connected to the gate of MOS transistor Mp6, the drains of MOS transistor Mp6 and MOS transistor Mn10 are connected to the gate of Mp7, and the sources of MOS transistor Mp6 and MOS transistor Mp7 are connected to VDD3.

[0013] Preferably, the inverter is used for buffer output, and the inverter includes MOS transistor Mp8 and MOS transistor Mn14;

[0014] The source of MOS transistor Mp8 is connected to VDD3, the source of MOS transistor Mn14 is connected to GND, the gates of MOS transistor Mp8 and MOS transistor Mn14 are connected to form the input end of the inverter and are connected to the connection point between the drain of MOS transistor Mn11 and the gate of MOS transistor Mp6, and the drains of MOS transistor Mp8 and MOS transistor Mn14 are connected to form the output signal.

[0015] Preferably, the maximum withstand voltage of MOS transistor Mn9 and MOS transistor Mn12 is 1.2V.

[0016] Preferably, the maximum withstand voltage of MOS transistor Mn10 and MOS transistor Mn11 is 3.3V.

[0017] Preferably, the output voltage of the DAC conversion module is less than the sum of the voltage VGS10 of MOS transistor Mn10, the voltage VGS11 of MOS transistor Mn11 and the 1.2V voltage, and at the same time greater than the threshold voltage of MOS transistor Mn10 and the threshold voltage of MOS transistor Mn11.

[0018] Compared with the prior art, the present invention has the following beneficial technical effects:

[0019] A level conversion circuit for resisting power supply and threshold disturbances provided by the present invention introduces a clamping circuit composed of MOS transistor Mn10, MOS transistor Mn11 and DAC. Since the gate voltages of MOS transistor Mn10 and MOS transistor Mn11 are controlled by the output voltage of an externally applied DAC, it has a clamping protection effect on MOS transistor Mn9 and MOS transistor Mn12, thereby preventing Mn9 and Mn12 from being damaged due to the drain voltage being higher than 1.2V; the gate voltages of MOS transistor Mn10 and MOS transistor Mn11 are both controlled by the output high level of the same externally applied DAC, and MOS transistor Mn10 and MOS transistor Mn11 are both in the conducting state. When the VIN+ input is high level and the VIN- input is low level, MOS transistor Mn12 conducts, and MOS transistor Mn9 turns off, causing node 3 to be pulled to low level, that is, the gate voltage of MOS transistor Mp6 is low, which causes MOS transistor Mp6 to conduct, and the voltage of node 4 is gradually pulled up, causing the conduction degree of MOS transistor Mp7 to decrease, so that the level of node 3 is pulled lower, realizing the working mechanism of the cross-coupled latch structure based on positive feedback. Finally, the output Vout2 is a high level of 3.3V, realizing the level conversion from the digital voltage of 1.2V to the analog voltage of 3.3V. It not only realizes the level conversion function of the level conversion circuit from the digital voltage of 1.2V to the analog voltage of 3.3V, but also provides an effective solution for realizing the level conversion under power supply disturbances and input pair transistor threshold changes in a harsh environment.

[0020] Furthermore, the gate voltages of MOS transistor Mn10 and MOS transistor Mn11 are adjustable. When the circuit does not need to work, the DAC outputs a low level to turn off MOS transistor Mn10 and MOS transistor Mn11, and the circuit is in a disconnected state. Therefore, the circuit also realizes low power consumption.

[0021] Furthermore, MOS transistors Mn9 and Mn12 are low-threshold digital transistors with a maximum withstand voltage of 1.2V. Therefore, compared with high-threshold analog transistors with a maximum withstand voltage of 3.3V, they have a lower threshold voltage. Compared with the high-threshold input pair transistors of traditional level conversion circuits, the improved structure greatly improves the tolerance to external harsh environment changes and disturbances. In the working state, the output voltage of the DAC needs to meet the conditions of being less than VGS10,11 + 1.2V and greater than VTH10,11, which can prevent MOS transistors Mn9 and Mn12 from being damaged due to the drain voltage being higher than 1.2V, achieving the purpose of resisting power supply and threshold disturbances during the actual level conversion process. Description of the Drawings

[0022] Figure 1 is the VIN+ and VIN- signal generation circuit;

[0023] Figure 2is a traditional level conversion circuit;

[0024] Figure 3 is the improved level conversion circuit of the present invention;

[0025] Figure 4 is the level conversion timing diagram of the invention. Detailed implementation manners

[0026] The present invention will be further described in detail below with reference to the accompanying drawings. The following is an explanation of the present invention rather than a limitation.

[0027] Refer to Figure 3 , a level conversion circuit for resisting power supply and threshold perturbations, comprising two input pair transistors, a clamping circuit, an inverter, a cross-coupled latch circuit, and an anti-interference circuit; the two input pair transistors are respectively MOS transistor Mn9 and MOS transistor Mn12, and the clamping circuit includes MOS transistor Mn10, MOS transistor Mn11, and a DAC conversion module. The clamping circuit is used for clamping and protecting the drain voltages of the two input pair transistors.

[0028] The gates of MOS transistor Mn9 and MOS transistor Mn12 are connected to the anti-interference circuit. The gate of MOS transistor Mn9 is used as the power supply VIN- input terminal, and the gate of MOS transistor Mn12 is used as the power supply VIN+ input terminal. The sources of MOS transistor Mn9 and MOS transistor Mn12 are connected to GND. The drain of MOS transistor Mn9 is connected to the source of MOS transistor Mn10, and the drain of MOS transistor Mn12 is connected to the source of MOS transistor Mn11. The gates of MOS transistor Mn10 and MOS transistor Mn11 are connected to the output signal of the DAC conversion module. The drain of MOS transistor Mn10 is connected to the cross-coupled latch circuit, and the drain of MOS transistor Mn11 is connected to the cross-coupled latch circuit and the inverter.

[0029] The anti-interference circuit includes MOS transistor Mn8 and MOS transistor Mn13. MOS transistor Mn8 and MOS transistor Mn13 are used to resist the interference of power supply ground signal fluctuations on the input. It is realized by the method of connecting the gate-source to the ground wire together. Specifically as follows:

[0030] The drains of MOS transistor Mn8 and MOS transistor Mn13 are respectively connected to the gates of MOS transistor Mn9 and MOS transistor Mn12, and the sources and gates of MOS transistor Mn8 and MOS transistor Mn13 are respectively grounded.

[0031] The cross-coupled latch circuit includes MOS transistor Mp6 and MOS transistor Mp7, and the inverter includes MOS transistor Mp8 and MOS transistor Mn14. Mp8 and Mn14 form an inverter and are used as a buffer output.

[0032] The drains of MOS transistor Mp7 and MOS transistor Mn11 are connected to the gate of MOS transistor Mp6 (node 3), and the drains of MOS transistor Mp6 and MOS transistor Mn10 are connected to the gate of Mp7 (node 4), forming a cross-coupled latch structure based on positive feedback. The sources of MOS transistor Mp6 and MOS transistor Mp7 are connected to VDD3;

[0033] The source of MOS transistor Mp8 is connected to VDD3, and the source of MOS transistor Mn14 is connected to GND. The gates of Mp8 and Mn14 are connected to form the input of an inverter and are connected to the connection point between the drain of MOS transistor Mn11 and the gate of MOS transistor Mp6 (node 3). The drains of Mp8 and Mn14 are connected to form the output of this level conversion circuit, and the output signal is Vout2.

[0034] As Figure 3 shown, the present invention proposes a level conversion circuit for resisting power supply and threshold perturbations. VDD3 is 3.3V. MOS transistors Mn8, Mn10, Mn11, Mn13, Mn14, Mp6, Mp7, and Mp8 are all high-threshold analog transistors with a maximum withstand voltage of 3.3V. MOS transistors Mn9 and Mn12 are low-threshold digital transistors with a maximum withstand voltage of 1.2V. VIN+ and VIN- are the same as Figure 2 in and are also the high and low level signals of 1.2V and 0V generated by the circuit shown in Figure 1 This level conversion circuit for resisting power supply and threshold perturbations not only realizes the level conversion function of the traditional level conversion circuit from the digital voltage of 1.2V to the analog voltage of 3.3V, but also provides an effective solution for power supply perturbations and input pair transistor threshold changes in a harsh environment.

[0035] As Figure 1The VIN- and VIN+, the MOS transistor Mp1 and the MOS transistor Mn1 form the first-stage inverter. The source of the MOS transistor Mp1 is connected to VDD1, the source of the MOS transistor Mn1 is connected to GND, the gates of the MOS transistor Mp1 and the MOS transistor Mn1 are connected to form the input terminal of the first-stage inverter. The input signal A is a digital signal of 1.2V to be converted. The drains of the MOS transistor Mp1 and the MOS transistor Mn1 are connected to form the output terminal of the first-stage inverter. The output of the first-stage inverter is a low-level signal VIN-. The MOS transistor Mp2 and the MOS transistor Mn2 form the second-stage inverter. The source of the MOS transistor Mp2 is connected to VDD1, the source of the MOS transistor Mn2 is connected to GND, the gates of the MOS transistor Mp2 and the MOS transistor Mn2 are connected to form the input terminal of the second-stage inverter. The input signal of the second-stage inverter is the output signal VIN- of the first-stage inverter. The drains of the MOS transistor Mp2 and the MOS transistor Mn2 are connected to form the output terminal of the second-stage inverter. The output of the second-stage inverter is a high-level signal VIN+. VIN- and VIN+ form the input of the level conversion circuit.

[0036] As Figure 2 shown, a traditional level conversion circuit; the drain of the MOS transistor Mn3 is connected to the gate of the MOS transistor Mn4 as the VIN- input terminal, the drain of the MOS transistor Mn6 is connected to the gate of the MOS transistor Mn5 as the VIN+ input terminal. The gates and sources of the MOS transistors Mn3 and Mn6 are connected to GND, the sources of the MOS transistors Mn4 and Mn5 are connected to GND, and the sources of the MOS transistors Mp3 and Mp4 are connected to VDD2. The drains of the MOS transistors Mp4 and Mn5 are connected to the gate of the MOS transistor Mp3 (node 1), and the drains of the MOS transistors Mp3 and Mn4 are connected to the gate of the MOS transistor Mp4 (node 2) to form a cross-coupled latch structure based on positive feedback. The MOS transistor Mp5 and the MOS transistor Mn7 form an inverter as a buffer output. The source of the MOS transistor Mp5 is connected to VDD2, the source of the MOS transistor Mn7 is connected to GND, the gates of the MOS transistor Mp5 and the MOS transistor Mn7 are connected to form the input terminal of the inverter, and the drains of the MOS transistor Mp5 and the MOS transistor Mn7 are connected to form the output terminal of the level conversion circuit. The output signal is Vout1.

[0037] As Figure 3 shown is the level conversion circuit proposed by the present invention for resisting power supply and threshold perturbations. The inverter and the cross-coupled latch structure based on positive feedback are the same as those in the traditional level conversion circuit. The difference is that, on the one hand, the two input pair transistors are replaced by low-threshold digital transistors from high-threshold analog transistors; on the other hand, a clamping circuit is introduced at the drain ends of the input pair transistors; on the third hand, the gates of the two clamping transistors are controlled by the DAC output level, so the gate voltage of the clamping transistors has adjustable properties.

[0038] In the first aspect, the input transistors of the power input signals VIN+ and VIN- are replaced from high-threshold analog transistors with a maximum withstand voltage of 3.3V to low-threshold digital transistors with a maximum withstand voltage of 1.2V. Since MOS transistors Mn9 and Mn12 have a maximum withstand voltage of 1.2V, compared with MOS transistors with a maximum withstand voltage of 3.3V, they have a lower threshold voltage. The tolerance of MOS transistor Mn12 to the disturbance of VIN+ caused by the external harsh environment can be greatly improved compared with MOS transistor Mn5.

[0039] In the second aspect, two MOS transistors Mn10 and Mn11 with a maximum withstand voltage of 3.3V are added above the MOS transistors Mn9 and Mn12 with a maximum withstand voltage of 1.2V respectively. MOS transistors Mn10, Mn11 and the DAC conversion module together form a clamping circuit. The gate voltages of MOS transistors Mn10 and Mn11 are both regulated and controlled by the same externally applied DAC. At the same time, the introduction of the clamping circuit is precisely to clamp and protect MOS transistors Mn9 and Mn12 to prevent MOS transistors Mn9 and Mn12 from being damaged due to the drain voltage being higher than 1.2V.

[0040] It should be noted that in the working state, the output voltage of the DAC conversion module needs to meet the conditions of being less than the sum of the voltage VGS10 of MOS transistor Mn10, the voltage VGS11 of MOS transistor Mn11 and the 1.2V voltage, and at the same time being greater than the threshold voltages of MOS transistor Mn10 and MOS transistor Mn11, so as to prevent MOS transistors Mn9 and Mn12 from being damaged due to the drain voltage being higher than 1.2V, achieving the purpose of resisting power supply disturbance in the actual level conversion process. Being greater than VTH10, 11 is to keep MOS transistors Mn10 and Mn11 in the conducting state, and being less than the sum of the voltage VGS10 of MOS transistor Mn10, the voltage VGS11 of MOS transistor Mn11 and the 1.2V voltage is to make the drain voltages of MOS transistors Mn9 and Mn12 lower than 1.2V.

[0041] In the third aspect, since the gate voltages of MOS transistors Mn10 and Mn11 are controlled by the output voltage of the externally applied DAC conversion module, the gate voltages of MOS transistors Mn10 and Mn11 are adjustable. When the circuit does not need to work, the DAC conversion module is made to output a low level to turn off the high-threshold analog transistors Mn10 and Mn11, and the circuit is in an off state. Therefore, the circuit also achieves low power consumption.

[0042] The technology for resisting power supply and threshold perturbations in the present invention is as follows: replace the two input pair transistors with low-threshold digital transistors from high-threshold analog transistors, so that the input pair transistors have a lower threshold voltage. The tolerance of MOS transistor Mn12 to perturbations of VIN+ caused by the external harsh environment can be greatly improved compared to MOS transistor Mn5, and the resistance to power supply and threshold perturbations can be achieved. The existence of the clamping circuit introduces a clamping circuit at the drain terminal of the input pair transistors. The main purpose is to protect the replaced low-threshold digital transistors from being damaged due to their drain voltage being higher than their maximum tolerance voltage. The gates of the two clamping transistors are controlled by the output level of the DAC. The gate voltage of the clamping transistors has the property of being adjustable. By using this DAC, MOS transistors Mn10 and Mn11 can be controlled to be in the conducting state during the working state and the circuit can be in the disconnected state during the non-working state, reducing the static power consumption as a whole. At this time, the output terminal of the DAC is equivalent to the enable terminal of the entire circuit.

[0043] The working process of the level conversion implemented by the present invention is as follows. Since the gate voltages of MOS transistors Mn10 and Mn11 are both controlled by the output high level of the same externally applied DAC, MOS transistors Mn10 and Mn11 are both in the conducting state. When VIN+ input is high level and VIN- input is low level, MOS transistor Mn12 conducts and MOS transistor Mn9 turns off, causing node 3 to be pulled to low level, that is, the gate voltage of MOS transistor Mp6 is low, which leads to the conduction of MOS transistor Mp6, and the voltage of node 4 is gradually pulled up, reducing the conduction degree of MOS transistor Mp7, and thus pulling the level of node 3 lower, realizing the working mechanism of the cross-coupled latch structure based on positive feedback.

[0044] Figure 4 It is the timing diagram of the improved level conversion. As can be seen from the figure, the output Vout2 is a high level of 3.3V, realizing the level conversion from the digital voltage of 1.2V to the analog voltage of 3.3V.

[0045] The level conversion circuit for resisting power supply and threshold perturbations of the present invention is improved on the basis of the traditional level conversion circuit and can be extended to all level conversion circuits. The method proposed in this article has the following advantages: ① Replace the two input pair transistors with low-threshold digital transistors from high-threshold analog transistors, and the input pair transistors will have a lower threshold voltage. Under the external harsh environment, the tolerance of the input pair transistors to power supply and threshold perturbations can be greatly improved, realizing the function of normal level conversion under harsh environments; ② The gates of the two clamping transistors are controlled by the output level of the DAC, so the gate voltage of the clamping transistors has the property of being adjustable. By using this DAC, MOS transistors Mn10 and Mn11 can be controlled to be in the conducting state during the working state and the circuit can be in the disconnected state during the non-working state, reducing the static power consumption as a whole.

[0046] The above content is only to illustrate the technical idea of the present invention, and the protection scope of the present invention cannot be limited thereby. Any modification made on the basis of the technical solution according to the technical idea proposed by the present invention falls within the protection scope of the claims of the present invention.

Claims

1. A level conversion circuit for resisting power supply and threshold perturbations, characterized in that, It includes MOS transistor Mn9, MOS transistor Mn12, an inverter, a cross-coupled latch circuit, and a clamping circuit. The clamping circuit is used for clamping protection of the drain voltages of MOS transistor Mn9 and MOS transistor Mn12, and includes MOS transistor Mn10, MOS transistor Mn11, and a DAC conversion module. The maximum withstand voltages of MOS transistor Mn10 and MOS transistor Mn11 are greater than those of MOS transistor Mn9 and MOS transistor Mn12. The gate of MOS transistor Mn9 serves as the input terminal of power supply VIN-, the gate of MOS transistor Mn12 serves as the input terminal of power supply VIN+, the sources of MOS transistor Mn9 and MOS transistor Mn12 are connected to GND, the drain of MOS transistor Mn9 is connected to the source of MOS transistor Mn10, the drain of MOS transistor Mn12 is connected to the source of MOS transistor Mn11, the gates of MOS transistor Mn10 and MOS transistor Mn11 are connected to the output signal of the DAC conversion module, the drain of MOS transistor Mn10 is connected to the cross-coupled latch circuit, and the drain of MOS transistor Mn11 is connected to the cross-coupled latch circuit and the inverter.

2. The level conversion circuit for resisting power supply and threshold perturbations according to claim 1, wherein The gates of MOS transistor Mn9 and MOS transistor Mn12 are connected to an anti-interference circuit, which is used to resist the interference of power supply and ground signal fluctuations on the input.

3. A level conversion circuit for resisting power supply and threshold perturbations according to claim 2, characterized in that, The anti-interference circuit includes MOS transistor Mn8 and MOS transistor Mn13. The drains of MOS transistor Mn8 and MOS transistor Mn13 are respectively connected to the gates of MOS transistor Mn9 and MOS transistor Mn12, and the sources and gates of MOS transistor Mn8 and MOS transistor Mn13 are respectively grounded.

4. A level conversion circuit for resisting power supply and threshold perturbations according to claim 1, wherein The cross-coupled latch circuit includes MOS transistor Mp6 and MOS transistor Mp7. The drains of MOS transistor Mp7 and MOS transistor Mn11 are connected to the gate of MOS transistor Mp6, the drains of MOS transistor Mp6 and MOS transistor Mn10 are connected to the gate of Mp7, and the sources of MOS transistor Mp6 and MOS transistor Mp7 are connected to VDD3.

5. A level conversion circuit for resisting power supply and threshold perturbations according to claim 4, wherein, The inverter is used for buffer output and includes MOS transistor Mp8 and MOS transistor Mn14. The source of MOS transistor Mp8 is connected to VDD3, the source of MOS transistor Mn14 is connected to GND, the gates of MOS transistor Mp8 and MOS transistor Mn14 are connected to form the input terminal of the inverter and are connected to the connection point between the drain of MOS transistor Mn11 and the gate of MOS transistor Mp6, and the drains of MOS transistor Mp8 and MOS transistor Mn14 are connected to form the output signal.

6. A level conversion circuit for resisting power supply and threshold perturbations according to claim 1, characterized in that, The maximum withstand voltages of MOS transistor Mn9 and MOS transistor Mn12 are 1.2V.

7. The level conversion circuit for resisting power supply and threshold perturbations according to claim 6, wherein The maximum withstand voltages of MOS transistor Mn10 and MOS transistor Mn11 are 3.3V.

8. A level conversion circuit for resisting power supply and threshold perturbations according to claim 7, wherein The output voltage of the DAC conversion module is less than the sum of the voltage VGS10 of MOS transistor Mn10, the voltage VGS11 of MOS transistor Mn11, and 1.2V, and at the same time is greater than the threshold voltages of MOS transistor Mn10 and MOS transistor Mn11.

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