Layout Graphics Optimization Method

Abstract

The present application relates to the field of semiconductor integrated circuit technology, and specifically to a layout graphics optimization method. The method comprises: gridding an initial layout graphic, an actual lithography graphic, and an ideal lithography graphic based on the same grid; determining a difference region between the actual lithography graphic and the ideal lithography graphic; determining in the difference region all cells through which the edge of the actual lithography graphic passes as actual edge cells; setting an optimization weight level corresponding to each actual edge cell based on the size of the gap between each actual edge cell and the edge of the ideal lithography graphic; and optimizing, outside the layout graphic, layout edge cells corresponding to actual edge cells of each optimization weight level in descending order of the optimization weight levels until all layout edge cells corresponding to actual edge cells of all optimization weight levels are optimized, thereby obtaining a final optimized layout graphic.

Description

Technical Field

[0001] The present application relates to the field of semiconductor integrated circuit technology, and in particular to a layout graphics optimization method. Background Art

[0002] In advanced technology nodes, the optical proximity correction (OPC) technology with resolution enhancement characteristics is used to optimize the layout based on optical diffraction theory to reduce image distortion and improve process stability.

[0003] Generally, the platform's OPC solution can meet most of the layout's structural requirements. For example, in some corner structures, compensation is generally achieved by adding a "hat" at the corner.

[0004] However, image sensor chips have more stringent requirements for the layout graphic structure. The solution of fine-tuning the layout through photoelectric characteristics in related technologies requires the use of more complex, special and dedicated OPC technology. If each special graphic structure is optimized one by one, repeated communication is required, which consumes a lot of manpower and time costs and is inefficient. Summary of the Invention

[0005] The present application provides a layout graphics optimization method that can solve the problem of low efficiency caused by optimizing each special graphic structure one by one in related technologies.

[0006] In order to solve the technical problems described in the background technology, the present application provides a layout graphic optimization method, which includes:

[0007] S1: Based on the same grid, the initial layout pattern, actual lithography pattern and ideal lithography pattern are meshed;

[0008] S2: determining a difference area between the actual lithography pattern and the ideal lithography pattern;

[0009] S3: in the difference area, determining all cells through which the edge of the actual lithography pattern passes as actual edge cells;

[0010] S4: setting an optimization weight level corresponding to each of the actual edge cells based on the size of the gap between the edge of each of the actual edge cells and the edge of the ideal lithography pattern;

[0011] S5: Outside the layout graph, optimizing the layout edge cells corresponding to the actual edge cells of each optimization weight level in descending order of the optimization weight levels, until all the layout edge cells corresponding to the actual edge cells of all optimization weight levels are optimized, thereby obtaining a final optimized layout graph;

[0012] The final lithography pattern obtained by the final optimized layout pattern satisfies: , wherein S2 is the area of ​​the ideal lithography pattern in the difference region, S1 is the area of ​​the final lithography pattern in the difference region, and S0 is the area of ​​the difference region.

[0013] Optionally, the step of setting the optimization weight of each actual edge cell based on the size of the gap between each actual edge cell and the edge of the ideal lithography pattern comprises:

[0014] S41: Calculating the Euclidean distance between the center point of each actual edge cell and the edge of the ideal lithography pattern respectively;

[0015] S42: Determine the size of the gap between each of the actual edge cells and the edge of the ideal lithography pattern based on the size of the Euclidean distance corresponding to each of the actual edge cells.

[0016] Optionally, the step of calculating the Euclidean distance between the center point of each actual edge cell and the edge of the ideal lithographic pattern in S41 includes:

[0017] S411: Calculating the distance x between the center point of each actual edge cell and the edge of the ideal lithographic pattern in the horizontal direction;

[0018] S412: Calculating the distance y between the center point of each actual edge cell and the edge of the ideal lithographic pattern in the longitudinal direction;

[0019] S413: Based on the distance x and distance y of each actual edge cell, and the formula: Calculate the Euclidean distance d corresponding to each of the actual edge cells.

[0020] Optionally, step S5: outside the layout graph, optimizing the layout edge cells corresponding to the actual edge cells of each optimization weight level in descending order of the optimization weight level, until the layout edge cells corresponding to the actual edge cells of all optimization weight levels are optimized, and obtaining the final optimized layout graph, including:

[0021] S51: Determine the current actual edge cell and the current layout edge cell corresponding to the current optimization weight level;

[0022] S52: searching for optimized cells outside the current layout graphic and surrounding the edge cells of the current layout, wherein the optimized cells can compensate for the error of the current actual edge cells;

[0023] S53: superimposing the optimized cells on the current layout graphic to obtain a subsequent layout graphic, and the subsequent layout graphic is used as the current layout graphic for the next optimization iteration cycle;

[0024] S54: Obtaining a predicted lithography pattern based on the light intensity distribution of the subsequent layout pattern;

[0025] S55: Based on whether the predicted lithography pattern completely covers the current actual edge cell, determine whether to repeat steps S51 to S55 for the actual edge cell of the subsequent optimization weight level to perform the next optimization iteration cycle until the actual edge cell corresponding to the lowest optimization weight level is completely covered by the predicted lithography pattern.

[0026] Optionally, the step S51: determining the current actual edge cell and the current layout edge cell corresponding to the current optimization weight level includes:

[0027] Step S511: after determining the current actual edge cell corresponding to the current optimization weight level, determining the tangent direction of the edge of the current actual lithography pattern located in the current actual edge cell;

[0028] Step S512: determining a vertical line perpendicular to the tangent direction and passing through the center of the current actual edge cell;

[0029] Step S513: Determine the cell where the intersection of the vertical line and the current layout graphic is located as the current layout edge cell.

[0030] Optionally, the step S52 of searching, outside the current layout graphic, for optimized cells located around the edge cells of the current layout, wherein the optimized cells can compensate for the error of the current actual edge cells, includes:

[0031] Step S521: When the edge portion of the current layout covers the edge cell of the current layout, the optimized cell includes the edge cell of the current layout.

[0032] Optionally, the step S52 of searching, outside the current layout graphic, for optimized cells located around the edge cells of the current layout, wherein the optimized cells can compensate for the error of the current actual edge cells, includes:

[0033] Step S522: When the edge of the current layout completely covers the edge cell of the current layout, the optimized cell includes other cells adjacent to the edge cell of the current layout.

[0034] Optionally, the step S55 of determining whether to repeat steps S51 to S55 for the actual edge cells of the subsequent optimization weight level to perform the next optimization iteration cycle based on whether the predicted lithography pattern completely covers the current actual edge cells until the actual edge cells corresponding to the lowest optimization weight level are completely covered by the predicted lithography pattern includes:

[0035] Step S551: When the predicted lithography pattern does not completely cover the current actual edge cell, repeat steps S51 to S55, and continue to perform the next optimization iteration cycle on the current actual edge cell and the current layout edge cell corresponding to the current optimization weight level until the current actual edge cell is completely covered by the predicted lithography pattern.

[0036] Step S552: When the predicted lithography pattern completely covers the current actual edge cell, repeat steps S51 to S55, and perform the next optimization iteration cycle on the current actual edge cell and the current layout edge cell corresponding to the subsequent optimization weight level until the actual edge cell corresponding to the lowest optimization weight level is completely covered by the predicted lithography pattern.

[0037] The technical solution of the present application includes at least the following advantages: first, the difference area between the actual lithography pattern and the ideal lithography pattern is grid-divided, and then the weight of the edge of the actual lithography pattern is determined. The larger the weight, the closer it is to the ideal lithography pattern. Then, by first giving priority to the layout edge cells corresponding to the actual edge cells with larger weight levels, and evaluating whether the optimization is completed based on the proportion of the area of ​​the ideal lithography pattern that is not covered by the final lithography pattern, the efficiency of the optimization process can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the specific implementation methods or the description of the prior art. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0039] Figure 1 A flow chart of a layout graphics optimization method provided by an embodiment of the present application is shown;

[0040] Figure 1aA superimposed comparison diagram of an initial layout pattern A and an actual lithographic pattern corresponding to the initial layout pattern A is shown;

[0041] Figure 1b A superimposed comparison diagram of the actual lithography pattern and the ideal lithography pattern corresponding to the initial layout pattern A is shown;

[0042] Figure 1c It shows that after meshing, Figure 1b An enlarged schematic diagram of the corner 100;

[0043] Figure 2a It shows that before optimization, Figure 1a or Figure 1b A schematic diagram of the superposition of the initial layout pattern, the actual lithography pattern and the ideal lithography pattern at the corner 100 is shown;

[0044] Figure 2b The figure shows the superposition of the initial layout pattern, the actual lithography pattern and the ideal lithography pattern at the corner 100 after optimization;

[0045] Figure 3a Shown Figure 2a Schematic diagram after mesh division;

[0046] Figure 3b A schematic diagram showing the optimization of cells E and F of the initial layout graphic A is shown. DETAILED DESCRIPTION

[0047] The following is a clear and complete description of the technical solutions in this application in conjunction with the accompanying drawings. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application.

[0048] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate the description of this application and simplify the description. They do not indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0049] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal connections between two components; they can refer to wireless connections or wired connections. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0050] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0051] Figure 1 The flow chart of the layout graphics optimization method provided by an embodiment of the present application is shown. Figure 1 As can be seen from the figure, the layout graphics optimization method includes the following steps:

[0052] Step S1: Based on the same grid, the initial layout pattern, the actual lithography pattern and the ideal lithography pattern are grid-divided.

[0053] Figure 1a The figure shows the superposition comparison of the initial layout pattern A and the actual lithography pattern corresponding to the initial layout pattern A. Figure 1b A superimposed comparison diagram of the actual lithography pattern and the ideal lithography pattern corresponding to the initial layout pattern A is shown.

[0054] from Figure 1a and Figure 1b It can be seen that at the corner 100 of the layout pattern A, there is a difference area between the actual lithography pattern and the ideal lithography pattern. Therefore, it is necessary to correct and optimize the difference area at the corner 100 of the layout pattern A so that the optimized layout pattern obtained after correction can produce Figure 1b The ideal photolithography pattern shown.

[0055] Figure 1c It shows that after meshing, Figure 1b An enlarged view of corner 100.

[0056] from Figure 1c As can be seen from the figure, the corner 100 is divided into a number of cells of the same size. For the convenience of description, the size of a cell is defined as 1×1 in this embodiment.

[0057] Step S2: determining a difference area between the actual lithography pattern and the ideal lithography pattern.

[0058] from Figure 1cIt can be seen that the region P is the difference region between the actual photolithography pattern and the ideal photolithography pattern. In the difference region P, the edge of the actual photolithography pattern 101 and the edge of the ideal photolithography pattern 102 do not overlap with each other, and there is a difference.

[0059] It should be noted that in this embodiment, the initial layout pattern, the actual lithographic pattern, and the ideal lithographic pattern are first gridded based on the same grid, and then the difference area is determined. In other embodiments, the difference area between the actual lithographic pattern and the ideal lithographic pattern can be first determined, and then the initial layout pattern, the actual lithographic pattern, and the ideal lithographic pattern corresponding to the difference area are gridded based on the same grid.

[0060] After meshing, the initial layout pattern, actual lithography pattern, and ideal lithography pattern are divided into several cells of the same size.

[0061] Step S3: in the difference area, determining all cells through which the edge of the actual lithography pattern passes as actual edge cells.

[0062] Continue to refer to Figure 1c The actual photolithography pattern 101 passes through cells including the B cell, the C cell, and the D cell, so that the B cell, the C cell, and the D cell are actual edge cells of the actual photolithography pattern 101 .

[0063] Step S4: setting an optimization weight level corresponding to each actual edge cell based on the size of the gap between each actual edge cell and the edge of the ideal lithography pattern.

[0064] The smaller the gap is, the higher the optimization weight level of the actual edge cell is. The closer the edge of the actual lithography pattern in the actual edge cell is to the edge of the ideal lithography pattern, the more optimization should be performed first.

[0065] Step S5: outside the initial layout graph, optimizing the layout edge cells corresponding to the actual edge cells of each optimization weight level in descending order of the optimization weight levels, until all the layout edge cells corresponding to the actual edge cells of all optimization weight levels are optimized, thereby obtaining a final optimized layout graph;

[0066] The final lithography pattern obtained by the final optimized layout pattern satisfies: , wherein S2 is the area occupied by the ideal lithography pattern in the difference region, S1 is the area occupied by the final lithography pattern in the difference region, and S0 is the area of ​​the difference region.

[0067] The preset threshold value may be preset according to a required error range between the final lithography pattern and the ideal lithography pattern.

[0068] Figure 2a It shows that before optimization, Figure 1a or Figure 1b A schematic diagram of the superposition of the initial layout pattern, the actual lithography pattern and the ideal lithography pattern at the corner 100 is shown. Figure 2b The diagram shows the superposition of the final optimized layout pattern, the actual lithography pattern and the ideal lithography pattern at the corner 100 after optimization.

[0069] from Figure 2a and Figure 2b It can be seen from the figure that the final optimized layout graph A0 extends the optimized layout part A01 outward relative to the initial layout graph A, and through Figure 2b The final lithographic pattern 201 obtained by the final optimized layout pattern A0 is shown. Compared with the actual lithographic pattern 101 obtained by the initial layout pattern A, the final lithographic pattern 201 is closer to the ideal lithographic pattern 102 and has a smaller error with the ideal lithographic pattern 102 .

[0070] This embodiment first divides the difference area between the actual lithography pattern and the ideal lithography pattern into grids, and then determines the weight of the edge of the actual lithography pattern. The larger the weight, the closer it is to the ideal lithography pattern. Then, by giving priority to the layout edge cells corresponding to the actual edge cells with larger weight levels, and evaluating whether the optimization is complete based on the proportion of the area of ​​the ideal lithography pattern that is not covered by the final lithography pattern, the efficiency of the optimization process can be improved.

[0071] for Figure 1 The step S4: setting the optimization weight of each actual edge cell based on the difference between the actual edge cell and the edge of the ideal lithography pattern can be achieved by the following steps S41 to S42:

[0072] Step S41: calculating the Euclidean distance between the center point of each actual edge cell and the edge of the ideal lithography pattern.

[0073] Step S42: determining the size of the gap between each of the actual edge cells and the edge of the ideal lithography pattern based on the size of the Euclidean distance corresponding to each of the actual edge cells.

[0074] When performing step S41, the following steps S411 to S413 may be performed:

[0075] Step S411: Calculate the distance x between the center point of each actual edge cell and the edge of the ideal lithography pattern in the horizontal direction.

[0076] Step S412: Calculate the distance y between the center point of each actual edge cell and the edge of the ideal lithography pattern in the longitudinal direction.

[0077] Step S413: Based on the distance x and distance y of each actual edge cell, and the formula: Calculate the Euclidean distance d corresponding to each of the actual edge cells.

[0078] For example, continue to refer to Figure 1c , where the distance x1=2.5 from the center of the B cell in the actual edge cell to the edge of the ideal lithographic pattern 102 in the x (horizontal) direction, the distance y1=1.5 from the center of the B cell to the edge of the ideal lithographic pattern 102 in the y (vertical) direction, and the Euclidean distance between the B cell and the edge of the ideal lithographic pattern 102

[0079] The distance x2 from the center of the C cell in the actual edge cell to the edge of the ideal lithographic pattern 102 in the x direction is 1.5, the distance y2 from the center of the C cell to the edge of the ideal lithographic pattern 102 in the y direction is 2.5, and the Euclidean distance between the C cell and the edge of the ideal lithographic pattern 102 is

[0080] The distance x3 from the center of the D cell in the actual edge cell to the edge of the ideal lithographic pattern 102 in the x direction is 1.5, the distance y3 from the center of the D cell to the edge of the ideal lithographic pattern 102 in the y direction is 3.5, and the Euclidean distance between the D cell and the edge of the ideal lithographic pattern 102 is

[0081] From this, it can be seen that for the three actual edge cells B, C, and D, the Euclidean distances of cell B and cell C are the same and smaller than the Euclidean distance of cell D, so the optimization weight levels of cell B and cell C are the same and larger than the optimization weight level of cell D.

[0082] for Figure 1 Step S5 in the above method: outside the layout graph, optimizing the layout edge cells corresponding to the actual edge cells of each optimization weight level in descending order of the optimization weight level, until the layout edge cells corresponding to the actual edge cells of all optimization weight levels are optimized, and obtaining the final optimized layout graph can be achieved by performing the following steps S51 to S55 in sequence:

[0083] Step S51: Determine the current actual edge cell and the current layout edge cell corresponding to the current optimization weight level.

[0084] Optionally, the current layout edge cell may be determined based on the current actual edge cell and the current layout graphic and according to the following steps S511 to S513:

[0085] After determining the current actual edge cell corresponding to the current optimization weight level, step S511 can be performed first: determine the tangent direction of the edge of the current actual lithography pattern located in the current actual edge cell; then step S512 can be performed: determine the vertical line perpendicular to the tangent direction and passing through the center of the current actual edge cell; finally, step S513 can be performed: determine that the cell where the intersection of the vertical line and the current layout pattern is located is the current layout edge cell.

[0086] Exemplarily, the cells through which the edge of the initial layout graphic A passes are the initial edge cells of the layout. After the first optimization iteration cycle is performed on the initial edge cells of the layout corresponding to the actual edge cells with the highest optimization weight in the initial layout graphic A, the subsequent layout graphic is obtained.

[0087] Compared to the initial layout pattern A, the subsequent layout pattern is expanded on the basis of the initial layout pattern A, so that the lithography pattern obtained by the subsequent layout pattern tends to cover the actual edge cells with the highest optimization weight.

[0088] For example, referring to Figure 3a , which shows Figure 2a Schematic diagram after meshing.

[0089] Figure 3a The layout graphic in is the initial layout graphic A. Figure 3a The E cell in is the cell with the highest optimization weight level, and through the above steps S511 to S513, it is determined that the initial edge cell of the layout corresponding to the E cell is the F cell.

[0090] From the above, it can be seen that in the first optimization iteration cycle of the initial layout graphic A, the E cell and the F cell are optimized. That is, in the first optimization iteration cycle, the E cell is the current actual edge cell, and the F cell is the current layout edge cell.

[0091] Step S52: outside the current layout pattern, searching for optimized cells located around the edge cells of the current layout, wherein the optimized cells can compensate for the error of the current actual edge cells.

[0092] Wherein, when the edge portion of the current layout covers the edge cell of the current layout, the optimized cell includes the edge cell of the current layout.

[0093] Continue to refer to Figure 3a ,from Figure 3a It can also be seen that the edge of the initial layout graphic A passes through the F cell, that is, the edge of the initial layout graphic A partially covers the F cell, and there is still a part of the F cell that is not covered by the initial layout graphic A. Therefore, when optimizing the E cell and the F cell of the initial layout graphic A, the F cell can be selected as the optimized cell.

[0094] Step S53: superimposing the optimized cells on the current layout graphic to obtain a subsequent layout graphic, and the subsequent layout graphic is used as the current layout graphic for the next optimization iteration cycle.

[0095] Reference Figure 3b , which shows the schematic diagram after the optimization of the E and F cells of the initial layout pattern A. Figure 3a and Figure 3b It can be seen that Figure 3b The subsequent layout pattern is shown in FIG, which is the initial layout pattern A superimposed with the optimized cell (cell F).

[0096] Step S54: obtaining a predicted lithography pattern through the light intensity distribution of the subsequent layout pattern.

[0097] The light intensity distribution of the subsequent layout pattern can be obtained by superimposing the light intensity distribution of the pre-acquired current layout pattern and the light intensity distribution of the pre-acquired optimized cell.

[0098] In addition, the predicted lithographic pattern obtained by the light intensity distribution of the later layout pattern can be used to predict the later actual lithographic pattern formed by the later layout pattern after actual exposure. That is, the predicted lithographic pattern can represent the later actual lithographic pattern.

[0099] For example, Figure 3b As shown in the figure, the subsequent layout pattern can be determined by superimposing the light intensity distribution of the initial layout pattern A and the light intensity distribution of the F cell.

[0100] Step S55: Based on whether the predicted lithography pattern completely covers the current actual edge cell, determine whether to repeat steps S51 to S55 for the actual edge cell of the subsequent optimization weight level to perform the next optimization iteration cycle until the actual edge cell corresponding to the lowest optimization weight level is completely covered by the predicted lithography pattern.

[0101] For example, when optimizing the E and F cells of the initial layout A for the first time, we get Figure 3bAfter the subsequent layout pattern A' is shown, if the predicted lithographic pattern obtained from the subsequent layout pattern A' can completely cover cell E, the cell corresponding to the next highest optimization weight level is optimized in the next iteration cycle. If the predicted lithographic pattern does not completely cover cell E, the next optimization iteration cycle will still be performed on cell E and cell F, which correspond to the highest optimization weight level.

[0102] After all the actual edge cells and layout edge cells corresponding to the optimization weight levels are completed through the above steps S51 to S55, the Figure 2b The final optimized layout is shown in Figure 4.

[0103] Obviously, the above embodiments are merely examples for clarity of explanation and are not intended to limit the implementation methods. Those skilled in the art will appreciate that other variations or modifications can be made based on the above description. It is not necessary and impossible to enumerate all implementation methods here. Obvious variations or modifications arising therefrom remain within the scope of protection of this application.

Claims

1. A layout graphics optimization method, characterized in that: The layout graphics optimization method comprises the following steps: S1: Based on the same grid, the initial layout pattern, actual lithography pattern and ideal lithography pattern are meshed; S2: determining a difference area between the actual lithography pattern and the ideal lithography pattern; S3: in the difference area, determining all cells through which the edge of the actual lithography pattern passes as actual edge cells; S4: setting an optimization weight level corresponding to each of the actual edge cells based on the size of the gap between the edge of each of the actual edge cells and the edge of the ideal lithography pattern; S41: Calculating the Euclidean distance between the center point of each actual edge cell and the edge of the ideal lithography pattern respectively; S42: determining the distance between each of the actual edge cells and the edge of the ideal lithography pattern based on the Euclidean distance corresponding to each of the actual edge cells; S5: Outside the layout graph, optimizing the layout edge cells corresponding to the actual edge cells of each optimization weight level in descending order of the optimization weight levels, until all the layout edge cells corresponding to the actual edge cells of all optimization weight levels are optimized, thereby obtaining a final optimized layout graph; The final lithography pattern obtained by the final optimized layout pattern satisfies: Wherein S2 is the area of ​​the ideal photolithography pattern in the difference region, S1 is the area of ​​the final photolithography pattern in the difference region, and S0 is the area of ​​the difference region.

2. The layout graphics optimization method according to claim 1, wherein: The step S41 of respectively calculating the Euclidean distance between the center point of each actual edge cell and the edge of the ideal lithography pattern comprises the following steps: S411: Calculating the distance x between the center point of each actual edge cell and the edge of the ideal lithographic pattern in the horizontal direction; S412: Calculating the distance y between the center point of each actual edge cell and the edge of the ideal lithographic pattern in the longitudinal direction; S413: Based on the distance x and distance y of each actual edge cell, and the formula: Calculate the Euclidean distance d corresponding to each of the actual edge cells.

3. The layout graphics optimization method according to claim 1, wherein: The step of S5: optimizing, outside the layout graphic, the layout edge cells corresponding to the actual edge cells of each optimization weight level in descending order of the optimization weight levels until the layout edge cells corresponding to the actual edge cells of all optimization weight levels are optimized, and obtaining the final optimized layout graphic, comprises the following steps: S51: Determine the current actual edge cell and the current layout edge cell corresponding to the current optimization weight level; S52: searching for optimized cells outside the current layout graphic and surrounding the edge cells of the current layout, wherein the optimized cells can compensate for the error of the current actual edge cells; S53: superimposing the optimized cells on the current layout graphic to obtain a subsequent layout graphic, and the subsequent layout graphic is used as the current layout graphic for the next optimization iteration cycle; S54: Obtaining a predicted lithography pattern based on the light intensity distribution of the subsequent layout pattern; S55: Based on whether the predicted lithography pattern completely covers the current actual edge cell, determine whether to repeat steps S51 to S55 for the actual edge cell of the subsequent optimization weight level to perform the next optimization iteration cycle until the actual edge cell corresponding to the lowest optimization weight level is completely covered by the predicted lithography pattern.

4. The layout graphics optimization method according to claim 3, wherein: The step S51: determining the current actual edge cell and the current layout edge cell corresponding to the current optimization weight level, includes the following steps: S511: after determining the current actual edge cell corresponding to the current optimization weight level, determining the tangent direction of the edge of the current actual lithography pattern located in the current actual edge cell; S512: Determine a vertical line that is perpendicular to the tangent direction and passes through the center of the current actual edge cell; S513: Determine that the cell where the intersection of the vertical line and the current layout graphic is located is the current layout edge cell.

5. The layout graphics optimization method according to claim 3, wherein: The step S52: searching for optimized cells located around the edge cells of the current layout outside the current layout pattern, wherein the optimized cells can compensate for the error of the current actual edge cells, comprises the following steps: Step S521: When the edge portion of the current layout covers the edge cell of the current layout, the optimized cell includes the edge cell of the current layout.

6. The layout graphics optimization method according to claim 3, wherein: The step S52: searching for optimized cells located around the edge cells of the current layout outside the current layout pattern, wherein the optimized cells can compensate for the error of the current actual edge cells, comprises the following steps: S522: When the edge of the current layout completely covers the edge cell of the current layout, the optimized cells include other cells adjacent to the edge cell of the current layout.

7. The layout graphics optimization method according to claim 3, wherein: The step S55 of determining whether to repeat steps S51 to S55 for the actual edge cells at the subsequent optimization weight level to perform the next optimization iteration cycle based on whether the predicted lithography pattern completely covers the current actual edge cells, until the actual edge cells corresponding to the lowest optimization weight level are completely covered by the predicted lithography pattern, includes the following steps: S551: When the predicted lithography pattern does not completely cover the current actual edge cell, repeat steps S51 to S55, and continue to perform the next optimization iteration cycle on the current actual edge cell and the current layout edge cell corresponding to the current optimization weight level until the current actual edge cell is completely covered by the predicted lithography pattern; S552: When the predicted lithography pattern completely covers the current actual edge cell, repeat steps S51 to S55, and perform the next optimization iteration cycle on the current actual edge cell and the current layout edge cell corresponding to the subsequent optimization weight level, until the actual edge cell corresponding to the lowest optimization weight level is completely covered by the predicted lithography pattern.

Images