A memory controller, a data reading method, and a memory system

Abstract

Embodiments of the present application disclose a memory controller, a data reading method and a memory system, which are used for improving the efficiency of data reading. The memory controller comprises a host side interface, a first cache, a page table buffer and a second cache. The page table buffer stores cache entries corresponding to the second cache, and the cache entries are used for indicating data pages stored in the second cache. The memory controller receives a read instruction through the host side interface, and the read instruction carries a read address. When it is determined that the first cache is not hit according to the read address, the memory controller queries the page table buffer according to the read address. When it is determined that a data page corresponding to the read address has been cached in the second cache, the memory controller reads the data corresponding to the read address from the second cache.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the computer field, and in particular, to a memory controller, a data reading method and a memory system. BACKGROUND

[0002] Memory is an indispensable important component in a server, and the cost of the memory accounts for about 30%-40% of the total cost of the server system. Therefore, reducing the cost of the memory without reducing or slightly reducing the performance is an important means to reduce the total cost of ownership (TCO) of the whole system, and the memory technology has become a hot technology researched by major server manufacturers and cloud operators. Using a hard compression engine to compress memory data or using a new medium (such as a non-volatile memory) with higher latency but lower cost to replace the traditional memory can significantly reduce the cost of the memory, but the increase in memory access latency has a negative impact on application performance. SUMMARY

[0003] Embodiments of the present application provide a memory controller, a data reading method and a memory system to solve the problem of long memory access latency.

[0004] In a first aspect, a memory controller is provided, and the memory controller comprises a host-side interface, a first-level cache, a page table buffer and a second-level cache. The page table buffer stores a cache entry corresponding to the second-level cache, and the cache entry is used to indicate a data page stored in the second-level cache. The memory controller is configured to receive a read instruction through the host-side interface, determine a first-level cache miss according to a read address carried by the read instruction, query the page table buffer according to the read address, and read data corresponding to the read address from the second-level cache when it is determined that a data page corresponding to the read address has been cached in the second-level cache.

[0005] The memory controller defined in the embodiments of the present application comprises a two-level cache and a page table buffer. The cache entry in the page table buffer records the data pages already cached in the second-level cache, so as to effectively utilize the data in the second-level cache and reduce the case of reading data from the memory, thereby effectively reducing the problem of long latency when reading data from the memory and improving the efficiency of data access.

[0006] Further, when it is determined that the data page corresponding to the read address is not cached in the second-level cache, the memory controller is further configured to read the data corresponding to the read address from the memory through a memory interface.

[0007] In a possible implementation, the memory controller is configured to cache the data page corresponding to the read address in the secondary cache after reading the data page from the memory via the memory interface, and add a cache entry corresponding to the read address in the page table buffer. By adding the missed data page to the secondary cache and adding the cache entry in the page table buffer, the amount of cached data pages is increased, and the possibility of data access hit is further increased.

[0008] The memory controller is further configured to evict a target cache entry according to an eviction rule, and write the data page corresponding to the target cache entry back to the memory. It should be noted that the eviction rule can be LRU or the least cache page principle. The least cache page principle refers to that a huge page with the least cached data page is preferentially evicted.

[0009] In another possible implementation, the secondary cache stores decompressed data of a data page, and the memory stores compressed data of the data page. The secondary cache is configured to prefetch the compressed data in the memory and cache the decompressed data corresponding to the compressed data.

[0010] The embodiments of the present application further provide a format of a read address and a format of a cache entry. For example, the read address includes a page tag, a page index, and a page offset. The cache entry includes a page tag, a cache flag, and a huge page index. The huge page index is used to indicate an address of a huge page in the secondary cache. The cache flag is used to indicate whether the data page has been cached in the huge page.

[0011] The memory controller is further configured to query the page table buffer according to the page tag in the read address, determine whether there is a cache entry corresponding to the page tag in the page table buffer, further query a cache flag corresponding to the page index in the read address, and determine whether the data page corresponding to the read address has been cached in the secondary cache if the cache entry corresponding to the page tag exists in the page table buffer. If the data page corresponding to the read address has been cached, the data corresponding to the read address is read from the secondary cache.

[0012] In another possible implementation, after the data page corresponding to the read address has been cached in the secondary cache, the memory controller is further configured to construct a cache address corresponding to the read address. The cache address BPA is

[0013] BPA = Huge Page Index * M + Page Index * N + Page offset

[0014] wherein Huge Page Index is the huge page index, Page Index is the page index, and Page offset is the page offset. M is the size of the huge page, and N is the size of the page.

[0015] The memory controller is specifically configured to read data corresponding to the read address from the second-level cache according to the cache address.

[0016] The number of bits of the page identifier is x, and the number of bits of the cache tag is 2 x , wherein the X is an integer greater than 0.

[0017] For example, the number of bits of the page tag is 19 bits, the number of bits of the page index is 9 bits, and the number of bits of the intra-page offset is 12 bits. The number of bits of the cache tag is 2 9 bits (512 bits).

[0018] In a possible implementation, the first-level cache is an SRAM, and the second-level cache is a DRAM.

[0019] In a possible implementation, the page table buffer includes a first-level page table buffer and a second-level page table buffer, wherein the number of cached entries in the first-level page table buffer is less than the number of cached entries in the second-level page table buffer. For example, the number of cached entries in the first-level page table buffer is 128, and the number of cached entries in the second-level page table buffer is 16k.

[0020] In a second aspect, an embodiment of the present application provides a data reading method performed by a memory controller, the memory controller including a host-side interface, a first-level cache, a page table buffer, and a second-level cache. The page table buffer stores a cache entry corresponding to the second-level cache. The cache entry is used to indicate a data page stored in the second-level cache,

[0021] The method includes:

[0022] The memory controller receives a read instruction through the host-side interface. The read instruction carries a read address.

[0023] The memory controller determines a first-level cache miss according to the read address.

[0024] The memory controller queries the page table buffer according to the read address. When it is determined that a data page corresponding to the read address has been cached in the second-level cache, the memory controller reads data corresponding to the read address from the second-level cache.

[0025] In a possible implementation, the method further includes:

[0026] When it is determined that the data page corresponding to the read address is not cached in the second-level cache, the memory controller reads data corresponding to the read address from a memory through a memory interface.

[0027] Further, the method can further include:

[0028] The memory controller caches the data page in the second level cache after reading the data page corresponding to the read address from the memory through the memory interface, and adds a cache entry corresponding to the read address in the page table buffer.

[0029] Further, the method can further include:

[0030] The memory controller evicts the target cache entry according to the eviction rule, and writes the data page corresponding to the target cache entry back to the memory.

[0031] In a possible implementation, the second level cache stores decompressed data of a data page, and the memory stores compressed data of the data page, and the second level cache is configured to prefetch the compressed data in the memory and cache the decompressed data corresponding to the compressed data.

[0032] For example, the read address includes a page tag, a page index, and a page offset, and the cache entry includes a page tag, a cache flag, and a huge page index, wherein the huge page index is used to indicate an address of a huge page in the second level cache, and the cache flag is used to indicate whether the data page has been cached in the huge page.

[0033] At this time, the memory controller queries the page table buffer according to the read address, and when it is determined that the data page corresponding to the read address has been cached in the second level cache, reading the data corresponding to the read address from the second level cache includes:

[0034] The memory controller queries the page table buffer according to the page tag in the read address, determines whether there is a cache entry corresponding to the page tag in the page table buffer, if there is, further queries the cache flag corresponding to the page index of the read address, and determines whether the data page corresponding to the read address has been cached in the second level cache, if the data page corresponding to the read address has been cached, reads the data corresponding to the read address from the second level cache.

[0035] In another possible implementation, after it is determined that the data page corresponding to the read address has been cached in the second level cache, the method further includes:

[0036] The memory controller constructs a cache address corresponding to the read address, and the cache address BPA is:

[0037] BPA = Huge Page Index * M + Page Index * N + Page offset

[0038] Wherein, the Huge Page Index is a huge page index, the Page Index is a page index, and the Page offset is a page offset,

[0039] The memory controller reads data corresponding to the read address from the second cache according to the cache address.

[0040] In a third aspect, the embodiments of the present application further provide a memory system, comprising a memory and the memory controller as described in the first aspect.

[0041] In a fourth aspect, the embodiments of the present application further provide a chip, comprising a storage medium and a hardware processing logic, the storage medium stores instructions, and the hardware processing logic is configured to execute the instructions in the storage medium to implement the method steps as described in the second aspect or any possible implementation manner of the second aspect.

[0042] In a fifth aspect, the embodiments of the present application further provide a server, comprising a processor and the memory system as described in the third aspect.

[0043] In a sixth aspect, the embodiments of the present application provide a computer readable storage medium, which stores a computer program or instructions, when the computer program or instructions are executed by a processor in a server, are configured to implement the operation steps of the method as described in the second aspect or any possible implementation manner of the second aspect.

[0044] In a seventh aspect, the embodiments of the present application provide a computer program product, which comprises instructions, when the computer program product is run on a server or a terminal, causes the server or the terminal to execute the instructions to implement the operation steps of the method as described in the second aspect or any possible implementation manner of the second aspect.

[0045] On the basis of the implementation manners of the above aspects, the embodiments of the present application can be further combined to provide more implementation manners. BRIEF DESCRIPTION OF DRAWINGS

[0046] Figure 1 FIG. 1 is a structural schematic diagram of a memory controller in the embodiments of the present application;

[0047] Figure 2 FIG. 2 is a structural schematic diagram of a memory system provided by the embodiments of the present application;

[0048] Figure 3 FIG. 3 is a format schematic diagram of a read address provided by the embodiments of the present application;

[0049] Figure 4 FIG. 4 is a data cache structure schematic diagram provided by the embodiments of the present application;

[0050] Figure 5Another data cache structure diagram provided by an embodiment of the present application;

[0051] Figure 6 A memory controller data reading method flow diagram provided by an embodiment of the present application. DETAILED DESCRIPTION

[0052] The terms "comprise", "comprising", "include", "including", "have", "having" and any variations thereof in the specification and claims of the present application and in the above description of the above figures are intended to cover a non-exclusive inclusion such that a process, method, system, product or apparatus that comprises, includes or has a series of steps or units is not necessarily limited to those listed steps or units but can include other steps or units not expressly listed or inherent to such process, method, system, product or apparatus.

[0053] In a memory-centric computing architecture scenario, real-time compression / decompression of data in a large-capacity memory becomes an important means to reduce memory cost. For example, compression / decompression in units of 4K pages reduces cost but greatly increases CPU memory access latency. Although data can be cached through a large-capacity cache, this simultaneously causes a high cost problem, and for a large-capacity and random access scenario, the effect is limited.

[0054] An embodiment of the present application introduces a certain capacity of secondary cache based on a traditional memory medium (for example, Low Power Double Data Rate SDRAM, LPDDR) in a serial memory chip to cache decompressed data, and introduces a small-spec static random access memory (SRAM) as a method to support a huge page TLB (Translation Lookaside Buffer, address translation buffer) index, thereby reducing multiple memory accesses caused by a traditional page table Page Table Walk method and improving data reading efficiency. Specifically, an embodiment of the present application introduces a small-capacity cache (SRAM), a medium-capacity uncompressed memory, a large-capacity compressed memory or a PCM medium memory on an external serial memory chip, which reduces the cost of memory and avoids the problem of long access latency when the CPU accesses a large-capacity compressed memory.

[0055] As Figure 1The memory controller 100 comprises a host side interface 101, a first level cache 102, a page table buffer 103 and a second level cache 104. The page table buffer 103 stores cache entries corresponding to the second level cache 104, and the cache entries are used to indicate data pages stored in the second level cache 104. The memory controller 100 receives a read instruction through the host side interface 101, determines that the first level cache 102 is not hit according to a read address carried by the read instruction, and then queries the page table buffer 103 according to the read address. When it is determined that a data page corresponding to the read address has been cached in the second level cache 104, the data corresponding to the read address is read from the second level cache 104.

[0056] Further, the memory controller further comprises a memory interface 105.

[0057] The first level cache 102 comprises cachelines and tags corresponding to the cachelines. The memory controller 100 first searches the first level cache 102 according to a read address to find data to be read. If the first level cache 102 is hit, the hit cacheline is directly read from the first level cache 102.

[0058] Further, the memory controller further comprises serial-parallel conversion logic.

[0059] The memory controller defined in the embodiments of the present application comprises a two-level cache and a page table buffer. The cache entries in the page table buffer record data pages cached in the second level cache, so that the data in the second level cache is effectively utilized, and the case of reading data from the memory is reduced, thereby effectively reducing the problem of long delay when reading data from the memory and improving the efficiency of data access.

[0060] As Figure 2 The memory system 200 comprises a memory controller 100 and a memory 205.

[0061] When it is determined that the data page corresponding to the read address is not cached in the second level cache 104, the memory controller 100 further reads the data corresponding to the read address from the memory 205 through the memory interface 105.

[0062] Specifically, the data read from the memory 205 may be compressed data. After reading the compressed data, the memory controller 100 stores the corresponding decompressed data in the secondary cache 104. The memory controller 100 is configured to, after reading the data page corresponding to the read address from the memory 205 through the memory interface 105, cache the data page in the secondary cache 104 and add a cache entry corresponding to the read address in the page table buffer 103.

[0063] The memory controller 100 is further configured to evict a target cache entry from the page table buffer 103 according to an eviction rule, and write the data page corresponding to the target cache entry back to the memory 205. It should be noted that the eviction rule may be a least recently used (LRU) or least cached page principle. The least cached page principle means that huge pages with the fewest cached data pages are prioritized for eviction.

[0064] In another possible embodiment, the secondary cache 104 stores decompressed data of the data page, and the memory 205 stores compressed data of the data page. The secondary cache 104 is used to prefetch the compressed data in the memory 205 and cache the decompressed data corresponding to the compressed data.

[0065] like Figure 3 FIG2 is a schematic diagram of a read address format provided in an embodiment of the present application, wherein the read address includes a page tag, a page index, and a page offset. For example, the page tag has 19 bits, the page index has 9 bits, and the page offset has 12 bits.

[0066] like Figure 4 As shown in FIG, a schematic diagram of a data cache structure provided by an embodiment of the present application, wherein cachelines (CL) and CL tags are recorded in the first-level cache, and cache entries are recorded in the page table buffer. For example, the cache entries include page tags, buffered flags, and huge page indexes. A cache entry corresponds to a huge page in the second-level cache, and a data page in each huge page corresponds to a compressed page in the memory. For example, Figure 5 As shown, the first-level cache size is 64M, and the number of cache tags in the cache entries in the page table buffer is 2 9 bits (512 bits), each 1-bit cache tag corresponds to a data page in the huge page. When the data page in the huge page has cached the pre-fetched data page in the memory, the cache tag can be recorded as 1, otherwise, it can be recorded as 0.

[0067] The memory controller is further configured to query the page table buffer according to a page tag in the read address, determine whether a cache entry corresponding to the page tag exists in the page table buffer, if exists, further query a cache tag corresponding to a page index of the read address, determine whether a data page corresponding to the read address has been cached in the second-level cache, and read data corresponding to the read address from the second-level cache if the data page corresponding to the read address has been cached.

[0068] In another possible implementation, after the data page corresponding to the read address has been cached in the second-level cache, the memory controller is further configured to construct a cache address corresponding to the read address, the cache address BPA is

[0069] BPA = Huge Page Index * M + Page Index * N + Page offset

[0070] wherein, Huge Page Index is a huge page index, Page Index is a page index, Page offset is a page offset, M is a size of a huge page, and N is a size of a page.

[0071] According to the foregoing Figure 5 The sizes of the respective parameters are, correspondingly, the value of M is 2M, and the value of N is 4k. At this time, the second-level cache has a capacity of 32G and contains 16k huge pages with a size of 2M. In a specific implementation, the size and the number of the huge pages can be flexibly adjusted according to the size of an actual physical memory, and the present application embodiment will not be described again.

[0072] The first-level cache in the memory controller can use a static random-access memory (SRAM) with a relatively high speed, and data is saved in the form of a cache line. The data of the first-level cache is indexed using a CL tag tag. According to a physical address carried by a read instruction, the first-level cache is queried, and if a corresponding tag is queried, the first-level cache is hit, and the data of the hit cache line is read out.

[0073] The second-level cache in the memory controller can use a DRAM. Exemplarily, in combination with Figure 5 The data in the second-level cache is saved in the form of a 2M huge page, and each 2M huge page is composed of 512 4K pages.

[0074] The memory controller uses a page table buffer to index the second level cache. For example, a two-level second level cache can be used, i.e., a first level page table buffer and a second level page table buffer, wherein the number of cache entries in the first level page table buffer is less than the number of cache entries in the second level page table buffer. For example, the number of cache entries in the first level page table buffer is 128, and the number of cache entries in the second level page table buffer is 16k.

[0075] The page tag in the cache entry corresponds to the page tag of the physical address carried by the read instruction.

[0076] In combination Figure 5 For example, the cache tag can be 512 bits, and each bit of the cache tag corresponds to a 4K page in a 2M huge page. The cache tag is used to indicate whether the corresponding 4K page has been cached into the second level cache. For example, 0: not cached, 1: cached. The huge page index in the cache entry indicates the actual address of the current 2M huge page in the second level cache. The memory controller can determine the address of the corresponding huge page in the second level cache through the huge page index. Correspondingly, if the physical address on the host side is in the second level cache, the buffered physical address (BPA) of the data in the second level cache can be obtained by calculation. The calculation formula of BPA is:

[0077] BPA = Page Index * 2M + Index * 4K + Page offset

[0078] When the address of the memory is 40 bits, 1T of memory space can be addressed.

[0079] In combination Figure 3 The format of the read address is that the high 19 bits of the memory physical address is the page tag, which can be used to query the 2M huge page in the page table buffer, the middle 9 bits of the address correspond to the address of the specific 4K page in the 2M huge page that needs to be accessed, and the low 12 bits of the address correspond to the final address in the 4K page.

[0080] As Figure 6 shown, a memory controller data reading method flowchart provided by an embodiment of the application, comprising:

[0081] 601: The memory controller receives the physical address of the memory space sent by the host side, first queries the first level cache, and confirms whether it is a first level cache hit. If it is not hit, step 602 is executed, and if it is hit, the cacheline data is returned;

[0082] 602: The memory controller queries the page table buffer TLB based on the page tag in the physical address, determines the cache entry corresponding to the page tag, and determines whether the cache tag corresponding to the physical address in the cache entry is 1 (exemplarily, a value of 1 indicates that the data page corresponding to the tag bit has been cached in the second-level cache), determines the huge page index included in the cache entry, thereby calculating the address of the data to be accessed in the second-level cache, and performs step 603; if the cache tag corresponding to the physical address in the cache entry is 0 (exemplarily, a value of 0 indicates that the data page corresponding to the tag bit has not been cached in the second-level cache), step 604 is performed;

[0083] Specifically, when the page table buffer includes a two-level TLB, the two-level TLB is queried in sequence.

[0084] 603: The memory controller reads the data from the second-level cache according to the address of the data to be accessed in the second-level cache;

[0085] 604: The memory controller reads the data from the memory according to the physical address.

[0086] In combination with Figure 5 , the memory controller can read the 2k compressed data from the memory according to the physical address, store the decompressed 4k data into the corresponding 4k data page in the huge page in the second-level cache, and set the cache tag in the cache entry corresponding to the 4k data page to 1.

[0087] Further, if the cache entry is not hit, the action of the foregoing 604 is also performed.

[0088] Further, the memory controller can also evict the target cache entry according to an eviction rule, and write the data page corresponding to the target cache entry back to the memory. The eviction rule can be LRU or the least cache page principle. The least cache page principle refers to that the huge page with the least cached data page is preferentially evicted.

[0089] The embodiment of the application provides a serial memory controller with a two-level cache, which provides a low-cost and low-latency memory access scheme by caching decompressed data in the memory controller.

[0090] Those skilled in the art can clearly understand the specific working process of the memory controller, the method and the memory system described above for the convenience and brevity of description, which can refer to the corresponding process in the foregoing embodiments, and will not be described here.

Claims

1. A memory controller, comprising: The memory controller comprises a host-side interface, a first-level cache, a page table buffer and a second-level cache, wherein the page table buffer stores cache entries corresponding to the second-level cache, and the cache entries are used to indicate data pages stored in the second-level cache, The memory controller is configured to receive a read instruction through the host-side interface, and the read instruction carries a read address; the read address comprises a page tag, a page index and a page offset; the cache entry comprises a page tag, a cache tag and a huge page index, wherein the huge page index is used to indicate the address of a huge page in the second-level cache, and the cache tag is used to indicate whether a data page in the huge page has been cached; one cache entry corresponds to one huge page in the second-level cache, and one data page in each huge page corresponds to one compressed page in the memory; The memory controller is further configured to determine a first-level cache miss according to the read address; The memory controller is further configured to query the page table buffer according to the read address, and read the data corresponding to the read address from the second-level cache when it is determined that the data page corresponding to the read address has been cached in the second-level cache; The memory controller is further configured to query the page table buffer according to the page tag in the read address, determine whether there is a cache entry corresponding to the page tag in the page table buffer, if there is, further query the cache tag corresponding to the page index of the read address, and determine whether the data page corresponding to the read address has been cached in the second-level cache, and if the data page corresponding to the read address has been cached, read the data corresponding to the read address from the second-level cache.

2. The memory controller of claim 1, wherein, When it is determined that the data page corresponding to the read address has not been cached in the second-level cache, the memory controller is further configured to read the data corresponding to the read address from the memory through a memory interface.

3. The memory controller of claim 2, wherein The memory controller is configured to cache the data page in the second-level cache after reading the data page corresponding to the read address from the memory through the memory interface, and add a cache entry corresponding to the read address in the page table buffer.

4. The memory controller of claim 3, wherein The memory controller is further configured to evict a target cache entry according to an eviction rule, and write the data page corresponding to the target cache entry back to the memory.

5. The memory controller of any one of claims 1-4, wherein The second-level cache stores decompressed data of the data page, and the memory stores compressed data of the data page, and the second-level cache is used to prefetch the compressed data in the memory and cache the decompressed data corresponding to the compressed data.

6. The memory controller of claim 1, wherein After the data page corresponding to the read address has been cached in the second-level cache, the memory controller is further configured to construct a cache address corresponding to the read address, and the cache address BPA is BPA = Huge Page Index * M + Page Index * N + Page offset wherein the Huge Page Index is a huge page index, the Page Index is a page index, and the Page offset is a page offset, The memory controller is specifically configured to read the data corresponding to the read address from the second-level cache according to the cache address. 7.The memory controller of claim 1, wherein, The number of bits of the page identifier is x, and the number of bits of the cache tag is 2x. 8.The memory controller of claim 1, wherein, The first-level cache is an SRAM, and the second-level cache is a DRAM. 9.The memory controller of claim 1, wherein, The page table buffer comprises a first-level page table buffer and a second-level page table buffer, wherein the number of cache entries in the first-level page table buffer is less than the number of cache entries in the second-level page table buffer.

10. A method for reading data by a memory controller, the method comprising: The memory controller comprises a host-side interface, a first-level cache, a page table buffer, and a second-level cache, wherein the page table buffer stores cache entries corresponding to the second-level cache, and the cache entries are used to indicate data pages stored in the second-level cache, The method comprises: The memory controller receives a read instruction through the host-side interface, and the read instruction carries a read address; the read address comprises a page tag, a page index, and a page offset, and the cache entry comprises a page tag, a cache tag, and a huge page index, wherein the huge page index is used to indicate the address of a huge page in the second-level cache, and the cache tag is used to indicate whether a data page in the huge page has been cached; one cache entry corresponds to one huge page in the second-level cache, and one data page in each huge page corresponds to one compressed page in the memory; The memory controller determines a first-level cache miss according to the read address; The memory controller queries the page table buffer according to the read address, and reads the data corresponding to the read address from the second-level cache when it is determined that the data page corresponding to the read address has been cached in the second-level cache; The memory controller queries the page table buffer according to the page tag in the read address, determines whether there is a cache entry corresponding to the page tag in the page table buffer, further queries the cache tag corresponding to the page index of the read address if there is a cache entry corresponding to the page tag, and determines whether the data page corresponding to the read address has been cached in the second-level cache, and reads the data corresponding to the read address from the second-level cache if the data page corresponding to the read address has been cached.

11. The method of claim 10, wherein, The method further comprises: When it is determined that the data page corresponding to the read address has not been cached in the second-level cache, the memory controller reads the data corresponding to the read address from the memory through a memory interface.

12. The method of claim 11, wherein, The method further comprises: After reading the data page corresponding to the read address from the memory through the memory interface, the memory controller caches the data page in the second-level cache and adds a cache entry corresponding to the read address in the page table buffer.

13. The method of claim 12, wherein, The method further comprises: The memory controller evicts a target cache entry according to an eviction rule and writes the data page corresponding to the target cache entry back to the memory.

14. The method of any one of claims 10-13, wherein the secondary cache stores decompressed data of data pages, and the memory stores compressed data of the data pages, and the secondary cache is configured to prefetch the compressed data in the memory and cache the decompressed data corresponding to the compressed data. After determining that the data page corresponding to the read address is cached in the secondary cache, the method further comprises:

15. The method of claim 10, wherein, The memory controller constructs a cache address corresponding to the read address, and the cache address BPA is: BPA = Huge Page Index * M + Page Index * N + Page offset wherein Huge Page Index is a huge page index, Page Index is a page index, and Page offset is a page offset, The memory controller reads the data corresponding to the read address from the secondary cache according to the cache address. A memory system comprising a memory and the memory controller of any one of claims 1-9.

16. A memory system, comprising: A memory system comprising a memory and the memory controller of any one of claims 1-9.

17. A chip, characterized by A memory system comprising a memory and the memory controller of any one of claims 1-9.

18. A server, characterized by A memory system comprising a memory and the memory controller of any one of claims 1-9.

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