Filtering circuit, method, apparatus, storage medium and electronic device

Abstract

The application relates to the technical field of communication, in particular to a filtering circuit, a filtering method, a filtering device, a storage medium and an electronic device, and solves the problem of glitch signals in an I2C circuit in the prior art. The filtering circuit is applied to an I2C circuit and comprises: a control circuit connected with the I2C circuit, used for acquiring a to-be-filtered signal, a response signal, buffered data and a clock signal in the I2C circuit, and generating a filtering control signal according to the signals; and a filtering counting circuit connected with the control circuit and the I2C circuit, used for performing counting filtering processing on the to-be-filtered signal according to the filtering control signal, and outputting the filtered signal to a data line of the I2C circuit. The filtering circuit is used for filtering the handshake signals of master and slave devices in I2C bus communication, the filtering circuit can be directly embedded in the original I2C circuit, and does not affect any timing and functions of the original circuit, so that the glitch signals in the handshake process of the master and slave devices in the I2C bus communication are removed.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of communication, in particular to a filtering circuit, method, device, storage medium and electronic equipment. BACKGROUND

[0002] The communication mode in the form of a bus is widely used in the circuit design of various chips. The form of the bus makes the communication between circuits standardized, and the I2C bus is one of the many bus communication modes. The I2C protocol stipulates that the device connected to the bus needs to use the open-drain output mode. The open-drain output mode has no ability to output a high level, and needs to use a pull-up resistor to pull up the bus to output a high level. Therefore, when the bus is in an idle state, i.e., neither the host nor the slave takes over the bus, the bus is pulled up to output a high level by the pull-up resistor.

[0003] In the handshake process of the master-slave device of the I2C communication, there is a short time when the bus is not taken over by any party. At this time, the bus is pulled up to output a high level by the pull-up resistor. If the output data before and after this time are both low, a glitch signal will appear on the bus at this time. The existing I2C circuit does not have a special glitch filtering circuit. SUMMARY

[0004] In view of the problem of the glitch signal in the existing I2C circuit, the present application provides a filtering circuit, method, device, storage medium and electronic equipment.

[0005] In a first aspect, the present application provides a filtering circuit applied to an I2C circuit, the filtering circuit comprising:

[0006] a control circuit connected with the I2C circuit, configured to acquire a to-be-filtered signal, a response signal, buffered data and a clock signal in the I2C circuit, and generate a filtering control signal according to the to-be-filtered signal, the response signal, the buffered data and the clock signal;

[0007] a filtering counting circuit connected with the control circuit and the I2C circuit, configured to perform counting filtering processing on the to-be-filtered signal according to the filtering control signal, and output the filtered signal to a data line of the I2C circuit.

[0008] In the above embodiment, the filtering circuit is used to filter the handshake signal of the master-slave device in the I2C bus communication. The filtering circuit can be directly embedded in the original I2C circuit, and does not affect any timing and function of the original circuit, so as to remove the glitch signal appearing in the handshake process of the master-slave device in the I2C bus communication.

[0009] According to the embodiment of the present application, optionally, in the filter circuit, the control circuit comprises:

[0010] A signal edge detection circuit is configured to detect edge states of the response signal and the clock signal.

[0011] A read-write bit state judgment circuit is configured to judge read-write bit states of the buffered data.

[0012] A filter control enable circuit is configured to generate a filter control signal according to the edge states of the response signal and the clock signal and the read-write bit states, so that the filter counting circuit performs filter processing on the to-be-filtered signal according to the filter control signal.

[0013] According to the embodiment of the present application, optionally, in the filter circuit, the response signal comprises a receiving response signal and a sending response signal, and the filter control enable circuit comprises:

[0014] A first filter enable circuit is configured to generate a first filter enable signal according to the edge state of the receiving response signal or the sending response signal.

[0015] A second filter enable circuit is configured to generate a second filter enable signal according to the edge states of the receiving response signal, the sending response signal and the clock signal.

[0016] According to the embodiment of the present application, optionally, in the filter circuit, the filter control enable circuit further comprises:

[0017] A counting enable circuit is configured to generate a counting enable signal according to the first filter enable signal and the second filter enable signal, so that the filter counting circuit performs counting filter processing on the to-be-filtered signal according to the counting enable signal.

[0018] According to the embodiment of the present application, optionally, in the filter circuit, the counting enable circuit comprises a first counting enable circuit and a second counting enable circuit.

[0019] In a second aspect, the present application provides a filter method, applied to the filter circuit as described in any one of the above first aspect, the method comprising:

[0020] Obtaining a to-be-filtered signal, a response signal, buffered data and a clock signal in an I2C circuit;

[0021] Generating a filter control signal according to the to-be-filtered signal, the response signal, the buffered data and the clock signal;

[0022] Performing counting filter processing on the to-be-filtered signal according to the filter control signal, and outputting the filtered signal to a data line of the I2C circuit.

[0023] According to the embodiments of the present application, optionally, in the filtering method, the step of generating the filtering control signal according to the to-be-filtered signal, the response signal, the buffered data and the clock signal comprises:

[0024] detecting the edge state of the response signal and the clock signal;

[0025] judging the read-write bit state of the buffered data;

[0026] generating the filtering control signal according to the edge state of the response signal and the clock signal and the read-write bit state, so that the filtering counting circuit performs filtering processing on the to-be-filtered signal according to the filtering control signal.

[0027] In a third aspect, the present application provides a filtering device, which is applied to the filtering circuit in any one of the above-mentioned second aspects, and the device comprises:

[0028] a signal acquisition module, configured to acquire a to-be-filtered signal, a response signal, buffered data and a clock signal in an I2C circuit;

[0029] a filtering control signal generation module, configured to generate a filtering control signal according to the to-be-filtered signal, the response signal, the buffered data and the clock signal;

[0030] a counting filtering module, configured to perform counting filtering processing on the to-be-filtered signal according to the filtering control signal, and output the filtered signal to a data line of the I2C circuit.

[0031] In a fourth aspect, the present application provides a storage medium, which stores a computer program that can be executed by one or more processors and can be used to implement the above-mentioned filtering method.

[0032] In a fifth aspect, the present application provides an electronic device, which comprises a memory and a processor, and the memory stores a computer program, and the computer program is executed by the processor to execute the above-mentioned filtering method.

[0033] Compared with the prior art, one or more embodiments in the above-mentioned solution can have the following advantages or beneficial effects:

[0034] The application provides a filtering circuit, a filtering method, a filtering device, a storage medium and an electronic device. The filtering circuit is applied to an I2C circuit. The filtering circuit comprises a control circuit connected with the I2C circuit, which is used to acquire a to-be-filtered signal, a response signal, buffered data and a clock signal in the I2C circuit, and generate a filtering control signal according to the to-be-filtered signal, the response signal, the buffered data and the clock signal; and a filtering counting circuit connected with the control circuit and the I2C circuit, which is used to perform counting filtering processing on the to-be-filtered signal according to the filtering control signal, and output the filtered signal to a data line of the I2C circuit. In the above embodiment, the filtering circuit is used to filter the handshake signal between the master and the slave in the I2C bus communication. The filtering circuit can be directly embedded in the original I2C circuit, and does not affect any timing and function of the original circuit, so that the glitch signal in the handshake process between the master and the slave in the I2C bus communication can be removed. BRIEF DESCRIPTION OF DRAWINGS

[0035] Hereinafter, the application will be described in more detail based on the embodiments and with reference to the drawings.

[0036] Figure 1 A schematic diagram of a filtering circuit provided for the first embodiment of the application.

[0037] Figure 2 Another schematic diagram of a filtering circuit provided for the second embodiment of the application.

[0038] Figure 3 A flowchart of a filtering method provided for the third embodiment of the application.

[0039] Figure 4 A connection block diagram of a filtering device provided for the fourth embodiment of the application.

[0040] Figure 5 A connection block diagram of an electronic device provided for the sixth embodiment of the application.

[0041] In the drawings, the same components are denoted by the same reference numerals, and the drawings are not drawn according to the actual scale. DETAILED DESCRIPTION

[0042] The embodiments of the application will be described in detail below with reference to the drawings and the embodiments, so that how the application applies technical means to solve technical problems and achieves the corresponding technical effects can be fully understood and implemented. The embodiments of the application and each feature in the embodiments can be combined with each other without conflict, and the formed technical solutions are all within the protection scope of the application.

[0043] Example One

[0044] The application provides a filter circuit applied to an I2C circuit, please refer to Figure 1 , and the filter circuit comprises:

[0045] a control circuit 100 connected with the I2C circuit, for acquiring a to-be-filtered signal, a response signal, buffered data and a clock signal in the I2C circuit, and generating a filter control signal according to the to-be-filtered signal, the response signal, the buffered data and the clock signal;

[0046] a filter counting circuit 200 connected with the control circuit and the I2C circuit, for performing counting filter processing on the to-be-filtered signal according to the filter control signal, and outputting a filtered signal to a data line of the I2C circuit.

[0047] As an implementation form, the control circuit 100 in the filter circuit comprises:

[0048] a signal edge detection circuit 110 for detecting edge states of the response signal and the clock signal;

[0049] a read-write bit state judgment circuit 120 for judging read-write bit states of the buffered data;

[0050] a filter control enabling circuit 130 for generating a filter control signal according to the edge states of the response signal and the clock signal and the read-write bit states, so that the filter counting circuit performs filter processing on the to-be-filtered signal according to the filter control signal.

[0051] The signal edge detection circuit 110 comprises a received response signal edge detection circuit, a received response signal edge detection circuit and a clock signal edge detection circuit.

[0052] In summary, the application provides a filter circuit applied to an I2C circuit, please refer to Figure 1The filter circuit comprises a control circuit 100 connected with the I2C circuit, for acquiring a to-be-filtered signal, a response signal, buffered data and a clock signal in the I2C circuit, and generating a filter control signal according to the to-be-filtered signal, the response signal, the buffered data and the clock signal; and a filter counting circuit 200 connected with the control circuit and the I2C circuit, for performing counting filter processing on the to-be-filtered signal according to the filter control signal, and outputting the filtered signal to a data line of the I2C circuit. The filter circuit is used for filtering the handshake signals of the master and slave devices in the I2C bus communication, and can be directly embedded in the original I2C circuit without affecting any timing and function of the original circuit, so as to remove the glitch signals in the handshake process of the master and slave devices in the I2C bus communication.

[0053] Example Two

[0054] On the basis of the first embodiment, the method in the first embodiment is described through a specific implementation case.

[0055] The response signal comprises a received response signal and a sent response signal, please refer to Figure 1 The filter control enabling circuit 130 comprises:

[0056] The first filter enabling circuit 131 is used for generating a first filter enabling signal according to the edge state of the received response signal or the sent response signal.

[0057] The second filter enabling circuit 132 is used for generating a second filter enabling signal according to the edge state of the received response signal, the sent response signal and the clock signal.

[0058] Further, the filter control enabling circuit 130 further comprises:

[0059] The counting enabling circuit 131 is used for generating a counting enabling signal according to the first filter enabling signal and the second filter enabling signal, so that the filter counting circuit performs counting filter processing on the to-be-filtered signal according to the counting enabling signal.

[0060] As an implementation mode, the counting enabling circuit 131 comprises a first counting enabling circuit and a second counting enabling circuit.

[0061] Please refer to Figure 2 , Figure 2Rx_ack is output from a receiving shift register IIC RX SHIFT in the I2C circuit, the sending response signal Tx_ack is output from a sending shift register IIC TX SHIFT in the I2C circuit, and the I2c clock signal I2c_clk is generated from a GEN CLK clock generator in the I2C circuit and output through the sending shift register IIC TX SHIFT.

[0062] Rx_ack is output from a receiving shift register IIC RX SHIFT in the I2C circuit, the sending response signal Tx_ack is output from a sending shift register IIC TX SHIFT in the I2C circuit, and the I2c clock signal I2c_clk is generated from a GEN CLK clock generator in the I2C circuit and output through the sending shift register IIC TX SHIFT.

[0063] RW_JUDE is a read-write bit state judging circuit, used for judging the read-write bit state of the buffer data, wherein the buffer data includes the sending buffer data Txbuf_data[0] and the receiving buffer data Rxbuf_data[0]. FILTER_ENABLE is a filter control enabling circuit, wherein the filter control enabling circuit includes a first filter enabling circuit FILTER1_EN and a second filter enabling circuit FILTER2_EN. The FILTER1_EN circuit outputs a first filter enabling signal filter1_en, which is valid when a glitch occurs between the 8th and 9th periods of the master-slave device handshake in the I2C bus communication. The RX_ACK_EDGE_DECET outputs a falling edge flag signal of Rx_ack, and the TX_ACK_EDGE_DECET outputs a falling edge flag signal of Tx_ack, and the filter1_en signal is generated. The filter2_en signal is generated in the same way, that is, the CLK_EDGE_DECET outputs a falling edge flag signal of the clock signal I2c_clk, and the RX_ACK_EDGE_DECET outputs a rising edge flag signal of Rx_ack; or the CLK_EDGE_DECET outputs a falling edge flag signal of the clock signal I2c_clk, and the TX_ACK_EDGE_DECET outputs a rising edge flag signal of Tx_ack, and the filter2_en signal is generated. The second filter enabling circuit FILTER2_EN outputs a second filter enabling signal filter2_en, which is valid when a glitch occurs between the 9th and 10th periods of the master-slave device handshake in the I2C bus communication.

[0064] The Rx_ack, Tx_ack, and I2c_clk are respectively subjected to edge detection in the RX_ACK_EDGE_DECET, TX_ACK_EDGE_DECET, and CLK_EDGE_DECET, and the rising and falling edges of the respective signals are captured, and the signal output by the edge detection circuit is a flag of the captured edge signal, wherein the rising and falling edge flag signals of Rx_ack output by the RX_ACK_EDGE_DECET and the rising and falling edge flag signals of Tx_ack output by the TX_ACK_EDGE_DECET can be used as the judgment condition for generating the filter1_en signal in the FILTER1_EN; and the falling edge flag signal of Rx_ack output by the RX_ACK_EDGE_DECET, the rising edge flag signal of Tx_ack output by the TX_ACK_EDGE_DECET, and the rising and falling edge flag signals of I2c_clk output by the CLK_EDGE_DECET can be used as the judgment condition for generating the filter2_en signal in the FILTER2_EN.

[0065] The first count enable circuit COUNT1_EN outputs a valid first count enable signal count1_en when the first filter enable signal filter1_en is valid. The second count enable circuit COUNT2_EN outputs a valid second count enable signal count2_en when the second filter enable signal filter2_en is valid. FILTER_CNT is a filter count circuit. The filter enable signal Filter_en input into the filter count circuit FILTER_CNT can be controlled by a software program, i.e. the value of Filter_en is written through the APB bus of I2C so as to realize that the user can control the filter working state of the whole filter circuit through the filter enable signal Filter_en. The filter count setting value Filter_cnt input into the filter count circuit FILTER_CNT is used to ensure that the maximum value of the count during the counting filtering of the filter count circuit cannot exceed the setting value. Understandably, the filter count setting value Filter_cnt can be controlled by a software program.

[0066] The filter data Filter_data after the filtering is obtained by inputting the signal to be filtered I2c_data into the filter count circuit FILTER_CNT and performing the counting filtering of the filter count circuit FILTER_CNT.

[0067] The I2c_data input into FILTER2_EN is the same signal as the signal to be filtered I2c_data input into the filter count circuit FILTER_CNT. In addition, the Sda_int input into FILTER2_EN is the original data signal.

[0068] In the filter circuit of Figure 2 In the filter circuit of

[0069] For example, when the rising edge of Tx_ack comes and txbuf_data[0]=0, or the rising edge of Rx_ack comes and rxbuf_data[0]=0, it can be judged that the glitch signal appears, at this time, filter1_en is 1 to start filtering; and when the falling edge of Tx_ack comes or the falling edge of Rx_ack comes, filter1_en is 0, and the filtering ends.

[0070] When the Tx_ack falling edge comes and Sda_int=0, or the Rx_ack falling edge comes and I2c_data=1, it can be judged that the glitch signal appears, filter2_en is 1, and the filtering starts; when the I2c_clk falling edge comes and Tx_ack=0, or the I2c_clk falling edge comes and Rx_ack=0, filter2_en is 0, and the filtering ends.

[0071] Example Three

[0072] The application provides a filtering method applied to the filtering circuit, please refer to Figure 3 , the method comprises the following steps:

[0073] Step S310: obtaining a to-be-filtered signal, a response signal, buffered data and a clock signal in an I2C circuit;

[0074] Step S320: generating a filtering control signal according to the to-be-filtered signal, the response signal, the buffered data and the clock signal;

[0075] Step S330: performing a filtering processing on the to-be-filtered signal according to the filtering control signal, and outputting the filtered signal to a data line of the I2C circuit.

[0076] According to the embodiment of the application, in the filtering method, the step of generating the filtering control signal according to the to-be-filtered signal, the response signal, the buffered data and the clock signal comprises:

[0077] detecting edge states of the response signal and the clock signal;

[0078] judging read-write bit states of the buffered data;

[0079] generating the filtering control signal according to the edge states of the response signal and the clock signal and the read-write bit states, so that the filtering counting circuit performs the filtering processing on the to-be-filtered signal according to the filtering control signal.

[0080] Example Four

[0081] Please refer to Figure 4 , the application provides a filtering device 100, which is applied to the filtering circuit, and the device comprises:

[0082] A signal acquisition module 410 is configured to acquire a to-be-filtered signal, a response signal, buffered data and a clock signal in an I2C circuit.

[0083] The filter control signal generation module 420 is configured to generate a filter control signal according to the to-be-filtered signal, the response signal, the buffered data, and the clock signal.

[0084] The count filter module 430 is configured to perform count filtering on the to-be-filtered signal according to the filter control signal, and output the filtered signal to a data line of the I2C circuit.

[0085] According to the embodiments of the present application, optionally, in the filtering method, the filter control signal generation module 420 comprises:

[0086] The edge state detection unit is configured to detect edge states of the response signal and the clock signal.

[0087] The read-write bit state judgment unit is configured to judge a read-write bit state of the buffered data.

[0088] The filter control signal generation unit is configured to generate a filter control signal according to the edge states of the response signal and the clock signal and the read-write bit state, so that the filter count circuit performs filtering on the to-be-filtered signal according to the filter control signal.

[0089] In summary, the present application provides a filtering device 100, which is applied to the filtering circuit, and comprises: a signal acquisition module 410 configured to acquire a to-be-filtered signal, a response signal, buffered data, and a clock signal in an I2C circuit; a filter control signal generation module 420 configured to generate a filter control signal according to the to-be-filtered signal, the response signal, the buffered data, and the clock signal; and a count filter module 430 configured to perform count filtering on the to-be-filtered signal according to the filter control signal, and output the filtered signal to a data line of the I2C circuit. The filtering circuit is used for filtering the handshake signals of the master and the slave in the I2C bus communication, and can be directly embedded in the original I2C circuit without affecting any timing and function of the original circuit, so as to remove the glitch signals in the handshake process of the master and the slave in the I2C bus communication.

[0090] Example Five

[0091] The embodiment also provides a computer readable storage medium, such as a flash memory, a hard disk, a multimedia card, a card memory (for example, an SD or DX memory, etc.), a random access memory (RAM), a static random access memory (SRAM), a read-only memory (ROM), an electrically erasable programmable read-only memory (EEPROM), a programmable read-only memory (PROM), a magnetic memory, a magnetic disk, an optical disk, a server, an App application market, etc., which stores a computer program. The computer program can implement the method steps in the above embodiment three when executed by a processor. The embodiment will not be repeated here.

[0092] Example Six

[0093] The embodiment of the present application provides an electronic device which can be a mobile phone, a computer or a tablet computer, etc. The electronic device comprises a memory and a processor. The memory stores a computer program. The computer program is executed by the processor to implement the method described in the embodiment three. It can be understood that, as shown in the figure, the electronic device 500 can further comprise a processor 501, a memory 502, a multimedia component 503, an input / output (I / O) interface 504 and a communication component 505. Figure 5

[0094] The processor 501 is configured to execute all or part of the steps in the filtering method in the embodiment one. The memory 502 is configured to store various types of data. The data can comprise, for example, instructions of any application program or method in the electronic device, and application program related data.

[0095] The processor 501 can be an application specific integrated circuit (ASIC), a digital signal processor (DSP), a digital signal processing device (DSPD), a programmable logic device (PLD), a field programmable gate array (FPGA), a controller, a microcontroller, a microprocessor or other electronic elements, which is configured to execute the method in the embodiment three.

[0096] ​The memory 502 can be implemented by any type of volatile or nonvolatile storage devices or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk or optical disk.

[0097] The multimedia component 503 can include a screen, which can be a touch screen, and an audio component for outputting and / or inputting audio signals. For example, the audio component can include a microphone for receiving external audio signals. The received audio signals can be further stored in the memory or transmitted through the communication component. The audio component also includes at least one speaker for outputting audio signals.

[0098] The I / O interface 504 provides an interface between the processor 501 and other interface modules, which can be a keyboard, a mouse, a button, etc. These buttons can be virtual buttons or physical buttons.

[0099] The communication component 505 is used for wired or wireless communication between the electronic device 500 and other devices. Wireless communication, such as Wi-Fi, Bluetooth, near field communication (NFC), 2G, 3G or 4G, or a combination of one or more of them, so the corresponding communication component 505 can include a Wi-Fi module, a Bluetooth module, an NFC module.

[0100] In conclusion, the application provides a filtering circuit, method, device, storage medium and electronic equipment. The filtering circuit is applied to an I2C circuit. The filtering circuit comprises a control circuit connected with the I2C circuit, for acquiring a to-be-filtered signal, a response signal, buffered data and a clock signal in the I2C circuit, and generating a filtering control signal according to the to-be-filtered signal, the response signal, the buffered data and the clock signal; and a filtering counting circuit connected with the control circuit and the I2C circuit, for performing counting filtering processing on the to-be-filtered signal according to the filtering control signal, and outputting the filtered signal to a data line of the I2C circuit. The filtering circuit is used for filtering the handshake signal between the master and the slave in the I2C bus communication. The filtering circuit can be directly embedded in the original I2C circuit, and does not affect any timing and function of the original circuit, so as to remove the glitch signal in the handshake process between the master and the slave in the I2C bus communication.

[0101] In several embodiments provided in the embodiments of the present application, it should be understood that the disclosed system and method can also be implemented in other ways. The system and method embodiments described above are only illustrative.

[0102] It should be noted that, in this document, the terms "comprising", "containing" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device that includes a list of elements not only includes those elements, but also includes other elements not explicitly listed, or further includes elements inherent in such a process, method, article or device. Without more limitations, the element defined by the statement "comprising a" does not exclude the presence of additional identical elements in the process, method, article or device that includes the element.

[0103] Although the embodiments disclosed in the present application are as above, the content described is only for the purpose of facilitating understanding of the embodiments adopted by the present application, and is not intended to limit the present application. Any person skilled in the art without departing from the spirit and scope of the present application can make any modification and change in the form and details of the implementation, but the patent protection scope of the present application shall be subject to the scope defined by the appended claims.

Claims

1. A filter circuit, characterized by, The filter circuit is applied to an I2C circuit, and the filter circuit comprises: a control circuit connected with the I2C circuit, configured to acquire a to-be-filtered signal, a response signal, buffered data and a clock signal in the I2C circuit, and generate a filter control signal according to the to-be-filtered signal, the response signal, the buffered data and the clock signal; a filter counting circuit connected with the control circuit and the I2C circuit, configured to perform counting filter processing on the to-be-filtered signal according to the filter control signal, and output a filtered signal to a data line of the I2C circuit; the control circuit comprises: a signal edge detection circuit configured to detect edge states of the response signal and the clock signal; a read-write bit state judgment circuit configured to judge read-write bit states of the buffered data; a filter control enabling circuit configured to generate a filter control signal according to the edge states of the response signal and the clock signal and the read-write bit states, so that the filter counting circuit performs filter processing on the to-be-filtered signal according to the filter control signal; the response signal comprises a receiving response signal and a sending response signal, and the filter control enabling circuit comprises: a first filter enabling circuit configured to generate a first filter enabling signal according to the edge states of the receiving response signal or the sending response signal; a second filter enabling circuit configured to generate a second filter enabling signal according to the edge states of the receiving response signal, the sending response signal and the clock signal; the filter control enabling circuit further comprises: a counting enabling circuit configured to generate a counting enabling signal according to the first filter enabling signal and the second filter enabling signal, so that the filter counting circuit performs counting filter processing on the to-be-filtered signal according to the counting enabling signal; the counting enabling circuit comprises a first counting enabling circuit and a second counting enabling circuit, the first counting enabling circuit outputs a valid first counting enabling signal when the first filter enabling signal is valid, the second counting enabling circuit outputs a valid second counting enabling signal when the second filter enabling signal is valid, and a filter counting setting value corresponding to the counting enabling signal is written through an APB bus of the I2C, so that a maximum value of counting during counting filter processing of the filter counting circuit does not exceed the filter counting setting value.

2. A filtering method, characterized by, The method is applied to the filter circuit of claim 1, and the method comprises: acquiring a to-be-filtered signal, a response signal, buffered data and a clock signal in an I2C circuit; generating a filter control signal according to the to-be-filtered signal, the response signal, the buffered data and the clock signal; performing counting filter processing on the to-be-filtered signal according to the filter control signal, and outputting a filtered signal to a data line of the I2C circuit.

3. The filtering method of claim 2, wherein, the step of generating the filter control signal according to the to-be-filtered signal, the response signal, the buffered data and the clock signal comprises: detecting edge states of the response signal and the clock signal; judging read-write bit states of the buffered data; The filter control signal is generated according to the response signal, the edge state of the clock signal and the read-write bit state, so that the filter counting circuit filters the to-be-filtered signal according to the filter control signal.

4. A filtering device, characterized in that The device is applied to the filter circuit in claim 1, and the device comprises: A signal acquisition module is configured to acquire a to-be-filtered signal, a response signal, buffered data and a clock signal in an I2C circuit. A filter control signal generation module is configured to generate a filter control signal according to the to-be-filtered signal, the response signal, the buffered data and the clock signal. A counting filter module is configured to perform counting filtering on the to-be-filtered signal according to the filter control signal and output the filtered signal to a data line of the I2C circuit.

5. A storage medium, characterized by The computer program stored in the storage medium, when executed by one or more processors, is used to implement the method in any one of claims 2-3.

6. An electronic device, comprising: The device comprises a memory and a processor, and the memory stores a computer program which is executed by the processor to perform the method in any one of claims 2-3.

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