Fpga integrated circuit layout optimization method, device and equipment and storage medium

Abstract

The application discloses a FPGA integrated circuit layout optimization method, device and equipment and a storage medium. The method comprises the following steps: performing a short logic connection line selection operation: selecting a short logic connection line with the lowest Slack value from a short logic connection line set as a selected short logic connection line; wherein the short logic connection line is a logic connection line with a length less than a preset value; the short logic connection line set is: at the beginning, a set of short logic connection lines in the FPGA integrated circuit; performing a first moving operation, and after the first moving operation is performed, removing the current selected short logic connection line from the short logic connection line set, and re-performing the short logic connection line selection operation; through the embodiment of the application, the direct connection optimization of the short logic connection line can be realized in the layout stage.

Description

Technical Field

[0001] This invention relates to the field of FPGA chip design technology, and in particular to an FPGA integrated circuit layout optimization method, apparatus, device, and storage medium. Background Technology

[0002] FPGA application design involves logic design and optimization at the front end, followed by placement and routing at the back end. During the placement phase, the location of logic devices is optimized based on estimated timings. Once the timing targets are met, placement ends, and the routing phase begins. Routing connects the logic relationships using physical wires. Typically, device positions are not adjusted during routing to avoid disrupting the optimized timing results. However, in practice, significant deviations can occur between the timings estimated during placement and the timings after routing, meaning the routing results may not meet expectations. One reason for this is the error caused by the way the wires are connected.

[0003] FPGA chips are designed with various types of interconnects. Most connections are achieved through RSB conversion, while some short lines can connect without conversion. RSB is also a pre-built internal circuit and incurs latency. For longer lines, the positional relationship between two pins is not particularly important because conversion is necessary, and there are many intermediate paths to choose from. However, for two closely spaced pins, their positional relationship has a significant impact on timing. This is because if two short-distance pins can be directly connected, the connection does not require RSB conversion or detours, greatly reducing latency. Short direct connections are pre-laid specific lines; not all closely spaced pins can be directly connected. A direct connection will only succeed if they are in specific positions. Increasing the utilization rate of short direct connections can save routing resources and reduce latency in critical circuits. Therefore, how to increase the number of short logic connections that can be directly connected during FPGA chip design is a pressing issue that needs to be addressed. Summary of the Invention

[0004] This invention provides an FPGA integrated circuit layout optimization method, apparatus, device, and storage medium, which can increase the number of short logic interconnects that can be directly connected during the layout stage.

[0005] An embodiment of the present invention provides an FPGA integrated circuit layout optimization method, comprising: performing a short logic connection selection operation: selecting the short logic connection with the lowest Slack value from a set of short logic connections as the selected short logic connection; wherein, the short logic connection is a logic connection with a length less than a preset value; the set of short logic connections is: the initial set of all short logic connections in the FPGA integrated circuit;

[0006] Perform the first move operation, and after the first move operation is completed, remove the currently selected short logic connection line from the set of short logic connection lines, and re-execute the short logic connection line selection operation;

[0007] The first moving operation includes: moving the first load device from the first original unit block to the first adjacent unit block, and after each movement, determining whether the first preset condition and the second preset condition are met simultaneously, and stopping the movement of the first load device when it is determined that the first preset condition and the second preset condition are met simultaneously.

[0008] The first load device is the load device corresponding to the selected short logic connection line;

[0009] The first preset condition is: the first load device is located within a preset direct connection range of the first driving device;

[0010] The second preset condition is: the competitive price of the first load device in the current cell block is greater than the competitive price of the first load device in the first original cell block;

[0011] The first driving device is the driving device corresponding to the selected short logic connection line;

[0012] The first original cell block is the cell block where the first load device is located at the beginning; the first adjacent cell block is the cell block adjacent to the first original cell block; the competitive price of the first load device is calculated based on the timing criticality of each short logic connection line corresponding to the first load device and the abundance of direct connection line resources.

[0013] Furthermore, the first movement operation also includes: when it is determined that the first load device does not meet the first preset condition after the current movement, determining whether the first load device has traversed all the first adjacent unit blocks; if the first load device has not traversed all the first adjacent unit blocks, then continue to move the first load device to the remaining first adjacent unit blocks; if the first load device has traversed all the first adjacent unit blocks, then move the first driving device from the second original unit block to the second adjacent unit block, and after each movement of the first driving device, determining whether the third preset condition and the fourth preset condition are met, and stopping the movement of the first driving device when it is determined that the third preset condition and the fourth preset condition are met simultaneously;

[0014] If the first load device meets the first preset condition but does not meet the second preset condition after the current movement, the first load device is restored to its position before the current movement. It is then determined whether the first load device has traversed all the first adjacent unit blocks. If the first load device has not traversed all the first adjacent unit blocks, the first load device continues to move to the remaining first adjacent unit blocks. If the first load device has traversed all the first adjacent unit blocks, the driving device is moved from the second original unit block to the second adjacent unit block. After each movement of the first driving device, it is determined whether the third preset condition and the fourth preset condition are met. If it is determined that the third preset condition and the fourth preset condition are met simultaneously, the movement of the first driving device is stopped.

[0015] Wherein, the second original unit block is: the unit block where the first driving device is located at the beginning;

[0016] The second adjacent unit block is the unit block adjacent to the second original unit block;

[0017] The third preset condition is: the first driving device is located within a preset direct connection range of the first load device;

[0018] The fourth preset condition is: when the first driving device is in the current cell block, the competition price of the first driving device is greater than the competition price of the first driving device when it is in the second original cell block;

[0019] The competitive price of the first driving device is calculated based on the timing criticality of each short logic connection line corresponding to the first driving device and the abundance of direct connection resources.

[0020] Furthermore, the first movement operation also includes:

[0021] When it is determined that the first driving device does not meet the third preset condition after the current movement, it is determined whether the first driving device has traversed all the second adjacent unit blocks. If the first driving device has not traversed all the second adjacent unit blocks, the first driving device continues to move to the remaining second adjacent unit blocks; if the first driving device has traversed all the second adjacent unit blocks, the movement of the first driving device is stopped.

[0022] If the first driving device satisfies the third preset condition but not the second preset condition after the current movement, the first driving device is restored to its position before the current movement. It is then determined whether the first driving device has traversed all the second adjacent unit blocks. If the first driving device has not traversed all the second adjacent unit blocks, the first driving device continues to move to the remaining second adjacent unit blocks. If the first driving device has traversed all the second adjacent unit blocks, the movement of the first driving device is stopped.

[0023] Furthermore, after all the first movement operations corresponding to the short logic connection lines have been executed, the process also includes:

[0024] Perform the second short logic connection selection operation: select the short logic connection with the lowest Slack value from the second short logic connection set as the second selected short logic connection; wherein, the second short logic connection set is: the set of short logic connections in the FPGA integrated circuit after all the first move operations corresponding to the short logic connections have been executed;

[0025] Perform the second move operation, and after the second move operation is completed, remove the currently selected second short logic connection from the set of second short logic connections, and re-execute the second short logic connection selection operation;

[0026] The second movement operation includes:

[0027] Perform pin swap operation: End the pin swap operation when it is determined that the second load pin and the second drive pin can be directly connected without internal adapters;

[0028] When it is determined that the second load pin and the second drive pin cannot be directly connected without an internal adapter, it is determined whether there are pins in the second load device that have not been swapped with the second load pin.

[0029] If the second load device does not have any pins that have not been swapped with the second load pins, the pin swapping operation ends.

[0030] If it is determined that there are pins in the second load device that have not been swapped with the pins of the second load device, the pins of the second load device are swapped with the remaining pins of the second load device one by one, and after each swap, it is determined whether the fifth preset condition is met.

[0031] If the fifth preset condition is met, the connection value of the second unit block is updated, and it is re-evaluated whether the second load pin and the second drive pin can be directly connected without internal adapters.

[0032] If the fifth preset condition is not met, then it is re-evaluated whether there are pins in the second load device that have not been swapped with the pins of the second load.

[0033] Wherein, the second load pin is the load pin corresponding to the second selected short logic connection; the second drive pin is the drive pin corresponding to the second selected short logic connection; the second load device is the load device where the second load pin is located; and the second unit block is the unit block where the second load device is currently located.

[0034] The fifth preset condition is: after the pin position swap, the connection value of the second unit block is less than the connection value before the pin position swap.

[0035] The connection value of the second unit block is calculated based on the number of internal connection transitions of each short logic connection line corresponding to the second unit block and the load timing criticality.

[0036] Furthermore, the second movement operation also includes:

[0037] After the pin swapping operation is completed, it is determined whether the second load pin and the second drive pin can be directly connected without an internal adapter. If yes, the second movement operation ends; otherwise, the device position swapping operation is performed.

[0038] The device position exchange operation includes:

[0039] When it is determined that there is a device in the second unit block that has not been swapped with the second load device, the second load device is swapped with the remaining devices in the second unit block one by one, and after each device swap, it is determined whether the sixth preset condition is met.

[0040] If the sixth preset condition is met, the connection value of the second unit block is updated, and it is determined whether the second load pin and the second drive pin can be directly connected without an internal adapter. If it is determined that the second load pin and the second drive pin can be directly connected without an internal adapter, the device position exchange operation is ended. If it is determined that the second load pin and the second drive pin cannot be directly connected without an internal adapter, the pin exchange operation is performed.

[0041] If the sixth preset condition is not met, then the pin swapping operation is performed;

[0042] The sixth preset condition is: after the second load device position is swapped, the connection value of the second unit block is less than the connection value before the position swap.

[0043] Furthermore, the device position exchange operation also includes:

[0044] If it is determined that there is no device in the second unit block that has not exchanged device positions with the second load device, then it is determined whether there is a device in the second unit block that has not exchanged device positions with the second drive device.

[0045] If there are no devices in the second unit block that have not exchanged device positions with the second driving device, then the device position exchange operation ends.

[0046] If there are devices in the second unit block that have not exchanged device positions with the second driving device, the second driving device will be exchanged with the remaining devices in the second unit block one by one, and after each device position exchange, it will be determined whether the seventh preset condition is met.

[0047] If the seventh preset condition is met, the connection value of the second unit block is updated, and it is determined whether the second load pin and the second drive pin can be directly connected without internal adapter. Then, when it is determined that the second load pin and the second drive pin can be directly connected without internal adapter, the device position exchange operation is ended. When it is determined that the second load pin and the second drive pin cannot be directly connected without internal adapter, it is re-determined whether there is a device in the second unit block that has not been exchanged with the second load device.

[0048] If the seventh preset condition is not met, then it is re-evaluated whether there is a device in the second unit block that has not exchanged device positions with the second load device.

[0049] Wherein, the second driving device is the device where the second driving pin is located;

[0050] The seventh preset condition is: after the second driving device position is swapped, the connection value of the second unit block is less than the connection value before the position swap.

[0051] Furthermore, the device position exchange operation also includes:

[0052] When it is determined that there are no devices in the second unit block that have not exchanged device positions with the second driving device, the device position exchange operation ends.

[0053] Based on the above method embodiments, the present invention provides corresponding apparatus embodiments;

[0054] One embodiment of the present invention provides an FPGA integrated circuit layout optimization device, including: a short logic connection line selection module and a movement operation module;

[0055] The short logic connection selection module is used to perform a short logic connection selection operation: selecting the short logic connection with the lowest Slack value from the short logic connection set as the selected short logic connection; wherein, the short logic connection is a logic connection with a length less than a preset value; the short logic connection set is: the initial set of all short logic connections in the FPGA integrated circuit;

[0056] The moving operation module is used to perform a first moving operation, and after performing the first moving operation, remove the currently selected short logical connection line from the short logical connection line set, and re-execute the short logical connection line selection operation.

[0057] The first moving operation includes: moving the first load device from the first original unit block to the first adjacent unit block, and after each movement, determining whether the first preset condition and the second preset condition are met simultaneously, and stopping the movement of the first load device when it is determined that the first preset condition and the second preset condition are met simultaneously.

[0058] The first driving load device is the load device corresponding to the selected short logic connection line;

[0059] The first preset condition is: the first load device is located within a preset direct connection range of the first driving device;

[0060] The second preset condition is: the competitive price of the first load device in the current cell block is greater than the competitive price of the first load device in the first original cell block;

[0061] The first driving device is the driving device corresponding to the selected short logic connection line;

[0062] The first original unit block is: the unit block where the first load device is located at the beginning; the competitive price of the first load device is calculated based on the timing criticality of each short logic connection line corresponding to the first load device and the abundance of direct connection line resources.

[0063] Based on the above method embodiments, the present invention provides a corresponding terminal device embodiment;

[0064] One embodiment of the present invention provides a terminal device, including a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor. When the processor executes the computer program, it implements the FPGA integrated circuit layout optimization method according to any one of the present invention.

[0065] Based on the above method embodiments, the present invention provides a corresponding storage medium embodiment;

[0066] One embodiment of the present invention provides a storage medium including a stored computer program, wherein, when the computer program is executed, it controls the device where the storage medium is located to execute the FPGA integrated circuit layout optimization method according to any one of the present invention.

[0067] The following beneficial effects can be achieved by implementing the embodiments of the present invention:

[0068] This invention discloses an FPGA integrated circuit layout optimization method, apparatus, device, and storage medium. In the FPGA integrated circuit layout stage, the method adjusts the position of the first load device corresponding to each short logic connection line by performing a first movement operation. The adjustment is based on a first preset condition and a second preset condition. Based on the first preset condition, more first load devices of short logic connections can be located within a preset direct connection range of the corresponding first driving device, thereby increasing the probability of short logic connections becoming direct connections and thus increasing the number of direct short logic connections in the FPGA integrated circuit. However, since a device has many inputs and outputs, other connections cannot be sacrificed for one connection. Furthermore, even within the range of short direct connections, the number and quality of direct connections supported by different distances vary. Therefore, this invention uses a value competition mechanism based on the second preset condition to reconcile this contradiction, ultimately achieving the effect of as many direct interconnects as possible. Attached Figure Description

[0069] Figure 1 This is a schematic diagram showing the short-line connection relationship between each PLB in an FPGA chip.

[0070] Figure 2 This is a schematic diagram of the short-wire connection relationship inside the PLB in an FPGA chip.

[0071] Figure 3 This is a schematic diagram of the direct short wire connection in an FPGA chip.

[0072] Figure 4 This is a flowchart illustrating an embodiment of the FPGA integrated circuit layout optimization method provided by the present invention.

[0073] Figure 5 This is another flowchart illustrating the FPGA integrated circuit layout optimization method provided in an embodiment of the present invention.

[0074] Figure 6 This is a schematic diagram of the device pin connections provided in an embodiment of the present invention.

[0075] Figure 7 This is a flowchart illustrating the first movement operation provided in an embodiment of the present invention.

[0076] Figure 8 This is a flowchart illustrating the second movement operation provided in an embodiment of the present invention.

[0077] Figure 9 This is a schematic flowchart of a pin swapping operation provided in an embodiment of the present invention.

[0078] Figure 10 This is a schematic flowchart of a device position exchange operation provided in an embodiment of the present invention.

[0079] Figure 11 This is a schematic diagram of the structure of an FPGA integrated circuit layout optimization device provided in an embodiment of the present invention. Detailed Implementation

[0080] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0081] To better understand this invention, we will first explain the relevant knowledge of logic interconnects in existing FPGA chip integrated circuits:

[0082] An FPGA chip consists of many PLBs (Programmable Logic Units, i.e., unit blocks as described in this invention). Each unit block is composed of multiple logic and register devices. Based on the pin position of the short line (i.e., the short logic connection line as described in this invention), the direct connection method of the short line can be divided into two types.

[0083] 1. This refers to the interconnection between different PLB unit blocks. These short, straight-through connections (i.e., short, direct logical connections) are typically specific routes from the current unit block to adjacent unit blocks. For example... Figure 1 As shown in Figure a, pin 01 of device I1 needs to drive pin A of device I2, but there is no direct connection between these two pins. It must go through an RSB (Programmable Interconnect Switch Block) for conversion. If we assume that pin 01 can be directly connected to pin B of I2, or that pin 01 of device I1 can be directly connected to pin A of device I2 when I2 is in position I3, then the load pin can be moved to pin B of device I2 to form a short direct connection (e.g., ...). Figure 1 As shown in Figure b), or by moving I2 to the position of I3 to form a short straight line (as shown in Figure b). Figure 1 (As shown in Figure c).

[0084] 2. Within the same PLB unit block, these short straight lines only exist between specific pins. For example... Figure 2 As shown in Figure a: Pin 01 of I1 needs to drive pin A of device I2 within the same unit block. Assuming there is no direct connection between these two pins, it must pass through PLB, undergo RSB conversion, and then return. However, if pin 01 can be directly connected to pin B of I2, or if pin 01 of device I1 can be directly connected to pin A of device I2 when I2 is in position I3, then the load pin can be moved to pin B of device I2 to form a short direct connection (e.g., ...). Figure 2As shown in Figure b), or by moving I2 to the position of I3 to form a short straight line (as shown in Figure b). Figure 2 (As shown in Figure c).

[0085] Furthermore, FPGA devices generally only have short direct connections pre-laid within the peripheral unit blocks, such as... Figure 3 As shown, taking one end of the connection as the center, the other end must be within the cell block covered by the example black line to have a direct connection opportunity. Therefore, this stage requires adjusting the devices at both ends of the connection to place them within this range. For example, if a device is at [x=2, y=1] at one end, it can be moved to [x=2, y=0] or [x=1, y=1] to obtain a direct connection opportunity. However, since short-line direct connection optimization is only a fine-tuning, the selection of the target connection is limited. This limitation varies depending on the FPGA design. In the example of this invention, only connections with a Manhattan distance (the sum of the absolute differences between the horizontal and vertical axes of two coordinate systems) between the two ends being no greater than 3 are selected, i.e., (Δx+Δy)<=3. In other words, the short logic connection lines described in this invention are logic connection lines where the Manhattan distance between the driver end and the load end is less than 3.

[0086] A direct connection refers to a direct connection between two cells, with connecting lines both inside and outside the cell. External connecting lines have longer latency and are in greater demand, while internal connecting lines are only used by devices within the cell and have relatively shorter latency. When using external lines, internal lines are usually unavoidable. Therefore, the use of external lines for short connections should be avoided as much as possible. Thus, using only one external line (between cells) or no external line at all (within a cell) constitutes a direct connection.

[0087] Having learned of the above, the technical solution disclosed in this invention will be described below;

[0088] like Figure 4 As shown, one embodiment of the present invention provides an FPGA integrated circuit layout optimization method, which includes at least:

[0089] Step S101: Perform short logic connection selection operation: Select the short logic connection with the lowest Slack value from the short logic connection set as the selected short logic connection; wherein, the short logic connection is a logic connection with a length less than a preset value; the short logic connection set is: the initial set of all short logic connections in the FPGA integrated circuit.

[0090] Step S102: Execute a first move operation, and after completing the first move operation, remove the currently selected short logic connection from the short logic connection set, and re-execute the short logic connection selection operation; wherein, the first move operation includes: moving the first load device from the first original cell block to the first adjacent cell block, and after each move, determining whether a first preset condition and a second preset condition are simultaneously met, and stopping the movement of the first load device when it is determined that the first preset condition and the second preset condition are simultaneously met; the first load device is the load device corresponding to the selected short logic connection; the first preset condition is: the first load device is located within a preset direct connection range of the first driving device; the second preset condition is: the competition price of the first load device in the current cell block is greater than the competition price of the first load device in the first original cell block; the first driving device is the driving device corresponding to the selected short logic connection; the first original cell block is: the cell block where the first load device is located initially; the first adjacent cell block is: the cell block adjacent to the first original cell block; the competition price of the first load device is calculated based on the timing criticality of each short logic connection corresponding to the first load device and the abundance of direct connection resources.

[0091] For step S101, firstly, logic connection lines in the FPGA integrated circuit with an initial Manhattan distance of less than 3 between the load terminal and the corresponding driver terminal (the specific value can be set according to the actual situation, and the value here is only illustrative) are taken as short logic connection lines as shown in this invention, and then a set of short logic connection lines is formed; then, according to the Slack value of each short logic connection line (the difference between the demand time of the register input port for the signal and the arrival time of the signal, a negative value indicates a violation that needs to be optimized to be positive, this value is to characterize whether the timing meets the requirements, the smaller the value, the more critical the timing path), the short logic connection line with the smallest Slack value is selected as the short logic connection line, and step S102 is executed.

[0092] For step S102, the corresponding first move operation is performed according to the selected short logic connection line. After the first move operation is performed, the currently selected short logic connection line is removed from the short logic connection line set. Then, step S101 is repeated and the cycle continues until the short logic connection line set is empty.

[0093] In a preferred embodiment, the first moving operation further includes:

[0094] When it is determined that the first load device does not meet the first preset condition after the current movement, it is determined whether the first load device has traversed all the first adjacent unit blocks. If the first load device has not traversed all the first adjacent unit blocks, the first load device is moved to the remaining first adjacent unit blocks. If the first load device has traversed all the first adjacent unit blocks, the first driving device is moved from the second original unit block to the second adjacent unit block. After each movement of the first driving device, it is determined whether the third preset condition and the fourth preset condition are met. When it is determined that the third preset condition and the fourth preset condition are met at the same time, the movement of the first driving device is stopped.

[0095] If the first load device meets the first preset condition but does not meet the second preset condition after the current movement, the first load device is restored to its position before the current movement. It is then determined whether the first load device has traversed all the first adjacent unit blocks. If the first load device has not traversed all the first adjacent unit blocks, the first load device continues to move to the remaining first adjacent unit blocks. If the first load device has traversed all the first adjacent unit blocks, the driving device is moved from the second original unit block to the second adjacent unit block. After each movement of the first driving device, it is determined whether the third preset condition and the fourth preset condition are met. If it is determined that the third preset condition and the fourth preset condition are met simultaneously, the movement of the first driving device is stopped.

[0096] Wherein, the second original unit block is: the unit block where the first driving device is located at the beginning;

[0097] The second adjacent unit block is: the unit block adjacent to the second original unit block;

[0098] The third preset condition is: the first driving device is located within a preset direct connection range of the first load device;

[0099] The fourth preset condition is: when the first driving device is in the current cell block, the competition price of the first driving device is greater than the competition price of the first driving device when it is in the second original cell block;

[0100] The competitive price of the first driving device is calculated based on the timing criticality of each short logic connection line corresponding to the first driving device and the abundance of direct connection resources.

[0101] In a preferred embodiment, the first moving operation further includes:

[0102] When it is determined that the first driving device does not meet the third preset condition after the current movement, it is determined whether the first driving device has traversed all the second adjacent unit blocks. If the first driving device has not traversed all the second adjacent unit blocks, the first driving device continues to move to the remaining second adjacent unit blocks; if the first driving device has traversed all the second adjacent unit blocks, the movement of the first driving device is stopped.

[0103] If the first driving device satisfies the third preset condition but not the second preset condition after the current movement, the first driving device is restored to its position before the current movement. It is then determined whether the first driving device has traversed all the second adjacent unit blocks. If the first driving device has not traversed all the second adjacent unit blocks, the first driving device continues to move to the remaining second adjacent unit blocks. If the first driving device has traversed all the second adjacent unit blocks, the movement of the first driving device is stopped.

[0104] After all the first movement operations corresponding to the short logic connection lines have been completed, the first load devices of more short logic connection lines are located within the preset direct connection range of the corresponding first driving device, thereby increasing the possibility of short logic connections becoming direct connections, and thus increasing the number of short logic connection lines in the FPGA integrated circuit.

[0105] To further optimize the short-line direct connection, in a preferred embodiment, after executing the first movement operation corresponding to all the short logic connection lines, the method further includes: executing a second short logic connection line selection operation: selecting the short logic connection line with the lowest Slack value from the second short logic connection line set as the second selected short logic connection line; wherein, the second short logic connection line set is: the set of short logic connection lines in the FPGA integrated circuit after all the first movement operations corresponding to the short logic connection lines have been executed;

[0106] Perform the second move operation, and after the second move operation is completed, remove the currently selected second short logic connection from the set of second short logic connections, and re-execute the second short logic connection selection operation;

[0107] The second movement operation includes:

[0108] Perform pin swap operation: End the pin swap operation when it is determined that the second load pin and the second drive pin can be directly connected without internal adapters;

[0109] When it is determined that the second load pin and the second drive pin cannot be directly connected without an internal adapter, it is determined whether there are pins in the second load device that have not been swapped with the second load pin.

[0110] If the second load device does not have any pins that have not been swapped with the second load pins, the pin swapping operation ends.

[0111] If it is determined that there are pins in the second load device that have not been swapped with the pins of the second load device, the pins of the second load device are swapped with the remaining pins of the second load device one by one, and after each swap, it is determined whether the fifth preset condition is met.

[0112] If the fifth preset condition is met, the connection value of the second unit block is updated, and it is re-evaluated whether the second load pin and the second drive pin can be directly connected without internal adapters.

[0113] If the fifth preset condition is not met, then it is re-evaluated whether there are pins in the second load device that have not been swapped with the pins of the second load.

[0114] Wherein, the second load pin is the load pin corresponding to the second selected short logic connection; the second drive pin is the drive pin corresponding to the second selected short logic connection; the second load device is the load device where the second load pin is located; and the second unit block is the unit block where the second load device is currently located.

[0115] The fifth preset condition is: after the pin position swap, the connection value of the second unit block is less than the connection value before the pin position swap.

[0116] The connection value of the second unit block is calculated based on the number of internal connection transitions of each short logic connection line corresponding to the second unit block and the load timing criticality.

[0117] In a preferred embodiment, the second moving operation further includes:

[0118] After the pin swapping operation is completed, it is determined whether the second load pin and the second drive pin can be directly connected without an internal adapter. If yes, the second movement operation ends; otherwise, the device position swapping operation is performed.

[0119] The device position exchange operation includes:

[0120] When it is determined that there is a device in the second unit block that has not been swapped with the second load device, the second load device is swapped with the remaining devices in the second unit block one by one, and after each device swap, it is determined whether the sixth preset condition is met.

[0121] If the sixth preset condition is met, the connection value of the second unit block is updated, and it is determined whether the second load pin and the second drive pin can be directly connected without an internal adapter. If it is determined that the second load pin and the second drive pin can be directly connected without an internal adapter, the device position exchange operation is ended. If it is determined that the second load pin and the second drive pin cannot be directly connected without an internal adapter, the pin exchange operation is performed.

[0122] If the sixth preset condition is not met, then the pin swapping operation is performed;

[0123] The sixth preset condition is: after the second load device position is swapped, the connection value of the second unit block is less than the connection value before the position swap.

[0124] In a preferred embodiment, the device position exchange operation further includes:

[0125] If it is determined that there is no device in the second unit block that has not exchanged device positions with the second load device, then it is determined whether there is a device in the second unit block that has not exchanged device positions with the second drive device.

[0126] If there are no devices in the second unit block that have not exchanged device positions with the second driving device, then the device position exchange operation ends.

[0127] If there are devices in the second unit block that have not exchanged device positions with the second driving device, the second driving device will be exchanged with the remaining devices in the second unit block one by one, and after each device position exchange, it will be determined whether the seventh preset condition is met.

[0128] If the seventh preset condition is met, the connection value of the second unit block is updated, and it is determined whether the second load pin and the second drive pin can be directly connected without internal adapter. Then, when it is determined that the second load pin and the second drive pin can be directly connected without internal adapter, the device position exchange operation is ended. When it is determined that the second load pin and the second drive pin cannot be directly connected without internal adapter, it is re-determined whether there is a device in the second unit block that has not been exchanged with the second load device.

[0129] If the seventh preset condition is not met, then it is re-evaluated whether there is a device in the second unit block that has not exchanged device positions with the second load device.

[0130] Wherein, the second driving device is the device where the second driving pin is located;

[0131] The seventh preset condition is: after the second driving device position is swapped, the connection value of the second unit block is less than the connection value before the position swap.

[0132] In a preferred embodiment, the device position exchange operation further includes:

[0133] When it is determined that there are no devices in the second unit block that have not exchanged device positions with the second driving device, the device position exchange operation ends.

[0134] To better understand this invention, the integrated circuit layout optimization method disclosed in this invention will be described in further detail below:

[0135] Schematic illustration: In a preferred embodiment of the present invention, a simplified flowchart of the integrated circuit layout optimization method is shown below. Figure 5 As shown, it includes:

[0136] Step S501: Perform the short logic connection selection operation.

[0137] Step S502: Execute the first move operation, and after the first move operation is completed, remove the currently selected short logic connection line from the short logic connection line set, and re-execute the short logic connection line selection operation.

[0138] Step S503: After all the first movement operations corresponding to the short logic connection lines have been completed, the second short logic connection line selection operation is performed.

[0139] Step S504: Perform the second move operation, and after the second move operation is completed, remove the current second selected short logic connection line from the set of second short logic connection lines, and re-execute the second short logic connection line selection operation.

[0140] The specific selection steps for step S501 are the same as those for step S101 above, and will not be repeated here.

[0141] The specific execution steps of step S502 and the first movement operation are the same as described above, and will be further explained here; the overall process of the first movement operation is as follows: Figure 7 As shown, the first movement operation is the optimization of the device positions between unit blocks, and the specific process includes:

[0142] 1. Move the first load device corresponding to the currently selected short logic connection line to the remaining first adjacent cell blocks (initially, start moving from the first original cell block to the adjacent cell, that is, start moving to any first adjacent cell block), jump to 2.

[0143] 2. Determine whether the first load device is within the preset direct connection range of the first driving device (i.e., determine whether the first preset condition is met). If yes, skip to step 3; otherwise, skip to step 5.

[0144] 3. Determine whether the competitive price of the first load device has increased (i.e., determine whether the second preset condition is met). If yes, proceed to step 4; otherwise, proceed to step 6.

[0145] 4. Stop moving the first load device, and the first movement operation is complete.

[0146] 5. Determine if there is a first adjacent cell block that the first load device has not moved to (i.e., determine if the first load device has not traversed all first adjacent cell blocks). If yes, skip to step 1; otherwise, skip to step 7.

[0147] 6. The position of the first load device is retracted (i.e., the first load device is restored to its position before the current movement), and the process jumps to step 5.

[0148] 7. Move the first driving device corresponding to the currently selected short logic connection line to the remaining second adjacent cell blocks (initially, start from the second original cell block and move to its neighboring cell, that is, move to any second adjacent cell block), and jump to 8.

[0149] 8. Determine whether the first driving device is within the preset direct connection range of the first load device (i.e., determine whether the third preset condition is met). If yes, skip to step 9; otherwise, skip to step 11.

[0150] 9. Determine whether the competitive price of the first driving device has increased (i.e., determine whether the fourth preset condition is met). If yes, proceed to step 10; otherwise, proceed to step 12.

[0151] 10. Stop the movement of the first driving device. End. The first movement operation is complete.

[0152] 11. Determine if there is a second adjacent cell block that the first driving device has not moved to (i.e., determine if the first driving device has not traversed all second adjacent cell blocks). If yes, skip to step 7; otherwise, skip to step 10.

[0153] 12. Rewind the position of the first driving device (that is, restore the first driving device to its position before the current movement), and jump to step 11.

[0154] Schematic diagram: When the Manhattan distance between the first load device and the first drive device is less than 3, the first load device is located within the preset direct connection range of the first drive device.

[0155] Each time a device is moved, all its connected connections will change. Therefore, the competition price for a device differs across different cell blocks. The competition price of a device is the sum of the competition prices of all its corresponding short logic connections. The competition price of a short logic connection is calculated based on its timing criticality and the abundance of direct connections, using the formula: cost = T * R; where cost is the competition price of a short logic connection; T is the timing criticality of the short logic connection; R is the abundance of direct connections for the short logic connection; and timing criticality is determined by the slack value of the short logic connection. For illustration, short logic connections are sorted from smallest to largest based on their slack values: the top 1% have a timing criticality of 6; 1%–5% have a timing criticality of 5; 5%–10% have a timing criticality of 4; 10%–20% have a timing criticality of 3; 20%–40% have a timing criticality of 2; and those below 40% have a timing criticality of 1. The resource richness of a direct connection is determined based on the distance between the driving device and the load device corresponding to the short logic connection. The illustrative rules for determining the resource richness of a direct connection are as follows: if the driving device and the load device corresponding to the short logic connection are located within the same cell block, the resource richness of the short logic connection is 3; if the distance between the driving device and the load device is 1, the resource richness of the short logic connection is 2; if the distance between the driving device and the load device is 2, the resource richness of the short logic connection is 1; otherwise, the resource richness of the short logic connection is 0. The specific value of the direct connection resource richness can be adjusted according to the actual situation, but it should follow the principle that the smaller the distance between the driving device and the load device, the greater the direct connection resource richness of the corresponding short logic connection.

[0156] by Figure 6 Taking one device as an example, in Figure 6 The device has four input signals (a, b, c, and d) that drive it (i.e., there are four corresponding short logic connection lines). Its two output ports drive m and n loads respectively (there are a total of m+n corresponding short logic connection lines). The competitive price TC of this device is calculated using the following formula:

[0157]

[0158] In this formula, Cost a Cost b Cost c Cost d Cost represents the competition price of the short logic connection lines corresponding to the four signals a, b, c, and d. kCost represents the competition price of the short logic connection line corresponding to the k-th load signal connected to terminal 01 of device. i This represents the competitive price of the short logic connection line corresponding to the i-th load signal connected to terminal 02 of device.

[0159] The competitive prices of the first load device before and after its movement, as well as the competitive prices of the first drive device before and after its movement, can be calculated using the above method, thereby completing the judgments in steps 3 and 9.

[0160] Based on the above method, after the first operation corresponding to the currently selected short logic line is completed, the currently selected short logic connection line is removed from the short logic connection line set, and then the process jumps to the above step S501. Steps S501 and S502 are repeated until the short logic connection line set is empty, and then step S503 is executed.

[0161] For step S503: the specific implementation of the second short logic connection line selection operation is the same as the content described above. After executing steps S501 and S502, the short logic connection lines in the FPGA integrated circuit will change. At this time, the short logic connection lines in the FPGA integrated circuit are extracted again to generate the second short logic connection line set.

[0162] For step S504, as follows Figure 8 As shown, the second movement operation includes:

[0163] Step S801: Perform a pin swap operation.

[0164] Step S802: After the pin exchange operation is completed, determine whether the second load pin and the second drive pin can be directly connected without internal switching. If yes, end the second movement operation; otherwise, perform the device position exchange operation.

[0165] The specific execution steps of step S801, the pin swapping operation, are the same as described above, and will be further explained here; the overall process of the pin swapping operation is as follows: Figure 9 As shown, the specific process includes:

[0166] 101: Determine whether the second load pin and the second drive pin can be directly connected without an internal adapter; if yes, jump to 106; otherwise, jump to 102.

[0167] 102: Determine whether there is a pin in the second load device that has not been swapped with the pin of the second load. If yes, jump to 103; otherwise, jump to 106.

[0168] 103: Swap the pin positions of the second load pin with the remaining pins and jump to 104.

[0169] 104: Determine whether the connection value of the second unit block after the swap is less than the connection value before the swap (i.e., determine whether the fifth preset condition is met). If yes, jump to 105; otherwise, jump to 102.

[0170] 105: Update the connection value of the second unit block and jump to 101.

[0171] 106: End pin swapping operation.

[0172] It should be noted that the connection value of a unit block is the sum of the connection values ​​of all the short logic connections corresponding to the unit block; the formula for calculating the connection value of a short logic connection is: cost = P * T = 4 n *(1+k*0.1 n );

[0173] Where P is the internal join conversion penalty, P = 4 n n represents the number of internal connection conversions corresponding to the short logic connection. The method for determining n is as follows: if the short logic connection is a straight connection and no internal connection conversion is required, then n = 0; if the short logic connection is a straight connection and one internal connection conversion is required, then n = 1; if the short logic connection is a straight connection and two internal connection conversions are required, then n = 2; otherwise, n is 6.

[0174] T is the time-series criticality penalty coefficient, T = 1 + k * 0.1 n ,k represents the load timing criticality corresponding to the short logic connection, which can be determined based on the slack value of the short logic connection. Illustratively, based on the slack value of each short logic connection, the short logic connections are sorted from smallest to largest: the top 1% have a load timing criticality of 0; the top 1% to 5% have a load timing criticality of 1; the top 5% to 10% have a load timing criticality of 2; the top 10% to 20% have a load timing criticality of 3; the top 20% to 40% have a load timing criticality of 4; and the top 40% and below have a load timing criticality of 5.

[0175] The formula for calculating the connectivity value of a single unit block is:

[0176]

[0177] In this formula, TC is the connection value of the unit block, m is the total number of short logic connections connected to the unit block (i.e., the total number of short logic connections corresponding to the unit block), and Cost is... i Let n(i) be the connection value of the i-th short logic connection, n(i) be the number of internal connection transitions of the i-th short logic connection, and k(i) be the load timing criticality coefficient of the i-th short logic connection.

[0178] The connection value of the second unit block before and after the pin swap is calculated in the above manner for judgment; at the end of the pin swap operation, step S802 is executed.

[0179] For step S802, the specific execution steps of the device position exchange operation are the same as described above, and will be further explained here; the overall flow of the device position exchange operation is as follows: Figure 10 As shown, the specific process includes:

[0180] 201: Determine whether there is a device in the second unit block that has not exchanged device positions with the second load device. If yes, jump to 202; otherwise, jump to 207.

[0181] 202: The second load device exchanges positions with the other devices and jumps to 203.

[0182] 203: Determine whether the connection value of the second unit block after the position swap of the second load device is less than the connection value before the swap (i.e., determine whether the sixth preset condition is met). If yes, jump to 204; if no, jump to 206.

[0183] 204: Update the connection value of the second unit block and jump to 205.

[0184] 205: Determine whether the second load pin and the second drive pin can be directly connected without an internal adapter. If yes, jump to 209; otherwise, jump to 206.

[0185] 206: Perform pin swapping operation, i.e., jump to step S801 (after step S801 is completed, step S802 is executed immediately, and the cycle repeats).

[0186] 207: Determine whether there is a device in the second unit block that has not exchanged device positions with the second driving device. If not, jump to 208; if yes, jump to 210.

[0187] 208: The connection value of the second unit block is rolled back (i.e., the connection value of the second unit block is reset to the previous state), and then jump to 209; it should be noted that this step is not mandatory and can be omitted in other preferred embodiments. If omitted, step 209 is used instead of this step.

[0188] 209: End device position exchange operation.

[0189] 210: Exchange the positions of the second driving device with the remaining devices in the second unit block one by one, and jump to 211.

[0190] 211: Determine whether the connection value of the second unit block after the second driving device is exchanged is less than the connection value before the exchange (i.e., determine whether the seventh preset condition is met). If yes, jump to 212; otherwise, jump to 201.

[0191] 212: Update the connection value of the second unit block and jump to 213.

[0192] 213: Determine whether the second load pin and the second drive pin can be directly connected without an internal adapter. If yes, jump to 209; otherwise, jump to 201.

[0193] Following the above method, after completing the entire second move operation, the currently selected second short logic connection line is removed from the second short logic connection line set, and step S503 is executed again. This process is repeated until the second short logic connection line set is empty.

[0194] By implementing the above embodiments of the present invention, direct connection optimization can be achieved during the layout stage, placing more pairs of driver and load terminals at both ends of the direct connection. This provides direct guidance information for routing, reduces wasted routing resources, and improves routing success rate. Direct connections also reduce timing path latency, aiding in timing convergence. Furthermore, by comparing competitive device prices and device connection values ​​to obtain local optimal solutions, as many short logic lines as possible are directly connected, improving the efficiency of direct connections. High-quality connections are used more frequently in timing-critical paths, accelerating timing convergence.

[0195] Based on the above method embodiments, the present invention provides corresponding apparatus embodiments;

[0196] like Figure 11 As shown, an embodiment of the present invention provides an FPGA integrated circuit layout optimization device, including: a short logic connection line selection module and a movement operation module;

[0197] The short logic connection selection module is used to perform a short logic connection selection operation: selecting the short logic connection with the lowest Slack value from the short logic connection set as the selected short logic connection; wherein, the short logic connection is a logic connection with a length less than a preset value; the short logic connection set is: the initial set of all short logic connections in the FPGA integrated circuit;

[0198] The moving operation module is used to perform a first moving operation, and after performing the first moving operation, remove the currently selected short logical connection line from the short logical connection line set, and re-execute the short logical connection line selection operation.

[0199] The first moving operation includes: moving the first load device from the first original unit block to the first adjacent unit block, and determining whether the first preset condition and the second preset condition are met simultaneously after each movement; when it is determined that the first preset condition and the second preset condition are met simultaneously, stopping the movement of the first load device.

[0200] The first driving load device is the load device corresponding to the selected short logic connection line;

[0201] The first preset condition is: the first load device is located within a preset direct connection range of the first driving device;

[0202] The second preset condition is: the competitive price of the first load device in the current cell block is greater than the competitive price of the first load device in the first original cell block;

[0203] The first driving device is the driving device corresponding to the selected short logic connection line;

[0204] The first original cell block is the cell block where the first load device is located at the beginning; the first adjacent cell block is the cell block adjacent to the first original cell block; the competitive price of the first load device is calculated based on the timing criticality of each short logic connection line corresponding to the first load device and the abundance of direct connection line resources.

[0205] In a preferred embodiment, the first moving operation further includes:

[0206] When it is determined that the first load device does not meet the first preset condition after the current movement, it is determined whether the first load device has traversed all the first adjacent unit blocks. If the first load device has not traversed all the first adjacent unit blocks, the first load device is moved to the remaining first adjacent unit blocks. If the first load device has traversed all the first adjacent unit blocks, the first driving device is moved from the second original unit block to the second adjacent unit block. After each movement of the first driving device, it is determined whether the third preset condition and the fourth preset condition are met. When it is determined that the third preset condition and the fourth preset condition are met at the same time, the movement of the first driving device is stopped.

[0207] If the first load device meets the first preset condition but does not meet the second preset condition after the current movement, the first load device is restored to its position before the current movement. It is then determined whether the first load device has traversed all the first adjacent unit blocks. If the first load device has not traversed all the first adjacent unit blocks, the first load device continues to move to the remaining first adjacent unit blocks. If the first load device has traversed all the first adjacent unit blocks, the driving device is moved from the second original unit block to the second adjacent unit block. After each movement of the first driving device, it is determined whether the third preset condition and the fourth preset condition are met. If it is determined that the third preset condition and the fourth preset condition are met simultaneously, the movement of the first driving device is stopped.

[0208] Wherein, the second original unit block is: the unit block where the first driving device is located at the beginning;

[0209] The second adjacent unit block is the unit block adjacent to the second original unit block;

[0210] The third preset condition is: the first driving device is located within a preset direct connection range of the first load device;

[0211] The fourth preset condition is: when the first driving device is in the current cell block, the competition price of the first driving device is greater than the competition price of the first driving device when it is in the second original cell block;

[0212] The competitive price of the first driving device is calculated based on the timing criticality of each short logic connection line corresponding to the first driving device and the abundance of direct connection resources.

[0213] In a preferred embodiment, the first moving operation further includes:

[0214] When it is determined that the first driving device does not meet the third preset condition after the current movement, it is determined whether the first driving device has traversed all the second adjacent unit blocks. If the first driving device has not traversed all the second adjacent unit blocks, the first driving device continues to move to the remaining second adjacent unit blocks; if the first driving device has traversed all the second adjacent unit blocks, the movement of the first driving device is stopped.

[0215] If the first driving device satisfies the third preset condition but not the second preset condition after the current movement, the first driving device is restored to its position before the current movement. It is then determined whether the first driving device has traversed all the second adjacent unit blocks. If the first driving device has not traversed all the second adjacent unit blocks, the first driving device continues to move to the remaining second adjacent unit blocks. If the first driving device has traversed all the second adjacent unit blocks, the movement of the first driving device is stopped.

[0216] In a preferred embodiment, the FPGA integrated circuit layout optimization device further includes: a second short logic connection line selection module and a second movement operation module;

[0217] The second short logic connection selection module is used to perform a second short logic connection selection operation after all the first movement operations corresponding to the short logic connections have been completed: selecting the short logic connection with the lowest Slack value from the second short logic connection set as the second selected short logic connection; wherein, the second short logic connection set is: the set of short logic connections in the FPGA integrated circuit after all the first movement operations corresponding to the short logic connections have been completed;

[0218] The second movement operation module is used to perform a second movement operation, and after performing the second movement operation, remove the currently selected second short logical connection line from the set of second short logical connection lines, and re-execute the second short logical connection line selection operation;

[0219] The second movement operation includes:

[0220] Perform pin swap operation: End the pin swap operation when it is determined that the second load pin and the second drive pin can be directly connected without internal adapters;

[0221] When it is determined that the second load pin and the second drive pin cannot be directly connected without an internal adapter, it is determined whether there are pins in the second load device that have not been swapped with the second load pin.

[0222] If the second load device does not have any pins that have not been swapped with the second load pins, the pin swapping operation ends.

[0223] If it is determined that there are pins in the second load device that have not been swapped with the pins of the second load device, the pins of the second load device are swapped with the remaining pins of the second load device one by one, and after each swap, it is determined whether the fifth preset condition is met.

[0224] If the fifth preset condition is met, the connection value of the second unit block is updated, and it is re-evaluated whether the second load pin and the second drive pin can be directly connected without internal adapters.

[0225] If the fifth preset condition is not met, then it is re-evaluated whether there are pins in the second load device that have not been swapped with the pins of the second load.

[0226] Wherein, the second load pin is the load pin corresponding to the second selected short logic connection; the second drive pin is the drive pin corresponding to the second selected short logic connection; the second load device is the load device where the second load pin is located; and the second unit block is the unit block where the second load device is currently located.

[0227] The fifth preset condition is: after the pin position swap, the connection value of the second unit block is less than the connection value before the pin position swap.

[0228] The connection value of the second unit block is calculated based on the number of internal connection transitions of each short logic connection line corresponding to the second unit block and the load timing criticality.

[0229] In a preferred embodiment, the second movement operation further includes:

[0230] After the pin swapping operation is completed, it is determined whether the second load pin and the second drive pin can be directly connected without an internal adapter. If yes, the second movement operation ends; otherwise, the device position swapping operation is performed.

[0231] The device position exchange operation includes:

[0232] When it is determined that there is a device in the second unit block that has not been swapped with the second load device, the second load device is swapped with the remaining devices in the second unit block one by one, and after each device swap, it is determined whether the sixth preset condition is met.

[0233] If the sixth preset condition is met, the connection value of the second unit block is updated, and it is determined whether the second load pin and the second drive pin can be directly connected without an internal adapter. If it is determined that the second load pin and the second drive pin can be directly connected without an internal adapter, the device position exchange operation is ended. If it is determined that the second load pin and the second drive pin cannot be directly connected without an internal adapter, the pin exchange operation is performed.

[0234] If the sixth preset condition is not met, then the pin swapping operation is performed;

[0235] The sixth preset condition is: after the second load device position is swapped, the connection value of the second unit block is less than the connection value before the position swap.

[0236] In a preferred embodiment, the device position exchange operation further includes:

[0237] If it is determined that there is no device in the second unit block that has not exchanged device positions with the second load device, then it is determined whether there is a device in the second unit block that has not exchanged device positions with the second drive device.

[0238] If there are no devices in the second unit block that have not exchanged device positions with the second driving device, then the device position exchange operation ends.

[0239] If there are devices in the second unit block that have not exchanged device positions with the second driving device, the second driving device will be exchanged with the remaining devices in the second unit block one by one, and after each device position exchange, it will be determined whether the seventh preset condition is met.

[0240] If the seventh preset condition is met, the connection value of the second unit block is updated, and it is determined whether the second load pin and the second drive pin can be directly connected without internal adapter. Then, when it is determined that the second load pin and the second drive pin can be directly connected without internal adapter, the device position exchange operation is ended. When it is determined that the second load pin and the second drive pin cannot be directly connected without internal adapter, it is re-determined whether there is a device in the second unit block that has not been exchanged with the second load device.

[0241] If the seventh preset condition is not met, then it is re-evaluated whether there is a device in the second unit block that has not exchanged device positions with the second load device.

[0242] Wherein, the second driving device is the device where the second driving pin is located;

[0243] The seventh preset condition is: after the second driving device position is swapped, the connection value of the second unit block is less than the connection value before the position swap.

[0244] In a preferred embodiment, the device position exchange operation further includes: ending the device position exchange operation when it is determined that there is no device in the second unit block that has not exchanged device positions with the second driving device.

[0245] It should be noted that the device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Furthermore, in the accompanying drawings of the device embodiments provided by this invention, the connection relationships between modules indicate that they have communication connections, which can be specifically implemented as one or more communication buses or signal lines. Those skilled in the art can understand and implement this without any creative effort.

[0246] Based on the above method embodiments, the present invention provides a corresponding terminal device embodiment;

[0247] An embodiment of the present invention provides a terminal device, including: a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, wherein the processor executes the computer program to implement the FPGA integrated circuit layout optimization method according to any one of the present invention.

[0248] The terminal device can be a desktop computer, laptop, handheld computer, or cloud server, etc.

[0249] The processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be a microprocessor or any conventional processor. The processor is the control center of the terminal device, connecting all parts of the terminal device via various interfaces and lines.

[0250] The memory can be used to store the computer program, and the processor implements various functions of the terminal device by running or executing the computer program stored in the memory and calling the data stored in the memory. The memory may mainly include a program storage area and a data storage area. The program storage area may store the operating system, at least one application program required for a function (such as sound playback function, image playback function, etc.), etc.; the data storage area may store data created according to the use of the mobile phone (such as audio data, phonebook, etc.). In addition, the memory may include high-speed random access memory, and may also include non-volatile memory, such as hard disk, memory, plug-in hard disk, smart media card (SMC), secure digital (SD) card, flash card, at least one disk storage device, flash memory device, or other volatile solid-state storage devices.

[0251] Based on the above-described method embodiments, another embodiment of the present invention provides a storage medium comprising a stored computer program, wherein, when the computer program is executed, it controls the device where the storage medium is located to execute the FPGA integrated circuit layout optimization method according to any one of the present invention.

[0252] The storage medium is a computer-readable storage medium. The computer program includes computer program code, which may be in the form of source code, object code, executable file, or some intermediate form. The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording media, USB flash drive, portable hard drive, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the content included in the computer-readable medium may be appropriately added to or subtracted according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media may not include electrical carrier signals and telecommunication signals.

[0253] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. A method for optimizing the layout of FPGA integrated circuits, characterized in that, The method comprises: performing a short logical connection line selection operation: selecting a short logical connection line with the lowest Slack value from a short logical connection line set as a selected short logical connection line; wherein the short logical connection line is a logical connection line with a length less than a preset value; and the short logical connection line set is a set of short logical connection lines in the FPGA integrated circuit at the initial time; performing a first moving operation, and after the first moving operation is performed, removing the current selected short logical connection line from the short logical connection line set and re-executing the short logical connection line selection operation; wherein the first moving operation comprises: moving a first load device from a first original cell block to a first adjacent cell block, and after each movement, determining whether a first preset condition and a second preset condition are met simultaneously, and when it is determined that the first preset condition and the second preset condition are met simultaneously, stopping the movement of the first load device; the first load device is a load device corresponding to the selected short logical connection line; the first preset condition is that the first load device is located within a preset direct connection range of a first driver device; the second preset condition is that a competitive price of the first load device at the current cell block is greater than a competitive price of the first load device at the first original cell block; the first original cell block is a cell block where the first load device is located at the initial time; the first adjacent cell block is a cell block adjacent to the first original cell block; the first driver device is a driver device corresponding to the selected short logical connection line; the competitive price of the first load device is calculated according to the timing criticality of each short logical connection line corresponding to the first load device and the direct connection line resource richness.

2. The FPGA integrated circuit layout optimization method of claim 1, wherein, The first moving operation further comprises: when it is determined that the first load device does not meet the first preset condition after the movement, determining whether the first load device has traversed all the first adjacent cell blocks, if the first load device has not traversed all the first adjacent cell blocks, continuing to move the first load device to the remaining first adjacent cell blocks, if the first load device has traversed all the first adjacent cell blocks, moving the first driver device from a second original cell block to a second adjacent cell block, and after each movement of the first driver device, determining whether a third preset condition and a fourth preset condition are met, and when it is determined that the third preset condition and the fourth preset condition are met simultaneously, stopping the movement of the first driver device; when it is determined that the first load device meets the first preset condition after each movement of the first load device but does not meet the second preset condition, the first load device is restored to the position before the movement, and it is determined whether the first load device has traversed all the first adjacent unit blocks; if the first load device has not traversed all the first adjacent unit blocks, the first load device is continuously moved to the remaining first adjacent unit blocks; if the first load device has traversed all the first adjacent unit blocks, the first driver is moved from the second original unit block to the second adjacent unit block, and after each movement of the first driver, it is determined whether the third preset condition and the fourth preset condition are met, and when it is determined that the third preset condition and the fourth preset condition are met, the movement of the first driver is stopped; The second original unit block is the unit block where the first driver is located at the initial time. The second adjacent unit block is a unit block adjacent to the second original unit block. The third preset condition is that the first driver is located within a preset direct connection range of the first load device. The fourth preset condition is that the first driver has a higher competitive price in the current unit block than in the second original unit block. The competitive price of the first driver is calculated according to the timing criticality of each short logical connection line corresponding to the first driver and the direct connection line resource richness.

3. The FPGA integrated circuit layout optimization method of claim 2, wherein, The first movement operation further includes: When it is determined that the first driver does not meet the third preset condition after each movement of the first driver, it is determined whether the first driver has traversed all the second adjacent unit blocks; if the first driver has not traversed all the second adjacent unit blocks, the first driver is continuously moved to the remaining second adjacent unit blocks; if the first driver has traversed all the second adjacent unit blocks, the movement of the first driver is stopped. When it is determined that the first driver meets the third preset condition after each movement of the first driver but does not meet the second preset condition, the first load device is restored to the position before the movement, and it is determined whether the first driver has traversed all the second adjacent unit blocks; if the first driver has not traversed all the second adjacent unit blocks, the first driver is continuously moved to the remaining second adjacent unit blocks; if the first driver has traversed all the second adjacent unit blocks, the movement of the first driver is stopped.

4. The FPGA integrated circuit layout optimization method of claim 3, wherein, After all the first movement operations corresponding to the short logical connection lines are performed, the following operations are further included: performing a second short logical connection line selection operation: selecting a short logical connection line with the lowest Slack value from a second short logical connection line set as a second selected short logical connection line; the second short logical connection line set is a set of short logical connection lines in the FPGA integrated circuit after all the first movement operations corresponding to the short logical connection lines are performed; performing a second movement operation, and after the second movement operation is performed, the current second selected short logical connection line is removed from the second short logical connection line set, and the second short logical connection line selection operation is re-performed; The second moving operation comprises: performing a pin exchange operation: when it is determined that the second load pin and the second drive pin can be directly connected without internal switching, ending the pin exchange operation; when it is determined that the second load pin and the second drive pin cannot be directly connected without internal switching, determining whether there is a pin in the second load device that has not been exchanged in pin position with the second load pin; if there is no pin in the second load device that has not been exchanged in pin position with the second load pin, ending the pin exchange operation; if it is determined that there is a pin in the second load device that has not been exchanged in pin position with the second load pin, exchanging the second load pin with the remaining pins in the second load device one by one, and after each exchange, determining whether a fifth preset condition is met; if the fifth preset condition is met, updating the connection value of the second unit block, and re-determining whether the second load pin and the second drive pin can be directly connected without internal switching; if the fifth preset condition is not met, re-determining whether there is a pin in the second load device that has not been exchanged in pin position with the second load pin; wherein the second load pin is a load pin corresponding to a second selected short logic connection; the second drive pin is a drive pin corresponding to the second selected short logic connection; the second load device is a load device in which the second load pin is located; and the second unit block is a unit block in which the second load device is currently located; the fifth preset condition is that, after the pin position exchange, the connection value of the second unit block is less than the connection value before the pin position exchange; the connection value of the second unit block is calculated according to the number of internal connection switches of each short logic connection line corresponding to the second unit block and the load timing criticality.

5. The FPGA integrated circuit layout optimization method of claim 4, wherein, The second moving operation further comprises: after the pin exchange operation is performed, determining whether the second load pin and the second drive pin can be directly connected without internal switching, and if so, ending the second moving operation; if not, performing a device position exchange operation; The device position exchange operation comprises: when it is determined that there is a device in the second unit block that has not been exchanged in device position with the second load device, exchanging the second load device with the remaining devices in the second unit block one by one, and after each device position exchange, determining whether a sixth preset condition is met; if the sixth preset condition is met, updating the connection value of the second unit block, and determining whether the second load pin and the second drive pin can be directly connected without internal switching, and then when it is determined that the second load pin and the second drive pin can be directly connected without internal switching, ending the device position exchange operation; when it is determined that the second load pin and the second drive pin cannot be directly connected without internal switching, performing the pin exchange operation; if the sixth preset condition is not met, performing the pin exchange operation; wherein the sixth preset condition is that, after the second load device position exchange, the connection value of the second unit block is less than the connection value before the position exchange.

6. The FPGA integrated circuit layout optimization method of claim 5, wherein, The device position exchange operation further comprises: determining whether there is a device in the second unit block that has not been exchanged in device position with the second driving device; if there is no device in the second unit block that has not been exchanged in device position with the second driving device, ending the device position exchange operation if there is a device in the second unit block that has not been exchanged in device position with the second driving device, exchanging the second driving device with the remaining devices in the second unit block one by one, and after each exchange of device position, determining whether a seventh preset condition is met; if the seventh preset condition is met, updating the connection value of the second unit block, and determining whether the second load pin and the second driving pin can be directly connected without internal switching, and then, when it is determined that the second load pin and the second driving pin can be directly connected without internal switching, ending the device position exchange operation, and when it is determined that the second load pin and the second driving pin cannot be directly connected without internal switching, re-determining whether there is a device in the second unit block that has not been exchanged in device position with the second load device; if the seventh preset condition is not met, re-determining whether there is a device in the second unit block that has not been exchanged in device position with the second load device; wherein the second driving device is a device in which the second driving pin is located; the seventh preset condition is that, after the second driving device position exchange, the connection value of the second unit block is less than the connection value before the position exchange.

7. The FPGA integrated circuit layout optimization method of claim 6, wherein, The device position exchange operation further comprises: determining whether there is a device in the second unit block that has not been exchanged in device position with the second driving device, and ending the device position exchange operation.

8. An FPGA integrated circuit layout optimization apparatus, characterized by, It includes a short logical connection line selection module and a moving operation module. The short logical connection line selection module is configured to perform a short logical connection line selection operation: selecting a short logical connection line with the lowest Slack value from a short logical connection line set as a selected short logical connection line; wherein the short logical connection line is a logical connection line with a length less than a preset value; and the short logical connection line set is a set of short logical connection lines in the FPGA integrated circuit at the initial time. The moving operation module is configured to perform a first moving operation, and after performing the first moving operation, remove the current selected short logical connection line from the short logical connection line set and re-perform the short logical connection line selection operation. The first moving operation includes moving the first load device from a first original unit block to a first adjacent unit block, and after each movement, determining whether a first preset condition and a second preset condition are met simultaneously, and when it is determined that the first preset condition and the second preset condition are met simultaneously, stopping the movement of the first load device. The first load device is a load device corresponding to the selected short logical connection line. The first preset condition is that the first load device is located within a preset direct connection range of the first driving device. The second preset condition is that the competitive price of the first load device in the current unit block is greater than the competitive price of the first load device in the first original unit block. The first driving device is a driving device corresponding to a selected short logical connection line; The first original unit block is a unit block where the first load device is located initially; the first adjacent unit block is a unit block adjacent to the first original unit block; and the competitive price of the first load device is calculated according to the timing criticality of each short logical connection line corresponding to the first load device and the direct connection line resource richness.

9. A terminal device, comprising: The memory and a computer program stored in the memory and configured to be executed by the processor, the processor implements the FPGA integrated circuit layout optimization method as claimed in any one of claims 1 to 7 when executing the computer program.

10. A storage medium, characterized by The storage medium includes a stored computer program, wherein the storage medium controls the device where the storage medium is located to execute the FPGA integrated circuit layout optimization method as claimed in any one of claims 1 to 7 when the computer program is running.

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