Display driver

Abstract

This disclosure provides a display driver for driving a display device including a pixel array. The display driver includes a plurality of drive channels. The drive channels are configured to output drive signals in a pulse-width modulation (PWM) manner to drive the pixel array to emit light in a first frame period, the first frame period being divided into a plurality of subframe periods. A first drive channel of the plurality of drive channels outputs a first drive signal in a combination of the first subframe periods. A second drive channel of the plurality of drive channels outputs a second drive signal in a second combination of subframe periods different from the first subframe period combination. Each of the first subframe period combination and the second subframe period combination includes at least one subframe period of the first frame period. The display driver of this disclosure provides effective display driving functionality.

Description

[0001] This application claims priority to U.S. Provisional Application No. 63 / 178,540, filed April 23, 2021. The entire contents of the aforementioned patent application are hereby incorporated in this application for reference and form part of this specification. Technical Field

[0002] This disclosure generally relates to a display driver, and more specifically, to a display driver that outputs a drive signal in a pulse width modulation manner. Background Technology

[0003] Traditional display drivers for driving light-emitting diode (LED) display devices drive each pixel in the pixel array of the display panel by outputting a drive signal corresponding to the pixel data (grayscale value) as a constant current pulse width modulation (PWM) signal to each pixel in the pixel array during each frame cycle. The pulse width of the drive signal controls the length of time each pixel remains illuminated. In this case, a drive signal with short pulses results in pixels that are briefly bright but long periods of darkness within a frame cycle. This flickering problem is particularly noticeable with low pixel data. However, the traditional solution simply divides the frame cycle into subframe cycles and allows the display driver to drive the entire pixel array to emit light uniformly within these subframe cycles. This traditional solution still exhibits significant screen flickering even with extremely low pixel data. Summary of the Invention

[0004] This disclosure relates to a display driver capable of providing effective display driving functionality.

[0005] A display driver according to an embodiment of this disclosure for driving a display device including a pixel array includes a plurality of driving channels. The plurality of driving channels are configured to output driving signals in a pulse-width modulation (PWM) manner to drive the pixel array to emit light in a first frame period, the first frame period being divided into a plurality of subframe periods. A first driving channel of the plurality of driving channels outputs a first driving signal in a combination of the first subframe periods. A second driving channel of the plurality of driving channels outputs a second driving signal in a second combination of subframe periods different from the first combination of subframe periods. Each of the first combination of subframe periods and the second combination of subframe periods includes at least one subframe period of the first frame period.

[0006] A display driver according to an embodiment of this disclosure for driving a display device including a pixel array includes a plurality of driving channels. The plurality of driving channels are configured to output driving signals in a pulse-width modulation (PWM) manner to drive the pixel array to emit light in a first frame period, the first frame period being divided into a plurality of subframe periods. Each of the plurality of subframe periods is divided into a plurality of scan line periods. A first driving channel of the plurality of driving channels outputs driving signals to the pixels in a first scan line period combination of the first subframe period of the first frame period. The first driving channel outputs driving signals in a second scan line period combination of the second subframe period of the first frame period. The number of scan line periods in the first scan line period combination or the second scan line period combination is less than the number of the plurality of scan line periods. Each of the first scan line period combination and the second scan line period combination includes at least one scan line period.

[0007] Based on the above, the display driver according to this disclosure can effectively drive the display device to reduce flickering.

[0008] To make the above content easier to understand, several embodiments accompanying the drawings will be described in detail below. Attached Figure Description

[0009] The accompanying drawings are included to provide a further understanding of this disclosure, and are incorporated in and form a part of this specification. The drawings illustrate exemplary embodiments of this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0010] Figure 1 This is a schematic diagram of a display device according to an embodiment of the present disclosure;

[0011] Figure 2 This is a schematic diagram illustrating the driving of the pixel array of a display device in multiple sub-frame periods of the Nth frame period according to an embodiment of the present disclosure.

[0012] Figure 3 This is a schematic diagram illustrating the driving of a pixel array of a display device in multiple subframe periods of the Nth frame period according to another embodiment of the present disclosure.

[0013] Figure 4 This is a schematic diagram illustrating the driving of the pixel array of a display device in multiple subframe periods of the (N+1)th frame period according to an embodiment of the present disclosure.

[0014] Figure 5 This is a schematic diagram illustrating the driving of a pixel array of a display device in multiple subframe periods of the Nth frame period according to another embodiment of the present disclosure.

[0015] Figure 6This is a schematic diagram illustrating the driving of a pixel array of a display device in multiple subframe periods of the Nth frame period according to another embodiment of the present disclosure.

[0016] Figure 7 This is a schematic diagram illustrating the driving of a pixel array of a display device in multiple subframe periods of the Nth frame period according to another embodiment of the present disclosure.

[0017] Figure 8 This is a schematic diagram illustrating the driving of a pixel array of a display device in multiple subframe periods of the Nth frame period according to another embodiment of the present disclosure.

[0018] Figure 9 This is a schematic diagram illustrating the driving of a pixel array of a display device in multiple subframe periods of the Nth frame period according to another embodiment of the present disclosure.

[0019] [Explanation of Symbols]

[0020] 10: Display devices;

[0021] 100: Display driver;

[0022] 110: Control circuit;

[0023] 120: Data drive circuit;

[0024] 121_1, 121_2, 121_3, 121_4~121_P: Drive channels;

[0025] 130: Switching circuit;

[0026] 131, 131_1, 131_2, 131_3, 131_4~131_Q: Switching channels;

[0027] 200: Pixel array;

[0028] 201~901: Frame period;

[0029] 201_1~201_P: Data cable;

[0030] 202_1, 202_2, 202_3, 202_4~202_Q: Scan lines;

[0031] 210_1~210_M: pixels;

[0032] SL1~SL4: Scan line period;

[0033] P(1,1), P(1,2), P(1,3), P(1,4), P(2,1), P(2,2), P(2,3), P(2,4), P(3,1), P(3,2), P(3,3), P(3,4), P(4,1), P(4,2), P(4,3), P(4,4): pixels. Detailed Implementation

[0034] Throughout this application's specification (including the claims), the term "coupled (or connected)" is used extensively and encompasses both direct and indirect connections or coupling methods. For example, if this disclosure describes a first device being coupled (or connected) to a second device, it should be interpreted as the first device being directly connected to the second device, or the first device being indirectly connected to the second device via other devices or through a specific coupling method. Furthermore, terms such as "first" and "second" used throughout this application's specification (including the claims) are used only to name elements or distinguish different embodiments or scopes, and are not intended to limit the upper or lower limit of the number of elements, nor are they intended to limit the order of elements. Additionally, in the drawings and embodiments, elements / components / steps with the same reference numerals represent the same or similar parts. Elements / components / symbols with the same reference numerals in different embodiments can be referred to the relevant descriptions.

[0035] Figure 1 This is a schematic diagram of a display device according to an embodiment of the present disclosure. (Refer to...) Figure 1The display device 10 includes a display driver 100 and a pixel array 200. The pixel array 200 includes a plurality of pixels 210_1 to 210_M, where M is a positive integer. In embodiments of this disclosure, the display device 10 may be a light-emitting diode (LED) display device, a micro LED display device, or a mini LED display device. Each of the pixels 210_1 to 210_M may be an LED, a micro LED, or a mini LED. The display driver 100 is configured to drive the pixel array 200 of the display device 10 to perform a display function. In embodiments of this disclosure, the display driver 100 includes a control circuit 110, a data driving circuit 120, and a switching circuit 130. The control circuit 110 is coupled to the data driving circuit 120 and the switching circuit 130. The data driving circuit 120 includes a plurality of driving channels 121_1 to 121_P, where P is a positive integer. Drive channels 121_1 to 121_P are coupled to multiple columns of pixel array 200 via multiple data lines 201_1 to 201_P. Data drive circuit 120 can function as a constant current driver, and each of drive channels 121_1 to 121_P can output a drive signal using pulse width modulation (PWM) with a constant current. Switching circuit 130 includes multiple switch units and multiple switch channels 131_1 to 131_Q, where Q is a positive integer. Switch channels 131_1 to 131_Q are coupled to multiple rows of pixel array 200 via multiple scan lines 202_1 to 202_Q. A switch unit can be a plurality of switching transistors respectively coupled to switch channels 131_1 to 131_Q, and is used to determine whether switch channels 131_1 to 131_Q are connected to ground, so that the corresponding pixels operate in the drive state.

[0036] In embodiments of this disclosure, control circuit 110 is configured to control data driving circuit 120 to output driving signals in a PWM manner to drive pixel array 200, and to provide multiple switching signals to control the switching units of switching circuit 130. For example, if switching channel 131_1 is connected to ground by a corresponding switching signal through a corresponding switching unit, then when pixel 210_1 receives a driving signal from driving channel 121_1, pixel 210_1 can be driven to emit light. Otherwise, if switching channel 131_1 is open due to the corresponding switching unit being cut off, then pixel 210_1 (pixel row) controlled by switching channel 131_1 is open. Driving channel 121_1 can output driving signals in a PWM manner to drive pixel 210_1 to emit light in a frame period divided into multiple subframe periods. The total pulse width of the driving signals in the frame period is equal to the duration for which pixel 210_1 is lit, the duration being determined by the grayscale data of pixel 210_1 to be displayed. Furthermore, the pulse width of the drive signal during the frame period can be divided into multiple sub-pulse widths to correspond to different sub-frame periods.

[0037] In embodiments of this disclosure, the display driver 100 can divide the pulse width of the drive signal generated based on pixel data into multiple sub-pulse widths, and output drive signals of sub-pulse widths in some sub-frame cycles within a frame cycle, thereby driving pixels in different sub-frame cycles, effectively reducing the duration of the non-light-emitting time interval between different frames. Furthermore, the display driver 100 can also drive different pixels of the pixel array 200 according to different sub-frame cycle combinations in different sub-frame cycles of a frame cycle (as if emitting light within the pixels of the pixel array 200 while spatially alternating), thereby effectively reducing flicker.

[0038] Figure 2 This is a schematic diagram illustrating the driving of a pixel array of a display device in multiple subframe periods within a frame period according to an embodiment of the present disclosure, where N is a positive integer. In the figures of this disclosure, a frame period is represented as a short frame and a subframe period is represented as a short subframe. Each subframe period includes multiple scan line periods, and each pixel row can be driven in the corresponding scan line period. (Refer to...) Figure 1 and Figure 2 Taking 16 pixels in pixel array 200 as an example, pixels P(1,1) to P(4,4) are 4*4 pixel arrays defined by the first column to the fourth column and the first row to the fourth row of pixels in pixel array 200. The first row to the fourth row of pixels can be driven in different scan line periods represented by SL1 to SL4, where the different scan line periods are... Figure 2 The pixels are shown in the diagram and omitted in other figures. In embodiments of this disclosure, the display driver 100 can drive pixels P(1,1) to P(4,4) in the Nth frame period 201 (frame period N). The drive channels 121_1 to 121_4 of the data drive circuit 120 can output drive signals in a pulse width modulation manner to drive pixels P(1,1) to P(4,4) to emit light in the Nth frame period 201, which is divided into, for example, 32 subframe periods, but this disclosure is not limited thereto. Most examples in this disclosure are based on the assumption that each frame period is divided into 32 subframe periods. Figure 2 In the figures below, regardless of whether the pulse width of the driving signal distributed within the corresponding scan line period is the full pulse width or a partial pulse width, pixels marked with a dot pattern represent pixels that are allowed to emit light (provided the corresponding grayscale value is not zero), and are driven by the driving signal of the corresponding scan line period of the subframe period. In fact, whether a pixel emits light is determined by its grayscale value (pixel data). For example... Figure 2 As shown, subframe period A can correspond to the first subframe period of the 32 subframe periods of the Nth frame period 201 (or one of the first to eighth subframe periods among the 32 subframe periods). Subframe period B can correspond to the ninth subframe period (or one of the ninth to sixteenth subframe periods that are eight subframe periods away from subframe period A). Subframe period C can correspond to the seventeenth subframe period (or one of the seventeenth to twenty-fourth subframe periods that are eight subframe periods away from subframe period B). Subframe period D can correspond to the twenty-fifth subframe period (or one of the twenty-fifth to thirty-second subframe periods that are eight subframe periods away from subframe period C).

[0039] In embodiments of this disclosure, at least two driving channels are driven in different subframe period combinations. One or more of the 32 subframe periods can be selected to form subframe period combinations. Figure 2 In this embodiment, each of driving channels 121_1 and 121_3 (odd-numbered driving channels) can output a driving signal in a first subframe period combination, which may consist of only one subframe period, such as subframe period A (first subframe period), and its pixel driving result (pixel illumination result) can be displayed in subframe period A. Furthermore, each of driving channels 121_2 and 121_4 (even-numbered driving channels) can output a driving signal in a second subframe period combination, which may consist of only one subframe period, such as subframe period C (seventeenth subframe period), and its pixel driving result can be displayed in subframe period C. In this disclosure… Figure 2In the embodiment, each of the driving channels 121_1 and 121_3 (a plurality of odd-numbered driving channels) can output a driving signal in each scan line period (or horizontal line period) of the first subframe period (subframe period A) of the first subframe period combination, and each of the driving channels 121_2 and 121_4 (a plurality of even-numbered driving channels) can output a driving signal in each scan line period of the seventeenth subframe period (subframe period C) of the second subframe period combination.

[0040] In other words, for pixels P(1,1), P(2,1), P(3,1), P(4,1), P(1,3), P(2,3), P(3,3), and P(4,3), the driver responsible for driving the pixel rows including pixels P(1,1), P(2,1), P(3,1), and P(4,1) and the pixel rows including pixels P(1,3), P(2,3), P(3,3), and P(4,3) in frame period 201 is... The driving channel 121_1 and the driving channel 121_3 output driving signals to pixels P(1,1), P(2,1), P(3,1), P(4,1), P(1,3), P(2,3), P(3,3) and P(4,3) in a first subframe period combination consisting of only one subframe period (subframe period A). Therefore, in terms of subframe period, the first subframe period combination is assigned to the driving channel 121_1 and the driving channel 121_3 for use. For pixels P(1,2), P(2,2), P(3,2), P(4,2), P(1,4), P(2,4), P(3,4), and P(4,4), the driving channel is responsible for driving the pixel rows including pixels P(1,2), P(2,2), P(3,2), and P(4,2) and the pixel rows including pixels P(1,4), P(2,4), P(3,4), and P(4,4) in frame period 201. Drive channels 121_2 and 121_4 output drive signals to pixels P(1,2), P(2,2), P(3,2), P(4,2), P(1,4), P(2,4), P(3,4), and P(4,4) in a second subframe period combination consisting of only one subframe period (subframe period C). Therefore, in terms of subframe period, the second subframe period combination is assigned to drive channels 121_2 and 121_4 for use.

[0041] Therefore, pixels P(1,1), P(2,1), P(3,1), P(4,1), P(1,3), P(2,3), P(3,3), and P(4,3) can be driven to emit light in the first subframe cycle, or more precisely, can be driven by a driving signal, and pixels P(1,2), P(2,2), P(3,2), P(4,2), P(1,4), P(2,4), P(3,4), and P(4,4) can be turned on to emit light in the seventeenth subframe cycle. That is, the display driver 100 can drive the pixel array 200 during consecutive frame cycles, and the driving result of each frame cycle can be similar to that of the Nth frame cycle 201. Therefore, the display refresh rate of the pixel array 200 can be doubled compared to displaying an image during each entire frame cycle, thereby effectively reducing image flicker.

[0042] Figure 2 This is based on the assumption that the pixel data of each pixel can be a sufficiently low grayscale value so that the corresponding driving signal with the full pulse width can be completely output to drive the pixel within one subframe period, without having to divide the pulse width of the driving signal into several partial pulse widths. However, as long as the grayscale value of a pixel does not correspond to an undivisible pulse width, such as a grayscale value of "1" between 0 and 65535, the corresponding driving signal pulse width can be divided and output separately in at least two subframe periods, and in... Figure 3 This explains the situation.

[0043] Figure 3 This is a schematic diagram illustrating the driving of a pixel array of a display device during multiple subframe periods of the Nth frame period according to another embodiment of this disclosure. (Refer to...) Figure 1 and Figure 3 ,and Figure 2 Unlike the illustrated embodiment, the first combination of subframe periods selected from the subframe periods of frame period 301 may include two subframe periods (the first and the seventeenth subframe periods), and the second combination of subframe periods selected from the subframe periods of frame period 301 may include two subframe periods (the ninth and the twenty-fifth subframe periods), which differs from the first combination of subframe periods. In another embodiment, the number of subframe periods in the combination of subframe periods is not limited to two, but may be more than two. Figure 3In the embodiments, each of driving channels 121_1 and 121_3 (odd-numbered driving channels) can output a driving signal to the pixel in a first subframe period combination including subframe periods A and C, and its pixel driving result can be displayed at least in at least one of subframe periods A and C; and each of driving channels 121_2 and 121_4 (even-numbered driving channels) can output a driving signal to the pixel in a second subframe period combination including subframe periods B and D, and its pixel driving result can be displayed at least in at least one of subframe periods B and D. In this disclosure... Figure 3 In the embodiment, each of the driving channels 121_1 and 121_3 can output driving signals in at least one subframe period of the first subframe period combination, and driving channels 121_2 and 121_4 can output driving signals in at least one subframe period of the second subframe period combination.

[0044] It should be noted that the entire pulse width of each of the above-mentioned driving signals is divided into partial pulse widths, for example, two or more partial pulse widths are output in two or more subframe cycles of the corresponding subframe cycle combination. In the embodiments of this disclosure, the two or more subframe cycles of each subframe cycle combination may be alternately distributed in frame cycle 301. Therefore, by reducing the non-lit interval between two subframe cycles in which some pixels of the pixel array are allowed to be lit (where the pixels of the pixel array are not lit), the display refresh rate of the pixel array 200 can be increased, thereby effectively reducing flickering.

[0045] In another embodiment of this disclosure, driving channels 121_1 and 121_3, which are responsible for outputting driving signals to pixels P(1,1), P(2,1), P(3,1), P(4,1), P(1,3), P(2,3), P(3,3), and P(4,3), respectively, can output driving signals in the first subframe period combination in response to the control circuit 110 determining that the pixel data of pixels P(1,1), P(2,1), P(3,1), P(4,1), P(1,3), P(2,3), P(3,3), and P(4,3) are lower than a predetermined gray value. The driving signals can be associated with non-zero gray values. Drive channels 121_2 and 121_4, which are responsible for outputting drive signals to pixels P(1,2), P(2,2), P(3,2), P(4,2), P(1,4), P(2,4), P(3,4), and P(4,4), respectively, can output drive signals in response to the control circuit 110 determining that the pixel data of pixels P(1,2), P(2,2), P(3,2), P(4,2), P(1,4), P(2,4), P(3,4), and P(4,4) are lower than a predetermined grayscale value, and can output drive signals in the second subframe period combination.

[0046] Figure 4 This is a schematic diagram illustrating the driving of the pixel array of a display device in multiple sub-frame periods during the (N+1)th frame period according to an embodiment of the present disclosure. (Refer to...) Figure 1 , Figure 3 and Figure 4 In the continuation Figure 3 In the (N+1)th frame period of frame period 301, control circuit 110 can change the arrangement of the first subframe period combination and the second subframe period combination. In the embodiments of this disclosure, driving channels 121_1 and 121_3, which are responsible for driving pixels P(1,1), P(2,1), P(3,1), P(4,1), P(1,3), P(2,3), P(3,3), and P(4,3), are in the first subframe period of the first subframe period combination of frame period 301. During the seventeenth subframe period, driving signals can be output to pixels P(1,1), P(2,1), P(3,1), P(4,1), P(1,3), P(2,3), P(3,3) and P(4,3). During the ninth and twenty-fifth subframe periods of the second subframe period combination of frame period 401, another driving signal can be output to pixels P(1,1), P(2,1), P(3,1), P(4,1), P(1,3), P(2,3), P(3,3) and P(4,3).

[0047] Furthermore, for pixels P(1,2), P(2,2), P(3,2), P(4,2), P(1,4), P(2,4), P(3,4), and P(4,4), the ninth and twentieth sub-frame periods of the first sub-frame period combination of the frame period 301 of driving channels 121_2 and 121_4, which are responsible for driving pixels P(1,2), P(2,2), P(3,2), P(4,2), P(1,4), P(2,4), P(3,4), and P(4,4), are also included. During the five-frame period, a driving signal can be output to pixels P(1,2), P(2,2), P(3,2), P(4,2), P(1,4), P(2,4), P(3,4), and P(4,4). In the first and seventeenth subframe periods of the second subframe period combination of the frame period of frame period 401, another driving signal can be output to pixels P(1,2), P(2,2), P(3,2), P(4,2), P(1,4), P(2,4), P(3,4), and P(4,4).

[0048] In other words, at least one driving channel can drive the corresponding pixel column of the pixel array 200 by using different subframe period combinations in subsequent frames. In other words, at least one driving channel can drive the pixels of the corresponding pixel column in the array 200 by not always using the same subframe period combination in consecutive frame periods. Thus, the driving result for every two adjacent frame periods can be similar to frame periods 301 and 401. Therefore, by using different subframe period combinations in different frame periods, the display refresh rate of the pixel array 200 can be improved, and flickering can be eliminated.

[0049] As mentioned earlier, a pixel cannot be segmented if its grayscale value does not correspond to a pulse width. For example, a grayscale value "1" is between 0 and 65535, and the corresponding pulse width is the driving signal, which can be segmented into outputs over at least two subframe periods. Even if the grayscale value is determined to be sufficiently low, the control circuit 110 can still determine whether the driving channel outputs a driving signal corresponding to a grayscale value that corresponds to a continuous full pulse width or several partial pulse widths. Figure 5 This is a schematic diagram illustrating the driving of a pixel array of a display device during multiple sub-frame periods of the Nth frame period according to another embodiment of this disclosure. Figure 5 As shown, the control circuit 110 determines that the pixel data of pixels P(1,3) and P(2,4) are ultra-low grayscale values, and there is no need (or no way) to divide the pulse width of the driving signals corresponding to pixels P(1,3) and P(2,4), so that the driving channel drives pixels P(1,3) only in one subframe period of frame period 501, and drives pixels P(2,4) only in one subframe period of frame period 501.

[0050] Figure 6 This is a schematic diagram illustrating the driving of a pixel array of a display device during multiple subframe periods of the Nth frame period according to another embodiment of this disclosure. (Refer to...) Figure 1 and Figure 6 ,and Figure 3 Unlike the illustrated embodiment, control circuit 110 may further control switching circuit 130 and data driving circuit 120 to drive only a portion of the pixel row in each subframe period of each subframe period combination. In embodiments of this disclosure, such as... Figure 6As shown in frame period 401, control circuit 110 can control drive channels 121_1 and 121_3 of data drive circuit 120 to output corresponding drive signals in the odd-numbered scan line periods of the first subframe period (subframe period A) of the first subframe period combination, and to output corresponding drive signals in the even-numbered scan line periods of the seventeenth subframe period (subframe period C) of the first subframe period combination. Control circuit 110 can control drive channels 121_2 and 121_4 of data drive circuit 120 to output corresponding drive signals in the odd-numbered (or even-numbered) scan line periods of the ninth subframe period (subframe period B) of the second subframe period, and to output corresponding drive signals in the even-numbered (or odd-numbered) scan line periods of the twenty-fifth subframe period (subframe period D) of the second subframe period combination. In addition, drive channels 121_2 and 121_4 do not output drive signals in each subframe period (subframe periods A and C) of the first subframe period combination, and drive channels 121_1 and 121_3 do not output drive signals in each subframe period (subframe periods B and D) of the second subframe period combination.

[0051] Figure 7 This is a schematic diagram illustrating the driving of a pixel array of a display device during multiple subframe periods of the Nth frame period according to another embodiment of this disclosure. (Refer to...) Figure 1 and Figure 7 ,and Figure 2Unlike the embodiments shown, each subframe period can be further divided into multiple scan line periods. Each scan line period is the period in which it performs the corresponding scan line. In the embodiments of this disclosure, different groups of pixel rows of the pixel array are driven in different scan line periods. The scan line period combination includes temporally discontinuous scan line periods, and the number of scan line periods in any scan line period combination is less than the number of multiple scan line periods in the subframe period. In the embodiments of this disclosure, the driving channels 121_1 to 121_4 (all driving channels), which are responsible for driving all pixels in each adjacent column, can output driving signals in the first scan line period combination (e.g., odd scan line periods) of the first subframe period (subframe period A), and the driving channels 121_2 to 121_4 (all driving channels) can output driving signals in the second scan line period combination (e.g., even scan line periods) of the seventeenth subframe period (subframe period C). Therefore, pixels P(1,1), P(1,2), P(1,3), P(1,4), P(3,1), P(3,2), P(3,3), and P(3,4) can be turned on to emit light in the first subframe period (subframe period A), and pixels P(2,1), P(2,2), P(2,3), P(2,4), P(4,1), P(4,2), P(4,3), and P(4,4) can be turned on to emit light in the seventeenth subframe period (subframe period C). According to this embodiment, the non-illumination interval (where no pixels in the pixel array are lit) between two subframe periods (e.g., subframe periods A and C) in which different groups of pixel rows of the pixel array are lit can also improve the display refresh rate of the pixel array 200, thereby effectively reducing flicker.

[0052] Figure 8 This is a schematic diagram illustrating the driving of a pixel array of a display device during multiple subframe periods of the Nth frame period according to another embodiment of this disclosure. (Refer to...) Figure 1 and Figure 8 ,and Figure 7The embodiments shown differ, with each adjacent driving channel outputting driving signals in different scan line cycle combinations. In the embodiments of this disclosure, driving channels 121_1 and 121_3, responsible for driving the first pixel column and the third pixel column, can output driving signals in the first scan line cycle combination (e.g., odd scan line cycles) of the subframe cycle A of the frame period of frame period 801. Driving channels 121_2 and 121_4, responsible for driving the second pixel column adjacent to the first pixel column and the fourth pixel column adjacent to the third pixel column, do not output driving signals in the first scan line cycle combination of the subframe cycle A of frame period 801. Driving channels 121_2 and 121_4 can output driving signals in the second scan line cycle combination (e.g., even scan line cycles) of the subframe cycle A of frame period 801, while driving channels 121_1 and 121_3 do not output driving signals in the second scan line cycle combination of the subframe cycle A of frame period 801.

[0053] Furthermore, drive channels 121_2 and 121_4 can output drive signals in the third scan line cycle combination of subframe period C of frame period 801, while drive channels 121_1 and 121_3 can not output drive signals in the third scan line cycle combination of subframe period C of frame period 801. Figure 3 In the example, the third scan line cycle combination includes an odd number of scan line cycles, the same as the first scan line cycle combination. Drive channels 121_2 and 121_4 can output drive signals in the fourth scan line cycle combination of subframe period C of frame period 801, and drive channels 121_2 and 121_4 can also not output drive signals in the fourth scan line cycle combination of subframe period C of frame period 801. Figure 3 In the example, the fourth scan line cycle combination includes an even number of scan line cycles, the same as the second scan line cycle combination. Therefore, by reducing the non-illuminating interval between two subframe cycles of some pixels (e.g., a chessboard) illuminating in the pixel array, the display refresh rate of the pixel array 200 can be increased, thereby effectively reducing flicker.

[0054] Figure 9 This is a schematic diagram illustrating the driving of a pixel array of a display device during multiple subframe periods of the Nth frame period according to another embodiment of this disclosure. (Refer to...) Figure 1 and Figure 9 ,and Figure 8The embodiments shown differ, with the driving channels outputting driving signals in different combinations of scan line cycles. In the embodiments of this disclosure, driving channels 121_1 to 201_4, responsible for driving the first to fourth pixel columns, output driving signals in the four different combinations of scan line cycles for each sub-frame cycle (sub-frame cycles A to D) of the frame period of the Nth frame period 901, and each driving channel outputs driving signals in the four different combinations of scan line cycles for sub-frame cycles A to D of the frame period of the frame period 901. Figure 9 The first scan line cycle combination, which allows drive channel 121_1 to output drive signals, includes (4n+1) scan line cycles, where n = 0, 1, 2, 3, ... The total number of scan line cycles depends on the total number of pixel rows on the display panel. The second scan line cycle combination, which allows drive channel 121_2 to output drive signals, includes (4n+4) scan line cycles, where n = 0, 1, 2, 3, ... The third scan line cycle combination, which allows drive channel 121_3 to output drive signals, includes (4n+3) scan line cycles, where n = 0, 1, 2, 3, ... And the fourth scan line cycle combination, which allows drive channel 121_4 to output drive signals, includes (4n+2) scan line cycles, where n = 0, 1, 2, 3, ... For any two drive channels driving adjacent pixel columns, since the scan line cycle combinations of these two drive channels are different, four subframe cycles separated by the same interval in the frame period can be used. Therefore, by reducing the non-lit interval between two subframe cycles in which some pixels of the pixel array are lit, the display refresh rate of the pixel array 200 can be increased, thereby effectively reducing flickering.

[0055] In summary, according to the display driver disclosed herein, the display driver can effectively drive the pixel array of the display device in different subframe cycles of each frame cycle according to different subframe cycle combinations or different scan line cycle combinations, thereby effectively reducing the duration of the non-emission time interval between two subframe cycles of a frame cycle. Therefore, image flicker of the display device can be effectively reduced.

[0056] It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of this disclosure. In view of the foregoing, this disclosure is intended to cover modifications and variations falling within the scope of the foregoing claims and their equivalents.

Claims

1. A display driver for driving a display device comprising a pixel array, characterized in that, include: Multiple driving channels output driving signals in a pulse width modulation manner to drive the pixel array to emit light in the first frame period. The first frame period is divided into multiple sub-frame periods, and the pulse width of the driving signal is the sum of the pulse widths of the multiple sub-pulse widths. The first driving channel of the plurality of driving channels outputs a portion of the pulse width of the first driving signal in each subframe period of the first subframe period combination in the first frame period. The second driving channel among the plurality of driving channels outputs a portion of the pulse width of the second driving signal in each subframe period of the second subframe period combination in the first frame period, and the first subframe period combination in the first frame period is different from the second subframe period combination in the first frame period. Each of the first subframe period combination and the second subframe period combination includes at least one subframe period of the first frame period. The first driving channel outputs a third driving signal to the pixel in at least one subframe period of the second subframe period combination of the second frame period adjacent to the first frame period. The second driving channel outputs a fourth driving signal to the pixel in the first subframe period combination of the second frame period adjacent to the first frame period. Each of the first driving channel and the second driving channel outputs a corresponding driving signal in each scan line period of each subframe period of the corresponding subframe period combination.

2. The display driver according to claim 1, characterized in that, For a pixel in the pixel array, the first driving channel responsible for driving the pixel in the first frame period outputs the first driving signal to the pixel in a combination of two or more sub-frame periods. The entire pulse width of the first driving signal is divided into local pulse widths that are output in two or more subframe periods of the first subframe period combination.

3. The display driver according to claim 2, characterized in that, The two or more subframe periods of the first subframe period combination are alternately distributed in the first frame period.

4. The display driver according to claim 1, characterized in that, The first driving channel outputs corresponding driving signals in some scan line periods of some subframe periods of the first subframe period combination, and outputs corresponding driving signals in other scan line periods of other subframe periods of the first subframe period combination.

5. The display driver according to claim 4, characterized in that, The second driving channel is responsible for driving the second pixel column adjacent to the first pixel column driven by the first driving channel, and the second driving channel does not output any pulse width or local pulse width of the second driving signal during the scan line period in which the first driving channel outputs the corresponding driving signal.

6. The display driver according to claim 1, characterized in that, It also includes control circuitry. Among the plurality of driving channels, the driving channel responsible for outputting the driving signal to the pixels of the pixel array outputs the driving signal in the corresponding subframe period combination in response to the control circuit determining that the pixel data of the pixel is lower than a predetermined grayscale value.

Images