A method for improving the single-particle gate punch-through resistance of trench-type MOSFET

Abstract

The present invention discloses a method for improving the single particle gate penetration resistance of a trench type MOSFET, and belongs to the field of semiconductor power devices. Based on the trench type radiation-resistant MOSFET process, the present invention uses polycrystalline oxidation at the bottom of the trench structure to achieve a thickened bottom oxide layer, and the thickness thereof is 0.0447 W / m2 by adding some process steps and modifying the processing sequence of some process flows without adding additional photolithography layers. Under the condition of limited increase in process difficulty and manufacturing cost, the single particle gate penetration resistance of the product can be effectively improved, and the product performance can be improved, so that it can be better applied to the space aerospace environment.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor power devices, and in particular to a method for improving the single particle gate punch-through resistance of a trench type MOSFET. Background Art

[0002] MOSFET is a new type of semiconductor power device. Compared with the performance of bipolar power devices, it has the advantages of low conduction loss, high operating frequency, voltage-controlled device, and simple control circuit. It is increasingly valued by the industry.

[0003] With the rapid development of space and nuclear physics technology, electronic equipment has higher and higher requirements for the radiation resistance performance of power MOSFET in its circuit system. In addition to meeting the conventional electrical parameter requirements, radiation-resistant power MOSFET devices must also have the ability to withstand various ionizing radiation, high-energy particles and cosmic rays in space for a long time. Therefore, the threshold voltage, drain breakdown voltage, gate breakdown voltage, etc. of power MOSFET devices are all affected by such ionizing radiation. Among them, the ability to resist the single event gate rupture (SEGR) is one of the key indicators of product radiation performance.

[0004] Compared with planar MOSFET, trench MOSFET has a higher channel density, which has a clear advantage over on-resistance for low-voltage products with a high channel resistance. Figure 1 The figure shows a schematic diagram of the cross-sectional structure of a primitive cell of an ordinary trench MOSFET device. For this type of trench MOSFET, the thickness of the bottom gate oxide layer is thinner than that of the side wall, the single-particle gate penetration resistance is weak, and the radiation performance also faces great challenges. Summary of the invention

[0005] The object of the present invention is to provide a method for improving the single particle gate punch-through resistance of a trench type MOSFET, so as to solve the problem that the radiation resistance of conventional low voltage trench type MOSFET products is relatively weak.

[0006] In order to solve the above technical problems, the present invention provides a method for improving the single particle gate punch-through resistance of trench type MOSFET, comprising:

[0007] An oxide layer is added at the bottom of the trench structure, and the thickness of the oxide layer is

[0008] In one embodiment, an oxide layer is added to the bottom of the trench structure by:

[0009] Growing a first silicon oxide layer on the epitaxial wafer, and implementing well implantation by ion implantation technology;

[0010] Depositing a first silicon nitride layer on the first silicon oxide layer on the surface, and digging out a trench structure;

[0011] By growing sacrificial oxide and stripping sacrificial oxide, the sidewall of the trench structure is repaired and the well is pushed to form a PN structure of the well and epitaxy.

[0012] sequentially growing a second silicon oxide layer and depositing a second silicon nitride layer in the trench structure, and etching away the second silicon nitride layer at the bottom of the trench structure;

[0013] Fill the trench structure with polycrystalline and etch;

[0014] Through furnace oxidation, all the polycrystalline at the bottom of the trench structure is oxidized;

[0015] The first silicon oxide layer, the first silicon nitride layer, the second silicon oxide layer, and the second silicon nitride layer are removed.

[0016] In one embodiment, the thickness of the first silicon oxide layer is The thickness of the first silicon nitride layer is The thickness of the second silicon oxide layer is The thickness of the second silicon nitride layer is

[0017] In one embodiment, etching the polycrystalline in the trench structure is divided into two steps: the first step is to etch the polycrystalline and stop at the first silicon oxide layer; the second step is to etch the polycrystalline and keep the thickness in the range of of polycrystalline.

[0018] In one embodiment, the first silicon nitride layer and the second silicon nitride layer are removed by a phosphoric acid solution, and the first silicon oxide layer and the second silicon oxide layer are removed by a hydrofluoric acid solution.

[0019] In one embodiment, the trench structure has smooth sidewalls, a semicircular bottom, an inclination angle of 88 to 90 degrees, and a depth of 0.7 to 2.5 um.

[0020] In one implementation, the depth of the trench structure varies according to actual product requirements. The rated voltage of the product is between 20V and 250V, and the corresponding trench structure includes a stripe gate structure and a triangle gate structure.

[0021] In one embodiment, after adding an oxide layer at the bottom of the trench structure, a trench MOSFET device is prepared by the following method:

[0022] The gate oxide layer is grown by low temperature wet oxygen process and polycrystalline gate is deposited, and the gate is led out by polycrystalline back etching process, and the gate oxide layer growth temperature is 800~950℃;

[0023] The source region is led out by using source region photolithography and implantation, thus completing the front-end process of the entire device.

[0024] Photolithography and etching are used to realize through-hole lead-out and metal interconnection to complete the overall device.

[0025] In a method for improving the single particle gate punch-through resistance of a trench type MOSFET provided by the present invention, a bottom oxide layer is thickened by polycrystalline oxidation at the bottom of the trench structure, and the thickness is Compared with ordinary commercial trench MOSFET, it has the following benefits:

[0026] (1) Using bottom polycrystalline oxidation to thicken the bottom of the trench structure and improve the ability to resist single particle gate penetration;

[0027] (2) The well implantation process is performed before the gate oxide process, and the sidewall sacrificial oxidation process of the trench structure is used to achieve the purpose of junction pushing;

[0028] (3) The gate oxide process uses a low-temperature wet oxygen process to ensure the total dose resistance characteristics of the trench MOSFET.

[0029] The present invention adds some process steps and modifies the processing order of some process flows without adding additional photolithography layers. With limited increase in process difficulty and manufacturing cost, it can effectively enhance the product's ability to resist single-particle gate penetration and improve product performance, making it better suitable for space aerospace environments. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 This is a schematic diagram of the cross-sectional structure of a conventional trench MOSFET device cell;

[0031] Figure 2 This is the top view of the trench MOSFET device.

[0032] Figure 3 It is a schematic diagram of the cross-sectional structure of a primitive cell for improving the single particle gate punch-through resistance of a trench-type MOSFET provided by the present invention;

[0033] Figure 4 is a schematic diagram of well injection;

[0034] Figure 5 It is a schematic diagram of the formation of the trench structure;

[0035] Figure 6is a schematic diagram of sacrificial oxidation to repair the sidewall and realize well push junction;

[0036] Figure 7 is a schematic diagram of etching the second silicon nitride layer at the bottom of the trench structure;

[0037] Figure 8 It is a schematic diagram of filling polycrystalline in trench structure and performing dry etching;

[0038] Fig. 9 It is a schematic diagram of polycrystalline oxidation in a trench structure;

[0039] Fig.10 is a schematic diagram of removing the first and second silicon nitride layers and the first and second silicon oxide layers;

[0040] Fig.11 This is a schematic diagram of the final device cell / gate region / terminal region. DETAILED DESCRIPTION

[0041] The following is a further detailed description of a method for improving the single-particle gate punch-through resistance of a trench-type MOSFET proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0042] The present invention provides a method for improving the single particle gate punch-through resistance of a trench type MOSFET. The radiation-resistant trench MOSFET device finally formed is a three-terminal discrete device, and its front view is shown in FIG. Figure 2 The front of the wafer is divided into two regions, the source region (Source) and the gate region (Gate), and these two regions are isolated from the outside world by trenches. The drain region (Drain) of the device is on the back of the wafer, and only needs to be thinned and metal-plated on the back to lead out, which is understood by those skilled in the art, so it is not described in the present invention. The present invention is mainly aimed at the source region of the wafer, which is a trench primitive cell region and adopts a repeated array trench structure; the gate region is led out to the edge of the tube core through the polycrystalline in the trench, and then connected through contact holes and metal interconnects; trench isolation rings are used on the periphery of the source and gate regions to achieve junction termination.

[0043] The present invention provides a method for improving the single particle gate punch-through resistance of a trench type MOSFET, which comprises: oxidizing a polycrystalline thick bottom oxide layer at the bottom of the trench structure to a thickness of like Figure 3As shown in the figure, the sidewalls of the trench structure still function as the channel as before. In this way, the conduction characteristics of the trench MOSFET will not change. The bottom oxide layer in the trench structure can effectively reduce the electric field strength between the gate and the drain during the single particle radiation process, reducing the probability of single particle gate burnout.

[0044] Specifically, the oxide layer is thickened at the bottom of the trench structure by the following methods:

[0045] Taking N-type devices as an example, P-type devices can be obtained by the corresponding method. Figure 4 As shown, a first silicon oxide layer 2 is grown on a silicon epitaxial wafer 1, and a P-well (i.e., PW) injection is achieved through an ion implantation process, and then a first silicon nitride layer 3 is deposited by chemical vapor deposition to form an epitaxial silicon-silicon oxide-silicon nitride three-layer thin film structure; wherein the thickness of the first silicon oxide layer 2 is The thickness of the first silicon nitride layer 3 is

[0046] Through TR lithography and etching process, a trench structure with smooth sidewalls, an inclination angle of 88-90°, a semicircular bottom and a certain depth is dug out on the wafer, such as Figure 5 The depth of the trench structure is 0.7-2.5um, which needs to match the actual product requirements. For example, the depth of the trench structure in the N40V product is about 1.2um.

[0047] After the trench process is completed, a layer of sacrificial oxide needs to be grown to repair the damage to the sidewalls and bottom silicon surface of the trench structure during the dry etching process, and then the oxide layer is removed by wet etching. Generally speaking, the sacrificial oxidation temperature ranges from 1000 to 1150°, and the oxide thickness is This sacrificial oxidation thermal process is also used to push the wells, such as Figure 6 As shown, PW diffuses deeper during the thermal process of sacrificial oxidation;

[0048] After the sacrificial oxidation growth and removal process of the trench structure is completed, a second silicon oxide layer 4 is grown in the trench structure by thermal oxidation, and then a second silicon nitride layer 5 is deposited. The second silicon nitride layer 5 at the bottom of the trench structure is etched away by a dry etching method, and only the second silicon nitride layer 5 on the side wall of the trench structure is retained. In order to ensure that the second silicon nitride layer 5 at the bottom of the trench structure is etched cleanly, there will be a certain amount of over-etching, resulting in a portion of the first silicon nitride layer 3 on the surface being lost, leaving only the first silicon nitride layer 3 on the surface as an etching barrier layer for the trench structure and the second silicon nitride layer 5 on the side wall of the trench structure, as shown in FIG. Figure 7 As shown;

[0049] The trench structure is filled with polycrystalline 6 by low pressure chemical vapor deposition, and the first silicon nitride layer 3 on the surface is used as a stop line. The polycrystalline layer is etched by dry method, and only a certain thickness of polycrystalline 6 is retained at the bottom of the trench. Figure 8 As shown;

[0050] The wafer is subjected to furnace oxidation to convert the bottom polycrystalline 6 into an oxide layer 7, such as Fig. 9 As shown;

[0051] The first silicon nitride layer 3 and the second silicon nitride layer 5 are removed by a phosphoric acid solution, and the first silicon oxide layer 2 and the second silicon oxide layer 4 are removed by a hydrofluoric acid solution. At this time, except for the oxide layer 7 at the bottom of the trench structure, the rest of the trench structure is bare silicon. Fig.10 As shown;

[0052] The next process is the same as the trench radiation-resistant MOSFET device process, using low-temperature wet oxygen to grow the gate oxide layer and deposit the polycrystalline gate, and the gate is led out through the polycrystalline back etching process;

[0053] The source region is led out by using source region photolithography and implantation, thus completing the front-end process of the entire device.

[0054] After the device area is completed, photolithography and etching are used to realize through-hole lead-out and metal interconnection. These processes can refer to standard processes and will not be repeated here. The overall schematic diagram of the device is as follows Fig.11 .

[0055] The present invention provides a method for improving the single particle gate punch-through resistance of a trench type MOSFET. Based on the trench type MOSFET device, the method effectively improves the single particle resistance performance quality of the trench type MOSFET by improving some processes.

[0056] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A method for improving the single-particle gate punch-through resistance of a trench-type MOSFET, characterized in that: include: An oxide layer is added at the bottom of the trench structure, wherein the thickness of the oxide layer is 2000Å to 6000Å; An oxide layer is added to the bottom of the trench structure by: Growing a first silicon oxide layer on the epitaxial wafer, and implementing well implantation by ion implantation technology; Depositing a first silicon nitride layer on the first silicon oxide layer on the surface, and digging out a trench structure; By growing sacrificial oxide and stripping sacrificial oxide, the sidewall of the trench structure is repaired and the well is pushed to form a PN structure of the well and epitaxy. sequentially growing a second silicon oxide layer and depositing a second silicon nitride layer in the trench structure, and etching away the second silicon nitride layer at the bottom of the trench structure; Fill the trench structure with polycrystalline and etch; Through furnace oxidation, all the polycrystalline at the bottom of the trench structure is oxidized; The first silicon oxide layer, the first silicon nitride layer, the second silicon oxide layer, and the second silicon nitride layer are removed.

2. The method for improving the single particle gate punch-through resistance of trench type MOSFET according to claim 1, characterized in that: The thickness of the first silicon oxide layer is 200Å~500Å; the thickness of the first silicon nitride layer is 2000Å~4000Å; the thickness of the second silicon oxide layer is 200Å~500Å; and the thickness of the second silicon nitride layer is 500Å~1500Å.

3. The method for improving the single particle gate punch-through resistance of trench type MOSFET according to claim 1, characterized in that: Etching the polycrystal in the trench structure is divided into two steps: the first step is to etch the polycrystal and stop at the first silicon oxide layer; the second step is to etch the polycrystal with a thickness ranging from 1000 to 3000 Å at the bottom of the trench structure by controlling the etching time.

4. The method for improving the single particle gate punch-through resistance of trench type MOSFET according to claim 1, characterized in that: The first silicon nitride layer and the second silicon nitride layer are removed by a phosphoric acid solution, and the first silicon oxide layer and the second silicon oxide layer are removed by a hydrofluoric acid solution.

5. The method for improving the single-particle gate punch-through resistance of trench-type MOSFET according to claim 1, characterized in that: The side wall of the trench structure is smooth, the bottom is semicircular, the inclination angle is 88-90 degrees, and the depth is 0.7-2.5um.

6. The method for improving the single-particle gate punch-through resistance of trench-type MOSFET according to claim 5, characterized in that: The depth of the trench structure varies according to actual product requirements. The rated voltage of the product is between 20V and 250V, and the corresponding trench structures include a stripe gate structure and a triangle gate structure.

7. The method for improving the single-particle gate punch-through resistance of trench-type MOSFET according to claim 1, characterized in that: After adding an oxide layer to the bottom of the trench structure, the trench MOSFET device is prepared by the following method: The gate oxide layer is grown and the polycrystalline gate is deposited by a low-temperature wet oxygen process, and the gate is led out by a polycrystalline back etching process. The gate oxide layer growth temperature is 800~950℃; The source region is led out by using source region photolithography and implantation, thus completing the front-end process of the entire device. Photolithography and etching are used to realize through-hole lead-out and metal interconnection to complete the overall device.

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