Surface Mounted Power Semiconductor Package Component and Its Manufacturing Method

Abstract

A surface-mount power semiconductor package component includes a chip, a plastic layer, and a conductive coating. Signal contacts are respectively provided on the front and back sides of the chip. The plastic layer covers the chip and has a first opening and a second opening formed in the plastic layer. The first opening is located on the side of the chip, and the second opening corresponds to the signal contact extending to the front side of the chip. A conductive layer is used for electrical conduction within each of the first and second openings. The signal contact on the front side of the chip is electrically connected to the conductive layer in the second opening, and the signal contact on the back side of the chip is electrically connected to the conductive layer in the first opening through the conductive coating. The conductive layers in the first and second openings protrude from the surface of the plastic layer, forming conductive terminals of the surface-mount power semiconductor package component. With this structure, the present invention can achieve electrical connection of the chip without using expensive die-bonding materials.

Description

Technical Field

[0001] The present invention relates to a packaging component, and more particularly to a surface mount (SMT) power semiconductor packaging component and a manufacturing method thereof. Background Art

[0002] A discrete package refers to an electronic component with independent functionality. Depending on the chip's function, it can be categorized into types such as diodes and power transistors. Its main components include the chip, leadframe, wires, and an insulating plastic housing. U.S. Patent No. 8,237,259 discloses a conventional discrete device manufacturing method. This patent applies materials such as silver paste, sintered silver, or solder paste to one side of the die as the primary bonding medium during the die bonding step. As shown in FIG6 of the patent, element 316 illustrates, this bonding medium is used to attach the die to the leadframe. However, the use of silver paste / sintered silver and leadframes requires expensive materials, making it difficult to reduce product manufacturing costs. Solder paste, on the other hand, poses environmental concerns and is therefore not recommended. Summary of the Invention

[0003] In order to reduce the manufacturing cost of a product, the present invention proposes a surface mount power semiconductor package component and a manufacturing method thereof.

[0004] To achieve the aforementioned objectives, the surface mount power semiconductor package device of the present invention comprises:

[0005] A chip having a front surface and a back surface opposite to each other, wherein the front surface and the back surface are respectively provided with signal contacts, wherein the chip is a power semiconductor chip;

[0006] a plastic encapsulation layer covering the chip and having a first opening and a second opening formed in the plastic encapsulation layer, wherein the first opening is located at a side of the chip and the second opening extends to a signal contact on the front surface of the chip, and a conductive layer is filled in the first opening and the second opening, wherein the conductive layer in the second opening is electrically connected to the signal contact on the front surface of the chip;

[0007] a conductive layer disposed on the back side of the chip and extending to electrically connect the conductive layer in the first opening and the signal contact on the back side of the chip, wherein the conductive layer is a single conductive plating layer;

[0008] The conductive layers in the first opening and the second opening protrude from the same surface of the plastic packaging layer and serve as conductive terminals of the surface-mounted power semiconductor packaging component.

[0009] The conductive layer filled in the first opening and the second opening can be formed by electroplating, so that the front and back signal contacts of the chip are electrically connected to the same surface of the package component, that is, no lead frame and die bonding material are needed.

[0010] According to another embodiment, the surface mount power semiconductor package device of the present invention includes:

[0011] A chip having a front surface and a back surface opposite to each other, wherein the front surface and the back surface are respectively provided with signal contacts, wherein the chip is a power semiconductor chip;

[0012] A conductive substrate is formed with a chip accommodating opening, so that the chip is disposed inside the chip accommodating opening;

[0013] a plastic encapsulation layer covering the chip and the conductive substrate, wherein a first opening and a second opening are formed in the plastic encapsulation layer, wherein the first opening is located at a side of the chip and extends to a surface of the conductive substrate, and the second opening extends to a signal contact on a front surface of the chip, and a conductive layer is filled in the first opening and the second opening, wherein the conductive layer in the first opening is connected to the conductive substrate, and the conductive layer in the second opening is connected to the signal contact on the front surface of the chip;

[0014] a conductive layer disposed on the back side of the chip and extending to connect the conductive substrate and the signal contacts on the back side of the chip;

[0015] The conductive layers in the first opening and the second opening protrude from the same surface of the plastic packaging layer and serve as conductive terminals of the surface-mounted power semiconductor packaging component. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figures 1A to 1M : Schematic diagram of the process of the first embodiment of the present invention.

[0017] Figure 2A to Figure 2L : A schematic diagram of the process of the second embodiment of the present invention.

[0018] Figure 3 : A schematic plan view of a copper substrate according to the present invention.

[0019] Figure 4 : The present invention Figure 3 A three-dimensional schematic diagram of the copper substrate shown.

[0020] Figure 5 : A three-dimensional schematic diagram of the present invention in which a chip is arranged in a copper substrate.

[0021] Figures 6A to 6J : A schematic diagram of the process of the third embodiment of the present invention.

[0022] Figure 7 :According to the present invention Figures 1A to 1M A schematic cross-sectional view of a surface mount power semiconductor package component fabricated in accordance with an embodiment.

[0023] Figure 8 :According to the present invention Figures 2A to 2L A schematic cross-sectional view of a surface mount power semiconductor package component fabricated in accordance with an embodiment.

[0024] Figure 9 :According to the present invention Figures 6A to 6J A schematic cross-sectional view of a surface mount power semiconductor package component fabricated in accordance with an embodiment. DETAILED DESCRIPTION

[0025] The present invention is a "surface-mounted power semiconductor packaging component and its manufacturing method". Figures 1A to 1M This is a schematic diagram of the process of the first preferred embodiment. The following diagrams are used to illustrate the production process of the present invention. Figure 1A In the process, a carrier 10 is first prepared, and a layer of adhesive tape 11 is attached to the carrier 10. The surface of the adhesive tape 11 is sticky.

[0026] Reference Figure 1B , the chip 20 is arranged on the adhesive tape 11 at intervals. The chip 20 is a power semiconductor chip, and signal contacts (not shown) for electrical connection are formed on its front and back surfaces. Figure 1B In the embodiment, the side where the chip 20 and the adhesive tape 11 are adhered to each other is defined as the back side of the chip, and the other side opposite thereto is defined as the front side of the chip.

[0027] Reference Figure 1C , each chip 20 is covered with a plastic layer 30, the material of the plastic layer 30 can be PP, EMC and other dielectric materials. After the plastic layer 30 is formed, further add Figure 1D In the planarization step shown, grinding or cleaning is performed on the surface of the plastic packaging layer 30 to make the entire surface of the plastic packaging layer 30 flat.

[0028] Reference Figure 1EFirst vias 31a and second vias 31b are formed at predetermined locations within the plastic layer 30. The locations of the first and second vias 31a, 31b are determined by the locations of the conductive terminals required for the product. The first vias 31a surrounding the wafer 20 may completely penetrate the plastic layer 30, while the second vias 31b extend downward from the surface of the plastic layer 30 to the signal contacts on the front surface of the wafer 20. The first and second vias 31a, 31b may be formed using techniques such as laser drilling, ultrasonic drilling, micro-EDM (Micro Electrical Discharge Machining), micro powder blasting, or inductively coupled plasma reactive ion etching (ICP-RIE). The present invention is not particularly limited to these methods. The first opening and the second opening described in this specification refer to openings at different positions to distinguish different types of openings, rather than referring to the first opening and the second opening in number.

[0029] Reference Figure 1F A pre-plating layer 40 is formed on the inner wall of each first opening 31a, the second opening 31b and the surface of the plastic packaging layer 30. The pre-plating layer 40 serves as a seed layer for the subsequent production of a conductive layer. The pre-plating layer 40 can be produced by electroless plating, sputtering, or other techniques.

[0030] Reference Figure 1G A patterned conductive layer 42 fills the interior of each first opening 31a and second opening 31b, as well as the surface of the plastic layer 30. The conductive layer 42 protruding from the surface of the plastic layer 30 is etched or otherwise formed into a plurality of independent conductive terminals. Each first opening 31a and second opening 31b can form an independent conductive terminal 42a, 42b. Alternatively, depending on the functional design of the chip 20, several first openings 31a and second openings 31b can be electrically connected to each other using the conductive layer 42 to form a common contact. The conductive layer 42 is preferably made of copper and can be formed by electroplating or printing.

[0031] Reference Figure 1H After the conductive layer 42 is formed, the carrier 10 and the adhesive tape 11 are removed to expose the bottom surface of the plastic layer 30 and the bottoms of the first opening 31a and the second opening 31b. Figure 1IAs shown, if the bottom surface of the plastic layer 30 is uneven or dirty, the bottom surface of the plastic layer 30 can be ground or cleaned as needed to make the entire bottom surface of the plastic layer 30 a flat surface.

[0032] Reference Figure 1J After the bottom surface of the plastic layer 30 is exposed, a conductive plating layer 43 is formed on the bottom surface of the plastic layer 30. The conductive plating layer 43 electrically connects the signal contacts on the back of the chip 20 to the corresponding conductive terminals 42a. The conductive plating layer 43 can be made by electroless plating, sputtering and other techniques. Figure 1J In the embodiment, the back side of the chip 20 has a single signal contact, which is electrically connected to one of the conductive terminals 42a around the chip 20 through the conductive plating layer 43 to form a signal transmission path; however, in other embodiments, the back side of the chip 20 has multiple signal contacts, which are respectively connected to multiple conductive terminals 42a around it.

[0033] Reference Figure 1K An insulating protective layer 44 is formed on the bottom and front surfaces of the plastic layer 30 using an insulating material. This layer has the functions of waterproofing and anti-oxidation. The insulating protective layer 44 on the front surface of the plastic layer 30 is distributed between adjacent conductive terminals 42a, 42b as a solder mask, which can reduce the probability of short circuits between adjacent conductive terminals 42a, 42b during the soldering process. After forming the insulating protective layer 44, a contact protection layer 45a, 45b can be further formed on the surface of each conductive terminal 42a, 42b. The contact protection layer 45a, 45b can be formed using an electroless nickel immersion gold (ENIG) plating method.

[0034] Reference Figure 1L As shown, the insulating protective layer 44 on the back of the plastic layer 30 can be further subjected to a marking process, such as laser marking or forming the desired product mark through a yellow light process. Figure 1M As shown, sawing is performed at a predetermined cutting position so that each chip 20 and its plastic packaging layer 30 form an independent packaged product.

[0035] See also Figure 2A to Figure 2L , is a schematic diagram of the process of the second preferred embodiment of the present invention, and the following diagrams are used to illustrate the production process of the present invention. Figure 2A In the process, a copper substrate 50 is first prepared, and a layer of adhesive tape 58 is attached to the bottom surface of the copper substrate 50. The surface of the adhesive tape 58 is sticky. The structure of the copper substrate 50 is as follows: Figure 3 、 Figure 4As shown, the copper substrate 50 is formed with a plurality of chip accommodating openings 51. Each chip accommodating opening 51 is rectangular and has an anti-collision notch 52 extending outward from each corner thereof (such as Figure 3 As shown, each anti-collision notch 52 is connected to the wafer receiving opening 51. In this embodiment, each anti-collision notch 52 is a circular notch extending outward from a corner vertex of the receiving opening 51 as a circle center C. In other embodiments, the anti-collision notch 52 can also be of other shapes, such as rectangular, square, or polygonal. The anti-collision notch 52 can be manufactured by mechanical processing (such as milling) or chemical processing (such as etching).

[0036] Reference Figure 2B A chip 60 is disposed inside each chip receiving opening 51. The chip 60 is a power semiconductor chip, and signal contacts (not shown) for electrical connection are formed on the front and back surfaces thereof. Figure 2B In the embodiment, the side where the chip 60 and the adhesive tape 50 are bonded to each other is defined as the back side of the chip, and the other side opposite thereto is defined as the front side of the chip. Figure 5 As shown, because the four corners of the chip accommodating opening 51 all extend outwardly with the anti-collision notches 52 , the corners of the chip 60 can be prevented from directly colliding with the copper substrate 50 , thereby avoiding damage to the chip 60 .

[0037] Reference Figure 2C The chip 60 is then covered with a plastic layer 70. The material of the plastic layer 70 can be a dielectric material such as PP or EMC. After the plastic layer 70 is formed, if necessary, a planarization step can be performed on the surface of the plastic layer 70. The surface of the plastic layer 70 can be ground or cleaned to make the entire surface of the plastic layer 70 smooth.

[0038] Reference Figure 2DFirst vias 71a and second vias 71b are formed at predetermined locations on the plastic layer 70. The locations of the first and second vias 71a and 71b depend on the locations of the conductive terminals required for the product. The first vias 71a surrounding the chip 60 extend to the copper substrate 50, while the second vias 71b extend downward from the surface of the plastic layer 70 to the signal contacts on the front surface of the chip 60. The first and second vias 71a and 71b can be formed using techniques such as laser drilling, ultrasonic drilling, micro-EDM (micro electrical discharge machining), micro powder blasting, or inductively coupled plasma reactive ion etching (ICP-RIE), but the present invention is not particularly limited to these methods.

[0039] Reference Figure 2E After the first opening 71a / second opening 71b is formed, the adhesive tape 58 is removed to expose the plastic layer 70, the chip 60 and the bottom surface of the copper substrate 50. Depending on the material properties of the adhesive tape 58, the adhesive tape 58 can be heated or irradiated with ultraviolet light to separate it from the copper substrate 50. Figure 2F As shown, if the bottom surfaces of the plastic layer 70 and the copper substrate 50 are uneven or dirty, grinding or cleaning can be performed on the bottom surfaces of the plastic layer 70 and the copper substrate 50 as needed.

[0040] Reference Figure 2G A pre-plating layer 80 is simultaneously formed on the inner wall of each first opening 71a / second opening 71b and the bottom surface of the plastic packaging layer 70, the chip 60 and the copper substrate 50. The pre-plating layer 80 serves as a seed layer for the subsequent formation of a conductive layer. The pre-plating layer 80 can be formed using techniques such as electroless plating and sputtering.

[0041] Reference Figure 2HA patterned conductive layer 82 fills the interior of each first opening 71a / second opening 71b and the surface of the plastic layer 30. The conductive layer 82 on the surface of the plastic layer 30 is etched or patterned to form multiple independent conductive terminals. Each first opening 71a / second opening 71b can be located at a separate conductive terminal 82a, 82b. Alternatively, depending on the functional design of the chip 60, multiple first openings 71a / second openings 71b can be electrically connected to each other through the conductive layer 82 to form a common contact. The conductive layer 82 is preferably made of copper and can be formed by electroplating or printing. A connection layer 83 is also formed on the bottom surfaces of the plastic layer 70, the chip 60, and the copper substrate 50. The signal contacts on the back of the chip 60 are connected to the corresponding conductive terminals 82a through the copper substrate 50 via this connection layer 83. This connection layer 83 can be formed using techniques such as electroless plating or sputtering, and is preferably made of copper.

[0042] After the conductive layer 82 and the connecting layer 83 are completed, the front and back surfaces of the product are subjected to subsequent surface processing to form a solder mask between the adjacent conductive terminals 82a and 82b. The surface processing process includes the following steps: Figures 2I to 2K Steps:

[0043] Reference Figure 2I An insulating protective layer 84 is formed on the bottom surface of the connection layer 83 and between adjacent conductive terminals 82a. This insulating protective layer 84 provides moisture and oxidation resistance. The insulating protective layer 84 between adjacent conductive terminals 82a, 82b acts as a solder resist to prevent short circuits between adjacent conductive terminals 82a, 82b during soldering.

[0044] Reference Figure 2J As shown, a marking process is performed on the insulating protection layer 84 located on the back of the connection layer 83, such as laser marking or a photolithography process to form the required product mark.

[0045] Reference Figure 2K As shown, after the imprinting process is completed, contact protection layers 85a, 85b are further formed on the surface of each conductive terminal 82a, 82b to prevent oxidation of the conductive terminals 82a, 82b. Furthermore, a protection layer 86 is formed on the back surface of the connection layer 83. This protection layer 86 not only protects the surface of the connection layer 83 but also creates a clear visual contrast with the pattern of the imprinted insulating protection layer 84, highlighting the pattern of the insulating protection layer 84. The contact protection layers 85a, 85b and the protection layer 86 can be fabricated simultaneously using the same process, such as electroless nickel immersion gold (ENIG).

[0046] The order of the surface processing steps 2I to 2K can be changed as needed. For example, Figure 2I After completing the insulating protective layer 84, a contact protection layer 85a, 85b is first formed on the surface of each conductive terminal 82a, 82b, and then a marking process is performed on the insulating protective layer 84 located on the back of the connecting layer 83. In this way, there is no need to form a protection layer 86 on the back of the connecting layer 83.

[0047] Finally, please refer to Figure 2L As shown, sawing is performed at a predetermined cutting position so that each chip 60 and its plastic encapsulation layer 70 form an independent packaged product.

[0048] Compared to the first embodiment, the copper substrate 50 in the second embodiment has a certain degree of support, which can increase the structural strength of the package product. Furthermore, the copper substrate 50 serves as a bridge conductive block in the finished package product, electrically connecting the signal contacts on the back of the chip 60 to the front of the package product. Because the bridge conductive block is formed below the first opening 71, the depth of the first opening 71a can be reduced compared to the first embodiment, making it easier for the conductive layer 82 to completely fill the interior of the first opening 71a, ensuring a better electrical connection.

[0049] Regarding the third preferred embodiment of the present invention, please refer to Figures 6A to 6I As shown, in Figure 6A In the process, a copper substrate 90 is first prepared, and a conductive tape 98 is attached to the bottom surface of the copper substrate 90. The surface of the conductive tape 98 is sticky. Figure 3 、 Figure 4 The embodiments shown are the same and therefore will not be described again.

[0050] Reference Figure 6B A chip 100 is disposed inside each chip accommodating opening 91, wherein the chip 100 is a power semiconductor chip, and signal contacts for electrical connection are formed on the front and back sides thereof (not shown in the figure). The side of the chip 100 that is adhered to the conductive tape 98 is defined as the back side of the chip, and the other side opposite thereto is defined as the front side of the chip.

[0051] Reference Figure 6C The chip 100 is covered with a plastic layer 110. The material of the plastic layer 110 can be a dielectric material such as PP or EMC. After the plastic layer 110 is formed, if necessary, a flattening step can be performed on its surface, and the surface of the plastic layer 110 can be ground or cleaned.

[0052] Reference Figure 6DFirst vias 111a and second vias 111b are formed at predetermined locations on the plastic layer 110. The locations of the first vias 111a and second vias 111b depend on the locations of the conductive terminals required for the product. The first vias 111a around the chip 100 extend to the copper substrate 90, while the second vias 111b extend downward from the surface of the plastic layer 110 to the signal contacts on the front surface of the chip 100. The first vias 111a and second vias 111b can be formed using techniques such as laser drilling, ultrasonic drilling, micro-EDM (micro electrical discharge machining), micro powder blasting, or inductively coupled plasma reactive ion etching (ICP-RIE), but the present invention is not particularly limited to these methods.

[0053] Reference Figure 6E A pre-plating layer 120 is formed on the inner wall surface of each first opening 111a / second opening 111b and the surface of the plastic packaging layer 110 and the signal contact of the chip 100. The pre-plating layer 120 serves as a seed layer for the subsequent production of a conductive layer. The pre-plating layer 120 can be produced by electroless plating, sputtering, or other techniques.

[0054] Reference Figure 6F A patterned conductive layer 122 fills the interior of each first opening 111a / second opening 111b and the surface of the plastic layer 110. The conductive layer 122 on the surface of the plastic layer 110 is formed into a plurality of independent conductive terminals through etching or other patterning processes. Each first opening 111a / second opening 111b can be located at an independent conductive terminal 122a, 122b; or, depending on the design of the chip 100, multiple first openings 111a / second openings 111b can be electrically connected to each other using the conductive layer 122 to form a common contact. The conductive layer 122 is preferably made of copper and can be formed by electroplating or printing.

[0055] After the conductive layer 122 is fabricated, subsequent surface processing is performed on the front and back surfaces of the product to form a solder mask between adjacent conductive terminals 122a and 122b. The surface processing process includes the following steps: Figures 6G to 6I Steps:

[0056] Please refer to Figure 6G As shown, an insulating protective layer 124 is formed of an insulating material on the bottom surface of the conductive tape 98 and between adjacent conductive terminals 122a, 122b. The insulating protective layer 124 provides water vapor and oxidation resistance. The insulating protective layer 124 between adjacent conductive terminals 122a, 122b acts as a solder resist to prevent short circuits between adjacent conductive terminals 122a, 122b during soldering.

[0057] Reference Figure 6H As shown, a contact protection layer 125a, 125b is further formed on the surface of each conductive terminal 122a, 122b, which can be formed by electroless nickel immersion gold (ENIG) method.

[0058] Reference Figure 6I As shown, a marking process is performed on the insulating protective layer 124 on the back of the conductive tape 98 , such as laser marking or a lithography process to form the desired product mark.

[0059] The order of the surface processing steps 6G to 6I can be changed as needed. For example, Figures 2I to 2K In the method shown, after the imprinting step is completed, a protective layer is formed on both the front and back sides of the product using an electroless nickel immersion gold (ENIG) method.

[0060] Finally, please refer to Figure 6J As shown, sawing is performed at a predetermined cutting position so that each chip 100 and its plastic encapsulation layer 110 form an independent packaged product.

[0061] According to the manufacturing methods of the above three embodiments, the following can be obtained respectively: Figures 7 to 9 Surface mount power semiconductor packaging components.

[0062] refer to Figures 1A to 1M The manufacturing method and the component symbols in the drawings can be obtained as follows Figure 7 Surface mount power semiconductor package components include:

[0063] A chip 20 having signal contacts on its front and back sides;

[0064] A plastic layer 30 covers the chip 20 and has a first opening 31 a and a second opening 31 b formed therein. The first opening 31 a is located around the chip 20, and the second opening 31 b extends to the signal contact on the front of the chip 20. The first opening 31 a and the second opening 31 b are filled with a conductive layer 42. The conductive layer 42 in the second opening 31 b is electrically connected to the signal contact on the front of the chip 20.

[0065] a conductive layer, wherein the conductive layer 42 in the first opening 31 a is electrically connected to the signal contact on the back side of the chip 20 through the conductive layer, and the conductive layer is composed of a conductive plating layer 43;

[0066] The conductive layer 42 in the first opening 31 a and the second opening 31 b protrudes from the surface of the plastic layer 30 and constitutes conductive terminals 42 a and 42 b of the surface mount power semiconductor package component.

[0067] refer to Figures 2A to 2L The manufacturing method and the component symbols in the drawings can be obtained as follows Figure 8 Surface mount power semiconductor package components include:

[0068] A chip 60 having signal contacts on its front and back sides;

[0069] A conductive substrate is formed with a chip accommodating opening 51, so that the chip 60 is disposed inside the chip accommodating opening 51, and the conductive substrate is composed of a copper substrate 50;

[0070] A plastic layer 70 covers the chip 60 and has a first opening 71 a and a second opening 71 b formed in the plastic layer 70. The first opening 71 a is located on the side of the chip 60 and extends to the surface of the conductive substrate. The second opening 71 b extends to the signal contact on the front of the chip 60. A conductive layer 82 is filled in each of the first opening 71 a and the second opening 71 b. The conductive layer 82 in the second opening 71 b is electrically connected to the signal contact on the front of the chip 60.

[0071] A conductive layer, wherein the conductive layer 82 in the first opening 71a is electrically connected to the signal contact on the back side of the chip 80 through the conductive substrate and the conductive layer. The conductive layer is a multi-layer structure including a pre-plating layer 80 and a connecting layer 83;

[0072] The conductive layer 82 in the first opening 71 a and the second opening 71 b protrudes from the surface of the plastic layer 70 and constitutes conductive terminals 82 a and 82 b of the surface mount power semiconductor package component.

[0073] refer to Figures 6A to 6J The manufacturing method and the component symbols in the drawings can be obtained as follows Figure 9 Surface mount power semiconductor package components include:

[0074] A chip 100 having signal contacts on its front and back sides;

[0075] A conductive substrate is formed with a chip accommodating opening 51, so that the chip 60 is disposed inside the chip accommodating opening 51, and the conductive substrate is composed of a copper substrate 50;

[0076] A plastic layer 110 covers the chip 100 and has a first opening 111a and a second opening 111b formed in the plastic layer 110. The first opening 111a is located around the chip 100 and extends to the surface of the conductive substrate. The second opening 111b extends to the signal contact on the front of the chip 100. A conductive layer 122 is filled in each of the first opening 111a and the second opening 111b. The conductive layer 122 in the second opening 111b is electrically connected to the signal contact on the front of the chip 60.

[0077] A conductive layer, wherein the conductive layer 122 in the first opening 111 a is electrically connected to the signal contact on the back side of the chip 100 through the conductive substrate and the conductive layer. The conductive layer includes a conductive tape 98 adhered to the back side of the chip 100;

[0078] The conductive layer 122 in the first opening 111 a and the second opening 111 b protrudes from the surface of the plastic layer 110 and constitutes conductive terminals 122 a and 122 b of the surface mount power semiconductor package component.

[0079] It can be understood from the above embodiments that the surface mount power semiconductor package product of the present invention has the following features:

[0080] First, the manufacturing process does not require the use of traditional lead frames and wire bonding, and there is no need to use expensive die-bonding materials such as silver glue or sintered silver, thus achieving die-bonding operations and reducing production costs.

[0081] 2. The thickness of the product can be reduced.

[0082] 3. The conductive material filled in the first opening / the second opening and the conductive block formed by the copper substrate can provide a good heat dissipation path.

[0083] 4. The bridge conductive member arranged on the side of the chip surrounds the power semiconductor chip and can provide shielding against electromagnetic interference (EMI) generated by the chip.

[0084] The above description is merely a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Although the present invention has been disclosed as a preferred embodiment, it is not intended to limit the present invention. Any technician familiar with the present profession can make some changes or modifications to equivalent embodiments of the technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. A surface mount power semiconductor package component, comprising: A chip having a front surface and a back surface opposite to each other, wherein the front surface and the back surface are respectively provided with signal contacts, wherein the chip is a power semiconductor chip; A plastic layer covers the chip, and a first opening and a second opening are formed in the plastic layer. The first opening is located on the side of the chip, and the second opening extends to the signal contact on the front of the chip. A conductive layer is filled in the first opening and the second opening, wherein: The conductive layer in the second opening is electrically connected to the signal contact on the front surface of the chip; a conductive layer disposed on the back side of the chip and extending to electrically connect the conductive layer in the first opening and the signal contact on the back side of the chip, wherein the conductive layer is a single conductive plating layer, and the side surface of the conductive plating layer is flush with the outer side surface of the plastic packaging layer; The conductive layer in the first opening and the second opening protrudes from the same surface of the plastic encapsulation layer and serves as a conductive terminal of the surface-mount power semiconductor package. Each of the first opening and the second opening constitutes an independent conductive terminal. The signal contact on the back side of the chip is electrically connected to one of the conductive terminals around the chip through the conductive plating layer, forming a signal transmission path. A contact protection layer is provided on the surface of each conductive terminal; A solder resist layer is distributed between each conductive terminal, and the solder resist layer is attached to the surface of the plastic packaging layer; An insulating protection layer is arranged on the back side of the conducting layer.

2. The surface mount power semiconductor package component according to claim 1, wherein: The first opening penetrates the plastic sealing layer; and a pre-plating layer is provided on the inner wall surfaces of the first opening and the second opening.

3. The surface mount power semiconductor package component according to claim 1, wherein: The conductive layer is a copper layer.

4. A surface mount power semiconductor package component comprising: A chip having a front surface and a back surface opposite to each other, wherein the front surface and the back surface are respectively provided with signal contacts, wherein the chip is a power semiconductor chip; A copper substrate is formed with a chip accommodating opening, so that the chip is disposed inside the chip accommodating opening; A plastic packaging layer covers the chip and the copper substrate, wherein The plastic encapsulation layer covers the four sides and a portion of the surface of the copper substrate. A first opening and a second opening are formed in the plastic encapsulation layer. The first opening is located on the side of the chip and extends to the surface of the copper substrate. The second opening extends to the signal contact on the front of the chip. A conductive layer is filled in the first opening and the second opening. The conductive layer in the first opening is connected to the copper substrate, and the conductive layer in the second opening is connected to the signal contact on the front of the chip. a conductive layer, contacting the plastic encapsulation layer, the chip, and the back surface of the copper substrate, and extending to connect the copper substrate and the signal contacts on the back surface of the chip, wherein the signal contacts on the back surface of the chip completely contact the conductive layer; The conductive layer in the first opening and the second opening protrudes from the same surface of the plastic packaging layer and serves as a conductive terminal of the surface-mount power semiconductor package component. Each of the first opening and the second opening constitutes an independent conductive terminal. The signal contact on the back side of the chip is connected to the conductive terminal on the front side of the chip through the conductive layer and the copper substrate.

5. The surface mount power semiconductor package component according to claim 4, wherein: The conducting layer is a multi-layer structure including a pre-electroplating layer and a connecting layer, and the connecting layer is a copper layer.

6. The surface mount power semiconductor package component according to claim 4, wherein: The conducting layer is a conductive tape.

7. The surface mount power semiconductor package component according to claim 5 or 6, wherein: A pre-plating layer is provided on the inner wall surfaces of the first opening and the second opening.

8. The surface mount power semiconductor package component according to claim 5 or 6, wherein: A contact protection layer is provided on the surface of each conductive terminal; A solder resist layer is distributed between each conductive terminal, and the solder resist layer is attached to the surface of the plastic packaging layer; An insulating protection layer is arranged on the back side of the conducting layer.

9. The surface mount power semiconductor package component according to claim 5 or 6, wherein: The conductive layer is a copper layer.

10. The surface mount power semiconductor package component according to claim 5 or 6, wherein: The four corners of the chip accommodating opening extend outwards to form an anti-collision notch, and each anti-collision notch is connected to the chip accommodating opening; wherein each anti-collision notch is a circular notch extending outwards with the corner vertex of the accommodating opening as a circle center.

11. A method for manufacturing a surface mount power semiconductor package component, comprising: A carrier board is prepared, and an adhesive tape is attached to the carrier board, wherein the surface of the adhesive tape is sticky; Adhere a chip to the surface of the adhesive tape, wherein the chip has a front side and a back side opposite to each other, and signal contacts are respectively provided on the front side and the back side, and the chip is a power semiconductor chip; Covering the chip with a plastic layer; A first opening and a second opening are formed in the plastic layer, wherein the first opening is located at the side of the chip and passes through the plastic layer, and the second opening extends to the signal contact on the front surface of the chip; A conductive layer is filled inside the first opening and the second opening, wherein: The conductive layer in the second opening is electrically connected to the signal contact on the front surface of the chip, and the conductive layers in the first opening and the second opening protrude from the front surface of the plastic packaging layer and serve as conductive terminals; Removing the carrier board and the adhesive tape to expose the bottom surface of the plastic packaging layer and the bottoms of the first opening and the second opening; forming a conductive plating layer, the conductive plating layer being bonded to the back surface of the chip and the bottom surface of the plastic layer, the conductive plating layer electrically connecting the signal contact on the back surface of the chip to the conductive layer in the first opening; An insulating protective layer is formed on the surface of the conductive plating layer with an insulating material, and a solder resist layer is formed between the conductive terminals. The solder resist layer is attached to the surface of the plastic sealing layer, and a contact protection layer is formed on the surface of each conductive terminal; Cutting is performed at a predetermined position to cut the insulating protective layer, the conductive coating, the plastic coating and the solder resist layer at one time to form a surface-mounted power semiconductor package component, wherein the side surface of the conductive coating of the surface-mounted power semiconductor package component is flush with the outer side surface of the plastic coating. 12 . The method for manufacturing a surface mount power semiconductor package device according to claim 11 , further comprising: performing an imprinting process on the insulating protection layer on the back side of the plastic packaging layer.

13. A method for manufacturing a surface mount power semiconductor package component, comprising: Prepare a copper substrate, wherein the copper substrate is formed with a chip accommodating opening, and a layer of adhesive tape is attached to the bottom surface of the copper substrate; A chip is disposed within each chip receiving opening, wherein the chip has a front surface and a back surface opposite to each other, and signal contacts are respectively provided on the front surface and the back surface. The chip is a power semiconductor chip, and the back surface of the chip is adhered to the surface of the adhesive tape; The chip and the copper substrate are covered with a plastic layer, wherein: The plastic packaging layer covers the four sides and part of the surface of the copper substrate; A first opening and a second opening are formed at a predetermined position on the plastic layer, wherein the first opening is located on the side of the chip and extends to the surface of the copper substrate, and the second opening extends to the signal contact on the front surface of the chip; Removing the adhesive tape to expose the bottom surface of the plastic packaging layer, the bottom surface of the copper substrate, and the back surface of the chip; Filling a conductive layer inside the first opening and the second opening, wherein the conductive layer in the first opening is connected to the copper substrate, and the conductive layer in the second opening is electrically connected to the signal contact on the front surface of the chip. The conductive layers in the first opening and the second opening protrude from the front surface of the plastic layer and serve as conductive terminals; forming a conductive layer, the conductive layer being bonded to the back surface of the chip, the bottom surface of the copper substrate, and the bottom surface of the plastic layer, wherein the signal contacts on the back surface of the chip are in complete contact with the conductive layer; The signal contact on the back side of the chip is electrically connected to the conductive layer in the first opening through the conductive layer and the copper substrate.

14. The method for manufacturing a surface mount power semiconductor package device according to claim 13, comprising a surface processing flow, wherein the surface processing flow comprises at least one of the following steps: forming a solder resist layer between the conductive terminals, wherein the solder resist layer is attached to the surface of the plastic packaging layer; forming an insulating protective layer on the back side of the conductive layer, and performing an imprinting process on the insulating protective layer; A contact protection layer is formed on the surface of each conductive terminal.

15. The method for manufacturing a surface mount power semiconductor package device as claimed in claim 13, wherein before filling the conductive layer, a pre-plating layer is formed on the inner walls of the first and second openings, the back surface of the chip and the bottom surface of the copper substrate. 16 . The method for manufacturing a surface mount power semiconductor package device as claimed in claim 15 , wherein the conductive layer comprises: the pre-plating layer and a copper layer formed on a surface of the pre-plating layer.

17. A method for manufacturing a surface mount power semiconductor package component, comprising: Prepare a copper substrate, wherein the copper substrate is formed with a chip accommodating opening, and a layer of conductive tape is attached to the bottom surface of the copper substrate; Adhere a back surface of a chip to the surface of the conductive tape, wherein the chip has a front surface and a back surface opposite to each other, and signal contacts are respectively provided on the front surface and the back surface, and the chip is a power semiconductor chip; The chip and the copper substrate are covered with a plastic layer, wherein: The plastic encapsulation layer covers the four sides and part of the surface of the copper substrate, so that the conductive tape is in contact with the back surface of the chip, the bottom surface of the copper substrate and the bottom surface of the plastic encapsulation layer, and the signal contact on the back surface of the chip is in complete contact with the conductive tape; A first opening and a second opening are formed at a predetermined position on the plastic layer, wherein the first opening is located on the side of the chip and extends to the surface of the copper substrate, and the second opening extends to the signal contact on the front surface of the chip; Filling a conductive layer inside the first opening and the second opening, wherein the conductive layer in the first opening is connected to the copper substrate, and the conductive layer in the second opening is electrically connected to the signal contact on the front surface of the chip. The conductive layers in the first opening and the second opening protrude from the front surface of the plastic layer and serve as conductive terminals; The signal contact on the back side of the chip is electrically connected to the conductive layer in the first opening through the conductive tape and the copper substrate.

18. The method for manufacturing a surface mount power semiconductor package device according to claim 17, comprising a surface processing flow, wherein the surface processing flow comprises at least one of the following steps: forming a solder resist layer between the conductive terminals, wherein the solder resist layer is attached to the surface of the plastic packaging layer; forming an insulating protective layer on the back side of the conductive tape, and performing an imprinting process on the insulating protective layer; A contact protection layer is formed on the surface of each conductive terminal. 19 . The method for manufacturing a surface mount power semiconductor package device as claimed in claim 17 , wherein a pre-plating layer is formed on the inner wall surfaces of the first opening and the second opening before filling the conductive layer.

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