Adjustable filter and preparation method thereof

Abstract

The present disclosure provides a tunable filter and a preparation method thereof, belonging to the field of electronic technology. The tunable filter disclosed in the present disclosure comprises: a substrate having a first surface and a second surface arranged opposite to each other along its thickness direction; the substrate having a first connecting via hole penetrating along its thickness direction; at least one inductor and at least one capacitor integrated on the substrate; wherein each of the at least one inductor comprises a first substructure arranged on the first surface, a second substructure arranged on the second surface, and a first connecting electrode arranged in the first connecting via hole, and the first connecting electrode connects the first substructure and the second substructure to form a coil structure of the inductor.

Description

Technical Field

[0001] The present invention belongs to the field of electronic technology, and in particular relates to an adjustable filter and a preparation method thereof. Background Art

[0002] In the contemporary era, the consumer electronics industry is developing rapidly. Mobile communication terminals represented by mobile phones, especially 5G mobile phones, are developing rapidly. Mobile phones need to process more and more signal frequency bands, and the number of RF chips required is also rising. The mobile phone forms that are popular with consumers are constantly developing towards miniaturization, lightness, and long battery life. In traditional mobile phones, there are a large number of discrete devices such as resistors, capacitors, inductors, filters, etc. on the RF PCB board. They have the disadvantages of large size, high power consumption, many solder joints, and large changes in parasitic parameters, which are difficult to meet future needs. The interconnection and matching between RF chips require integrated passive devices with small area, high performance, and good consistency. The integrated passive devices on the market are mainly based on Si (silicon) substrates and GaAs (gallium arsenide) substrates. Si-based integrated passive devices have the advantage of low price, but Si itself has trace impurities (poor insulation), which leads to high microwave loss and poor performance of the device; GaAs-based integrated passive devices have the advantage of excellent performance, but are expensive. Summary of the invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art and provides a tunable filter and a preparation method thereof.

[0004] The present disclosure provides an adjustable filter, comprising:

[0005] A base substrate, which has a first surface and a second surface arranged opposite to each other along a thickness direction thereof; the base substrate has a first connecting via hole penetrating along the thickness direction thereof;

[0006] At least one inductor and at least one capacitor are arranged on the substrate; wherein each of the at least one inductor includes a first substructure arranged on the first surface, a second substructure arranged on the second surface, and a first connecting electrode arranged in the first connecting via, and the first connecting electrode connects the first substructure and the second substructure.

[0007] Wherein, the at least one capacitor includes a first capacitor and a second capacitor; the number of the inductor is one; the second capacitor includes a first plate and a second plate sequentially arranged in a direction away from the substrate, and a P-type semiconductor layer, an intrinsic semiconductor layer and an N-type semiconductor layer, which are located between the first plate and the second plate;

[0008] The first lead end of the inductor is connected to the first signal end, the second lead end of the inductor is connected to the second signal end and the first plate of the first capacitor; the second plate of the first capacitor is connected to the second plate of the second capacitor and the first bias voltage end; the first plate of the second capacitor is connected to the second bias voltage end.

[0009] The second substructure of the inductor, the first electrode plate of the first capacitor and the first electrode plate of the second capacitor are arranged in the same layer and made of the same material; and / or,

[0010] The first electrode plate of the first capacitor and the second electrode plate of the second capacitor are arranged in the same layer and made of the same material.

[0011] Wherein, a first interlayer dielectric layer is arranged on a side of the second plate of the second capacitor away from the base substrate, and the first signal terminal, the second signal terminal, the first bias voltage terminal and the second bias voltage terminal are formed on a side of the first interlayer dielectric layer away from the base substrate;

[0012] The first signal terminal is connected to the first lead terminal of the inductor through a second connecting via penetrating the first interlayer dielectric layer; the second signal terminal is connected to the second plate of the second capacitor through a third connecting via penetrating the first interlayer dielectric layer; the first bias voltage terminal is connected to the second plate of the second capacitor through a fourth connecting via penetrating the first interlayer dielectric layer; and the second bias voltage terminal is connected to the first plate of the second capacitor through a fifth connecting via penetrating the first interlayer dielectric layer.

[0013] Wherein, it also includes a first connection pad, a second connection pad, a third connection pad and a fourth connection pad located on the side of the layer where the first signal terminal, the second signal terminal, the first bias voltage terminal and the second bias voltage terminal are located away from the substrate;

[0014] The first connecting pad covers the side of the first signal end away from the substrate; the second connecting pad covers the side of the second signal end away from the substrate; the third connecting pad covers the side of the first bias voltage end away from the substrate; the fourth connecting pad covers the side of the second bias voltage end away from the substrate.

[0015] Wherein, the at least one inductor includes a first inductor and a second inductor; the at least one capacitor includes a third capacitor and a fourth capacitor;

[0016] The tunable filter comprises a first resonant unit and a second resonant unit, a first switch transistor, a second switch transistor, and a third switch transistor; wherein the first resonant unit comprises a first inductor and a third capacitor; and the second resonant unit comprises a second inductor and a fourth capacitor;

[0017] The first lead end of the first inductor is connected to the third signal end, and the second lead end of the first inductor is connected to the first plate of the third capacitor; the second plate of the third capacitor is connected to the first electrode of the first switch transistor; the second electrode of the first switch transistor is connected to the fourth signal end; the control electrode of the first switch transistor is connected to the first control signal end and the first electrode of the second switch transistor; the second electrode of the second switch transistor is connected to the reference voltage end; the control electrode of the second switch transistor is connected to the second control signal end and the control electrode of the third switch transistor; the first electrode of the third switch transistor is connected to the second plate of the third capacitor; the second electrode of the third switch transistor is connected to the second plate of the fourth capacitor; the first plate of the fourth capacitor is connected to the second lead end of the second inductor; and the first lead end of the second inductor is connected to the fifth signal end.

[0018] The second substructure of the first inductor, the second substructure of the second inductor, the first electrode plate of the third subcapacitor, the first electrode plate of the fourth capacitor, the first electrode and the second electrode of the first switching transistor, the first electrode and the second electrode of the second switching transistor, and the first electrode and the second electrode of the third switching transistor are arranged in the same layer and made of the same material; and / or,

[0019] The second plate of the third capacitor, the second plate of the fourth capacitor, the control electrode of the first switch transistor, the control electrode of the second switch transistor, and the control electrode of the third switch transistor are arranged in the same layer and made of the same material.

[0020] Wherein, a first interlayer dielectric layer is arranged on the side of the second plate of the second capacitor away from the base substrate, and the third signal terminal, the fourth signal terminal, the fifth signal terminal, the first control signal terminal, and the second control signal terminal are formed on the side of the first interlayer dielectric layer away from the base substrate;

[0021] The third signal terminal is connected to the first lead terminal of the first inductor through the sixth connecting via penetrating the first interlayer dielectric layer; the fourth signal terminal is connected to the second plate of the third capacitor through the seventh connecting via penetrating the first interlayer dielectric layer; the fifth signal terminal is connected to the first lead terminal of the second inductor through the eighth connecting via penetrating the first interlayer dielectric layer; the first control signal terminal is connected to the control electrode of the first switching transistor through the ninth connecting via penetrating the first interlayer dielectric layer; the second control signal terminal is connected to the control electrode of the second switching transistor and the control electrode of the third switching transistor through the tenth connecting via penetrating the first interlayer dielectric layer.

[0022] Wherein, the tunable filter further includes a fifth connecting pad, a sixth connecting pad, a seventh connecting pad, an eighth connecting pad and a ninth connecting pad located on a side of the layer where the third signal terminal, the fourth signal terminal, the fifth signal terminal, the first control signal terminal and the second control signal terminal are located away from the substrate;

[0023] The fifth connecting pad covers the side of the third signal terminal away from the substrate substrate; the sixth connecting pad covers the side of the fourth signal terminal away from the substrate substrate; the seventh connecting pad covers the side of the fifth signal terminal away from the substrate substrate; the eighth connecting pad covers the side of the first control signal terminal away from the substrate substrate; the ninth connecting pad covers the side of the second control signal terminal away from the substrate substrate.

[0024] Wherein, the substrate comprises a glass base.

[0025] The present disclosure provides a method for preparing a tunable filter, which includes:

[0026] Providing a base substrate, the base substrate having a first surface and a second surface arranged opposite to each other along a thickness direction thereof; the base substrate having a first connecting via hole penetrating along the thickness direction thereof;

[0027] At least one inductor and at least one capacitor are integrated on the substrate; wherein,

[0028] Forming the inductor comprises:

[0029] A first substructure of the inductor is formed on the first surface, a second substructure of the inductor is formed on the second surface, and a first connecting electrode is formed in the first connecting via; the first connecting electrode connects the first substructure and the second substructure to form a coil structure of the inductor. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 A circuit diagram of an adjustable filter according to an embodiment of the present disclosure.

[0031] Figure 2 FIG. 4 is a top view of an inductor according to an embodiment of the present disclosure.

[0032] Figure 3 for Figure 2 A cross-sectional view of the low-pass filter is shown.

[0033] Figure 4 It is a schematic diagram of the structure formed in step S11 in the method for preparing a tunable filter according to an embodiment of the present disclosure.

[0034] Figure 5It is a schematic diagram of the structure formed in step S12 in the method for preparing an adjustable filter according to an embodiment of the present disclosure.

[0035] Figure 6 It is a schematic diagram of the structure formed in step S13 in the method for preparing an adjustable filter according to an embodiment of the present disclosure.

[0036] Figure 7 It is a schematic diagram of the structure formed in step S14 of the method for preparing an adjustable filter according to an embodiment of the present disclosure.

[0037] Figure 8 FIG. 4 is a circuit diagram of another tunable filter according to an embodiment of the present disclosure.

[0038] Figure 9a for Figure 8 The layout of the tunable filter is shown.

[0039] Figure 9b for Figure 8 A cross-sectional view of the tunable filter is shown.

[0040] Fig.10a This is a layout formed in step S21 of another method for preparing a tunable filter according to an embodiment of the present disclosure.

[0041] Fig.10b It is a schematic diagram of the structure formed by step S21 of another method for preparing a tunable filter according to an embodiment of the present disclosure.

[0042] Fig.11a This is a layout formed in step S22 of another method for preparing a tunable filter according to an embodiment of the present disclosure.

[0043] Fig.11b It is a schematic diagram of the structure formed in step S22 of another method for preparing an adjustable filter according to an embodiment of the present disclosure.

[0044] Fig.12a This is a layout formed in step S23 of another method for preparing a tunable filter according to an embodiment of the present disclosure.

[0045] Figure 12b It is a schematic diagram of the structure formed in step S23 of another method for preparing a tunable filter according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0046] In order to enable those skilled in the art to better understand the technical solution of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0047] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0048] The embodiments of the present disclosure provide a tunable filter and a preparation method thereof, and the tunable filter may be a low-pass filter, a high-pass filter, a band-pass filter, a band-stop filter, a duplexer, etc. It can be seen that the tunable filter at least includes a capacitor and an inductor L. The capacitor selects high-frequency signals and blocks low-frequency signals from passing through; the inductor L selects low-frequency signals and blocks high-frequency signals from passing through. Figure 1 is a circuit diagram of an adjustable filter according to an embodiment of the present disclosure; Figure 1 As shown, the adjustable filter is a low-pass filter, which includes a first signal terminal, a second signal terminal, a first bias voltage terminal Bias, a second bias voltage terminal, an inductor L, a first capacitor C1 and a second capacitor C2; wherein the first signal terminal is used as a signal input terminal Input, and the second signal terminal is used as a signal output terminal Output. The second capacitor C2 adopts an adjustable capacitor, for example: the adjustable capacitor includes a first plate and a second plate, and a P-type semiconductor, an intrinsic semiconductor and an N-type semiconductor arranged between the first plate and the second plate and stacked in sequence. At this time, the capacitance can be adjusted by controlling the bias voltage applied to the first plate and the second plate.

[0049] Specifically, the first lead terminal 22 of the inductor L is connected to the signal input terminal Input, the second lead terminal 23 of the inductor L is connected to the first plate 31 of the first capacitor C1, the second plate 32 of the first capacitor C1 is connected to the second plate 32 of the second capacitor C2 and the first bias voltage terminal Bias, and the first plate 31 of the second capacitor C2 is connected to the second bias voltage terminal. In the embodiment of the present disclosure, taking the second bias voltage terminal as the ground terminal GND as an example, in this case, the size of the second capacitor C2 can be changed by only changing the voltage input to the first bias voltage terminal Bias, thereby realizing the adjustable function of the filter frequency.

[0050] To make it clearer Figure 1 The specific structure of the tunable filter shown in the figure is described for each film layer structure of the tunable filter. Among them, the inductor L, the first capacitor C1 and the second capacitor C2 in the tunable filter are integrated on the substrate. For example: the inductor L adopts a serpentine coil, which is formed on the substrate; the first plate 31 of the first capacitor C1 and the first plate 31 of the second capacitor C2 can be arranged on the same layer as the inductor L, and the same material is used. A P-type semiconductor layer, an intrinsic semiconductor layer and an N-type semiconductor layer are formed in sequence on the side of the first plate 31 of the second capacitor C2 away from the substrate substrate, and an interlayer dielectric layer is formed on the side of the first plate 31 of the first capacitor C1 away from the substrate substrate. The second plate 32 of the first capacitor C1 is formed on the side of the interlayer dielectric layer away from the substrate substrate, and the interlayer dielectric layer serves as the intermediate medium between the first plate 31 and the second plate of the first capacitor C1. The second plate 32 of the second capacitor C2 is formed on the side of the N-type semiconductor layer away from the substrate substrate. A first interlayer dielectric layer 40 is formed on the side of the second plate 32 of the first capacitor C1 and the second plate 32 of the second capacitor C2 away from the substrate substrate, and a signal input terminal Input, a signal output terminal Output, a first bias voltage terminal Bias and a ground terminal GND are formed on the side of the first interlayer dielectric layer 40 away from the substrate substrate. The signal input terminal Input is connected to the first lead terminal 22 of the inductor L through a second connecting via 41 penetrating the first interlayer dielectric layer 40, the signal output terminal Output is connected to the second plate 32 of the second capacitor C2 of the inductor L through a third connecting via 42 penetrating the first interlayer dielectric layer 40, the first bias voltage terminal Bias is connected to the second plate 32 of the second capacitor C2 through a fourth connecting via 43 penetrating the first interlayer dielectric layer 40; the ground terminal GND is connected to the first plate 31 of the second capacitor C2 through a fifth connecting via 44 penetrating the first interlayer dielectric layer 40. Of course, the adjustable filter in the embodiment of the present disclosure may also include a first connecting pad 51, a second connecting pad 52, a third connecting pad 53 and a fourth connecting pad 54 formed on the side of the layer where the signal input terminal Input, the signal output terminal Output, the first bias voltage terminal Bias and the second bias voltage terminal are located away from the substrate substrate; the first connecting pad 51 covers the side of the signal input terminal Input away from the substrate substrate; the second connecting pad 52 covers the side of the signal output terminal Output away from the substrate substrate; the third connecting pad 53 covers the side of the first bias voltage terminal Bias away from the substrate substrate; the fourth connecting pad 54 covers the side of the ground terminal GND away from the substrate substrate.

[0051] In some examples, the substrate includes, but is not limited to, any one of a glass substrate 10, a flexible substrate, and an interlayer dielectric layer including at least an organic insulating layer. Since the passive device is integrated on the glass substrate 10, it has the advantages of small size, light weight, high performance, low power consumption, etc., in the embodiment of the present disclosure, the substrate preferably adopts a glass substrate 10. In the following, the transparent dielectric layer adopts a glass substrate 10 as an example for explanation.

[0052] In some examples, in order to realize a small-sized filter, the glass substrate 10 may be processed to form a three-dimensional inductor L to reduce the size of the filter. For example: Figure 2 is a top view of the inductor L of the embodiment of the present disclosure; Figure 2 , each first substructure 211 of the inductor L extends along the first direction and is arranged side by side along the second direction; each second substructure 212 of the inductor L extends along the third direction and is arranged side by side along the second direction. Among them, the first direction, the second direction, and the third direction are all different directions. In the embodiment of the present disclosure, the first direction and the second direction are perpendicular to each other, and the first direction and the third direction intersect and are arranged non-perpendicularly as an example. Of course, the extension directions of the first substructure 211 and the second substructure 212 can also be interchanged, both within the protection scope of the embodiment of the present disclosure. In addition, in the present embodiment, the inductor L is illustrated as an example including N first substructures 211 and N-1 second substructures 212, wherein N≥2, and N is an integer. The first end and the second end of the first substructure 211 respectively overlap at least partially with the orthographic projection of a first connecting via 11 on the glass substrate 10. And the first end and the second end of a first substructure 211 correspond to different first connecting vias 11, that is, the orthographic projections of a first substructure 211 and two first connecting vias 1111 on the glass substrate 10 at least partially overlap. At this time, the first end of the i-th second substructure 212 of the inductor L is connected to the first end of the i-th first substructure 211 and the second end of the i+1-th first substructure 211 to form an inductor L coil, wherein 1≤i≤N-1, and i is an integer.

[0053] It should be noted that the first lead terminal 22 is connected to the second end of the first first substructure 211 of the inductor L coil, and the second lead terminal 23 is connected to the first end of the Nth first substructure 211. Further, the first lead terminal 22 and the second lead terminal 23 can be arranged in the same layer as the second substructure 212 and made of the same material. In this case, the first lead terminal 22 can be connected to the second end of the first first substructure 211 through the first connecting via 11, and correspondingly, the second lead terminal 23 can be connected to the first end of the Nth first substructure 211 through the first connecting via 11.

[0054] Figure 3 for Figure 2 A cross-sectional view of the low-pass filter shown in FIG. Figure 3 As shown, the first substructure 211 in the inductor L of the low-pass filter is arranged on the first surface of the glass substrate 10, and the second substructure 212 is arranged on the second surface of the glass substrate 10. The first capacitor C1 and the second capacitor C2 of the low-pass filter are also arranged on the second surface.

[0055] For example: the second substructure 212 of the inductor L coil is arranged in the same layer as the first plate 31 of the first capacitor C1 and the first plate 31 of the second capacitor C2, and the same material is used. A P-type semiconductor layer, an intrinsic semiconductor layer and an N-type semiconductor layer are formed in sequence on the side of the first plate 31 of the second capacitor C2 away from the substrate substrate, and an interlayer dielectric layer is formed on the side of the first plate 31 of the first capacitor C1 away from the substrate substrate. The second plate 32 of the first capacitor C1 is formed on the side of the interlayer dielectric layer away from the substrate substrate, and the interlayer dielectric layer serves as the intermediate medium between the first plate 31 and the second plate of the first capacitor C1. The second plate 32 of the second capacitor C2 is formed on the side of the N-type semiconductor layer away from the substrate substrate. A first interlayer dielectric layer 40 is formed on the side of the second plate 32 of the first capacitor C1 and the second plate 32 of the second capacitor C2 away from the substrate substrate, and a signal input terminal Input, a signal output terminal Output, a first bias voltage terminal Bias and a ground terminal GND are formed on the side of the first interlayer dielectric layer 40 away from the substrate substrate. The signal input terminal Input is connected to the first lead terminal 22 of the inductor L through a second connecting via 41 penetrating the first interlayer dielectric layer 40, and the signal output terminal Output is connected to the second plate 32 of the second capacitor C2 of the inductor L through a third connecting via 42 penetrating the first interlayer dielectric layer 40. The first bias voltage terminal Bias is connected to the second plate 32 of the second capacitor C2 through a fourth connecting via 43 penetrating the first interlayer dielectric layer 40; the ground terminal GND is connected to the first plate 31 of the second capacitor C2 through a fifth connecting via 44 penetrating the first interlayer dielectric layer 40. Of course, the adjustable filter in the embodiment of the present disclosure may also include a first connecting pad 51, a second connecting pad 52, a third connecting pad 53 and a fourth connecting pad 54 formed on the side of the layer where the signal input terminal Input, the signal output terminal Output, the first bias voltage terminal Bias and the second bias voltage terminal are located away from the substrate substrate; the first connecting pad 51 covers the side of the signal input terminal Input away from the substrate substrate; the second connecting pad 52 covers the side of the signal output terminal Output away from the substrate substrate; the third connecting pad 53 covers the side of the first bias voltage terminal Bias away from the substrate substrate; the fourth connecting pad 54 covers the side of the ground terminal GND away from the substrate substrate.

[0056] In addition, in the tunable filter of the embodiment of the present disclosure, because a P-type semiconductor layer, an intrinsic semiconductor layer and an N-type semiconductor layer are provided between the first plate and the second plate of the capacitor, the magnitude of the bias voltage applied to the first plate and the second plate can be controlled to achieve the adjustment of the capacitor, so as to realize the frequency tunable function of the filter. For example, the larger the value of the capacitor, the stronger the blocking ability to low-frequency signals.

[0057] To make it clearer Figure 3 The structure of the low-pass filter shown in FIG. 1 is described below in conjunction with a method for preparing the low-pass filter. It should be noted that: Figure 3 Only the structure of the second capacitor C2 and the inductor L is shown. Figure 3 There is no schematic diagram, wherein the first electrode plate 31 of the first capacitor C1 and the first electrode plate 31 of the second capacitor C2 are prepared by a single patterning process, and the second electrode plate 32 of the first capacitor C1 and the second electrode plate 32 of the second capacitor C2 are prepared by a single patterning process. Therefore, in the following description, only the preparation process of the inductor L and the second capacitor C2 is explained.

[0058] Figure 3 The preparation method of the low-pass filter shown specifically comprises the following steps:

[0059] S11, providing a glass substrate 10, and forming a first connecting via hole 11 on the glass substrate 10 that runs through the thickness direction thereof, such as Figure 4 shown.

[0060] In some examples, the first connection via hole 11 on the glass substrate 10 can be punched by methods including but not limited to mechanical punching, laser punching, photolithography punching, etc. The following describes the process of forming the first connection via hole 11 by taking laser punching as an example.

[0061] In some examples, step S11 may specifically include the following steps:

[0062] (1) Cleaning: The glass substrate 10 enters a cleaning machine for cleaning.

[0063] In some examples, the thickness of the glass substrate 10 is about 0.1 mm-1.1 mm.

[0064] (2) Laser drilling: Use a laser to vertically incident the laser beam onto the surface of the glass substrate 10 to form a plurality of first connection vias 11 on the glass substrate 10. Specifically, when the laser beam interacts with the glass substrate 10, the atoms in the glass substrate 10 are ionized and ejected out of the surface of the glass substrate 10 due to the high energy of the laser photons. As time goes by, the holes drilled gradually deepen until the entire glass substrate 10 is drilled through, that is, a plurality of first connection vias 11 are formed. Among them, the generally selectable laser wavelength is 532nm, 355nm, 266nm, 248nm, 197nm, etc., the laser pulse width can be selected from 1-100fs, 1-100ps, 1-100ns, etc., and the type of laser can be selected from continuous laser, pulsed laser, etc. The laser drilling method may include but is not limited to the following two. In the first method, when the spot diameter is large, the relative position of the laser beam and the glass substrate 10 is fixed, and the glass substrate 10 is directly penetrated by high energy. At this time, the shape of the first connection via 11 formed is an inverted cone, and the diameter of the inverted cone decreases from top to bottom (from the second surface to the first surface). In the second method, when the spot diameter is small, the laser beam scans in circles on the glass substrate 10, the focal point of the spot is constantly changing, and the depth of the focus is also constantly changing. A spiral line is drawn from the lower surface of the glass substrate 10 (the first surface) to the upper surface of the glass substrate 10 (the second surface), and the spiral radius decreases from bottom to top. The glass substrate 10 is cut into a truncated cone by laser and falls down due to gravity. The first connection via 11 is thus formed, and the shape of the first connection hole is a truncated cone.

[0065] In some examples, the diameter of the formed first connecting via hole 11 is about 10 μm-1 mm.

[0066] (3) HF etching: Since a stress zone is formed in the area of ​​about 5-20 microns on the upper surface of the inner wall of the first connecting via 11 near the hole during the laser drilling process, the surface of the glass substrate 10 in this area is uneven and presents a molten state with many burrs, and there are a large number of microcracks and macrocracks, and there is residual stress. At this time, a 2%-20% HF etching solution is used, and wet etching is performed at an appropriate temperature for a certain period of time to etch away the glass in the stress zone, so that the interior of the first connecting via 11 and the surface area near the hole are smooth and flat, without microcracks and macrocracks, and the stress zone is completely etched away.

[0067] S12, forming a first substructure 211 of the inductor L coil on the first surface of the glass substrate 10 after completing step S11, forming a second substructure 212 and a first electrode plate 31 of the second capacitor C2 on the second surface, and a first connecting electrode 213 located in the first connecting via 11, as shown in FIG. Figure 5 shown.

[0068] In some examples, step S12 may specifically include the following steps:

[0069] (1) Growth of seed layer: A first metal film is deposited on the first surface of the glass substrate 10 by magnetron sputtering as a plating seed layer. During this process, the first metal film is also deposited on the inner wall of the first connecting via 11. The glass substrate 10 is then turned over and the first metal film is formed on the second surface of the glass substrate 10 by magnetron sputtering. Of course, the first metal film on the second surface also serves as the plating seed layer.

[0070] In some examples, the material of the first metal film includes but is not limited to at least one of copper (Cu), aluminum (Al), molybdenum (Mo), and silver (Ag), and the thickness of the first metal film is about 100nm-500nm, and further can be 50nm-35μm. In the following description, the material of the first metal film is copper as an example.

[0071] In some examples, in order to increase the adhesion between the first metal film and the glass substrate 10, before forming the deposited first metal film, a layer of auxiliary metal film can be formed on the first surface and the second surface of the glass substrate 10 by means including but not limited to magnetron sputtering. The material of the auxiliary metal film includes but is not limited to at least one of nickel (Ni), molybdenum (Mo) alloy, and titanium (Ti) alloy, for example, MoNb is used, and the thickness of the auxiliary metal film is about 2nm-20nm.

[0072] (2) Electroplating hole filling: Place the glass substrate 10 on the electroplating machine carrier, press the power pad, place it in the hole filling electroplating tank (special hole filling electrolyte is used in the tank), add current, keep the electroplating solution on the surface of the glass substrate 10 and continue to flow rapidly. The cations in the electroplating solution on the inner wall of the first connecting via 11 obtain electrons and become atoms and deposit on the inner wall. Through the special hole filling electrolyte with a special ratio, it is possible to deposit metal copper mainly in the first connecting hole at a high speed (deposition rate 0.5-3um / min), while the first surface and the second surface of the glass substrate 10 are flat areas, and the deposition rate of metal copper on these two surfaces is extremely low (0.005-0.05um / min). As time goes by, the metal copper on the inner wall of the first connecting hole gradually grows thicker, and even the first connecting via 1111 can be completely filled, that is, the connection part of the inductor L coil is formed (that is, the spiral area of ​​the inductor L is prepared), and finally the glass is taken out and cleaned with deionized water.

[0073] (3) First surface metal patterning: The glass substrate 10 is turned over (first surface facing upward), and the metal copper layer on the first surface is coated with glue, exposed, and developed, and then copper wet etching is performed. After etching, the strip is removed, and the first surface metal patterning is completed. At this time, the first substructure 211 of the inductor L line located on the first surface is formed.

[0074] (4) Second surface metal patterning: The glass substrate 10 is turned over (the second surface faces upward), and the metal copper layer on the second surface is coated with glue, exposed, and developed, and then wet-etched with copper. After etching, the glue is stripped off, and the second surface metal patterning is completed. At this time, the second substructure 212 of the inductor L coil 21 and the first electrode 31 of the second capacitor C2 located on the second surface are formed.

[0075] In some examples, after (3) first surface metal patterning and before (4) second surface metal patterning in step two, a first protective layer 60 is formed on the first surface of the glass substrate 10 on which the first substructure 211 of the inductor L coil is formed to prevent the first substructure 211 from being oxidized due to exposure.

[0076] The material of the first protective layer 60 is an inorganic insulating material. For example, the first protective layer 60 is an inorganic insulating layer formed of silicon nitride (SiNx), or an inorganic insulating layer formed of silicon oxide (SiO2), or a stacked composite film layer of a SiNx inorganic insulating layer and a SiO2 inorganic insulating layer.

[0077] S13, on the glass substrate 10 after completing step S12, a P-type semiconductor layer, an intrinsic semiconductor layer, an N-type semiconductor layer and a second electrode plate of the second capacitor C2 are formed, such as Figure 6 shown.

[0078] In some examples, step S13 may include sequentially depositing a P-type semiconductor film, an intrinsic semiconductor film, an N-type semiconductor film, and a second metal film on the side of the first plate 31 of the second capacitor C2 away from the glass substrate 10, applying glue, exposing, developing, and then wet etching, stripping after etching, and simultaneously forming a pattern including a P-type semiconductor layer, an intrinsic semiconductor layer, an N-type semiconductor layer, and a second plate of the second capacitor C2. In some examples, the material of the second metal film may be the same as that of the first metal film, so it will not be repeated here. The material of the P-type semiconductor film may be P-amorphous silicon, the intrinsic semiconductor film may be amorphous silicon, and the material of the N-type semiconductor film may be N-amorphous silicon.

[0079] S14, forming a first interlayer dielectric layer 40 on the glass substrate 10 after completing step S13, and forming a second connecting via 41, a third connecting via 42, a fourth connecting via 43 and a fifth connecting via 44 penetrating the first interlayer dielectric layer 40, as shown in FIG. Figure 7As shown. The second connecting via 41 is used to connect the first lead end 22 of the inductor L coil with the signal input terminal Input to be formed; the third connecting via 42 is used to connect the second plate 32 of the second capacitor C2 with the signal output terminal Output to be formed; the fourth connecting via 43 is used to connect the second plate 32 of the second capacitor C2 with the first bias voltage line to be formed; the fifth connecting via 44 is used to connect the first plate 31 of the second capacitor C2 with the ground terminal GND to be formed.

[0080] In some examples, step S14 may include forming a first interlayer dielectric layer 40 on the side of the second plate 32 of the second capacitor C2 facing away from the glass substrate 10 by plasma chemical vapor deposition (PECVD), then coating the first interlayer dielectric layer 40 with glue, exposing, and developing, and then dry etching, and stripping the glue after etching to obtain a second connecting via 41, a third connecting via 42, a fourth connecting via 43, and a fifth connecting via 44.

[0081] The material of the first interlayer dielectric layer 40 is an inorganic insulating material. For example, the first interlayer dielectric layer 40 is an inorganic insulating layer formed of silicon nitride (SiNx), or an inorganic insulating layer formed of silicon oxide (SiO2), or a stacked composite film layer of a SiNx inorganic insulating layer and a SiO2 inorganic insulating layer.

[0082] S15. On the glass substrate 10 after completing step S14, a signal input terminal Input, a signal output terminal Output, a first bias voltage terminal Bias and a ground terminal GND are formed; wherein the signal input terminal Input is connected to the first lead terminal 22 of the inductor L coil through the second connecting via 41; the signal output terminal Output is connected to the second electrode 32 of the second capacitor C2 through the third connecting via 4242; the first bias voltage line is connected to the second electrode 32 of the second capacitor C2 through the fourth connection; and the ground terminal GND is connected to the first electrode 31 of the second capacitor C2 through the fifth connecting via 44.

[0083] In some examples, step S15 may include depositing a third metal film by magnetron sputtering, then performing glue coating, exposure, development, and then wet etching, and stripping the glue after etching to form a pattern including a signal input terminal Input, a signal output terminal Output, a first bias voltage terminal Bias, and a ground terminal GND. The material of the third metal film may be the same as that of the first metal film side, so it is not repeated here.

[0084] S16, forming a first connection pad 51, a second connection pad 52, a third connection pad 53 and a fourth connection pad 54 on the glass substrate 10 after completing step S15. The first connection pad 51 covers the signal input terminal Input, the second connection pad 52 covers the signal output terminal Output, the third connection pad 53 covers the first bias voltage terminal Bias, and the fourth connection pad 54 covers the ground terminal GND, as shown in FIG. Figure 3 shown.

[0085] In some examples, the first connection pad 51 , the second connection pad 52 , the third connection pad 53 , and the fourth connection pad 54 include, but are not limited to, solder.

[0086] This completes the preparation of the low-pass filter.

[0087] Figure 8 is a circuit diagram of another tunable filter according to an embodiment of the present disclosure; Figure 8 As shown, the filter includes a third signal terminal, a fourth signal terminal, a fifth signal terminal, a first control signal terminal, a second control signal terminal, a first tuning unit, a second tuning unit, a first switch transistor T1, a second switch transistor T2, and a third switch transistor T3. Among them, the third signal terminal is used as a signal input terminal Input, the fourth signal terminal is used as a first signal input terminal Input, the fifth signal terminal is used as a second signal output terminal Output2, and the reference signal terminal can be a ground terminal GND. The first tuning unit includes a first inductor L1 and a third capacitor C3, which are configured to select the main frequency signal; the second tuning unit includes a second inductor L2 and a fourth capacitor C4, which are configured to cooperate with the first resonance unit to filter the variable frequency signal.

[0088] It should be noted that the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain of the transistors used are symmetrical, there is no difference between the source and drain. In the embodiments of the present disclosure, in order to distinguish the source and drain of the transistor, one of the electrodes is called the first electrode, the other electrode is called the second electrode, and the gate is called the control electrode. In addition, transistors can be divided into N-type and P-type according to the characteristics of the transistor. The following embodiments are described with N-type transistors. When N-type transistors are used, the first electrode is the source of the N-type transistor, the second electrode is the drain of the N-type transistor, and when the gate inputs a high level, the source and drain are turned on, and the P-type is the opposite. It can be imagined that the use of P-type transistors is something that a person skilled in the art can easily think of without paying creative labor, so it is also within the scope of protection of the embodiments of the present disclosure. Among them, since the transistors used in the embodiments of the present disclosure are N-type transistors, the working level signal in the embodiments of the present disclosure refers to a high level signal, and the non-working level signal is a low level signal.

[0089] For details, please refer to Figure 8 In the tunable filter, the first lead terminal 22 of the first inductor L1 is connected to the signal input terminal Input, the second lead terminal 23 of the first inductor L1 is connected to the first plate 31 of the third capacitor C3; the second plate 32 of the third capacitor C3 is connected to the source of the first switch transistor T1; the drain of the first switch transistor T1 is connected to the first signal output terminal Output1; the gate of the first switch transistor T1 is connected to the first control signal terminal and the source of the second switch transistor T2; the drain of the second switch transistor T2 is connected to the ground terminal GND; the gate of the second switch transistor T2 is connected to the second control signal terminal and the gate 103 of the third switch transistor T3; the source of the third switch transistor T3 is connected to the second plate 32 of the third capacitor C3; the drain of the third switch transistor T3 is connected to the second plate 32 of the fourth capacitor C4; the first plate 31 of the fourth capacitor C4 is connected to the second lead terminal 23 of the second inductor L2; the first lead terminal 22 of the second inductor L2 is connected to the second signal output terminal Output2.

[0090] For example: when a high-level signal is input to the first control signal terminal and a low-level signal is input to the second control signal terminal, the first switch transistor T1 is turned on, and the second switch transistor T2 and the third switch transistor T3 are turned off; the signal input to the signal input terminal Input is output through the first resonant unit (the first inductor L1 and the third capacitor C3) through the first signal output terminal Output1. When a high-level signal is input to the second control signal terminal and a low-level signal is input to the first control signal terminal, the second switch transistor T2 and the third switch transistor T3 are turned on, and the first switch transistor T1 is turned off; at this time, the signal input to the signal input terminal Input is output through the first tuning unit (the first inductor L1 and the third capacitor C3) and the second tuning unit (the second inductor L2 and the fourth capacitor C4) through the second output terminal, thereby realizing the screening of the variable frequency signal.

[0091] In order to make the specific structure of the filter clearer, the specific structure of each film layer structure of the filter is described below. Among them, the first inductor L1 and the third capacitor C3 in the first resonance unit of the filter, the second inductor L2 and the fourth capacitor C4 in the second resonance unit; the first switch transistor T1, the second switch transistor T2, and the third switch transistor T3 can all be integrated on the glass base 10. For example: the first inductor L1 and the second inductor L2 both adopt a serpentine coil structure and are arranged on the glass base 10. The first plate 31 of the third capacitor C3 and the first plate 31 of the fourth capacitor C4 can be arranged in the same layer as the first inductor L1 and the second inductor L2, and the same material is used. At the same time, the source and drain 81 of the first switch transistor T1, the source and drain 82 of the second switch transistor T2, and the source and drain 83 of the third switch transistor T3 can also be arranged in this layer structure. A second interlayer dielectric layer, as well as an active layer 91 of the first switch transistor T1, an active layer 92 of the second switch transistor T2, and an active layer 93 of the third switch transistor T3, are formed on the side of the first electrode plate 31 of the third capacitor C3 and the first electrode plate 31 of the fourth capacitor C4 away from the glass substrate 10. A second electrode plate 32 of the third capacitor C3, a second electrode plate 32 of the fourth capacitor C4, and a gate of the first switch transistor T1, a gate of the second switch transistor T2, and a gate 103 of the third switch transistor T3 are formed on the side of the second interlayer dielectric layer away from the glass substrate 10. A first interlayer dielectric layer 40 is formed on the side of the layer where the second electrode plate 32 of the third capacitor C3, the second electrode plate 32 of the fourth capacitor C4, and the gate of the first switch transistor T1, the gate of the second switch transistor T2, and the gate 103 of the third switch transistor T3 are located away from the glass substrate 10. A signal input terminal Input, a first signal output terminal Output1, a second signal output terminal Output2, a first control signal terminal and a second control signal terminal are formed on the side of the first interlayer dielectric layer 40 away from the glass substrate 10; the signal input terminal Input is connected to the first lead terminal 22 of the first inductor L1 through a sixth connecting via penetrating the first interlayer dielectric layer 40; the first signal output terminal Output1 is connected to the second electrode 32 of the third capacitor C3 through a seventh connecting via penetrating the first interlayer dielectric layer 40; the second signal output terminal Output2 is connected to the first lead terminal 22 of the second inductor L2 through an eighth connecting via penetrating the first interlayer dielectric layer 40; the first control signal terminal is connected to the gate of the first switching transistor T1 through a ninth connecting via penetrating the first interlayer dielectric layer 40; the second control signal terminal is connected to the gate of the second switching transistor T2 and the gate 103 of the third switching transistor T3 through a tenth connecting via penetrating the first interlayer dielectric layer 40.The fifth connecting pad 55, the sixth connecting pad 56, the seventh connecting pad 57, the eighth connecting pad 58 and the ninth connecting pad 59 on the side of the layer where the signal input terminal Input, the first signal output terminal Output1, the second signal output terminal Output2, the first control signal terminal and the second control signal terminal are located away from the glass base 10; the fifth connecting pad 55 covers the side of the signal input terminal Input away from the substrate substrate; the sixth connecting pad 56 covers the side of the first signal output terminal Output1 away from the substrate substrate; the seventh connecting pad 57 covers the side of the second signal output terminal Output2 away from the substrate substrate; the eighth connecting pad 58 covers the side of the first control signal terminal away from the substrate substrate; the ninth connecting pad 59 covers the side of the second control signal terminal away from the substrate substrate.

[0092] In some examples, in order to realize a small-sized filter, the glass substrate 10 may be processed to form a three-dimensional inductor L to reduce the size of the filter. That is, the first inductor L1 and the second inductor L2 in the filter may also adopt the above-mentioned Figure 2 structure, that is, a three-dimensional inductor L structure is adopted. Figure 9a for Figure 8 The layout of the tunable filter is shown; Figure 9b for Figure 8 A cross-sectional view of the tunable filter shown; Figure 9a and Figure 9bAs shown, the glass substrate 10 has a first connection via 11 that runs through the thickness direction thereof. The first inductor L1 and the second inductor L2 both include a first substructure 211 disposed on the first surface of the glass substrate 10, a second substructure 212 disposed on the second surface, and a first connection electrode 213 disposed in the first connection via 11. The first plate 31 of the third capacitor C3 and the first plate 31 of the fourth capacitor C4 can be disposed in the same layer as the second substructure 212 of the first inductor L1 and the second substructure 212 of the second inductor L2, and use the same material. At the same time, the source and drain 81 of the first switch transistor T1, the source and drain 82 of the second switch transistor T2, and the source and drain 83 of the third switch transistor T3 can also be disposed in this layer structure. A second interlayer dielectric layer, as well as an active layer 91 of the first switch transistor T1, an active layer 92 of the second switch transistor T2, and an active layer 93 of the third switch transistor T3 are formed on the side of the first plate 31 of the third capacitor C3 and the first plate 31 of the fourth capacitor C4 that are away from the glass substrate 10. The second plate 32 of the third capacitor C3, the second plate 32 of the fourth capacitor C4, and the gate 103 of the first switch transistor T1, the gate 103 of the second switch transistor T2 are formed on the side of the second interlayer dielectric layer away from the glass substrate 10. The first interlayer dielectric layer 40 is formed on the side of the layer where the second plate 32 of the third capacitor C3, the second plate 32 of the fourth capacitor C4, and the gate 103 of the first switch transistor T1, the gate 103 of the second switch transistor T2 are located away from the glass substrate 10. A signal input terminal Input, a first signal output terminal Output1, a second signal output terminal Output2, a first control signal terminal and a second control signal terminal are formed on the side of the first interlayer dielectric layer 40 away from the glass substrate 10; the signal input terminal Input is connected to the first lead terminal 22 of the first inductor L1 through a sixth connecting via penetrating the first interlayer dielectric layer 40; the first signal output terminal Output1 is connected to the second electrode 32 of the third capacitor C3 through a seventh connecting via penetrating the first interlayer dielectric layer 40; the second signal output terminal Output2 is connected to the first lead terminal 22 of the second inductor L2 through an eighth connecting via penetrating the first interlayer dielectric layer 40; the first control signal terminal is connected to the gate of the first switch transistor T1 through a ninth connecting via penetrating the first interlayer dielectric layer 40; the second control signal terminal is connected to the gate of the second switch transistor T2 and the gate 103 of the third switch transistor T3 through a tenth connecting via penetrating the first interlayer dielectric layer 40.The fifth connecting pad 55, the sixth connecting pad 56, the seventh connecting pad 57, the eighth connecting pad 58 and the ninth connecting pad 59 on the side of the signal input terminal Input, the first signal output terminal Output1, the second signal output terminal Output2, the first control signal terminal and the second control signal terminal where the layer is located away from the glass base 10; the fifth connecting pad 55 covers the side of the signal input terminal Input away from the substrate substrate; the sixth connecting pad 56 covers the side of the first signal output terminal Output1 away from the substrate substrate; the seventh connecting pad 57 covers the side of the second signal output terminal Output2 away from the substrate substrate; the eighth connecting pad 58 covers the side of the first control signal terminal away from the substrate substrate; the ninth connecting pad 59 covers the side of the second control signal terminal away from the substrate substrate.

[0093] To make it clearer Figure 8 The structure of the tunable filter shown is described below in conjunction with a method for preparing the filter with this structure.

[0094] S21, providing a glass substrate 10, and forming a first connecting via hole 11 on the glass substrate 10 that runs through the thickness direction thereof, such as Fig.10a and Fig.10b shown.

[0095] In some examples, step 21 may be performed in the same manner as the above-mentioned step S11, and thus will not be repeated here.

[0096] S22, forming a first substructure 211 of the inductor L coil on the first surface of the glass substrate 10 after completing step S21, forming a second substructure 212, a first electrode plate 31 of the third capacitor C3, a first electrode plate 31 of the fourth capacitor C4, a source and a drain 81 of the first switch transistor T1, a source and a drain 82 of the second switch transistor T2, a source and a drain 83 of the third switch transistor T3, and a first connection electrode 213 located in the first connection via 11 on the second surface, as shown in FIG. Fig.11a and Fig.11b shown.

[0097] In some examples, step S22 may be the same as the process of step S12 described above, except that the first plate 31 of the third capacitor C3, the first plate 31 of the fourth capacitor C4, the source and drain 81 of the first switch transistor T1, the source and drain 82 of the second switch transistor T2, and the source and drain 83 of the third switch transistor T3 are formed while forming the second substructure 212 on the second surface. The detailed process steps of step S22 are not described in detail.

[0098] S23, forming an active layer 91 of the first switch transistor T1, an active layer 92 of the second switch transistor T2, and an active layer 93 of the third switch transistor T3 on the glass substrate 10 after completing step S22. Fig.12a As shown in FIG. 12 b , a second interlayer dielectric layer is formed on the side of the active layer 91 of the first switch transistor T1 , the active layer 92 of the second switch transistor T2 , and the active layer 93 of the third switch transistor T3 away from the glass substrate 10 .

[0099] It should be noted that the second interlayer dielectric layer serves as an intermediate medium between the first electrode plate 31 and the second electrode plate of the third capacitor C3, and also serves as an intermediate medium between the first electrode plate 31 and the second electrode plate of the fourth capacitor C4. Therefore, the second interlayer dielectric layer can also be arranged only at the positions of the first electrode plate 31 of the third capacitor C3 and the first electrode plate 31 of the fourth capacitor C4. Of course, the second interlayer dielectric layer can also cover the active layer 91 of the first switch transistor T1, the active layer 92 of the second switch transistor T2, the active layer 93 of the third switch transistor T3, and the active layer 91 of the first switch transistor T1, the active layer 92 of the second switch transistor T2, the first electrode plate 31 of the third capacitor C3, and the first electrode plate 31 of the fourth capacitor C4. In this way, there is no need to form an interlayer insulating layer on the side of the active layer 91 of the first switch transistor T1, the active layer 92 of the second switch transistor T2, and the active layer 93 of the third switch transistor T3 away from the glass substrate 10. In the embodiment of the present disclosure, the second interlayer dielectric layer may also cover the active layer 91 of the first switch transistor T1, the active layer 92 of the second switch transistor T2, the active layer 93 of the third switch transistor T3, as well as the active layer 91 of the first switch transistor T1, the active layer 92 of the second switch transistor T2, the first plate 31 of the third capacitor C3, and the first plate 31 of the fourth capacitor C4 as an example for explanation.

[0100] In some examples, step S23 may include using plasma chemical vapor deposition to deposit a semiconductor material layer, applying glue on the semiconductor material layer, exposing, developing, and then dry etching, and stripping the glue after etching to obtain a pattern including an active layer 91 of the first switch transistor T1, an active layer 92 of the second switch transistor T2, and an active layer 93 of the third switch transistor T3. Afterwards, a second interlayer dielectric layer is deposited using plasma chemical vapor deposition. The material of the semiconductor material layer includes but is not limited to metal oxides, polycrystalline silicon, amorphous silicon, etc. The material of the second interlayer dielectric layer may be the same as the material of the first interlayer dielectric layer 40 described above.

[0101] S24, forming the gate of the first switch transistor T1, the gate of the second switch transistor T2, the gate 103 of the third switch transistor T3, the second plate 32 of the third capacitor C3, and the second plate 32 of the fourth capacitor C4 on the glass substrate 10 after completing step S23. In some examples, in step S24, the fourth metal film can be deposited by magnetron sputtering, and then coated, exposed, developed, and then wet-etched, and the strip is stripped after etching to form a pattern including the gate of the first switch transistor T1, the gate of the second switch transistor T2, the gate 103 of the third switch transistor T3, the second plate 32 of the third capacitor C3, and the second plate 32 of the fourth capacitor C4; Figure 9a and Figure 9b shown.

[0102] The material of the fourth metal film may be the same as that of the first metal film, so it will not be described again.

[0103] S25, forming a first interlayer dielectric layer 40 on the glass substrate 10 after completing step S24, and forming a sixth connecting via, a seventh connecting via, an eighth connecting via, a ninth connecting via and a tenth connecting via. Among them, the sixth connecting via is used to connect the signal input terminal Input to be formed with the first lead terminal 22 of the first inductor L1; the seventh connecting via is used to connect the first signal output terminal Output1 to be formed with the second electrode 32 of the third capacitor C3; the eighth connecting via is used to connect the second signal input terminal Input to be formed with the first lead terminal 22 of the second inductor L2; the ninth connecting via is used to connect the first control signal terminal to be formed with the gate of the first switch transistor T1; the tenth connecting via is used to connect the second control signal terminal to be formed with the gate of the second switch transistor T2 and the gate 103 of the third switch transistor T3.

[0104] In some examples, step S25 may include forming a first interlayer dielectric layer 40 on the side of the second plate 32 of the second capacitor C2 facing away from the glass substrate 10 by plasma chemical vapor deposition (PECVD), then coating the first interlayer dielectric layer 40 with glue, exposing, and developing, and then dry etching, and stripping the glue after etching to obtain a sixth connecting via, a seventh connecting via, an eighth connecting via, a ninth connecting via, and a tenth connecting via.

[0105] The material of the first interlayer dielectric layer 40 is an inorganic insulating material. For example, the first interlayer dielectric layer 40 is an inorganic insulating layer formed of silicon nitride (SiNx), or an inorganic insulating layer formed of silicon oxide (SiO2), or a stacked composite film layer of a SiNx inorganic insulating layer and a SiO2 inorganic insulating layer.

[0106] S26, on the glass substrate 10 after completing step S25, a signal input terminal Input, a first signal output terminal Output1, a second signal output terminal Output2, a first control signal terminal and a second control signal terminal are formed; the signal input terminal Input is connected to the first lead terminal 22 of the first inductor L1 through the sixth connecting via hole penetrating the first interlayer dielectric layer 40; the first signal output terminal Output1 is connected to the second electrode plate 32 of the third capacitor C3 through the seventh connecting via hole penetrating the first interlayer dielectric layer 40; the second signal output terminal Output2 is connected to the first lead terminal 22 of the second inductor L2 through the eighth connecting via hole penetrating the first interlayer dielectric layer 40; the first control signal terminal is connected to the gate of the first switch transistor T1 through the ninth connecting via hole penetrating the first interlayer dielectric layer 40; the second control signal terminal is connected to the gate of the second switch transistor T2 and the gate 103 of the third switch transistor T3 through the tenth connecting via hole penetrating the first interlayer dielectric layer 40, as shown in FIG. Figure 9a and Figure 9b shown.

[0107] In some examples, step S15 may include depositing a third metal film by magnetron sputtering, then performing glue coating, exposure, development, and subsequent wet etching, and stripping the glue after etching to form a pattern including a signal input terminal Input, a first signal output terminal Output1, a second signal output terminal Output2, a first control signal terminal, and a second control signal terminal. The material of the third metal film may be the same as that of the first metal film side, so it is not repeated here.

[0108] S27, forming a fifth connection pad 55, a sixth connection pad 56, a seventh connection pad 57, an eighth connection pad 58 and a ninth connection pad 59 on the glass substrate 10 after completing step S26, as shown in FIG. Figure 9a and Figure 9b As shown. Among them, the fifth connection pad 55 covers the side of the signal input terminal Input away from the substrate substrate; the sixth connection pad 56 covers the side of the first signal output terminal Output1 away from the substrate substrate; the seventh connection pad 57 covers the side of the second signal output terminal Output2 away from the substrate substrate; the eighth connection pad 58 covers the side of the first control signal terminal away from the substrate substrate; the ninth connection pad 59 covers the side of the second control signal terminal away from the substrate substrate.

[0109] In some examples, the fifth connection pad 55 , the sixth connection pad 56 , the seventh connection pad 57 , the eighth connection pad 58 , and the ninth connection pad 59 include, but are not limited to, solder.

[0110] Completed Figure 8 The preparation of the tunable filter is shown.

[0111] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present invention, but the present invention is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A tunable filter, comprising: A base substrate, which has a first surface and a second surface arranged opposite to each other along a thickness direction thereof; the base substrate has a first connecting via hole penetrating along the thickness direction thereof; The substrate includes a glass base; At least one inductor and at least one capacitor are arranged on the substrate; wherein each of the at least one inductor includes a first substructure arranged on the first surface, a second substructure arranged on the second surface, and a first connecting electrode arranged in the first connecting via, and the first connecting electrode connects the first substructure and the second substructure; The at least one capacitor includes a first capacitor and a second capacitor; the number of the inductor is one; The first lead end of the inductor is connected to the first signal end, the second lead end of the inductor is connected to the second signal end and the first plate of the first capacitor; the second plate of the first capacitor is connected to the second plate of the second capacitor and the first bias voltage end; The first plate of the second capacitor is connected to the second bias voltage terminal.

2. The tunable filter according to claim 1, wherein: The first plate and the second plate of the second capacitor are arranged in sequence along a direction away from the substrate; the second capacitor also includes a P-type semiconductor layer, an intrinsic semiconductor layer and an N-type semiconductor layer which are stacked and located between the first plate and the second plate.

3. The tunable filter according to claim 2, wherein: The second substructure of the inductor, the first electrode plate of the first capacitor and the first electrode plate of the second capacitor are arranged in the same layer and made of the same material; and / or, The first electrode plate of the first capacitor and the second electrode plate of the second capacitor are arranged in the same layer and made of the same material.

4. The tunable filter according to claim 2 or 3, wherein: A first interlayer dielectric layer is provided on a side of the second plate of the second capacitor away from the base substrate, and the first signal terminal, the second signal terminal, the first bias voltage terminal and the second bias voltage terminal are formed on a side of the first interlayer dielectric layer away from the base substrate; The first signal terminal is connected to the first lead terminal of the inductor through a second connecting via penetrating the first interlayer dielectric layer; the second signal terminal is connected to the second plate of the second capacitor through a third connecting via penetrating the first interlayer dielectric layer; the first bias voltage terminal is connected to the second plate of the second capacitor through a fourth connecting via penetrating the first interlayer dielectric layer; and the second bias voltage terminal is connected to the first plate of the second capacitor through a fifth connecting via penetrating the first interlayer dielectric layer.

5. The tunable filter according to claim 4, wherein: It also includes a first connection pad, a second connection pad, a third connection pad and a fourth connection pad located on a side of the layer where the first signal terminal, the second signal terminal, the first bias voltage terminal and the second bias voltage terminal are located away from the substrate; The first connecting pad covers the side of the first signal end away from the substrate; the second connecting pad covers the side of the second signal end away from the substrate; the third connecting pad covers the side of the first bias voltage end away from the substrate; the fourth connecting pad covers the side of the second bias voltage end away from the substrate.

6. The tunable filter according to claim 1, wherein: The at least one inductor includes a first inductor and a second inductor; the at least one capacitor includes a third capacitor and a fourth capacitor; The adjustable filter comprises a first resonant unit and a second resonant unit, a first switch transistor, a second switch transistor, and a third switch transistor; wherein the first resonant unit comprises a first inductor and a third capacitor; and the second resonant unit comprises a second inductor and a fourth capacitor; The first lead end of the first inductor is connected to the third signal end, and the second lead end of the first inductor is connected to the first plate of the third capacitor; the second plate of the third capacitor is connected to the first electrode of the first switch transistor; the second electrode of the first switch transistor is connected to the fourth signal end; the control electrode of the first switch transistor is connected to the first control signal end and the first electrode of the second switch transistor; the second electrode of the second switch transistor is connected to the reference voltage end; the control electrode of the second switch transistor is connected to the second control signal end and the control electrode of the third switch transistor; the first electrode of the third switch transistor is connected to the second plate of the third capacitor; the second electrode of the third switch transistor is connected to the second plate of the fourth capacitor; the first plate of the fourth capacitor is connected to the second lead end of the second inductor; and the first lead end of the second inductor is connected to the fifth signal end.

7. The tunable filter according to claim 6, wherein: The second substructure of the first inductor, the second substructure of the second inductor, the first electrode plate of the third capacitor, the first electrode plate of the fourth capacitor, the first electrode and the second electrode of the first switching transistor, the first electrode and the second electrode of the second switching transistor, and the first electrode and the second electrode of the third switching transistor are arranged in the same layer and made of the same material; and / or, The second plate of the third capacitor, the second plate of the fourth capacitor, the control electrode of the first switch transistor, the control electrode of the second switch transistor, and the control electrode of the third switch transistor are arranged in the same layer and made of the same material.

8. The tunable filter according to claim 6 or 7, wherein: A first interlayer dielectric layer is provided on a side of the second plate of the second capacitor away from the base substrate, and the third signal terminal, the fourth signal terminal, the fifth signal terminal, the first control signal terminal, and the second control signal terminal are formed on a side of the first interlayer dielectric layer away from the base substrate; The third signal terminal is connected to the first lead terminal of the first inductor through the sixth connecting via penetrating the first interlayer dielectric layer; the fourth signal terminal is connected to the second plate of the third capacitor through the seventh connecting via penetrating the first interlayer dielectric layer; the fifth signal terminal is connected to the first lead terminal of the second inductor through the eighth connecting via penetrating the first interlayer dielectric layer; the first control signal terminal is connected to the control electrode of the first switching transistor through the ninth connecting via penetrating the first interlayer dielectric layer; the second control signal terminal is connected to the control electrode of the second switching transistor and the control electrode of the third switching transistor through the tenth connecting via penetrating the first interlayer dielectric layer.

9. The tunable filter according to claim 8, wherein: It also includes a fifth connecting pad, a sixth connecting pad, a seventh connecting pad, an eighth connecting pad and a ninth connecting pad located on a side of the layer where the third signal terminal, the fourth signal terminal, the fifth signal terminal, the first control signal terminal and the second control signal terminal are located away from the substrate; The fifth connecting pad covers the side of the third signal terminal away from the substrate substrate; the sixth connecting pad covers the side of the fourth signal terminal away from the substrate substrate; the seventh connecting pad covers the side of the fifth signal terminal away from the substrate substrate; the eighth connecting pad covers the side of the first control signal terminal away from the substrate substrate; the ninth connecting pad covers the side of the second control signal terminal away from the substrate substrate.

10. A method for preparing a tunable filter, comprising: A base substrate is provided, wherein the base substrate has a first surface and a second surface arranged opposite to each other along a thickness direction thereof; and the base substrate has a first connecting via hole penetrating along the thickness direction thereof; At least one inductor and at least one capacitor are integrated on the substrate; wherein, Forming the inductor comprises: A first substructure of the inductor is formed on the first surface, a second substructure of the inductor is formed on the second surface, and a first connecting electrode is formed in the first connecting via hole; the first connecting electrode connects the first substructure and the second substructure to form a coil structure of the inductor; The at least one capacitor includes a first capacitor and a second capacitor; the number of the inductor is one; The first lead end of the inductor is connected to the first signal end, the second lead end of the inductor is connected to the second signal end and the first plate of the first capacitor; the second plate of the first capacitor is connected to the second plate of the second capacitor and the first bias voltage end; the first plate of the second capacitor is connected to the second bias voltage end.

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