Integrated planar-channel gate power mosfet

Abstract

A transistor device and method of manufacturing the same includes a heavily doped substrate of a first conductivity type and an epitaxial layer of a lightly doped first conductivity type on top of the substrate. A body region doped with a second conductivity type is formed in the epitaxial layer, wherein the second conductivity type is opposite to the first conductivity type, and a source region doped with the first conductivity type is formed in the body region of the epitaxial layer. An integrated planar channel gate having a planar gate portion is formed on a surface of the epitaxial layer, which is connected with a gate channel portion formed in the epitaxial layer.

Description

TECHNICAL FIELD

[0001] Various aspects of the present invention relate generally to transistors, and more particularly to vertical double-diffused metal-oxide-semiconductor (VDMOS) field effect transistors and channel-gated metal-oxide-semiconductor field effect transistors (MOSFETs). BACKGROUND

[0002] The consumer market demands smaller devices. In addition, computing power and performance increase as the number of transistors that can be installed on a single wafer increases. Reducing transistor pitch, reducing on-resistance (Rdson), can reduce cooling requirements and power consumption.

[0003] Currently, there is a limit to the pitch of planar transistors for high voltage applications. As the distance between body regions sharing a gate decreases, the lateral depletion rate of charge carriers in the JFET region between the two body regions increases. This results in an increase in resistance from drain to source (RDS). One solution to this problem is to increase the doping concentration of the JFET region, but the resulting size reduction is limited.

[0004] It is with respect to these and other general considerations that the various embodiments of the present invention have been made. SUMMARY

[0005] A transistor device is disclosed, comprising: a heavily doped first conductivity type substrate; a lightly doped first conductivity type epitaxial layer formed on the substrate; a body region of a second conductivity type formed in the epitaxial layer, wherein the second conductivity type is opposite the first conductivity type; a source region of the first conductivity type formed in the epitaxial layer in the body region; an integrated planar-channel gate having a planar gate portion formed on a surface of the epitaxial layer connected to a channel gate portion formed in a channel in the epitaxial layer, wherein a depth of a bottom of the channel gate portion in the substrate is less than a lowest doping depth of the body region.

[0006] wherein the channel gate portion is formed in the body region of the epitaxial layer.

[0007] wherein further comprising a localized JFET implant region of the first conductivity type formed around a bottom and edges of the channel gate portion.

[0008] wherein the lightly doped first conductivity type region of the epitaxial layer separates the localized JFET implant from the body region.

[0009] The transistor device of claim 1, further comprising a thick insulating layer at a bottom of the channel, wherein the thick insulating layer at the bottom of the channel is thicker than the insulating layer at least one edge of the channel.

[0010] The transistor device of claim 1, wherein the epitaxial layer further comprises an optional body region pillar of the second conductivity type doped, and a lightly doped first conductivity type epitaxial layer pillar.

[0011] wherein the channel sidewall of the gate channel portion intersects the channel floor of the gate channel portion at an angle greater than 90 degrees.

[0012] wherein the gate channel portion has a channel depth between 0.3 and 0.8 microns.

[0013] wherein the insulating layer thickness at the channel floor of the gate channel portion is 1.5 to 2 times the insulating layer thickness at the channel edge.

[0014] The invention also discloses a method of making a transistor device, comprising: making a lightly doped first conductivity type epitaxial layer on a heavily doped first conductivity type substrate, wherein the first conductivity type is opposite the second conductivity type; making a channel in the epitaxial layer; making an insulating layer on the surface of the epitaxial layer and in the channel; and creating an integrated planar channel gate by forming a continuous conductive layer on the insulating layer on the surface of the epitaxial layer and in the channel.

[0015] wherein further comprising forming a thick bottom insulating layer at the channel floor prior to forming the insulating layer on the surface of the epitaxial layer and in the channel.

[0016] wherein prior to forming the insulating layer, doping the sides and floor of the channel with the first conductivity type to create a locally heavily doped first conductivity type JFET implant around the sides and floor of the channel.

[0017] wherein further doping an epitaxial region with the second conductivity line to form a body region.

[0018] wherein the channel is formed in a body region of the epitaxial layer.

[0019] wherein the body region further comprises making alternating pillars doped with the first conductivity type and the second conductivity type, respectively.

[0020] wherein the body region is doped deeper than the channel floor.

[0021] wherein further comprising making a source region in the body region of the epitaxial layer.

[0022] wherein the source layer thickness at the channel floor is 1.5 to 2 times the insulating layer thickness at the channel edge.

[0023] wherein forming the channel further comprises forming a sidewall of the channel that intersects the floor of the channel at an angle greater than 90 degrees. BRIEF DESCRIPTION OF DRAWINGS

[0024] Other features and advantages of the present application will be apparent from the following detailed description, and from the drawings.

[0025] Figure 1 A side cross-sectional view of an integrated planar-channel gate transistor device is shown, in accordance with aspects of the present application.

[0026] Figure 2 A side cross-sectional view of an alternative configuration of an integrated planar-channel gate transistor device is shown, in accordance with aspects of the present application.

[0027] Figure 3 A side cross-sectional view of a super junction transistor device with an integrated planar-channel gate is shown, in accordance with aspects of the present application.

[0028] Figure 4A A heavily doped first conductivity type ionized substrate and a more lightly doped epitaxial layer are shown, in accordance with aspects of the present application.

[0029] Figure 4B A side cross-sectional view of the preparation of a channel in an epitaxial layer for an integrated planar-channel gate transistor device is shown, in accordance with aspects of the present application.

[0030] Figure 4C A side cross-sectional view of the preparation of a localized JFET implant region is shown, in accordance with aspects of the present application.

[0031] Figure 4D A cross-sectional view of the preparation of a thick bottom insulating layer at the bottom of the channel is shown, in accordance with aspects of the present application.

[0032] Figure 4E A cross-sectional side view of the preparation of a gate insulating layer having a planar portion and a channel portion is shown, in accordance with aspects of the present application.

[0033] Figure 4F A cross-sectional side view of the formation of an integrated planar-channel gate having a continuous planar portion and a channel portion of a conductive layer is shown, in accordance with aspects of the present application.

[0034] Figure 4G A cross-sectional side view of the patterning of a conductive layer having a planar gate portion and a channel gate portion connected to form an integrated planar-channel gate is shown, in accordance with aspects of the present application.

[0035] Figure 4H A cross-sectional side view of the preparation of a body region for a transistor device having an integrated planar-channel gate is shown, in accordance with aspects of the present application.

[0036] Figure 4IA cross-sectional side view showing the fabrication of a source region for a transistor device having an integrated planar-channel gate in accordance with various aspects of the present application.

[0037] Figure 4J A cross-sectional side view showing the fabrication of other structures on an integrated planar-channel gate transistor device in accordance with various aspects of the present application. DETAILED DESCRIPTION

[0038] While the following detailed description contains many specific details for the purpose of providing a thorough understanding of the present application, it will be apparent to those skilled in the art that many variations and modifications in the details are possible without departing from the scope of the present application. Accordingly, the exemplary embodiments of the present application described herein are not intended to be limiting, but by way of illustration.

[0039] The present application relates to silicon doped with ions of a first conductivity type or a second conductivity type. The ions of the first conductivity type can be the opposite of the ions of the second conductivity type. For example, the ions of the first conductivity type can be n-type, which when doped into silicon creates charge carriers. The ions of the first conductivity type include phosphorus, antimony, bismuth, lithium, and arsenic. The ions of the second conductivity type can be p-type, which when doped into silicon creates holes for charge carriers, and in this way is referred to as being opposite n-type. The ions of the p-type include boron, aluminum, gallium, and indium. Although the above description refers to n-type as the first conductivity type and p-type as the second conductivity type, the present application is not so limited, and the p-type can be the first conductivity type and the n-type can be the second conductivity type.

[0040] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which are shown, by way of illustration, specific embodiments in which the application can be practiced. For the purposes of convenience and clarity, the use of + or - following a designation of conductivity or net impurity carrier type (p or n) generally refers to the relative concentration of net impurity carriers of the designated type within a semiconductor material. In general, n+ material has a higher concentration of n-type net dopants (e.g., electrons) than n material, and n material has a higher concentration of carriers than n- material. Similarly, p+ material has a higher concentration of p-type net dopants (e.g., holes) than p material, and p material has a higher concentration of carriers than p- material. It is noted that what is relevant is the net concentration of carriers, not necessarily the dopants. For example, a material can be heavily doped with n-type dopants, but if the material is also sufficiently counter-doped with p-type dopants, the material can still have a relatively low net carrier concentration. As used herein, a dopant concentration of less than about 10 16 / cm 3 may be considered "lightly doped," while a dopant concentration of greater than about 10 17 / cm 3 may be considered "heavily doped."

[0041] INTRODUCTION

[0042] According to various aspects of the present invention, pitch of a transistor device can be improved by creating an integrated planar channel gate having a continuous gate portion and a channel portion. The integrated planar channel gate allows for smaller planar gate dimensions and reduces R DS Previous devices have implemented a combination of planar gate and channel gate separated by an insulating layer and electrically coupled by a wire. These previous devices are made with large deep channels, thus it is not possible to form an integrated gate channel with a planar gate connected between the planar gate portion and the channel gate portion. The previous devices fill the larger channel with an insulating layer and a conductive layer resulting in a gate that is not flat enough. The intermediate insulating layer between the planar gate and the channel gate is used to create the planar gate. Due to the difficulty of aligning the channel gate and the planar gate, creating an opening through the insulating layer between the planar gate and the channel gate to electrically couple the two gates is not practical. Therefore, the planar gate and the channel gate are electrically connected using a wire instead of a direct contact between the conductive layers of the two gates. The deep channel and the indirect connection of the two gates in the prior art devices increase the complexity of the prior art devices and make it difficult to scale down the size of the prior art devices.

[0043] To solve this problem, a transistor device and a method of manufacturing the same are designed, which includes a heavily doped substrate of a first conductivity type and an epitaxial layer of a lightly doped first conductivity type on top of the substrate. A body region doped with a second conductivity type opposite to the first conductivity type is formed in the epitaxial layer, and a source region doped with the first conductivity type is formed in the body region of the epitaxial layer. The device includes an integrated planar channel gate having a planar gate portion formed on a surface of the epitaxial layer connected to a channel gate portion formed in a channel in the epitaxial layer. In some embodiments, the device can also include a local JFET implant region heavily doped with the first conductivity type formed around the bottom and sides of the channel gate portion. A region of the epitaxial layer of the lightly doped first conductivity type can separate the local JFET implant and the body region. In some embodiments, the channel gate portion can be formed in the body region of the epitaxial layer.

[0044] In some other embodiments, the bottom depth of the channel gate portion in the substrate can be less than the lowest doping depth of the body region. In other embodiments, the channel gate portion can be insulated from the epitaxial layer by a thick insulating layer at the bottom of the gate channel, which is thicker than the insulating layer on at least one side of the gate channel. In yet other embodiments, the epitaxial layer can further include alternating body region pillars doped with a second conductivity type and epitaxial layer pillars lightly doped with a first conductivity type forming a so-called super junction structure. In some embodiments, the sidewalls of the channel of the gate channel portion of the device can intersect the bottom of the channel of the gate channel portion at an angle greater than 90 degrees. The channel depth of the gate channel portion of the transistor device can be between 0.3 and 0.8 microns. In some embodiments of the invention, the thickness of the channel bottom insulating layer of the gate channel portion of the device can be 1.5 to 2 times the thickness of the insulating layer on one side of the channel.

[0045] Device

[0046] Figure 1A side cross-sectional view of an integrated planar channel gate transistor device is shown, in accordance with various aspects of the present application. As shown, the integrated planar channel gate transistor device includes a substrate 101 heavily doped with ions of a first conductivity type. An epitaxial layer 102 can be formed on top of the substrate 101. By way of example, and not limitation, the epitaxial layer 102 can be grown using epitaxial growth on the surface of the substrate 101 or otherwise deposited on the surface of the substrate. A channel 103 is formed in the epitaxial layer 102. In some embodiments, the area around the sides and bottom of the channel 103 can be heavily doped with ions of the first conductivity type, forming a local JFET implant region 108. A dielectric layer 106 is formed on the surface of the substrate to electrically insulate a planar gate portion 107 of the integrated planar channel gate from the epitaxial layer 102. The dielectric layer 106 also lines the sidewalls and bottom of the channel 103, creating an insulating layer for the sidewalls 105 and bottom 104 of the channel portion of the integrated planar channel gate. In some embodiments, the thickness of the insulating layer on the bottom 104 of the channel 103 can be 1.5 to 2 times the thickness of the insulating layer on the sides 103 of the channel, referred to herein as the thick bottom insulator. The insulating layer can be composed of a dielectric material such as silicon oxide. The planar gate portion 107 can be formed by patterning a conductive layer formed on the surface of the insulating layer 106. A portion of the conductive layer fills the portion of the channel 103 not occupied by the dielectric layer 106 and is insulated from the epitaxial layer 102 by the partial insulating layer on the sidewalls 105 and bottom 104 of the channel. The conductive layer creates the integrated planar channel gate connecting between the planar portion 107 of the gate and the channel portion 112 of the gate. The conductive layer can be composed of polysilicon or other conductive material such as titanium nitride (TiN) or tungsten. A gate contact 113 is coupled to the conductive layer 107. Due to the continuity of the planar gate portion 107 and channel gate portion 112 of the gate, the channel portion 112 does not have a separate gate contact. Instead, the channel portion 112 is held at the gate potential level due to its connection to the planar gate portion 107 of the gate. One or more body regions 109 can be formed in the epitaxial layer 102. A source region 110 can be formed in the body 109 of the epitaxial layer 102. A source contact 111 couples the source region to the source and can also include a body short contact. A drain metal 114 can be formed on the bottom of the substrate 101. A drain contact 115 can be coupled to the drain metal 114.

[0047] During operation, the gate potential at the gate contact 113 allows current to be conducted through the transistor device. For example, without limiting the N-type MOSFET configuration, current applied to the drain contact 115 is conducted through the drain metal 114, the substrate 101, and the epitaxial layer 102. Charge carriers from the epitaxial layer 102 combine with opposite charge holes in the body region 109, allowing current to be conducted to the source region 110 and the source contact 111.

[0048] Figure 2 FIG. 1 illustrates a side cross-sectional view of an integrated planar-channel gate transistor device according to various aspects of the present application. Figure 2 In the illustrated embodiment, the body regions 209 contact a localized junction field effect transistor (JFET) implant region 208. In addition, the source regions 210 are closer to the gate channel 203 than in embodiments without intersecting body regions and integrated planar-channel gates. As shown, the two body regions 209 are arranged very close to the channel 203 such that the regions intersect underneath the channel 203. The planar portion 207 of the integrated planar-channel gate is shorter than in embodiments without intersecting body regions underneath the channel. The integrated planar-channel gate and the localized JFET implant 208 allow for a reduction in pitch of the transistor device because the width of the planar portion 207 of the integrated planar-channel gate can be reduced without significantly impacting the R DS .

[0049] Figure 3 FIG. 3 illustrates a side cross-sectional view of a super junction transistor device with an integrated planar-channel gate according to various aspects of the present application. As shown, the body regions 309 of the device include pillars 320 doped with ions of a second conductivity type that terminate near the substrate 101. The epitaxial layer 302 forms pillars doped with ions of a first conductivity type. Thus, the combination of the doped body pillars 320 and the epitaxial layer regions doped with ions of the first conductivity 302 creates alternating pillars doped with ions of the first and second conductivity types, respectively, in the epitaxial layer for a super junction device.

[0050] Method of manufacture

[0051] Figures 4A-4J FIG. 4 illustrates a side cross-sectional view of a method of fabricating an integrated planar-channel gate transistor device according to various aspects of the present application. Figure 4A FIG. 5 illustrates a substrate 401 and an epitaxial layer 402 doped with ions of a first conductivity type according to various aspects of the present application. The substrate 401 can be doped with an ion concentration between 1 x 1018and 1 x 1020cm-3. The substrate can be composed of, for example, but not limited to, silicon, silicon carbide, gallium nitride, or gallium arsenide. The epitaxial layer 402 can be formed on a surface of the substrate 401. The epitaxial layer 402 can be grown on the upper surface of the epitaxial layer 401 by a process such as vapor phase epitaxy. The epitaxial layer 402 can be lightly doped with ions of the first conductivity type during or after formation. The epitaxial layer 402 can be doped with an ion concentration between 1 x 1018and 6 x 1019cm-3. 19 20 -3 The substrate can be composed of, for example, but not limited to, silicon, silicon carbide, gallium nitride, or gallium arsenide. The epitaxial layer 402 can be formed on a surface of the substrate 401. The epitaxial layer 402 can be grown on the upper surface of the epitaxial layer 401 by a process such as vapor phase epitaxy. The epitaxial layer 402 can be lightly doped with ions of the first conductivity type during or after formation. The epitaxial layer 402 can be doped with an ion concentration between 1 x 1018and 6 x 1019cm-3. 17 17 -3 ​​​​​

[0052] Figure 4B FIG. 4B illustrates a side cross-sectional view of the formation of a channel 403 in an epitaxial layer 402 for an integrated planar channel gate transistor device, according to aspects of the present disclosure. Initially, a hard mask comprising a stack of silicon oxide layer 407, silicon nitride layer 406, silicon oxide layer 405 can be deposited on the surface of the epitaxial layer 402. The oxide layers 407, 405 and nitride layer 406 can be formed by chemical vapor deposition techniques (CVD) to form Si02and silicon nitride, or by thermal oxidation process to form Si02. A mask pattern 404 is formed on the surface of the hard mask. The mask pattern 404 can be created using photolithography techniques or applied by a mechanical mask process. The mask pattern 404 includes a channel gap 408. An etching process is applied to the mask pattern and the hard mask, such as plasma dry etching or wet etching using phosphoric acid or other such selective etchants. The hard mask is etched away at the channel gap 408, exposing the epitaxial layer 402 in the channel gap. The epitaxial layer 402 can then be etched to a desired depth through the channel gap 408 by a plasma etching technique such as deep reactive ion etching (DRIE). The depth of the created channel 403 can be between 0.3 microns to 0.8 microns of the epitaxial layer. Alternatively, the depth of the channel can be selected based on desired device characteristics. A general effect of the channel depth is that as the spacing between the two P-type body regions decreases, the channel depth increases. The sides of the channel 403 can be formed at an angle such that the sides of the channel intersect the bottom of the channel at an angle greater than 90 degrees. For example, without limitation, the angle formed by one side of the channel and the channel bottom surface can be between 101 degrees and 105 degrees.

[0053] Figure 4C FIG. 4C illustrates a side cross-sectional view of the formation of a local JFET implant region 409, according to aspects of the present disclosure. As shown, a local JFET implant region 409 can be formed in the epitaxial layer 402 around the bottom and sides of the channel 403. In some embodiments, the local JFET implant region 409 can be formed by ion implantation 410 through a pattern mask and the hard mask. The local JFET implant region 411 can be heavily doped with ions of the first conductivity type. The local JFET implant region can be doped at 2 to 3 times the ion concentration of the epitaxial layer. The local JFET implant region can reduce the depletion charge carriers, thus helping to reduce the RDS of the device.

[0054] Figure 4DThis diagram illustrates a cross-sectional view of a thick bottom insulating layer 411 formed at the bottom of a channel 403 according to various aspects of the invention. The thick bottom insulating layer 411 can be formed using deposition techniques such as high-density plasma (HDP) deposition or chemical vapor deposition (CVD). The thick bottom insulating layer can consist of a silicon oxide, nitride, or ONO (SiO2 / nitride / SiO2) film. Plasma dry etching or wet etching is then applied to the sidewalls of the channel 403 to remove any excess insulating layer deposited on the channel sides. The initial thickness of the thick bottom insulating layer is between 1500 nm and... In some embodiments, the final thickness of the thick bottom insulation layer is 1.5 to 2 times the thickness of the trench sidewall insulation layer, and this final thickness is achieved after the insulation layers are formed on the trench sides and bottom, such as... Figure 4E As shown.

[0055] Figure 4E Showing a cross-sectional side view of the formation of a gate insulating layer having a planar portion 412 and a channel portion 413 according to various aspects of the invention. As shown, an insulating layer is deposited on the surface of epitaxial layer 402. The planar portion 412 of the insulating layer on the surface of epitaxial layer 402 will form part of the planar portion of the integrated planar channel gate. Insulating layer material is also deposited on the bottom and sidewalls 413 of channel 403. In an embodiment, insulating material having a thick bottom insulating layer is deposited on top of previously deposited insulating material, forming a final thickness of the thick bottom insulating layer 411. The insulating layer may be composed of silicon oxide. The thicknesses of the planar portion 412 of the insulating layer and the channel portion 413 at the bottom of channel 403 may be substantially the same, for example, between 800 and 1000 angstroms.

[0056] like Figure 4F As shown, the conductive layer includes a planar portion 415 and a channel portion 416 on the planar portion 412 of the insulating layer. The conductive layer can be deposited on the surface of the insulating layer. The channel portion 416 of the conductive layer fills the portion of the channel 413 not occupied by the insulating layer portion, including the thick-bottom insulator (optional) 411 and the insulating layer on the sides of the channel 413. The planar portion 415 of the conductive layer covers the planar portion 412 of the insulating layer. The technique described herein creates an extremely flat surface of the conductive layer on the planar portion and the channel portion of the insulating layer without forming an intermediate insulating layer between the planar portion and the channel portion.

[0057] Figure 4GA cross-sectional side view of the formation of a body region 417 of a transistor device with an integrated planar channel gate is shown, in accordance with various aspects of the present application. A mask 419 can be formed on the surface of the epitaxial layer, with an opening at the location of the body region 417. The mask can be a photoresist mask applied to the surface of the epitaxial layer. Ion implantation 418 can be used to dope the epitaxial layer 402 with ions of a second conductivity type (e.g., if the first conductivity type is n-type, then the second conductivity type is p-type). After the formation of the body region 417, the mask 419 can be removed by plasma ashing and rinsing with a removal solution or any other known mask removal technique, such as but not limited to planarization or polishing.

[0058] Figure 4H A cross-sectional side view of the formation of a body region 417 of a transistor device with an integrated planar channel gate is shown, in accordance with various aspects of the present application. A mask 419 can be formed on the surface of the epitaxial layer, with an opening at the location of the body region 417. The mask can be a photoresist mask applied to the surface of the epitaxial layer. Ion implantation 418 can be used to dope the epitaxial layer 402 with ions of a second conductivity type (e.g., if the first conductivity type is n-type, then the second conductivity type is p-type). After the formation of the body region 417, the mask 419 can be removed by plasma ashing and rinsing with a removal solution or any other known mask removal technique, such as but not limited to planarization or polishing.

[0059] In some embodiments, the body region can be formed prior to the formation of the channel and the integrated planar channel gate. In these embodiments, the channel can be formed in the body region of the epitaxial layer. Then, a local JFET implant region can be formed in the body region by counter-ion doping. This implementation of the method can be used to produce a device as shown in FIG. 4B. Figure 2 In yet another embodiment, doping pillars can be formed under the body region. These doping pillars form a super-junction device as shown in FIG. 4C. Figure 3

[0060] Figure 4I A cross-sectional side view of the formation of a source region of a transistor device with an integrated planar channel gate is shown, in accordance with various aspects of the present application. A source mask 420 can be formed on the surface of the epitaxial layer, with an opening at the location of the source region 422. One or more source regions 422 can be formed in the body region 417 of the epitaxial layer 402 by ion implantation 421 through the opening in the source mask 420. The source regions 422 can be doped with a higher concentration of ions of the first conductivity type of the epitaxial layer. After the formation of the source region 422, the source mask 420 can be removed by plasma ashing and rinsing with a removal solution or any other known mask removal technique, such as but not limited to planarization or polishing.

[0061] Figure 4J ​A cross-sectional side view showing the formation of other structures on an integrated planar channel gate transistor device according to various aspects of the present application. After the source region 422 is formed, an isolation layer 424 is formed on the surface of the epitaxial layer 402. The isolation layer can be, for example, but not limited to, silicon oxide deposited on the surface of the epitaxial layer. The isolation layer can also cover 423 the integrated gate channel, completing the insulating layer of the gate. A source contact mask is applied to the isolation layer 424 over the source region 422 and body region 417 of the epitaxial layer. The isolation layer is etched away and a source contact metal 426 is deposited on the surface of the epitaxial layer 402 over the source region 422 and body region 417. A gate contact mask is applied to the gate insulating 426, the gate contact is etched away and a gate contact metal 425 is deposited on the conductive layer 415 of the gate. The etching of the gate contact and the source contact can be performed by using a plasma dry etch. After the etching, the gate contact mask and the source contact mask can be removed by plasma ashing and using a suitable mask removal solution or any other known mask removal technique such as, but not limited to, planarization or polishing. A drain conductive layer 427 can be formed on the backside of the substrate 401. The drain conductive layer 427 can be, for example, but not limited to, a metal deposited on the backside of the substrate 401.

[0062] While the application has been described in detail with respect to certain preferred versions thereof, alternative, modified and equivalent versions thereof should become apparent to those skilled in the art. Accordingly, the scope of the present application should not be limited to the description of the above versions but should be given the full scope of the appended claims and any and all equivalents thereof. Any optional feature of the application can be set forth (regardless of whether it is preferred or not) in combination with any other feature or combination of other features of the application. In the claims, means-plus-function clauses, if used, are intended to cover the structures described herein as performing the recited function and not only structural equivalents but also equivalent structures. The benefits, advantages, solutions to problems, and any element(s) that aids in obtaining a benefit, advantage, or solution to, or is otherwise related to a problem, are inherently described throughout the specification. None of the features or benefits are intended to be critical or essential to the application unless expressly stated as being "essential" or "critical". As used herein, the terms "comprises", "comprising", or the like are not intended to exclude the presence of other elements or additional steps. It will be apparent that aspects of the application can be practiced by other than the described embodiments, which are presented for purposes of illustration and not of limitation.

Claims

1. A transistor device, characterized by, A transistor device comprising: a heavily doped substrate of a first conductivity type; an epitaxial layer of a lightly doped first conductivity type formed on the substrate; a body region of a second conductivity type formed in the epitaxial layer, wherein the second conductivity type is opposite the first conductivity type; a source region of the first conductivity type formed in the body region of the epitaxial layer; an integrated planar-channel gate having a planar gate portion formed on a surface of the epitaxial layer connected to a channel gate portion formed in a channel in the epitaxial layer, wherein a depth of a bottom of the channel gate portion in the substrate is less than a minimum doping depth of the body region; and further comprising a localized JFET implant region of the first conductivity type formed around a bottom and edges of the channel gate portion.

2. The transistor device of claim 1, wherein the channel gate portion is formed in the body region of the epitaxial layer.

3. The transistor device of claim 1, wherein a lightly doped first conductivity type region of the epitaxial layer separates the localized JFET implant and the body region.

4. The transistor device of claim 1, further comprising a thick insulating layer at a bottom of the channel, wherein the thick insulating layer at the bottom of the channel is thicker than an insulating layer at least one edge of the channel.

5. The transistor device of claim 1, wherein the epitaxial layer further comprises a body region pillar of the second conductivity type and an epitaxial layer pillar of the first conductivity type.

6. The transistor device of claim 1, wherein channel sidewalls of the channel gate portion intersect a channel floor of the channel gate portion at an angle greater than 90 degrees.

7. The transistor device of claim 1, wherein the channel gate portion has a channel depth between 0.3 and 0.8 microns.

8. The transistor device of claim 1, wherein an insulating layer thickness at a bottom of the channel of the channel gate portion is 1.5 to 2 times an insulating layer thickness at an edge of the channel.

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