Trench gate power MOSFET and manufacturing method thereof

Abstract

The present application discloses a trench-gate power MOSFET including a substrate of a wide bandgap semiconductor having a first conductivity type, an epitaxial layer grown on the substrate and having the first conductivity type, a body region formed in the epitaxial layer and having a second conductivity type, a trench etched into the body region and having a length parallel to a projection on the wafer surface of one selected crystal direction of all crystal directions of the wafer, a second conductivity type column formed by implanting first ions into a bottom region of the trench along a crystal direction of the wide bandgap semiconductor material, the bottom region of the trench being located below the trench and in contact with the bottom of the trench, and a vertical depth of the column being at least 50% or more of the thickness of the epitaxial layer located in the bottom region of the trench, and a trench gate formed by filling the trench with a filler. The present invention is advantageous in that it can improve the current capability and reliability of a trench-type MOSFET.

Description

[Technical Field]

[0001] Technical Field BACKGROUND OF THE INVENTION This application relates to the field of semiconductors, and more particularly to trench-gate power MOSFETs and methods for fabricating the same.

[0002] Background technology Semiconductor devices such as power MOSFETs are widely used in fields such as automotive electronics, switching power supplies, and industrial controls. To continuously improve power conversion efficiency and power density, designing efficient power switching devices such as power MOSFETs is crucial. The most important performance parameter of a power MOSFET is its specific on-resistance (Rsp). The magnitude of the drain-source on-resistance is directly proportional to the power consumed by the power MOSFET. For a device with the same breakdown voltage and on-resistance, a smaller specific on-resistance allows for a smaller chip area and a smaller parasitic capacitance of the power MOSFET, thereby reducing switching losses in the power conversion process. Trench-gate and super-junction power devices have lower on-resistance, which leads to lower switching losses and faster switching speeds, making them one of the most widely used power switching devices. However, trench-gate and super-junction power devices currently require high manufacturing costs and are difficult to control. Summary of the Invention

[0003] Summary of the Invention To solve the above problems in the prior art, the present invention provides a trench-gate power MOSFET and a manufacturing method thereof.

[0004] According to a first aspect, the present invention provides a trench-gate power MOSFET, the trench-gate power MOSFET being formed in a single wafer; a substrate of wide bandgap semiconductor material having a first conductivity type; an epitaxial layer grown on the substrate and having the first conductivity type; a body region formed in the epitaxial layer and having a second conductivity type; a trench etched into the body region, the length of the trench being parallel to a projection on the wafer surface of a crystal direction in which a channel effect is most pronounced among all crystal directions of the wafer; a second conductivity type column formed by implanting first ions into a bottom region of the trench that is located below the trench and in contact with the bottom of the trench along a crystal direction in which a channel effect of the wide bandgap semiconductor material is most pronounced, the column having a vertical depth of 50% or more of the thickness of the epitaxial layer located in the bottom region of the trench; and a trench gate formed by filling the trench with a filler.

[0005] In one possible embodiment of the first aspect, the power trench-gate power MOSFET further includes a connecting body having the second conductivity type between the second conductivity type column and the body region, one end of the connecting body being electrically connected to the body region and the other end of the connecting body being electrically connected to the second conductivity type column.

[0006] In one possible embodiment of the first aspect, the trench-gated power MOSFET further includes a drain located below the substrate, a gate located on a central axis of the body region, and sources located on both sides of the gate.

[0007] In one possible embodiment of the first aspect, in the power trench-gate power MOSFET, the epitaxial layer is a single epitaxial layer.

[0008] In one possible embodiment of the first aspect, in the power trench-gated power MOSFET, the epitaxial layer includes a first epitaxial layer and a second epitaxial layer, the first epitaxial layer is located below the second epitaxial layer, the thickness of the first epitaxial layer is smaller than the thickness of the second epitaxial layer, the doping concentration of the first epitaxial layer is smaller than the doping concentration of the second epitaxial layer, the bottom of the trench and the second conductivity type column are located in the second epitaxial layer, and a vertical depth of the second conductivity type column is 50% or more of the thickness of the second epitaxial layer located in the bottom region of the trench.

[0009] In one possible embodiment of the first aspect, in the trench gate power MOSFET, the wide bandgap semiconductor material is silicon carbide.

[0010] In one possible embodiment of the first aspect, in the trench gate power MOSFET, the silicon carbide includes 4H—SiC or 6H—SiC.

[0011] In one possible embodiment of the first aspect, in the trench-gate power MOSFET, the ratio of the depth of the trench to the width of the trench is in the range of 1:1 to 5:1.

[0012] In one possible embodiment of the first aspect, in the trench gate power MOSFET, an oxide is formed on an inner surface of the trench.

[0013] In one possible embodiment of the first aspect, in the trench-gate power MOSFET, the filling includes polycrystalline silicon.

[0014] In one possible embodiment of the first aspect, in the trench-gate power MOSFET, the first ions include aluminum ions, and the first ions are implanted in at least two separate doses, i.e., with a first dose and a first energy and a second dose and a second energy, into the bottom region of the trench along the C-axis direction of the silicon carbide crystalline body.

[0015] According to a second aspect, the present invention provides a method for producing a trench-gate power MOSFET in a wafer, the method comprising: growing an epitaxial layer having a first conductivity type on a wide bandgap semiconductor substrate; forming a body region having a second conductivity type in the epitaxial layer; forming a trench by etching in the body region, the length of the trench being parallel to a projection on the wafer surface of a crystal direction in which a channel effect is most pronounced among all crystal directions of the wafer; forming a second conductivity type column by implanting first ions into a bottom region of the trench along a crystal direction in which a channel effect of the wide bandgap semiconductor material is most pronounced, the bottom region of the trench being located below the trench and in contact with the bottom of the trench, and the vertical depth of the second conductivity type column being 50% or more of a thickness of the epitaxial layer located at the bottom region of the trench; and filling the trench with a filler.

[0016] In one possible embodiment of the second aspect, in the manufacturing method, forming a trench by etching in the body region further includes implanting first ions into the body region and the epitaxial layer to form a connector having the second conductivity type, one end of the connector being electrically connected to the body region and the other end of the connector being electrically connected to the second conductivity type column, and a depth of the connector being equal to or greater than a depth of the trench.

[0017] In one possible embodiment of the second aspect, in the manufacturing method, the wide band gap semiconductor material is silicon carbide, and the crystal direction in which the channel effect of the wide band gap semiconductor material is most prominent is the C-axis direction of the silicon carbide crystal.

[0018] In one possible embodiment of the second aspect, in the manufacturing method, the silicon carbide includes 4H—SiC or 6H—SiC.

[0019] In one possible embodiment of the second aspect, in the manufacturing method, the step of implanting first ions into a bottom region of the trench along a crystal direction in which a channel effect of the wide bandgap semiconductor material is most pronounced includes: The first ions are implanted at least twice, i.e., at a first dose, a first energy, and a second dose, a second energy, into the bottom region of the trench along the C-axis direction of the silicon carbide crystal body.

[0020] In one possible embodiment of the second aspect, in the manufacturing method, the first dose is 5E13 to 5E14 atoms / cm 2 the first energy is 500 kev to 1500 kev, and the second dose is 5E12 to 5E13 atoms / cm 2 and the second energy is 50 keV to 300 keV.

[0021] In one possible embodiment of the second aspect, the manufacturing method further includes the step of growing the first epitaxial layer having the first conductivity type on the wide bandgap semiconductor substrate, and growing the second epitaxial layer having the first conductivity type on the first epitaxial layer.

[0022] In one possible embodiment of the second aspect, the manufacturing method is characterized in that a thickness of the first epitaxial layer is less than a thickness of the second epitaxial layer, and a doping concentration of the first epitaxial layer is less than a doping concentration of the second epitaxial layer.

[0023] In one possible embodiment of the second aspect, in the manufacturing method, the bottom of the trench and the second conductivity type column are located in the second epitaxial layer, and the vertical depth of the second conductivity type column is 50% or more of the thickness of the second epitaxial layer located in the bottom region of the trench.

[0024] In one possible embodiment of the second aspect, in the manufacturing method, the ratio of the depth of the trench to the width of the trench is in the range of 1:1 to 5:1.

[0025] In one possible embodiment of the second aspect, in the manufacturing method, the step of filling the trench with a filling material includes: The method includes forming an oxide on the inner surface of the trench, and then filling the trench with a filler.

[0026] In one possible embodiment of the second aspect, in the manufacturing method, the filling comprises polycrystalline silicon.

[0027] In one possible embodiment of the second aspect, in the manufacturing method, the first ions include aluminum ions.

[0028] Compared with the conventional trench-type super-junction MOSFET, the trench-gate power MOSFET of the present invention has a second conductivity type column, such as a deep P column, below the trench, which not only protects the bottom of the trench but also serves as a charge balance P column in the super-junction. At the same time, the specific on-resistance Rsp is reduced, thereby reducing the chip area, the parasitic capacitance of the power MOSFET, and the switching loss in the power conversion process of the power MOSFET.

[0029] According to the manufacturing method of the present invention, deep P columns are formed by implanting high-energy ions. Unlike conventional techniques that implant ions along the normal direction of the wafer, the manufacturing method of the present invention implants ions along a specific crystal direction of the semiconductor material (in the case of silicon carbide wafers, implantation along the C-axis). Due to the channel effect of the crystal, for a similar implantation depth, the implantation energy ranges from several tens of Kev to over a thousand Kev. This significantly reduces the implantation energy compared to conventional techniques, thereby significantly reducing manufacturing costs and making the manufacturing process easier to control.

[0030] In the present invention, a symmetrical P column structure can be formed by arranging the trench length parallel to the projection of the specific crystal direction on the wafer surface. As known to those skilled in the art, a symmetrical P column structure is necessary for the superjunction structure, because an asymmetric structure can cause uneven electric field distribution, which can easily lead to partial breakdown of the MOSFET device and reduce the device's withstand voltage capability. [Brief explanation of the drawings]

[0031] [Figure 1] FIG. 1 shows the structure of a planar power MOSFET produced by a conventional process. [Figure 2] FIG. 2 shows the structure of a trench-type power MOSFET produced using a conventional process. [Figure 3]FIG. 3 shows the structure of a type of trench-type power MOSFET manufactured by Infineon. [Figure 4] FIG. 4 shows the structure of a type of trench-type power MOSFET manufactured by ROHM. [Figure 5] FIG. 5 is a diagram showing the angular relationship between a general silicon carbide crystal and the surface of a silicon carbide wafer. [Figure 6] FIG. 6 is a diagram showing the structure of a trench-type power MOSFET in which non-axisymmetric P columns are obtained by conventional ion implantation along the C-axis when a silicon carbide wafer is cut in the direction shown in FIG. [Figure 7] FIG. 7 is a diagram illustrating a cross section of a trench-gate power MOSFET structure according to some embodiments of the present application. [Figure 8a] FIG. 8a is a perspective view of the schematic diagram shown in FIG. 7 viewed from a 45° angle above, in accordance with some embodiments of the present application. [Figure 8b] FIG. 8b is a diagram showing a mask pattern in the manufacturing process of the P column connector in FIG. 8a. [Figure 8c] FIG. 8c illustrates another P column connector according to some embodiments of the present application. [Figure 9a] FIG. 9a illustrates the placement orientation of trenches in a trench-gate power MOSFET according to some embodiments of the present application. [Figure 9b] FIG. 9b shows the trench installation direction according to the prior art. [Figure 10] FIG. 10 is a diagram illustrating the relationship between the C-axis of a silicon carbide crystal in a trench gate power MOSFET structure and the wafer surface coordinate system according to some embodiments of the present application. [Figure 11] FIG. 11 shows a flowchart of a method for manufacturing a trench-gate power MOSFET according to some embodiments of the present application. DETAILED DESCRIPTION OF THE INVENTION

[0032] MODE FOR CARRYING OUT THE INVENTION Exemplary embodiments of the present application include, but are not limited to, trench-gate power MOSFETs and methods of fabricating the same.

[0033] Exemplary embodiments are described in detail herein, examples of which are illustrated in the figures. When the following description refers to the drawings, the same numerals in different drawings represent the same or similar elements unless otherwise stated. The embodiments described in the following exemplary embodiments are by no means representative of all embodiments consistent with the present application. Rather, they are merely illustrative of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

[0034] The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the scope of the present application. As used in this application and the appended claims, the singular forms "a," "the," and "the" are intended to include the plural forms unless the context clearly dictates otherwise. The term "and / or," as used herein, should also be understood to refer to the inclusion of any and all possible combinations of one or more of the associated listed items. Similar terms, such as "comprises" and "including," mean that the elements or things preceding "comprises" or "including" include the elements or things listed after "comprises" or "including" and equivalents thereof, but do not in any way exclude other elements or things. Similar terms, such as "connected" and "connected," are in no way limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0035] Although the present application may use terms such as "first," "second," and "third" to describe various types of information, it is understood that such information should not be limited to these terms. These terms are used only to distinguish between information of the same type. For example, first information may be referred to as "second information," and similarly, second information may be referred to as "first information," without departing from the scope of the present application. Depending on the context, for example, the phrase "if..." used herein may be interpreted as "upon...," "when...," or "depending on the decision."

[0036] The embodiments of the present invention will be described in more detail below with reference to the drawings.

[0037] Figure 1 is a cross-sectional view showing the structure of a planar MOSFET produced by a conventional process. The MOSFET shown in Figure 1 includes a heavily doped N-type substrate 101, a lightly doped N-type epitaxial layer 102 formed on the substrate 101, a P-type body region 103 formed on the epitaxial layer 102, a source 104 located in the P-type body region 103, and a polycrystalline silicon gate 105 located on the P-type body region 103. Since the gate, source, and drain of a planar MOSFET are all located on the same plane, they can be integrated within a plane, but there are significant limitations on their size, preventing them from achieving sufficient performance.

[0038] FIG. 2 is a cross-sectional view showing the structure of a trench MOSFET produced by a conventional process. The MOSFET shown in FIG. 2 includes a heavily doped N-type substrate 201, a lightly doped N-type epitaxial layer 202 formed on the substrate 201, a P-type body region 203 formed on the epitaxial layer 202, a source 204 located within the P-type body region 203, a trench 205 etched within the P-type body region 203, a gate oxide film 206 grown on the inner wall of the trench 205, and polycrystalline silicon 207 deposited on the gate oxide film 206. Compared to the planar MOSFET shown in FIG. 1, the trench MOSFET shown in FIG. 2 does not have a JFET region, and the vertical trenches on the sidewalls of the trenches allow for a smaller trench pitch. However, because the critical electric field of wide bandgap semiconductors such as silicon carbide is 10 times that of silicon, the electric field strength at the bottom of the trench is relatively large. Such high electric fields in the semiconductor can lead to high electric fields on the trench oxide, leading to device reliability problems.

[0039] Figure 3 is a cross-sectional view showing the structure of a trench MOSFET manufactured by Infineon Electronics. The MOSFET shown in Figure 3 includes a heavily doped N-type substrate 301, a lightly doped N-type epitaxial layer 302 formed on the substrate 301, a P-type body region 303 formed on the epitaxial layer 302, a trench 304 etched in the P-type body region 303, a gate oxide film 306 grown on the inner wall of the trench 304, and polycrystalline silicon 305 deposited on the gate oxide film 306. Compared to the trench MOSFET shown in Figure 2, the trench MOSFET shown in Figure 3 further includes a heavily doped first P-type region 307 and a second P-type region 308 below the trench 304 to reduce the high electric field at the bottom of the trench 304, and the vertical depth of the P-type region is greater than the vertical depth of the P-type body region.

[0040] Figure 4 is a cross-sectional view showing the structure of a type of trench MOSFET manufactured by ROHM Co. The MOSFET shown in Figure 4 includes a heavily doped N-type substrate 401, a lightly doped N-type epitaxial layer 402 formed on the substrate 401, a P-type body region 403 formed on the epitaxial layer 402, a trench 406 etched in the P-type body region 403, a gate oxide film 407 grown on the inner wall of the trench 406, and polycrystalline silicon 408 deposited on the gate oxide film 407. 2, the trench MOSFET shown in FIG. 4 further includes a first P-type region 404 and a second P-type region 405 with high doping concentrations below the trench 406 to reduce the high electric field at the bottom of the trench 406, the first P-type region 404 and the second P-type region 405 being located on both sides of the trench 406, respectively, and the vertical depths of the first P-type region 404 and the second P-type region 405 being smaller than the vertical depth of the P-type body region in which they are located. However, the trench MOSFET structures shown in FIGS. 3 and 4 are expensive to manufacture and require difficult process control.

[0041] For trench MOSFET devices, the source-drain on-resistance Rds (on)It consists of several parts: Rds (on) =R N+ +R CH + R D +R sub

[0042] where R N+ is the resistance of the source region and N+ diffusion region. Because the doping concentration of the N+ region is high, the resistance is very small, so the resistance of this part is the source-drain on-resistance Rds (on) may be neglected for other resistances that make up

[0043] R CH is the trench resistance, i.e., the trench resistance under the gate, and R CH is the source-drain on-resistance Rds (on) The trench aspect ratio, gate oxide thickness, and gate voltage are all important parameters that determine R CH can affect changes in

[0044] R D is the drift region resistance, i.e., the resistance of the epitaxial layer. The epitaxial layer is a high-resistivity layer grown on the substrate to receive high voltage. Under the action of an external voltage, carriers drift in the drift region. For high-voltage MOSFET devices, the drift resistance is the source-drain on-resistance Rds (on) Therefore, the drift region resistance R D When the source-drain on-resistance Rds is reduced, (on) can be reduced.

[0045] R sub is the wafer substrate resistance, and this resistance can be reduced by processing such as thinning the backside.

[0046] At the same breakdown voltage, characteristic on-resistance Rsp = source-drain on-resistance Rds (on) *Due to the effective area of ​​the chip, the same source-drain on-resistance Rds(on) If this is the case, the smaller the specific on-resistance Rsp, the smaller the effective chip area, and further the smaller the parasitic capacitance of the power MOSFET, which makes it possible to reduce the switching loss in the power conversion process of the power MOSFET.

[0047] Figure 5 shows the angular relationship between a typical silicon carbide crystal and the silicon carbide wafer surface in a silicon carbide wafer, i.e., the angular relationship between a microscopic crystal and a macroscopic wafer. The figure shows the X direction of the wafer surface and the Y direction perpendicular to the wafer surface (i.e., the normal direction), as well as two mutually perpendicular crystal directions of a silicon carbide (4H-SiC) crystal: the

[0001] direction and the [11-20] direction. (Note: To express negative indices in crystallographic notation, a minus sign is used before the number instead of the overline above the number, which is not permitted in patent application procedures. The same applies below.) As is well known, a crystal is a structure in which a large number of microscopic material units (atoms, ions, molecules, etc.) are regularly arranged according to a certain rule. Therefore, a crystal usually has a specific shape, and the shape can define the crystallographic axes, directions, and planes of the crystal. For example, silicon carbide (4H-SIC) crystals define at least two crystal directions: the C-axis direction (i.e., the

[0001] direction) and the [11-20] direction, as shown in Figure 5. In the semiconductor industry, to ensure stable crystal growth during the production process, the crystal direction shown in Figure 5 is typically selected when cutting wafers. This means that there is an included angle between the crystal axis direction (C-axis) and the normal direction (Y-direction) of the wafer surface. This included angle is typically 4°, and the projection of one of the crystal directions, i.e., the [11-20] direction, on the wafer surface overlaps with the X-direction of the wafer. However, in production practice, for convenience, this included angle is sometimes ignored, and the crystal direction of the crystal and the direction of the wafer surface are directly indicated by a mirror image.

[0048] FIG. 6 is a cross-sectional view showing the structure of a trench power MOSFET in which a non-axisymmetric P column is obtained by conventional ion implantation along the C-axis when a silicon carbide wafer is cut in the direction shown in FIG. 5 . The trench power MOSFET shown in the figure includes a substrate 01, an epitaxial layer 02 formed on the substrate 01 by a process such as epitaxial growth, a P-type body region 04 formed in the epitaxial layer 02, and a trench 00 penetrating the P-type body region 04 and extending deep into the epitaxial layer 02. A P column is located below the trench 00 and embedded in the epitaxial layer 02, typically formed by ion implantation. To utilize the channel effect, the ion implantation direction is typically set to the crystal direction in which the channel effect is most pronounced. In a silicon carbide (4H-SiC) crystal, the C-axis direction is the crystal direction in which the channel effect is most pronounced. As can be seen from FIG. 5 , the C-axis of silicon carbide is never perpendicular to the wafer surface. That is, in the structure shown in FIG. 6 , the P columns 11 formed by ion implantation are not perpendicular to the wafer surface. That is, in the cross-sectional view of one unit cell as shown in FIG. 6 , the P columns 11 cannot be symmetrical about the central axis of the unit cell. It is common knowledge in this field that those skilled in the art should know that MOSFET device performance is optimal when the shape of the P columns is an axially symmetrical pattern in the cross-section shown in FIG. 6 . However, the cross-section of the P columns 11 obtained by ion implantation using conventional techniques is a parallelogram, as shown in FIG. 6 , and is not symmetrical about the central axis of the unit cell. This tends to lower the breakdown voltage of the MOSFET device.

[0049] To address the above deficiencies, the present invention proposes a novel trench-gate power MOSFET structure. This will be described below with reference to FIGS. 7, 8a, and 8b. FIG. 7 illustrates a cross-sectional view of a trench-gate power MOSFET structure according to some embodiments of the present disclosure. FIG. 8a illustrates a perspective view of the MOSFET shown in FIG. 7 viewed from a 45° angle above the MOSFET according to some embodiments of the present disclosure. FIG. 8b illustrates a mask pattern used in the manufacturing process of P column connector 505 in FIG. 8a.

[0050] The trench gate power MOSFET provided by the present invention includes a power MOSFET having a trench gate and a super junction (or quasi-super junction) structure. Hereinafter, the structure and forming process of the trench gate power MOSFET of the present invention will be specifically described using an example in which the wide band gap semiconductor substrate is a silicon carbide material, the first conductivity type is N-type, the second conductivity type is P-type, the second conductivity type column is P-column, and the first ion is aluminum ion.

[0051] As shown in FIG. 7 , the substrate 501 is a substrate of a wide bandgap semiconductor having a first conductivity type. For example, the substrate 501 may be a heavily doped N-type silicon carbide substrate. Above the substrate 501, a first epitaxial layer 502 and a second epitaxial layer 503, each having a low doping concentration, are grown in this order by an epitaxial growth process. The first epitaxial layer 502 is located below the second epitaxial layer 503, and the thickness of the first epitaxial layer 502 is smaller than the thickness of the second epitaxial layer 503, and the doping concentration of the first epitaxial layer 502 is smaller than the doping concentration of the second epitaxial layer 503. In one embodiment, the N-type doping concentration of the first epitaxial layer 502 is 1E14 atoms / cm 3 . 2 (atoms / cm 2 )~2E16atoms / cm 2 The thickness of the first epitaxial layer 502 is between 0.2 μm and 40 μm. The N-type doping concentration of the second epitaxial layer 503 is between 2E15 atoms / cm 2 ~2E17atoms / cm 2 and the thickness of the second epitaxial layer 503 is between 2 μm and 200 μm. It is understood that the thickness and doping concentration of the first epitaxial layer 502 and the thickness and doping concentration of the second epitaxial layer 503 can be determined depending on the required withstand voltage rating of the device. In this embodiment, a device with a quasi-superjunction structure is formed using epitaxial layers with two different doping concentrations, thereby improving the avalanche resistance.

[0052] 7, it is understood that the wide bandgap semiconductor substrate is silicon carbide material for illustrative purposes only and is in no way limiting. In other embodiments of the present application, the wide bandgap semiconductor substrate may be other wide bandgap semiconductor materials, such as gallium nitride, aluminum nitride, etc. With respect to the present invention, the difference in the selection of different substrate materials is the selection of different trench placement directions and ion implantation directions based on the different crystal orientations of different wafers (bodies).

[0053] It is understood that the doped impurities in the N-type doped first epitaxial layer 502 and second epitaxial layer 503 may be nitrogen or phosphorus, or may be other N-type impurities.

[0054] The P body region 504 is located above the second epitaxial layer 503 and is formed by implanting ions of a different conductivity type than the substrate 501, the first epitaxial layer 502, and the second epitaxial layer 503, for example, P-type ions, into the upper end of the second epitaxial layer 503.

[0055] The P column connector 505 is formed in the P body region 504 (P body region) and the second epitaxial layer 503 by an ion implantation process. Specifically, as shown in FIG. 8b, a mask pattern 5051 that exposes the P column connector 505 is first formed on the upper surface of the P body region 504 by a photolithography mask process. The mask pattern is symmetrical about the central axis of the upper surface of the P body region 504 (see FIG. 8b). Then, P-type impurities are implanted into the region toward the P body region 504 and the second epitaxial layer 503 by an ion implantation process, thereby forming a columnar P column connector 505. The P column connector 505 realizes a connection from the P column 511 to the P body region 504, thereby achieving an electrical connection between the P column 511 and the P body region 504, which will be created in a subsequent step, and is not electrically floating under any operating conditions. That is, the depth of the P column connector 505 needs to extend from the upper surface of the P body region 504 deep into the second epitaxial layer 503. Only after the trench-gate power MOSFET is processed can the P column 511 embedded in the second epitaxial layer 503 be electrically connected to the P body region 504 in the horizontal direction (referring to the horizontal direction in FIGS. 7, 8a, and 8b) via the P column connector 505 in the vertical direction (referring to the vertical direction in FIGS. 7, 8a, and 8b).

[0056] By continuing the implantation of ions above the P body region 504 (including the P column connector 505), an ohmic contact resistance portion is formed. For example, by implanting heavily N-type doped impurities into the middle portion of the P body region 504, i.e., the portion including the P column connector 505, to obtain a heavily N-type doped region 506, i.e., the portion indicated by S in FIG. 7, it is possible to easily form a relatively low source ohmic contact resistance. Furthermore, by implanting heavily P-type doped impurities into both ends of the P body region 504, i.e., the positions connected to both ends of the heavily N-type doped region 506, it is possible to obtain a first heavily P-type doped region 507 and a second heavily P-type doped region 508, which makes it possible to easily form a relatively low ohmic contact resistance in the P body (i.e., the P body region 504).

[0057] 8b, a hard mask layer pattern 5002 for processing trenches 500 is formed on both sides of the central axis of the surface of the P body region 504. The mask pattern is not continuous along the central axis but is complementary to the mask pattern 5051 of the P column connector 505. After etching is performed based on the hard mask pattern, the P body region 504 and a portion of the second epitaxial layer 503 under the hard mask layer pattern 5002 of the trench 500 are etched to form trenches 500. The P column connector 505 under the mask pattern 5051 of the P column connector 505 remains as a conductor electrically connecting the P column 511 and the P body region 504. In some embodiments, the hard mask layer may be composed of silicon dioxide or nickel. It is understood that in other embodiments, the hard mask layer may be composed of other elements or compounds.

[0058] Specifically, as shown in FIG. 8a, a bottom 5001 of trench 500 is located within second epitaxial layer 503. The depth-to-width ratio of trench 500 may range from 1:1 to 5:1, e.g., trench 500 may have a width of 0.4 μm and a depth of 1.2 μm. In some embodiments, trench 500 may have a depth-to-width ratio of 3:1. It is understood that the width and depth of trench 500 in the illustrated embodiment are exemplary and not limiting, and that other widths and depths may be used in other embodiments of the present application.

[0059] The issue of the orientation of the trench 500 is further explained below with reference to Figures 9a and 9b.

[0060] 9a and 9b illustrate the positional relationship between the trench and the wafer 71. In the first pattern 72 and the second pattern 72', the shaded portions illustrate the relationship between the trench 500, particularly the length direction of the trench 500, and the crystal planes of the wafer 71. The surface of the wafer 71 is shown with multiple crystal directions (indicated by square brackets) and crystal planes (indicated by round brackets). However, as can be seen from the above explanation, the axial direction of the silicon carbide wafer surface and the silicon carbide crystal are not perpendicular to each other. Therefore, the directions on the wafer surface shown in the figures are actually projections of the crystal directions of the silicon carbide crystal on the wafer surface. Therefore, in the industry, for convenience of explanation, it is common to directly refer to the directions on the wafer surface using the crystal directions of the crystal.

[0061] Many trenches 500 can be etched in one wafer 71, and all of these trenches have the same direction. In the prior art, trenches are etched in the direction shown in FIG. 9b, i.e., the length direction of the trench is perpendicular to the crystal plane (1-100) as shown in the second pattern 72' in FIG. 9b. According to the analysis of the present researchers, this trench direction is the root cause of the parallelogram-shaped P columns shown in FIG. 6.

[0062] Therefore, the present invention adjusts the industry's default trench installation direction so that the length of the trench is parallel to the projection of a selected crystal direction of the wafer (body) on the wafer surface. Because the C-axis is the crystal direction in which the channel effect is prominent and also the crystal direction with the smallest deviation from the wafer normal in current SiC wafer fabrication methods, the trench installation direction of the present invention ensures that the length of the trench is parallel to the plane formed by the C-axis and the wafer normal. Thus, implantation along the C-axis does not cause a shielding effect due to the influence of the trench sidewall and mask. Specifically, according to the present embodiment, the selected crystal direction is the crystal direction in which the channel effect is most prominent among all the crystal directions of the wafer, i.e., the direction that can reach the deepest depth during ion implantation. For example, the projection direction of the C-axis on the wafer surface is selected as shown in first pattern 72 in FIG. 9a. This modification is advantageous for forming symmetric P columns during subsequent ion implantation, such as forming symmetric P columns 511 when implanting ions along the C-axis (out of the page) in Figure 9a. For a specific analysis, see the discussion of Figure 10 below.

[0063] 8a, ions are implanted toward the bottom of trench 500 along the ion implantation direction shown in the figure, i.e., along the C-axis direction of silicon carbide, to obtain P columns 511 with a symmetrical cross-sectional pattern. In some embodiments, the first energy is 500 keV to 1500 keV, and the first dose is 5E13 atoms / cm. 2 ~5E14atoms / cm 2 , and the second energy is 50 kev to 300 kev, and the second dose is 5E12 atoms / cm 2 ~5E13atoms / cm 2Aluminum ions (e.g., Al-27) are implanted into the bottom region of the trench 500 along the silicon carbide c-axis direction (for 4H-SIC, the included angle between the ion implantation direction and the normal direction of the 4H-SIC wafer is 4°) to achieve uniform doping in the silicon carbide, thereby forming a P column 511. Due to the trench effect, the aluminum ions are implanted to a sufficiently deep depth to obtain a sufficiently deep P column 511, significantly reducing the number of ion implantations and the implantation energy, thereby reducing manufacturing costs. The depth of the P column 511 is more than 50% of the thickness of the second epitaxial layer 503 located below the bottom of the trench 500. The P column 511 is located within the second epitaxial layer 503, and the P column 511 and the low-doped N-type second epitaxial layer 503 form a quasi-superjunction structure. This achieves a widthwise connection between the P column 511 and the P body region 504.

[0064] In another embodiment, the P column connectors 505 may be realized by implanting ions into the sidewalls of the trench 500 after etching of the trench 500 is completed. Referring to FIG. 8c, the trench 500 is continuously etched along the central axis of the unit cell, rather than intermittently as shown in FIG. 8b. The etching depth penetrates the P body region 504 and reaches the second epitaxial layer 503. After forming the trench 500, ions are implanted into the sidewalls of the trench 500 to form P column connectors 505 with a uniform thickness on both sidewalls. The depth of this set of P column connectors 505 is at least equal to the depth of the trench 500, so that they can be electrically connected to the subsequently formed P column 511 (the P column 511 is formed at the bottom of the trench 500 by the ion implantation process and is connected to the bottom of the trench 500). At the same time, a part of the P column connector 505 is formed in the P body region 504, so that the P body region 504 and the P column 511 can be effectively electrically connected by the P column connector 505.

[0065] FIG. 10 shows an XYZ coordinate system on the upper surface of the wafer, with the X and Y directions parallel to the wafer surface and the Z direction perpendicular to the wafer surface. FIG. 10 also shows multiple crystal directions and crystal planes of the silicon carbide crystal. The schematic diagram of the crystal direction is slightly tilted to show the included angle between the crystal and the wafer. As can be seen from the cross-section of the silicon carbide wafer shown in FIG. 5, the silicon carbide crystal plane (1-100) is parallel to the XY plane, the projection [11-20]x of the crystal direction [11-20] on the wafer surface is parallel to the X axis, and the projection Cy of the C axis on the YZ plane is parallel to the Y axis. As mentioned previously, there is an included angle between the crystal and the wafer, and this included angle is approximately 4°. Because of this included angle, when the length of the trench is perpendicular to the XY plane, i.e., parallel to the Z axis (as shown in Figure 9b), ions implanted into the bottom of the trench along the C axis can only form non-axisymmetric P columns in the bottom region of the trench, approximating a parallelogram. As mentioned previously, a symmetric (axisymmetric) pattern of P columns is preferable, and P columns with a parallelogram cross section can cause many hidden problems, such as device destruction and failure.

[0066] The present invention rotates the industry's default trench orientation by 90°, so that the trench length direction is parallel to the X-axis, as shown in FIG. 9a. From the above analysis, it can be seen that ions implanted along the C-axis are implanted along two directions: the Y-axis (i.e., the Cy direction perpendicular to the wafer) and the X-axis (i.e., the [11-20]x direction parallel to the wafer). Here, the X-axis is the trench length direction, and ion implantation along this direction should not affect the cross-sectional shape of the P column 511 in the width direction of the trench 500. Therefore, in this embodiment, the ion implantation range does not exceed the expected range. From the cross-section shown in FIG. 8a, the P column 511 can form a structure that approximates a symmetrical rectangle. Compared to the prior art shown in FIG. 9b, the present invention improves the stability and reliability of trench MOSFETs.

[0067] The trench-type MOSFET of the present invention can improve the withstand voltage capability compared to the planar structure MOSFET produced by the conventional process shown in FIG. 1. In addition, the sufficiently deep P column 511 improves the doping concentration of the second epitaxial layer 503, and reduces the resistance R of the drift region. D By reducing the on-resistance Rds (on) can be reduced.

[0068] It will be appreciated that the above numerical values ​​for the number of implants, corresponding energies and doses for implanting aluminum ions (e.g., Al-27) into silicon carbide are exemplary and not limiting, and that in other embodiments of the present application, the number of implants, corresponding energies and doses may be selected depending on the required implant depth.

[0069] Here, implanting aluminum ions (e.g., Al-27) from the C-axis direction of the 4H-SiC wafer is illustrative and not limiting. It is understood that in other embodiments of the present application, ions of another conductivity type, P-type, may be implanted into the second epitaxial layer along the crystal direction of another wide bandgap semiconductor, thereby achieving a deep implantation depth with low implantation energy due to the trench effect of the crystal.

[0070] This is followed by a step of activating the ions implanted in the second epitaxial layer 503 by high-temperature annealing, a step of forming silicon dioxide on the inner surface of the trench 500 and then depositing polycrystalline silicon in the trench 500 to form a polycrystalline silicon gate, a step of growing a silicon dioxide insulating layer 515 on the polycrystalline silicon gate, and a step of forming electrodes (source S and gate G) through a conventional ohmic contact process, metallization process, etc. The structure of the trench-gate quasi-super junction power MOSFET finally formed in this application is shown in Figure 7.

[0071] An embodiment of the present application also provides a trench-gate super junction power MOSFET (not shown), whose structure and manufacturing method are similar to those of the trench-gate quasi-super junction power MOSFET, with the only difference being the following: In the manufacturing process of the trench-gate super junction MOSFET, only a single epitaxial layer is required, and the depth of the P column formed therein must be 50% or more of the thickness of the epitaxial layer below the bottom of the trench, so that the P column and the epitaxial layer form a super junction structure. For a detailed description, please refer to the above content, and it will not be repeated here.

[0072] 11 shows a flowchart of a method for manufacturing a trench-gate power MOSFET according to some embodiments of the present application. Specifically, as shown in FIG. 11, the method for manufacturing a trench-gate power MOSFET of the present application includes the following steps:

[0073] 1) Step 902: Growing an epitaxial layer having a first conductivity type on a wide bandgap semiconductor substrate. Here, the material of the wide bandgap semiconductor substrate may be silicon carbide, gallium nitride, aluminum nitride, diamond, etc. An epitaxial layer may be formed on the wide bandgap semiconductor substrate by an epitaxial growth process. The epitaxial layer of the first conductivity type is an epitaxial layer doped with a first conductivity type element. In some embodiments, the first conductivity type element may be an element such as nitrogen or phosphorus, which makes the epitaxial layer an N-type semiconductor (free electrons are majority carriers and holes are minority carriers). In some embodiments, the first conductivity type element may be a trivalent element such as boron or aluminum, which makes the epitaxial layer a P-type semiconductor (holes are majority carriers and free electrons are minority carriers). It is understood that whether the first conductivity type is P-type or N-type can be selected according to actual needs and is not limited herein.

[0074] 2) forming a body region of a second conductivity type in the epitaxial layer (904), where the body region of the second conductivity type is a body region doped with a second conductivity type element. The second conductivity type is different from the first conductivity type. For example, if the first conductivity type is N-type, the second conductivity type is P-type, and if the first conductivity type is P-type, the second conductivity type is N-type. It is understood that the first conductivity type and the second conductivity type can be determined according to actual needs and are not limited here.

[0075] In some embodiments, an ion implantation process may be performed to implant an element of second conductivity type into the epitaxial layer to form a body region of second conductivity type.

[0076] 3) forming a trench by etching in the body region (906). The ion implantation direction may be matched to the direction of the trench to obtain a cross-sectionally symmetric second conductivity type column in subsequent ion implantation. The matching may include ensuring that the ion implantation direction is perpendicular to the bottom surface of the trench, or may include decomposing the ion implantation direction into a direction perpendicular to the bottom surface of the trench and a direction parallel to the length of the trench. Based on the ion implantation direction, a crystal direction in which the channel effect is most pronounced is generally selected. If the crystal direction in which the channel effect is most pronounced is perpendicular to the wafer surface, the trench can be positioned arbitrarily on the wafer surface, and the ion implantation direction can always be perpendicular to the bottom of the trench. If the crystal direction in which the channel effect is most pronounced is not perpendicular to the wafer surface, the crystal direction in which the channel effect is most pronounced can be decomposed into an X direction parallel to the wafer surface and a Y direction perpendicular to the wafer surface, and the length of the trench can be positioned parallel to the X direction.

[0077] For example, in some embodiments, the length direction of the trench is set to a direction perpendicular to the crystal plane (11-20) of wafer 71 as shown in Figure 9a, rather than the direction as shown in Figure 9b, i.e., the length direction of the trench is set to be parallel to the crystal direction [11-20] (or more precisely, parallel to the projection of the crystal direction [11-20] on the wafer). In addition, to maintain electrical connection between P column 511 to be subsequently formed and P body region 504, P column connector 505 may be further formed between bottom 5001 of trench 500 and P body region 504 by ion implantation.

[0078] There are two ways to form the P column connector 505.

[0079] First, a P column connector 505 is formed. This can be understood with reference to FIGS. 8a and 8b. After forming a body region having a second conductivity type, e.g., a P body region 504, regions of a mask pattern 5051 for the P column connector 505 are created on both sides of the central axis (shown in FIG. 8b) of the upper surface of the P body region 504, as shown in the figure. P-type ions are then implanted into the P body region 504 and the second epitaxial layer 503 within the regions to obtain the P column connector 505. The ion implantation depth is greater than the depth of the trench 500, i.e., the depth reaches the region of the P column 511, thereby achieving electrical connection between the P body region 504 and the subsequently processed P column 511 through the P column connector 505. Then, in the region of the hard mask layer pattern 5002 for trench processing shown in FIG. 8b, an etching process is performed to form a trench 500 in the P body region 504 and the second epitaxial layer 503, and the depth and width of the trench can be controlled. Those skilled in the art may understand that the position of the mask pattern 5051 of the P-column connector 505 shown in FIG. 8b may be at any position on the central axis, or there may be multiple positions in one unit cell, and similar settings will not be described here.

[0080] In some embodiments, the body region may be etched to form the trench using a dry etching technique. In some embodiments, the body region may be etched to form the trench using a wet etching technique. It is understood that either dry etching or wet etching may be selected depending on the actual situation to form the trench, and this is not a limitation.

[0081] Furthermore, to ensure an effective electrical connection between the P body region 504 and the P column 511, the P-type ion implantation may be further increased on the sidewalls near the P column connector 505 to ensure a sufficient connection between the P column connector 505 and the P body region 504, thereby forming an effective P-type connection and avoiding the electrical floating of the subsequently processed P column 511.

[0082] In some other embodiments, after the first P-type highly doped region 507, the second P-type highly doped region 508, and the N-type highly doped region 506 are further formed, the region of the P column connector 505 may be surrounded by a mask on both sides of the central axis of the device surface (see FIG. 8a), and then the P column connector 505 may be formed in the P body region 504 and the second epitaxial layer 503 by an ion implantation process.

[0083] Second, the P column connectors 505 are subsequently formed. This can be understood with reference to FIGS. 8a and 8c. In contrast to the above-described case where the trench 500 is discontinuous, the P column connectors 505 can be subsequently formed to obtain a continuous trench 500. That is, in the embodiment shown in FIG. 8c, there is no P column connector crossing the trench 500, which somewhat reduces the complexity of trench etching. After forming a body region having a second conductivity type, e.g., the P body region 504, a trench 500 as shown in the figure is etched in the P body region 504 and the second epitaxial layer 503 using a conventional process. Then, ion implantation is performed on both sidewalls of the trench 500 to form a heavily doped P ion region of a certain thickness on the sidewall, thereby forming a pair of P column connectors 505. From another perspective, this can be understood as the P column connectors manufactured by the previous method being embedded in both sidewalls of the trench 500. For the same reason, to ensure an effective electrical connection between the P body region 504 and the P column 511, an additional ion implant may be performed downward at the connection point between the P column connector 505 and the bottom of the trench 500 to ensure a more reliable electrical connection between the P column connector 505 and the subsequently processed P column 511.

[0084] It is well known in the art that a symmetrical P column is preferable, because an asymmetric P column is disadvantageous in reducing the electric field strength in the superjunction structure, and excessive electric field strength can easily lead to device breakdown. Therefore, the present application breaks with industry practice by etching a trench in the [11-20]x direction (see FIG. 10). As can be seen from FIGS. 7 and 8a, 8b, and 8c, P column 511 is located below trench 500 and has a rectangular structure that matches the shape and dimensions of trench 500. Only when the length of trench 500 is parallel to the [11-20]x direction can the projection of the silicon carbide (4H-SiC) C-axis direction on the wafer surface be in the [11-20]x direction. Furthermore, the cross-section of the P column obtained during the subsequent ion implantation step resembles a symmetrical rectangle, rather than a P column with a cross-section resembling a parallelogram, as in some prior art techniques.

[0085] 4) Step 908: Implanting first ions into the bottom region of the trench along a crystal direction of the wide bandgap semiconductor material to form a second conductivity type column, the bottom region of the trench being located below and in contact with the bottom of the trench, and the crystal direction being selected so that the implantation of the first ions can fully utilize the trench effect of the crystal. In this way, when the first ions are implanted along the crystal direction of the semiconductor, the trench effect significantly increases the range of the first ions compared to when they are incident in a random direction or along the wafer normal direction, resulting in stronger penetration, which can significantly reduce the energy of the first ion implantation and reduce manufacturing costs. In some embodiments, the wide bandgap semiconductor material is a hexagonal wide bandgap semiconductor material (e.g., silicon carbide, gallium nitride, etc.), and the crystal direction refers to the vertical crystal plane (i.e., the C-axis direction) of the hexagonal wide bandgap semiconductor material. In some embodiments, when the wide bandgap semiconductor material is silicon carbide, the crystal direction of the wide bandgap semiconductor material is selected as the C-axis direction of the silicon carbide, and the C-axis direction and the normal direction of the silicon carbide wafer form a certain included angle. In some embodiments, when the wide bandgap semiconductor material is 4H-SiC or 6H-SiC, the included angle between the C-axis direction and the normal direction of the 4H-SiC or 6H-SiC wafer is 4°. It is understood that for other types of silicon carbide wafers, the included angle between the corresponding C-axis direction and the normal direction of the corresponding wafer may be other values, and is not limited herein.

[0086] Here, the vertical depth of the second conductivity type column is 50% or more of the thickness of the epitaxial layer located at least in the bottom region of the trench. In some embodiments, the epitaxial layer is a single epitaxial layer, and the vertical depth of the second conductivity type column is 50% or more of the thickness of the epitaxial layer located at least in the bottom region of the trench. In some embodiments, the epitaxial layer includes a first epitaxial layer and a second epitaxial layer, and the first epitaxial layer is located below the second epitaxial layer. The bottom of the trench and the second conductivity type column are located in the second epitaxial layer, and the vertical depth of the second conductivity type column is 50% or more of the thickness of the second epitaxial layer located at least in the bottom region of the trench.

[0087] 5) Filling the trench (910). In some embodiments, an oxide (e.g., silicon dioxide) may be formed on the interior surface of the trench before filling the trench. Filling the trench may involve depositing polysilicon into the trench.

[0088] In one example, a trench silicon carbide MOSFET with a pitch of 2.4 μm was designed using TCAD (semiconductor process / device simulation tool), and the specific on-resistance Rsp was 0.2 Ω / cm 2 Considering the transition ratio of the trench and the thickness of the silicon carbide substrate (the thickness of the silicon carbide substrate is assumed to be 180 μm), the specific on-resistance Rsp of the device can be reached to 0.896 Ω / cm 2The breakdown voltage of the device was set to 950V (rated voltage: 750V or 650V). Silicon carbide super junction structure MOSFETs have a typical static output capacitance Coss curve, and as the source-drain voltage Vds increases, the static output capacitance Coss becomes significantly smaller. Due to this characteristic, the Qoss obtained by integrating the static output capacitance Coss curve becomes smaller (advantageous for soft switching) and the power consumption due to the static output capacitance Coss becomes smaller (advantageous for hard switching). Compared to silicon carbide devices or silicon devices manufactured by conventional processes in the related art, MOSFETs having trench gates and a super junction structure (or a quasi-super junction structure) manufactured by the method for manufacturing a power MOSFET having a trench gate and a super junction structure (or a quasi-super junction structure) according to the present application have a thinner epitaxial layer, a lower specific on-resistance, and higher device stability at the same breakdown voltage.

[0089] In one comparative experiment, a comparison was made between the conventional process for power MOSFETs and the method of the present invention, using an example in which p-type impurity Al-27 was implanted into a silicon carbide epitaxial layer at a dose of 2e16 cm-3. The total impurity dose was 1E14 / cm 2 In this case, Al-27 was implanted at an energy of 500 Kev in the manufacturing method of the present invention, while it was implanted at an energy of 3.3 Mev in the manufacturing method of the prior art. Comparing the two, the technical means of the present invention can achieve a deeper second conductivity type column. This shows that the manufacturing method of the present invention can achieve the same implantation depth as the high energy conditions of the prior art with a much lower implantation energy, and that the manufacturing process can be more easily controlled under low implantation energy conditions.

[0090] It should be noted that in the examples and specification of this patent, relational terms such as "first" and "second," etc., are merely used to distinguish one entity or operation from another and do not necessarily require or imply any actual relationship or order between those entities or operations. Furthermore, the terms "comprise," "include," or any other variant thereof are intended to cover a non-exclusive inclusion, whereby a process, method, article, or equipment comprising a set of elements not only includes those elements but may also include other elements not expressly listed, or may further include elements inherent in such process, method, article, or equipment. Unless otherwise specifically limited, an element defined by the phrase "comprises a ..." does not exclude the presence of additional identical elements in the process, method, article, or equipment that includes the element.

[0091] While the present application has been shown and described with reference to certain preferred embodiments thereof, those skilled in the art should understand that various changes in form and detail can be made therein without departing from the spirit and scope of the present application.

Claims

1. 1. A method for fabricating a trench-gate power MOSFET for producing a trench-gate power MOSFET in a wafer, comprising: growing an epitaxial layer having a first conductivity type on a substrate of silicon carbide material; forming a body region having a second conductivity type in the epitaxial layer; forming a trench by etching in the body region, the length direction of the trench being parallel to a projection of a C-axis direction of a silicon carbide crystal body on the wafer surface; implanting first ions into a bottom region of the trench along a C-axis direction of the silicon carbide crystalline body of silicon carbide material to form a second conductivity type column, the bottom region of the trench being located below the trench and in contact with a bottom of the trench, and the vertical depth of the second conductivity type column being 50% or more of a thickness of the epitaxial layer located in the bottom region of the trench; and filling the trench with a filler.

2. 2. The method of claim 1, further comprising: forming a connector having the second conductivity type by implanting first ions into the body region and the epitaxial layer; one end of the connector electrically connected to the body region; the other end of the connector electrically connected to the second conductivity type column; and a depth of the connector equal to or greater than a depth of the trench.

3. The step of implanting the first ions into the bottom region of the trench along the C-axis direction of the silicon carbide crystal body includes:

2. The manufacturing method according to claim 1, further comprising implanting the first ions into the bottom region of the trench along the C-axis direction of the silicon carbide crystal body at least twice, i.e., with a first dose, a first energy, and a second dose, a second energy, respectively.

4. The first dose is 5E13 to 5E14 atoms / cm ２ the first energy is 500 keV to 1500 keV, and the second dose is 5E12 to 5E13 atoms / cm ２ 4. The manufacturing method according to claim 3, wherein the second energy is 50 keV to 300 keV.

5. 2. The method of claim 1, wherein the epitaxial layer comprises a first epitaxial layer and a second epitaxial layer, and further comprising the steps of growing the first epitaxial layer having the first conductivity type on a substrate of silicon carbide material, and growing the second epitaxial layer having the first conductivity type on the first epitaxial layer.

6. 6. The method of claim 5, wherein the thickness of the first epitaxial layer is less than the thickness of the second epitaxial layer, and the doping concentration of the first epitaxial layer is less than the doping concentration of the second epitaxial layer.

7. 6. The method of claim 5, wherein the bottom of the trench and the second conductivity type column are located within the second epitaxial layer, and the vertical depth of the second conductivity type column is 50% or more of the thickness of the second epitaxial layer located in the bottom region of the trench.

8. 2. The method of claim 1, wherein the ratio of the depth of the trench to the width of the trench is in the range of 1:1 to 5:1.

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