An array integrated device with gating and multi-bit storage functions and a method for manufacturing the same

Abstract

The application discloses an array integrated device with gating and multi-bit storage functions and a preparation method thereof. The device comprises a substrate, a linear bottom electrode formed on the substrate, a first oxide thin film layer formed on the linear bottom electrode, a first doped active metal oxide thin film layer formed on the first oxide thin film layer, a linear intermediate layer electrode formed on the first doped active metal oxide thin film layer, the extending direction of the linear intermediate layer electrode being perpendicular to the extending direction of the linear bottom electrode, a second oxide thin film layer formed on the linear intermediate layer electrode, a second doped active metal oxide thin film layer formed on the second oxide thin film layer, and a linear top electrode formed on the second doped active metal oxide thin film layer, the extending direction of the linear top electrode being perpendicular to the extending direction of the linear intermediate layer electrode. When a voltage is applied to the linear top electrode of the device, the gating effect of the top electrode of the device is achieved, the excitation effect of the directly connected memory is realized, and the multi-state storage function of the device is obtained.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and specifically to an array integrated device with gating and multi-bit storage functions and its fabrication method. Background Technology

[0002] Emerging non-volatile memories such as resistive random access memory (RRAM), phase-change memory (PCM), and ferroelectric memory play a crucial role in the integrated circuit field by storing data and ensuring data integrity even after power loss. Among these, RRAM, with its easily integrated two-terminal crossover structure, high erase / write speed, low switching power consumption, and excellent durability and retention characteristics, has become the core of next-generation non-volatile memory development. While RRAM can achieve high-density integration through a crossover array structure, crosstalk currents are unavoidable during integration, limiting large-scale integration. Therefore, it is necessary to develop devices with gating functions and integrate them with RRAM to achieve precise voltage application to different channels, thereby avoiding the impact of crosstalk currents on signal acquisition.

[0003] In the integration of gating and storage devices, the high standards required for current matching, material matching, process matching, and voltage matching increase the integration difficulty. Selecting devices with the same operating current range, compatible material systems, compatible fabrication processes, and matching operating voltages makes it difficult to construct perfectly matched gating and storage devices. Therefore, developing an electronic device that simultaneously possesses gating and storage functions would perfectly solve this problem, enabling homogeneous integration, greatly improving the device's integrability, and reducing production costs.

[0004] Considering that the ultimate goal of gating devices and memory devices is to improve device integration and achieve high-density storage, implementing polymorphic storage within the same device unit will increase the overall storage capacity from the perspective of individual hardware. Therefore, developing novel memory devices with multi-bit storage has significant application prospects in constructing array-integrated high-density memory chips. Summary of the Invention

[0005] This invention utilizes active metal atom doping to construct functional layers with gradually varying concentrations to fabricate array integrated devices with gating and multi-bit storage functions. The device state can be controlled and adjusted by the diffusion of active metal atoms, achieving gating and multi-bit storage functions within the same device unit. Furthermore, the invention utilizes the same device structure to achieve high-density cross-integration of the selector and memory, solving crosstalk current problems, misreading problems, and current matching problems during the integration process in integrated arrays, thereby improving the integrability and storage capacity of the device.

[0006] Specifically, the array integrated device with gating and multi-bit storage functions of the present invention includes: a substrate; a linear bottom electrode, wherein multiple linear bottom electrodes are spaced apart and arranged in parallel on the substrate; a first oxide thin film layer is formed on the linear bottom electrode; a first oxide thin film layer doped with an active metal is formed on the first oxide thin film layer; a linear intermediate layer electrode, wherein multiple linear intermediate layer electrodes are spaced apart and arranged in parallel, and their extension direction is perpendicular to the extension direction of the linear bottom electrode, and are formed on the first oxide thin film layer doped with an active metal; a second oxide thin film layer is formed on the linear intermediate layer electrode; a second oxide thin film layer doped with an active metal is formed on the second oxide thin film layer; and a linear top electrode, wherein multiple linear top electrode electrodes are spaced apart and arranged in parallel, and their extension direction is perpendicular to the extension direction of the linear intermediate layer electrode, and are formed on the second oxide thin film layer doped with an active metal. When a voltage is applied to the linear top electrode of the device, the gating effect of the top device is used to stimulate the directly connected memory, thereby obtaining the multi-state storage function of the device.

[0007] In the array integrated device with gating and multi-bit storage functions of the present invention, preferably, the first oxide thin film layer and the second oxide thin film layer are HfO2, ZrO2, and ZnO.

[0008] In the array integrated device with gating and multi-bit storage functions of the present invention, preferably, the first oxide thin film layer doped with active metal and the second oxide thin film layer doped with active metal are Ag or Cu-doped HfO2, ZrO2, ZnO.

[0009] In the array integrated device with gating and multi-bit storage functions of the present invention, preferably, the material of the linear intermediate layer electrode is Ag or Cu.

[0010] In the array integrated device with gating and multi-bit storage functions of the present invention, preferably, the materials of the linear bottom electrode and the linear top electrode are Au, Pt, Pd, and Al.

[0011] This invention also discloses a method for fabricating an array integrated device with gating and multi-bit storage functions, comprising the following steps: forming multiple parallel linear bottom electrodes spaced apart on a substrate; forming a first oxide thin film layer on the linear bottom electrodes; forming a first oxide thin film layer doped with an active metal on the first oxide thin film layer; forming multiple parallel linear intermediate layer electrodes spaced apart on the first oxide thin film layer, with their extension direction perpendicular to the extension direction of the linear bottom electrodes; forming a second oxide thin film layer on the linear intermediate layer electrodes; forming a second oxide thin film layer doped with an active metal on the second oxide thin film layer; and forming a linear top electrode, on which multiple parallel linear top electrodes spaced apart on the second oxide thin film layer, with their extension direction perpendicular to the extension direction of the linear intermediate layer electrodes. When a voltage is applied to the linear top electrode of the device, the gating effect of the top device is used to stimulate the directly connected memory, thereby obtaining the multi-state storage function of the device.

[0012] In the method for fabricating an array integrated device with gating and multi-bit storage functions of the present invention, preferably, the first oxide thin film layer and the second oxide thin film layer are HfO2, ZrO2, and ZnO.

[0013] In the method for fabricating an array integrated device with gating and multi-bit storage functions of the present invention, preferably, the first oxide thin film layer doped with active metal and the second oxide thin film layer doped with active metal are Ag or Cu-doped HfO2, ZrO2, ZnO.

[0014] In the method for fabricating an array integrated device with gating and multi-bit storage functions of the present invention, preferably, the material of the linear intermediate layer electrode is Ag or Cu.

[0015] In the method for fabricating an array integrated device with gating and multi-bit storage functions of the present invention, preferably, the materials of the linear bottom electrode and the linear top electrode are Au, Pt, Pd, and Al.

[0016] Beneficial effects:

[0017] (1) Breaking the traditional device working mode, the device is constructed based on the concentration difference of active metal atoms, which enables the device to simultaneously realize the gating function and the storage function, increasing the functionality and reconfigurability of the device.

[0018] (2) Using homogeneous devices with the same structure to achieve cross-array integration of gating and storage devices perfectly solves problems such as current matching, material matching, process matching and voltage matching, reduces the cost of device integration and avoids the incompatibility in the integration process of different devices.

[0019] (3) An integrated device with multi-bit storage function was constructed, and multi-value storage function was realized in the same device, which improved the storage density from the perspective of memory and further increased the high-density storage capability of the device. Attached Figure Description

[0020] Figure 1 This is a flowchart of a method for fabricating an array-integrated device with gating and multi-bit storage functions.

[0021] Figures 2-6 This is a schematic diagram of the structure of each stage of the fabrication method of an array integrated device with gating and multi-bit storage functions.

[0022] Figure 7 This is a schematic diagram of the various resistive states of an array integrated device with gating and multi-bit storage functions. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only for explaining this invention and are not intended to limit this invention. The described embodiments are merely some embodiments of this invention, not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0024] In the description of this invention, it should be noted that the terms "upper," "lower," "vertical," and "horizontal," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0025] Furthermore, many specific details of the invention, such as the structure, materials, dimensions, processing techniques, and methods of the device, are described below to provide a clearer understanding of the invention. However, as those skilled in the art will understand, the invention may be implemented without adhering to these specific details. Unless specifically indicated below, various parts of the device may be made of materials known to those skilled in the art, or may employ materials with similar functionality developed in the future.

[0026] Figure 1 This is a flowchart illustrating the fabrication method of an array-integrated device with gating and multi-bit storage capabilities. (For example...) Figure 1As shown, the fabrication method of an array integrated device with gating and multi-bit storage functions includes the following steps:

[0027] Step S1: Prepare a silicon substrate 100 for fabricating an array integrated device with gating and multi-bit storage functions. The substrate can also be SiC, glass, GaN, etc.

[0028] Step S2: A linear bottom electrode Pt101 with a thickness of 50 nm to 100 nm is fabricated on the substrate 100 using photolithography and magnetron sputtering, as shown below. Figure 2 As shown. Multiple linear bottom electrodes Pt101 are spaced apart and arranged in parallel. The material of the bottom electrodes can also be inert metals such as Au, Pd, and Al; the linewidth of the linear bottom electrodes is preferably 50 μm, and can range from 10 μm to 100 μm; the line length is preferably 500 μm, and can range from 200 μm to 500 μm.

[0029] Step S3: A 50 nm thick oxide film HfO2¹O2 is grown on the bottom electrode using magnetron sputtering. Figure 3 As shown. The oxide film can also be ZrO2, ZnO, etc.; the thickness range can be 20nm to 70nm.

[0030] Step S4: An Ag-doped ZnO thin film 103 with a thickness of 30 nm is grown on the oxide thin film HfO2 102 using multi-source magnetron co-sputtering, as shown below. Figure 4 As shown. The doped metal can also be an active metal such as Cu; the oxide film can also be ZrO2, HfO2, etc.; the thickness range can be 10nm to 40nm.

[0031] Step S5: A 70 nm thick linear intermediate layer electrode Ag104 is grown on the Ag-doped ZnO thin film 103 using magnetron sputtering. This enables the device to achieve a structure where Ag atoms are diffusely distributed according to their concentration, completing the fabrication of the underlying memory device. Figure 5 As shown, the linear intermediate layer electrode has a width of 50 μm and a length of 500 μm. Multiple linear intermediate layer electrodes of Ag104 are spaced apart and arranged in parallel, with the extension direction of the linear intermediate layer electrodes perpendicular to the extension direction of the linear bottom layer electrodes, to achieve a single-layer cross-array structure. The material of the linear intermediate layer electrode can also be an active metal such as Cu; the thickness can range from 50 nm to 100 nm; the linewidth can range from 10 μm to 100 μm; and the line length can range from 200 μm to 500 μm.

[0032] Steps S6 and S7 repeat the methods of steps S3 and S4 to form an HfO2 thin film 105 and an Ag-doped ZnO thin film 106 on the intermediate layer electrode 104 in one step, thus completing the fabrication of the top-layer gate device.

[0033] Step S8: A linear top-layer electrode Au107 is formed on the above structure to obtain a device structure of Pt101 / HfO2102 / ZnO-Ag103 / Ag104 / HfO2105 / ZnO-Ag106 / Au107, completing the fabrication of an array integrated device with gating and multi-bit storage functions. Multiple linear top-layer electrodes Au107 are spaced apart and arranged in parallel, with the extension direction of the linear top-layer electrodes perpendicular to the extension direction of the linear intermediate layer electrodes, such as... Figure 6 As shown. The thickness of the linear top electrode is preferably 70 nm, the linewidth is preferably 50 μm, and the length is preferably 500 μm. However, the present invention is not limited to these, and the electrode material can also be inert metals such as Pt, Pd, and Al; the thickness range can be 50 nm to 100 nm; the linewidth range can be 10 μm to 100 μm; and the line length range can be 200 μm to 500 μm.

[0034] like Figure 7 As shown, when a voltage is applied to the top electrode of the device, the selection effect of the top device enables the activation of the directly connected memory, achieving the device's multi-state storage function and meeting the requirements of high-density memory arrays. Specifically, when no voltage is applied, the device is initially in an initial resistive state, corresponding to resistive state 1. When a voltage is applied to the top electrode, the top device first reaches a conducting state, achieving the selection effect. Subsequently, a weak conductive channel is formed in the bottom device, and the device's resistance decreases, placing the device in resistive state 2. Continuing to apply a voltage to the top electrode strengthens the conductive channel of the bottom device, further reducing the device's resistance, placing the device in resistive state 3. Continuing to apply a voltage to the top electrode, the conductive channel of the bottom device reaches its strongest point, further reducing the device's resistance, placing the device in resistive state 4.

[0035] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. An array-integrated device with gating and multi-bit storage functions, characterized in that, include: Substrate; Linear bottom electrode, multiple linear bottom electrodes are spaced apart from each other and arranged in parallel, formed on the substrate; A first oxide thin film layer is formed on the linear bottom electrode; A first oxide thin film layer doped with an active metal is formed on the first oxide thin film layer; Linear intermediate layer electrodes, multiple linear intermediate layer electrodes spaced apart from each other, arranged in parallel, and their extension direction is perpendicular to the extension direction of the linear bottom layer electrodes, are formed on the first oxide thin film layer doped with active metal. A second oxide thin film layer is formed on the linear intermediate layer electrode; A second oxide thin film layer doped with an active metal is formed on the second oxide thin film layer; A series of linear top-layer electrodes, spaced apart and arranged in parallel, with their extension direction perpendicular to the extension direction of the linear intermediate-layer electrodes, are formed on the oxide thin film layer of the second doped active metal. When a voltage is applied to the linear top electrode of the device, the concentration difference of active metal atoms is used to achieve the excitation effect on the directly connected memory through the gating effect of the top device, thereby obtaining the multi-state storage function of the device and realizing the gating effect and multi-bit storage function in the same device unit.

2. The array integrated device with gating and multi-bit storage functions according to claim 1, characterized in that, The first oxide thin film layer and the second oxide thin film layer are HfO2, ZrO2 or ZnO.

3. The array integrated device with gating and multi-bit storage functions according to claim 1, characterized in that, The first oxide thin film layer doped with the active metal and the second oxide thin film layer doped with the active metal are Ag or Cu-doped HfO2, ZrO2 or ZnO.

4. The array integrated device with gating and multi-bit storage functions according to claim 1, characterized in that, The material of the linear intermediate layer electrode is Ag or Cu.

5. The array integrated device with gating and multi-bit storage functions according to claim 1, characterized in that, The materials of the linear bottom electrode and the linear top electrode are Au, Pt, Pd or Al.

6. A method for fabricating an array-integrated device with gating and multi-bit storage functions, characterized in that, Includes the following steps: Multiple parallel, spaced-apart linear bottom electrodes are formed on the substrate; A first oxide thin film layer is formed on the linear bottom electrode; An oxide thin film layer doped with a first active metal is formed on the first oxide thin film layer; Multiple parallel linear intermediate layer electrodes are formed on the oxide thin film layer of the first doped active metal, with their extension direction perpendicular to the extension direction of the linear bottom layer electrode. A second oxide thin film layer is formed on the linear intermediate layer electrode; A second oxide thin film layer doped with an active metal is formed on the second oxide thin film layer; The linear top-layer electrode is formed on the oxide thin film layer of the second doped active metal by forming multiple parallel, spaced-apart linear top-layer electrodes, and the extension direction of the top-layer electrodes is perpendicular to the extension direction of the linear intermediate layer electrodes. When a voltage is applied to the linear top electrode of the device, the concentration difference of active metal atoms is used to achieve the excitation effect on the directly connected memory through the gating effect of the top device, thereby obtaining the multi-state storage function of the device and realizing the gating effect and multi-bit storage function in the same device unit.

7. The method for fabricating an array integrated device with gating and multi-bit storage functions according to claim 6, characterized in that, The first oxide thin film layer and the second oxide thin film layer are HfO2, ZrO2 or ZnO.

8. The method for fabricating an array integrated device with gating and multi-bit storage functions according to claim 6, characterized in that, The first oxide thin film layer doped with the active metal and the second oxide thin film layer doped with the active metal are Ag or Cu-doped HfO2, ZrO2 or ZnO.

9. The method for fabricating an array integrated device with gating and multi-bit storage functions according to claim 6, characterized in that, The material of the linear intermediate layer electrode is Ag or Cu.

10. The method for fabricating an array integrated device with gating and multi-bit storage functions according to claim 6, characterized in that, The materials of the linear bottom electrode and the linear top electrode are Au, Pt, Pd or Al.

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