A memory protection unit, an electronic device, and an access monitoring method

Abstract

The present application discloses a memory protection unit, an electronic device, and an access monitoring method, relating to the technical field of access control. The memory protection unit is configured to receive an access signal sent by an access unit when the access unit needs to access memory; after determining that the main controller in the access unit has valid access and determining that the access unit is restricted from accessing memory based on the access signal sent by the access unit, send a bus exception signal to the main controller, so that the main controller performs exception access processing after receiving the bus exception signal. Since the bus exception signal is not affected by the interrupt enable and the interrupt signal, the main controller can quickly receive the bus exception signal; the time delay from when the main controller receives the bus exception signal to when it enters the bus exception handling program is short, so as to perform exception access processing in a timely manner.

Description

Technical Field

[0001] This application relates to the technical field of access control, and in particular, to a memory protection unit, an electronic device, and an access monitoring method. Background Art

[0002] In a system-on-chip (SOC), a central processing unit (CPU) and other master devices can access memory. To protect the security of memory data, a memory protection unit (MPU) can be used to monitor the access of the CPU and other master devices.

[0003] In related technologies, when the MPU detects that the CPU or other master devices request to access a restricted address, it will send an interrupt signal to the CPU, and the CPU will perform exception access processing after receiving the interrupt signal.

[0004] However, in scenarios where the CPU is processing other interrupt signals or the interrupt enable is turned off, the CPU cannot respond to the interrupt signal sent by the MPU in a timely manner, resulting in the CPU being unable to perform exception access processing in a timely manner. Summary of the Invention

[0005] Embodiments of this application provide a memory protection unit, an electronic device, and an access monitoring method, which are used to perform exception access processing in a timely manner.

[0006] In a first aspect, embodiments of this application provide a memory protection unit, which is used for:

[0007] Receiving an access signal sent by an access unit when the access unit needs to access memory;

[0008] After determining that the master controller in the access unit has valid access and determining that the access unit is restricted from accessing memory based on the access signal sent by the access unit, sending a bus exception signal to the master controller, so that the master controller performs exception access processing after receiving the bus exception signal.

[0009] In the above solution, after the memory protection unit determines that the master controller has valid access and determines that the access unit is restricted from accessing memory based on the access signal sent by the access unit, it sends a bus exception signal to the master controller. Since the bus exception signal is not affected by the interrupt enable and interrupt signals, the master controller can quickly receive the bus exception signal; the latency from when the master controller receives the bus exception signal to when it enters the bus exception handling program is short, so as to perform exception access processing in a timely manner.

[0010] In some alternative embodiments, the memory protection unit includes a detection module, an exception handling module, and an address configuration register;

[0011] The detection module is configured to, based on the access signal sent by the access unit and the protection access information in the address configuration register, notify the exception handling module after determining that the access unit's access to the memory is restricted;

[0012] The exception handling module is configured to send the bus exception signal to the main controller after determining that the main controller's access is valid and the detection module notifies that the access unit's access to the memory is restricted.

[0013] In some alternative embodiments, if the main controller in the access unit sends the access signal when accessing the memory, the exception handling module is specifically configured to:

[0014] Based on the first signal indicating the access type in the access signal sent by the main controller, determine whether the main controller's access is valid.

[0015] In some alternative embodiments, if the slave controller in the access unit sends the access signal when accessing the memory, the exception handling module is specifically configured to:

[0016] Receive the access signal sent by the main controller when accessing the memory, and based on the first signal indicating the access type in the access signal sent by the main controller, determine whether the main controller's access is valid.

[0017] In the above solution, based on the first signal indicating the access type sent by the main controller, the exception handling module can accurately determine whether the main controller's access is valid.

[0018] In some alternative embodiments, the exception handling module includes a comparator, a delay unit, and a selector, where:

[0019] The first input end of the comparator is connected to the output end of the main controller for receiving the first signal sent by the main controller; the second input end of the comparator is used for receiving the signal indicating the valid access type; the output end of the comparator is connected to the first input end of the delay unit for outputting a second signal indicating that the main controller's access is valid or a third signal indicating that the main controller's access is invalid;

[0020] The second input terminal of the delay unit is connected to the output terminal of the detection module, and is used to receive a fourth signal sent by the detection module after determining that the access unit has limited access to the memory; the output terminal of the delay unit is connected to the first input terminal of the selector, and is used to output a fifth signal indicating an abnormal selection bus or a sixth signal indicating a normal selection bus;

[0021] The second input terminal of the selector is used to receive a bus normal signal; the third input terminal of the selector is used to receive a bus abnormal signal; the output terminal of the selector is connected to the input terminal of the main controller, and is used to output the bus normal signal or the bus abnormal signal.

[0022] In some alternative embodiments, the comparator is configured to:

[0023] If the first signal sent by the main controller received is the same as the signal representing the valid access type, then output the second signal through the output terminal; otherwise, output the third signal.

[0024] In some alternative embodiments, the delay unit is configured to:

[0025] If the second signal and the fourth signal are received, then output the fifth signal through the output terminal;

[0026] If the third signal and the fourth signal are received, then output the sixth signal through the output terminal.

[0027] In some alternative embodiments, the delay unit is specifically configured to:

[0028] After a target duration of receiving the second signal and the fourth signal, output the fifth signal, where the target duration is determined based on the bus protocol of the main controller.

[0029] In some alternative embodiments, the selector is configured to:

[0030] If the fifth signal is received, then output the bus abnormal signal through the output terminal;

[0031] If the sixth signal is received, then output the bus normal signal through the output terminal.

[0032] In a second aspect, an embodiment of the present application provides an electronic device, including the memory protection unit described in the first aspect above.

[0033] In a third aspect, an embodiment of the present application provides an access monitoring method, which is applied to a memory protection unit, and the method includes:

[0034] Receiving an access signal sent by an access unit when it needs to access the memory;

[0035] After determining that the access of the master controller in the access unit is valid and determining that the access of the access unit to the memory is restricted based on the access signal sent by the access unit, a bus exception signal is sent to the master controller, so that the master controller performs exception access processing after receiving the bus exception signal. Description of the Drawings

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0037] Figure 1 Shown is a schematic structural diagram of the first electronic device provided in the embodiment of the present application;

[0038] Figure 2 Shown is a schematic structural diagram of the second electronic device provided in the embodiment of the present application;

[0039] Figure 3 Shown is a schematic structural diagram of the detection module provided in the embodiment of the present application;

[0040] Figure 4 Shown is a schematic structural diagram of the third electronic device provided in the embodiment of the present application;

[0041] Figure 5 Shown is a schematic structural diagram of the comparator provided in the embodiment of the present application;

[0042] Figure 6 Shown is a schematic structural diagram of the delay element provided in the embodiment of the present application;

[0043] Figure 7 Shown is a schematic structural diagram of the selector provided in the embodiment of the present application;

[0044] Figure 8 Shown is a flowchart of the access monitoring method provided in the embodiment of the present application. Detailed Embodiments

[0045] In order to make the objectives, technical solutions and advantages of the present application clearer, the following will further describe the present application in detail with reference to the drawings. Obviously, the described embodiments are only some embodiments of the present application, rather than all embodiments. All other embodiments obtained by those of ordinary skill in the art without creative efforts based on the embodiments in the present application belong to the scope of protection of the present application.

[0046] In the SOC, the CPU and other master devices can all access the memory. To protect the security of the memory data, the access of the CPU and other master devices can be monitored by the MPU.

[0047] In the related art, when the MPU detects that the CPU or other master device requests to access a restricted address, it will send an interrupt signal to the CPU, and the CPU will perform exception access processing after receiving the interrupt signal.

[0048] However, the CPU may be processing other interrupt signals at this time; or the interrupt enable is turned off due to timeliness requirements, so that the CPU cannot receive this interrupt signal in time. In addition, the delay from when the CPU receives the interrupt signal to entering the interrupt handler is relatively long. That is, after a long time of abnormal access, the CPU enters the interrupt handler to perform abnormal access processing, which is not conducive to accurately locating the abnormal access.

[0049] Based on this, the embodiments of the present application provide a memory protection unit, an electronic device, and an access monitoring method to perform exception access processing in a timely manner. The technical solutions of the present application and how the technical solutions of the present application solve the above technical problems will be described in detail below with specific embodiments.

[0050] Figure 1 It is a schematic structural diagram of an electronic device provided by an embodiment of the present application. Refer to Figure 1 As shown, the electronic device may include a main controller 100, a slave controller 200 (the number of slave controllers may be one or more, Figure 1 taking m slave controllers as an example for illustration), and a memory protection unit 300, where:

[0051] An access unit (the above main controller 100 or slave controller 200) is configured to send an access signal to the memory protection unit 300 when accessing the memory is required;

[0052] The memory protection unit 300 is configured to send a bus exception signal to the main controller when it is determined that the access of the main controller in the above access unit is valid and it is determined based on the access signal sent by the access unit that the access unit's access to the memory is restricted;

[0053] The main controller 100 is configured to perform exception access processing after receiving the bus exception signal.

[0054] That is to say, the electronic device described in the embodiments of the present application may include an access unit and a memory protection unit connected to the access unit. The access unit may include a main controller and a slave controller. When any of the above access units (the main controller or the slave controller in the access unit) needs to access the memory, it sends an access signal to the memory protection unit. After determining that the access of the main controller is valid and determining that the access of the access unit to the memory is restricted based on the access signal sent by the access unit, the memory protection unit sends a bus exception signal to the main controller. The bus exception signal is not affected by the interrupt enable and the interrupt signal, and the main controller can quickly receive the bus exception signal. The time delay from when the main controller receives the bus exception signal to when it enters the bus exception handling program is short, so that the abnormal access can be processed in time.

[0055] Consistent with a conventional electronic device, the electronic device described in the embodiments of the present application may further include a memory (not shown in the figure) for storing data, which will not be elaborated herein.

[0056] It should be noted that the specific circuits in each module provided in the embodiments of the present application can be built by oneself, and any one or more (two or more) of the modules can be integrated on the corresponding Printed Circuit Board (PCB) or chip to achieve miniaturization and integration of the electronic device, which will not be elaborated herein.

[0057] Specifically, the above main controller can be a CPU, and the slave controller is a master that can access the memory other than the CPU in the electronic device, such as a Digital Signal Processing (DSP), a Direct Memory Access (DMA), etc.

[0058] In some optional embodiments, the above memory protection unit 300 may include a detection module 310, an exception handling module 320, and an address configuration register 330. Then, the specific structural schematic diagram of the electronic device may be as Figure 2 shown.

[0059] The above detection module 310 is configured to notify the exception handling module 320 after determining that the access of the access unit to the memory is restricted based on the access signal sent by the access unit (the above main controller 100 or the slave controller 200) and the protection access information in the address configuration register 330.

[0060] Specifically, the detection module 310 is connected to the main controller 100 and the slave controller 200 described above, and can detect whether the access signals sent by the main controller 100 and the slave controller 200 are restricted. For example: both the main controller and the slave controller have their respective restricted access types and corresponding restricted access addresses. The main controller writes the protection access information of the main controller and each slave controller (each protection access information includes information representing the restricted access type and the corresponding information representing the restricted access address) into the above address configuration register; when the access unit (main controller or slave controller) sends an access signal (including a first signal representing the access type and a seventh signal representing the access address) when accessing the memory, after receiving the first signal and the seventh signal, the detection module determines the protection access information corresponding to the access unit in the address configuration register. If there is target protection access information in the determined protection access information (the information representing the restricted access type in the target protection access information is the same as or corresponding to the first signal, and the information representing the restricted access address in the target protection access information is the same as or corresponding to the seventh signal), it is determined that the access unit's access to the memory is restricted. Refer to Figure 3 As shown, the detection module includes a type comparator corresponding to the main controller and each slave controller, an address comparator corresponding to the main controller and each slave controller, an AND gate corresponding to the main controller and each slave controller, and an OR gate connected to each AND gate. After the type comparator corresponding to the main controller receives the first signal sent by the main controller, if there is information representing the restricted access type in the protection access information corresponding to the main controller that matches the first signal, the type comparator outputs a signal representing the restricted access type to the corresponding AND gate; after the address comparator corresponding to the main controller receives the seventh signal sent by the main controller, if there is information representing the restricted access address in the protection access information corresponding to the main controller that matches the seventh signal, the address comparator outputs a signal representing the restricted access address to the corresponding AND gate. After receiving the signal representing the restricted access type and the signal representing the restricted access address, the AND gate outputs a signal representing the restricted access of the main controller to the OR gate. In the same way, after the AND gate corresponding to the slave controller receives the signal representing the restricted access type and the signal representing the restricted access address, it outputs a signal representing the restricted access of the slave controller to the OR gate. As long as the OR gate receives a signal representing the restricted access of any access unit, the fourth signal is triggered.

[0061] The above abnormal processing module 320 is connected to the main controller 100 and is used to send a bus exception signal to the main controller 100 after determining that the access of the main controller 100 is valid and the detection module notifies that the access unit's access to the memory is restricted.

[0062] Refer to Figure 2, The exception handling module is connected in series to the bus for the main controller to access memory, and can send a bus exception signal to the main controller. After receiving this bus exception signal, the main controller will immediately enter the bus exception handling program.

[0063] In implementation, it is determined that the main controller access is valid, that is, it is determined that the main controller issues an access request of a valid access type.

[0064] In some embodiments, if the main controller in the access unit sends the access signal when accessing memory, the exception handling module is specifically configured to: based on the first signal indicating the access type in the access signal sent by the main controller, determine whether the main controller access is valid. That is, determine whether the access type indicated by the first signal sent by the main controller is a valid access type.

[0065] In some embodiments, if the slave controller in the access unit sends the access signal when accessing memory, the exception handling module is specifically configured to: receive the access signal sent by the main controller when accessing memory, and based on the first signal indicating the access type in the access signal sent by the main controller, determine whether the main controller access is valid.

[0066] That is to say, the main controller can send an access signal before the slave controller sends an access signal; or send an access signal after the slave controller sends an access signal; or send an access signal when the slave controller sends an access signal. The exception handling module determines whether the main controller access is valid based on the first signal (the signal indicating the access type) in the access signal sent by the main controller. That is, determine whether the access type indicated by the first signal sent by the main controller is a valid access type.

[0067] In some alternative embodiments, the exception handling module 320 includes a comparator 321, a delay unit 322, and a selector 323, and the specific structural schematic diagram of the electronic device can be as Figure 4 shown.

[0068] Refer to Figure 4 and Figure 5 shown, the first input terminal (IN1) of the comparator 321 is connected to the output terminal of the main controller 100 for receiving the first signal sent by the main controller 100; the second input terminal (IN2) of the comparator 321 is used for receiving a signal indicating a valid access type; the output terminal (OUT) of the comparator 321 is connected to the first input terminal (IN1) of the delay unit 322 for outputting a second signal indicating that the main controller access is valid or a third signal indicating that the main controller access is invalid;

[0069] Refer to Figure 4 and Figure 6As shown, the second input terminal (IN2) of the delay device 322 is connected to the output terminal of the detection module 310, and is used to receive the fourth signal sent by the detection module 310 after determining that the access unit has limited access to the memory; the output terminal (OUT) of the delay device 322 is connected to the first input terminal (IN1) of the selector 323, and is used to output a fifth signal representing an abnormal selection bus or a sixth signal representing a normal selection bus;

[0070] Refer to Figure 4 and Figure 7 As shown, the second input terminal (IN2) of the selector 323 is used to receive a bus normal signal; the third input terminal (IN3) of the selector 323 is used to receive a bus abnormal signal; the output terminal of the selector 323 is connected to the input terminal of the main controller, and is used to output the bus normal signal or the bus abnormal signal.

[0071] In some optional embodiments, the comparator 321 is used for:

[0072] If the first signal sent by the received main controller is the same as the signal representing the valid access type, then output the second signal through the output terminal; otherwise, output the third signal.

[0073] Exemplarily, the valid access types are "write operation" and "read operation", and the signals corresponding to the valid access types are "1" and "0". If the first signal is "1" or "0", it means that the access type represented by the first signal is a valid access type and the main controller access is valid. If the second signal is a high-level signal (the high-level signal represents that the main controller access is valid); then the third signal is a low-level signal (the low-level signal represents that the main controller access is invalid). If the second signal is a low-level signal (the low-level signal represents that the main controller access is valid); then the third signal is a high-level signal (the high-level signal represents that the main controller access is invalid). It can be specifically set according to the actual application scenario, and this embodiment does not limit this.

[0074] In some optional embodiments, the delay device 322 is used for:

[0075] If the second signal and the fourth signal are received, then output the fifth signal through the output terminal;

[0076] If the third signal and the fourth signal are received, then output the sixth signal through the output terminal.

[0077] As described above, the detection module will send the fourth signal to the timer only after determining that the access unit has limited memory access. If the timer receives this fourth signal and the second signal indicating that the main controller access is valid, the exception handling module needs to send a bus exception signal to the main controller. In implementation, when the timer receives the second signal and the fourth signal, it outputs a fifth signal indicating the selection of bus exception through the output terminal of the timer; when it receives the third signal and the fourth signal, it outputs a sixth signal indicating the selection of bus normality through the output terminal of the timer. If the fifth signal is a high-level signal (the high-level signal indicates the selection of bus exception); then the sixth signal is a low-level signal (the low-level signal indicates the selection of bus normality). If the fifth signal is a low-level signal (the low-level signal indicates the selection of bus exception); then the sixth signal is a high-level signal (the high-level signal indicates the selection of bus normality). Specifically, it can be set according to the actual application scenario, and this embodiment does not limit it.

[0078] In some alternative embodiments, the timer 322 is specifically configured to:

[0079] After a target duration of receiving the second signal and the fourth signal, output the fifth signal, and after a target duration of receiving the third signal and the fourth signal, output the sixth signal. The target duration is determined based on the bus protocol of the main controller.

[0080] Specifically, different main controllers correspond to different bus protocols, and the bus protocol stipulates the delay requirements for the bus exception signal and the bus normality signal. After the timer receives the second signal and the fourth signal, it starts counting the delay. After reaching the number of clock cycles of the delay requirement, it outputs the fifth signal to the selector; after the timer receives the third signal and the fourth signal, it starts counting the delay. After reaching the number of clock cycles of the delay requirement, it outputs the sixth signal to the selector.

[0081] In some alternative embodiments, the selector 323 is used to:

[0082] If it receives the fifth signal indicating the selection of bus exception, output the bus exception signal through the output terminal;

[0083] If it receives the sixth signal indicating the selection of bus normality, output the bus normality signal through the output terminal.

[0084] As described above, the second input terminal of the selector is used to input the bus normality signal, and the third input terminal is used to input the bus exception signal. The selector responds to the fifth signal indicating the selection of bus exception received through the first input terminal and selects the bus exception signal for output; or, responds to the sixth signal indicating the selection of bus normality received through the first input terminal and selects the bus normality signal for output.

[0085] Based on the same inventive concept, an embodiment of the present application further provides an access monitoring method, which is applied to the above-mentioned memory protection unit. Refer to Figure 8 as shown, the method includes:

[0086] Step S801: Receive an access signal sent by an access unit when it needs to access memory.

[0087] Step S802: After determining that the main controller in the access unit has a valid access and determining that the access unit is restricted from accessing memory based on the access signal sent by the access unit, send a bus exception signal to the main controller, so that the main controller performs exception access processing after receiving the bus exception signal.

[0088] Among them, the specific implementation of the above-mentioned memory protection unit can refer to the above-mentioned embodiment, which will not be elaborated here.

[0089] Correspondingly, the access monitoring method described in the embodiment of the present application can be implemented by a corresponding entity device, such as a corresponding computing device, etc.

[0090] Furthermore, the access monitoring method described in the embodiment of the present application can also be implemented by a corresponding computer. Each step in the method can correspond to corresponding computer program instructions. A computer storage medium can be used to store the computer program instructions used for the above-mentioned computing device, which includes a program for executing the above-mentioned access monitoring method.

[0091] The computer storage medium can be any available medium or data storage device that can be accessed by a computer, including but not limited to magnetic memories (such as floppy disks, hard disks, magnetic tapes, magneto-optical disks (MO), etc.), optical memories (such as CDs, DVDs, BDs, HVDs, etc.), and semiconductor memories (such as ROMs, EPROMs, EEPROMs, non-volatile memories (NAND FLASH), solid state drives (SSDs)), etc.

[0092] Those skilled in the art should understand that the embodiments of the present application can be provided as methods, devices (equipment), or computer program products. Therefore, the present application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk memories, CD-ROMs, optical memories, etc.) containing computer-usable program codes.

[0093] This application is described with reference to the flowcharts and / or block diagrams of methods, apparatuses (devices), and computer program products according to embodiments of the present application. It should be understood that each flow and / or block in the flowchart and / or block diagram can be implemented by computer program instructions, as well as the combination of flows and / or blocks in the flowchart and / or block diagram. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, such that the instructions executed by the processor of the computer or other programmable data processing devices generate a device for implementing the functions specified in one or more flows Figure 1 or more flows and / or blocks Figure 1 or more blocks.

[0094] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, such that the instructions stored in the computer-readable memory generate a manufactured article including an instruction device that implements the functions specified in one or more flows Figure 1 or more flows and / or blocks Figure 1 or more blocks.

[0095] These computer program instructions can also be loaded onto a computer or other programmable data processing device, such that a series of operation steps are executed on the computer or other programmable device to generate a computer-implemented process, so that the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more flows Figure 1 or more flows and / or blocks Figure 1 or more blocks.

[0096] Although the preferred embodiments of the present application have been described, those skilled in the art can make additional changes and modifications once they learn the basic creative concepts. Therefore, the appended claims are intended to be construed to include the preferred embodiments as well as all changes and modifications falling within the scope of the present application.

[0097] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application is also intended to include these changes and modifications.

Claims

1. A memory protection unit, characterized in that, The memory protection unit is used for: Receiving an access signal sent by the access unit when the access unit needs to access memory; After determining that the main controller in the access unit has a valid access and determining that the access unit is restricted from accessing memory based on the access signal sent by the access unit, sending a bus exception signal to the main controller so that the main controller performs exception access processing after receiving the bus exception signal; The memory protection unit includes a detection module, an exception processing module, and an address configuration register; The detection module is used for, based on the access signal sent by the access unit and the protection access information in the address configuration register, notifying the exception processing module after determining that the access unit is restricted from accessing memory; The exception processing module is used for, after determining that the main controller has a valid access and the detection module notifies that the access unit is restricted from accessing memory, sending the bus exception signal to the main controller; The exception processing module includes a comparator, a delay unit, and a selector, where: A first input end of the comparator is connected to an output end of the main controller and is used for receiving a first signal representing an access type in the access signal sent by the main controller; a second input end of the comparator is used for receiving a signal representing a valid access type; an output end of the comparator is connected to a first input end of the delay unit and is used for outputting a second signal representing that the main controller has a valid access or a third signal representing that the main controller has an invalid access; A second input end of the delay unit is connected to an output end of the detection module and is used for receiving a fourth signal sent by the detection module after determining that the access unit is restricted from accessing memory; an output end of the delay unit is connected to a first input end of the selector and is used for outputting a fifth signal representing selecting a bus exception or a sixth signal representing selecting a normal bus; A second input end of the selector is used for receiving a bus normal signal; a third input end of the selector is used for receiving a bus exception signal; an output end of the selector is connected to an input end of the main controller and is used for outputting the bus normal signal or the bus exception signal.

2. The memory protection unit according to claim 1, characterized in that, If the main controller in the access unit sends the access signal when it needs to access memory, the exception processing module is specifically used for: Judging whether the main controller has a valid access based on the first signal representing the access type in the access signal sent by the main controller.

3. The memory protection unit according to claim 1, wherein If the slave controller in the access unit sends the access signal when it needs to access memory, the exception processing module is specifically used for: Receiving the access signal sent by the main controller when it needs to access memory, and judging whether the main controller has a valid access based on the first signal representing the access type in the access signal sent by the main controller.

4. The memory protection unit according to claim 1, characterized in that The comparator is used for: If the received first signal sent by the main controller is the same as the signal representing the valid access type, outputting the second signal through the output end; otherwise, outputting the third signal.

5. The memory protection unit according to claim 1, characterized in that, The delay unit is used for: If receiving the second signal and the fourth signal, outputting the fifth signal through the output end; If the third signal and the fourth signal are received, the sixth signal is output through the output terminal.

6. The memory protection unit as claimed in claim 5, wherein, The delay unit is specifically configured to: After a target duration of receiving the second signal and the fourth signal, output the fifth signal, where the target duration is determined based on the bus protocol of the main controller.

7. The memory protection unit according to claim 1, characterized in that, The selector is configured to: If the fifth signal is received, output the bus exception signal through the output terminal; If the sixth signal is received, output the bus normal signal through the output terminal.

8. An electronic device, characterized in that, It includes a memory protection unit as described in any one of claims 1 to 7.

9. An access monitoring method, characterized in that, Applied to a memory protection unit, the method includes: Receiving an access signal sent by an access unit when it needs to access memory; After determining that the access of the main controller in the access unit is valid and determining that the access unit is restricted from accessing memory based on the access signal sent by the access unit, sending a bus exception signal to the main controller, so that the main controller performs exception access processing after receiving the bus exception signal; The memory protection unit includes a detection module, an exception processing module, and an address configuration register; after determining that the access of the main controller in the access unit is valid and determining that the access unit is restricted from accessing memory based on the access signal sent by the access unit, sending a bus exception signal to the main controller, so that the main controller performs exception access processing after receiving the bus exception signal, including: Through the detection module, based on the access signal sent by the access unit and the protection access information in the address configuration register, after determining that the access unit is restricted from accessing memory, notify the exception processing module; Through the exception processing module, after determining that the main controller access is valid and the detection module notifies that the access unit is restricted from accessing memory, send the bus exception signal to the main controller; The exception processing module includes a comparator, a delay unit, and a selector. After determining that the main controller access is valid and the detection module notifies that the access unit is restricted from accessing memory, sending the bus exception signal to the main controller includes: Receiving, through a first input terminal of the comparator, a first signal representing an access type in the access signal sent by the main controller, and receiving, through a second input terminal of the comparator, a signal representing a valid access type; outputting, through an output terminal of the comparator, a second signal representing that the main controller access is valid or a third signal representing that the main controller access is invalid; Receiving, through a second input terminal of the delay unit, a fourth signal sent by the detection module after determining that the access unit is restricted from accessing memory; outputting, through an output terminal of the delay unit, a fifth signal representing selecting a bus exception or a sixth signal representing selecting a bus normal; Receiving, through a second input terminal of the selector, a bus normal signal; receiving, through a third input terminal of the selector, a bus exception signal; the output terminal of the selector outputs the bus normal signal or the bus exception signal.

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