Stacked register with different ferroelectric memory element configurations

Abstract

Stacked registers having different ferroelectric memory element configurations are disclosed. Apparatuses and methods for managing data in processing systems, such as but not limited to data storage devices such as solid state drives (SSDs). A ferroelectric stacked register memory has a first arrangement of ferroelectric memory cells (FMEs) of a first configuration and a second arrangement of FMEs of a different second configuration, the first and second arrangements being arranged to provide respective cache lines for use by a controller, such as a programmable processor. A pointer mechanism is configured to provide a pointer to each of the respective cache lines based on a time sequence of operations of the processor. Data sets can be migrated into the different arrangements as needed by the controller based on different operational characteristics of the respective FME configurations. The FMEs can be non-volatile and read-disturbive. Refresh circuitry can be selectively implemented in different operational modes.

Description

[0001] Related Applications

[0002] This application claims domestic priority under 35 U.S.C. 119(e) to co-pending U.S. Provisional Patent Application No. 63 / 201,395, filed April 28, 2021, the contents of which are incorporated by reference herein. SUMMARY

[0003] Various embodiments of the present disclosure generally relate to a stack register comprised of ferroelectric memory elements (FMEs), such as but not limited to FeRAM (ferroelectric random access memory), FTJ (ferroelectric tunnel junction), and FeFET (ferroelectric field effect transistor).

[0004] In some embodiments, a ferroelectric stack register memory has a first arrangement of FMEs of a first configuration and a second arrangement of FMEs of a different second configuration, the first and second arrangements being arranged to provide respective cache lines for use by a controller, such as a programmable processor. A pointer mechanism is configured to provide a pointer to each of the respective cache lines based on a time sequence of operations of the processor. Data sets can be migrated into the different arrangements as needed by the controller based on different operational characteristics of the respective FME configurations. The FMEs can be non-volatile and read destructive. A refresh circuitry can be selectively implemented in different operational modes.

[0005] These and other features and advantages of various embodiments can be understood from a review of the following detailed description, taken in conjunction with the drawings. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figure 1 is a functional block diagram of a data processing system constructed and operative in accordance with various embodiments.

[0007] Figure 2 is a functional block representation of a data storage device characterized as a solid state drive (SSD) in some embodiments. Figure 1

[0008] Figure 3 illustrates a stack register comprised of FME elements that can be incorporated in a data storage device of Figure 1 and Figure 2 in accordance with some embodiments.

[0009] Figure 3A illustrates a time sequence of data sets written to a stack register of Figure 3 in accordance with some embodiments.

[0010] Figure 4 illustrates another ferroelectric-based stack register constructed and operative in accordance with some embodiments.​

[0011] Figure 5 Yet another ferroelectric-based stack register is shown, according to some embodiments, to illustrate various control circuitry for accessing data bits therein.

[0012] Figure 6 is a functional block diagram of an FME configured as a ferroelectric tunnel junction (FTJ).

[0013] Figure 7 is a functional block diagram of an FME configured as a FeRAM memory element having a transistor and a capacitor.

[0014] Figure 8 is a functional block diagram of an FME configured as a FeFET having a ferroelectric layer.

[0015] Figure 9 Another ferroelectric stack register is shown, according to further embodiments, having a cache line composed of FMEs of different configurations.

[0016] Figure 10 Systems having programmable processors and various types of local memory are shown constructed and operated according to various embodiments. DETAILED DESCRIPTION

[0017] Various embodiments of the present disclosure generally relate to systems and methods for providing stack register memory composed of ferroelectric memory elements (FMEs).

[0018] FMEs are semiconductor-based memory elements that provide non-volatile data storage with fast response and low power consumption characteristics. Depending on the configuration, FMEs can include various semiconductor layers such as one or more of conductive electrodes, ferroelectric layers, tunneling layers, dielectric layers, channel layers, drain, source, and gate regions, etc. Data bit(s) are stored by the FME according to a programmed polarity stored in one or more ferroelectric layers of the element.

[0019] Different polarities provide different current densities through the memory element when current is passed through the programmed ferroelectric layer. In this way, FMEs can be viewed as operating in a manner similar to resistive random access memory (RRAM), phase change memory, spin-torque memory, etc., where programmed states can be detected based on different electrical responses (e.g., different electrical conductivity, current density, resistance, voltage drop, etc.) across the element. Like these elements, FMEs tend to be non-volatile, thus retaining stored programmed bit configurations even in the absence of applied power.

[0020] A wide variety of FME constructions have been proposed. These include ferroelectric tunnel junctions (FTJ), ferroelectric field effect transistors (FeFET), and ferroelectric random access memories (FeRAM). Other forms of FME have also been proposed.

[0021] Generally, FTJ are somewhat analogous to magnetic tunnel junctions (MTJ) and are typically arranged as a two-junction cell having a ferroelectric layer and a tunnel barrier layer sandwiched between opposing electrodes. FTJ are particularly well suited for cross-point arrays and other architectures having two connection points to each memory element.

[0022] FeFET are somewhat analogous to flash memory cells and typically include a gate structure arranged between respective source and drain doped regions. The gate structure includes a ferroelectric layer. FeFET typically have three junctions (drain, source, gate) and can be readily arranged as two-dimensional (2D) or three-dimensional (3D) structures.

[0023] FeRAM cells are somewhat analogous to DRAM cells and are typically arranged with at least one transistor and at least one capacitor. The capacitor structure includes a ferroelectric layer. A tunnel barrier layer can also be provided in the capacitor. Numerous FeRAM arrangements have been proposed, including 1T1FC (one transistor, one ferroelectric capacitor) cells, 2T2C cells, 1T4C cells, 6T4C cells, etc. The transistor in each FeRAM cell can be a conventional transistor (e.g., a regular field effect transistor FET), but in some cases, ferroelectric layer(s) can be applied to the gate structure of the transistor as well as the capacitor (“double-layer FeRAM”).

[0024] A wide variety of materials, metals, and alloys can be used to construct the respective ferroelectric, tunnel, and electrode layers. Suitable materials for the ferroelectric layer can include, but are not limited to, Hf02, Zr02, Hf 1-x Z x O2, etc. These materials can be doped with other elements such as, but not limited to, Si, Ge, Al, Ti, Sc, Y, La, Ce, Gd, Nb, Sr, Ba, N, etc. The tunnel layer(s) can be suitable non-ferroelectric dielectrics including, but not limited to, Al203, MgO, SrTi03, etc. The electrodes are conductive materials and can include, but are not limited to, TiN, TaN, Pt, Ag, CrRu, CrMo, CrW, CrTi, and RuAl. In some cases, an anti-ferroelectric material such as Zr02may be used in place of a ferroelectric layer if an internal bias field is introduced (e.g., from two dissimilar electrodes) to shift its hysteresis loop to enable storage of binary information. These and other examples are merely illustrative and not limiting.

[0025] A programmable processor is a complex electronic circuit having the ability to execute executable instructions stored in local memory. One form of memory commonly used with processors is a stack register, which is a memory configured to maintain data (e.g., instructions, control parameters, etc.) in a stack. While not required, most stacks are logically arranged such that information elements are pushed into the stack and pulled from the stack in a selected order. Pointer mechanisms are used to track the location of various entries in the stack.

[0026] In this manner, in certain applications, a stack register can be viewed as a "stack" of data entries that are at least logically "pushed down" into the stack as entries are added, and then "pulled out" of the stack as needed. While it is possible to maintain a stack register such that various data bits are physically moved up and down among physically oriented memory cells, it is more common to perform these moves virtually. In the latter case, pointers are used to identify the location of the "top" of the stack, and to maintain the virtual order of the stack among physical memory locations.

[0027] While one particularly useful form of a stack register is in the realm of local memory for programmable processors (e.g., LI cache, L2 cache, etc.), other forms of stack registers have been used in many operating environments, including in the realm of data storage devices at various locations in a data pipeline as data is processed for storage to main memory, and as data is retrieved from main memory and processed for relocation or presentation to a host (client) device.

[0028] Ferroelectric memory offers many advantages over existing memory types, including guaranteed transfer speeds that meet or exceed that of volatile DRAM (dynamic random access memory), and wear resistance capabilities that exceed that of flash memory. Accordingly, there is a need to incorporate ferroelectric memory into conventional areas where these or other forms of conventional memory have been utilized, including into the realm of stack memory.

[0029] The present disclosure generally relates to stack register memory that is constructed with FMEs having different response characteristics. The present disclosure contemplates different available FME constructions having different resonance characteristics to meet the needs of a given operating environment. In certain cases, a multi-layer construction can be provided, where the stack order is selected based on various internal and external parameters. This solution provides flexibility to provide the necessary storage and pointer (tracking) functionality to manage data / instruction sets, while taking advantage of different types of FME responses. Both two-dimensional (2D) and three-dimensional (3D) arrangements can be used.

[0030] These and other features and advantages of various embodiments can be Figure 1 appreciated, Figure 1A functional representation of a data processing system 100 is shown. The system 100 includes a client (host) device 101 in communication with a data storage device 102 via an interface 103. The client device 101 can take the form of a personal computer, a smart phone, a workstation, a tablet computer, a laptop computer, a gaming system, a microcontroller, a server, an edge device, an Internet of Things (IoT) device, a mass storage array, and the like.

[0031] The data storage device 102 is configured to store and retrieve data used by a user of the client device 101 and can be a local processor memory, a data cache, a server cache, a RAID storage system, a cloud storage system, a solid state drive (SSD), a hard disk drive (HDD), a hybrid storage device, a storage device array, a portable thumb (e.g., USB) drive, and the like. The interface 103 can take substantially any form, including but not limited to a local wired or wireless interface, a local area network (LAN), a wide area network (WAN), a cloud computing interface, the Internet, and the like. Substantially any useful interface protocol can be implemented for the interface 103, including Ethernet, USB, SCSI, SAS, Fibre Channel, PCMI, wireless connections, and the like.

[0032] Of interest is the data storage device 102, which is shown to include a controller 104 and a memory 106. The controller 104 can include one or more programmable processors that execute program instructions stored in local memory to perform various functions, including controlling the transfer of data between the memory 106 and the client device 101 over the interface 103. Additionally or alternatively, the controller 104 can utilize a processor based on hardware circuitry, such as a processor constructed from ASICs (application specific integrated circuits), FPGAs (field programmable gate arrays), system on a chip (SOCs), state machines, or other arrangements of gate logic.

[0033] The memory 106 can include any number of useful forms, including local memory for the controller, cache memory, buffers, main storage, and the like. The memory 106 includes non-volatile memory (NVM) consistent with the customary usage of the term, which will be understood to be a persistent storage that continues to retain information stored therein even after removal of applied power to the memory. The form of main data storage can take any number of forms, including semiconductor-based memory, rotatable data storage memory, tape-based memory, and the like.

[0034] Figure 2 Aspects of a data storage device 110 corresponding to the data storage device 102 from Figure 1 is depicted in some embodiments. In Figure 2In the depicted embodiment, the data storage device 110 is characterized as a solid state drive (SSD) that utilizes flash memory as the primary storage. This is not limiting, as any number of other forms of data storage devices can be utilized, including but not limited to hard disk drives (HDDs), hybrid drives, tape drives, optical drives, magneto-optical (MO) drives, and the like. Moreover, while flash memory constitutes the primary storage, other semiconductor memory types can be used, including but not limited to ferroelectric memory.

[0035] The SSD 110 includes a device controller 112 corresponding to the controller 104 in Figure 1 The write cache 114 is internal buffer storage that temporarily stores write data sets prior to transmission to the primary storage by an external host. These write data sets can be accompanied by write commands from a requesting client to store data for future use.

[0036] The flash memory electronics (FME) circuit 116 receives and processes the write data sets for transmission to the flash memory array 118. The read buffer 120 temporarily stores respective read-back data sets retrieved from the flash memory array 118 via the FME 116 in response to read commands. The read-back data is then transmitted from the read buffer 120 to the requesting client that issued the read command. The internal controller memory (MEM) 122 can store program instructions, data queues, command queues, mapping data, and other forms of control data to facilitate these operations.

[0037] Figure 3 The FME stack register memory 130 is shown as being incorporated into any of the above-described memory element locations of the SSD 110. Figure 2 This can include, but is not limited to, the controller 112, the write cache 114, the FME 116, the flash memory 118, the read buffer 120, and / or the embedded memory 122. The FME stack register memory 130 can also be incorporated into other operating environments, including but not limited to the client and data storage device as shown in Figure 1

[0038] The stack register 130 includes a plurality of FME cells 132 arranged sequentially along various addressable cache lines 134 represented by each "row" in the register. Any number of sequentially, serially connected cells can be provided along each cache line as desired. Read / write circuitry 136 writes multi-bit data ("entries") to the respective cache lines 134. Pointer circuitry 138 tracks different locations of data within the stack. While some arrangements store a single bit of data in each cell, this is not necessarily required; more than one bit or less than one bit per cell can be provided using known techniques.

[0039] ​At this point, it will be understood that each of the cells 132 in the stack register is an FME cell, such that the cells each have at least one ferroelectric layer configured to store data, the cells are non-volatile, and in most cases the cells are contemplated to be read destructive (e.g., once read, a refresh operation is needed to replenish the data to return the previously stored data to the array). However, as described below, various alternative configurations are contemplated, including stack registers with different configurations of FMEs, FME-based and non-FME-based cells, cells with special configurations of refresh characteristics, etc.

[0040] At this point it will be recognized that it is common to describe a "stack" of memory from a physical perspective, especially in the context of three-dimensional (3D) arrangements of memory cells, FMEs are particularly well suited for three-dimensional arrangements, and in some embodiments are expressly contemplated to be three-dimensional arrangements. However, in the context of a "stack register" or similar memory configuration, the concept of a "stack" is not so much related to the physical location of the data, but rather to the functional stack of data. Typically, the basis for the division of data in a stack register is a temporal reference; that is, a typical stack register operates like a FIFO (first-in-first-out) type buffer, such that a relative local priority or ordering is maintained. However, other functional bases for the sequence of data can be used, such as source, priority, etc.

[0041] Figure 3A A time-based priority ordering is depicted in FIG. 1 30, showing various sets of data 139 that have been stored to the stack register of 130, such as in a memory device 100. As depicted, a first set of data (set 1) is written first, followed by a second set of data (set 2), a third set of data (set 3), a fourth set of data (set 4), etc. The elapsed time is indicated by the arrow 139A. From a temporal perspective, set 4 is the most recently stored set of data, and set 1 is the oldest set of data residing in the memory stack. However, the physical location of these sets of data within the register 130 is not necessarily important, so long as the temporal (or other sequence reference) is maintained. Figure 3 Figure 3A As depicted, a first set of data (set 1) is written first, followed by a second set of data (set 2), a third set of data (set 3), a fourth set of data (set 4), etc. The elapsed time is indicated by the arrow 139A. From a temporal perspective, set 4 is the most recently stored set of data, and set 1 is the oldest set of data residing in the memory stack. However, the physical location of these sets of data within the register 130 is not necessarily important, so long as the temporal (or other sequence reference) is maintained.

[0042] In this way, data is pushed onto the stack, and pulled from the stack as needed. Due to the fast response, non-volatility, and low power consumption characteristics of FMEs, it is possible to physically migrate data through the stack as needed, such that data is transferred from one cache line to the next. In other words, while a physical location is not necessarily required to maintain order, there are some circumstances where it can be useful to physically migrate a set of data, such as those shown in FIG. 1 30, to a different location within the stack register. This can be particularly advantageous in constructions that use different types of FMEs, as described below. Figure 3A

[0043] ​​Returning to Figure 3 Each cell 132 in the stack register 130 includes at least one ferroelectric memory layer that is configured to store data in the form of one bit of data, a fraction of one bit of data, or multiple bits of data. The bits of data are stored with respect to the electrical orientation (polarization) of the respective layers. During use of the stack register, bits are read in and read out as needed. Because FMEs can generally be rewritten in place (e.g., a separate erase operation is generally not needed prior to writing new data), old data can be discarded by overwriting with new data, by overwriting with a baseline pattern (e.g., all zeros, etc.). Because certain FME constructions are read destructive, old data can also be discarded by simply reading without flushing the cell.

[0044] Figure 4 Another stack register 140 is shown in accordance with some embodiments. A single cache line is depicted as being composed of spaced ferroelectric memory layers (F) 142 that are spaced apart from other elements / layers 144. Data can be entered and retrieved in order as shown. Each memory layer 142 stores one or more bits along the cache line. A first end of the register is represented at 146, and a second end of the register is represented at 148. In some cases, read / write circuitry 149 can be used to propagate data bits through the stack register from the first end 146 to the second end 148. This can include the operation of reading a given programmed state of a given memory layer 142 and pushing that state (writing) to the next layer.

[0045] Figure 5 Additional aspects of another ferroelectric-based stack register 150 are shown in accordance with further embodiments. Figure 5 Various additional circuitry is shown for managing the ferroelectric programming state of the various ferroelectric layers of the memory. This circuitry includes program (write) drivers 152, read drivers 154, sense circuitry 156, and refresh circuitry 158.

[0046] The program drivers 152 are used to write (program) data to the various memory cells of the stack on a cache line basis. This can include presenting appropriate voltages and / or currents on control lines to place the associated ferroelectric layers into the desired programmed orientation.

[0047] The read drivers 154 place appropriate voltages and / or currents on the various control lines to enable the sense circuitry 156 to sense the programmed orientation of the various ferroelectric layers.

[0048] The refresh circuit 158 operates to refresh the current programmed state of the ferroelectric layer 402 at the appropriate time. In some cases, the refresh circuit 158 operates at the end of each read operation, as in those cases where the FME cell is read destructive, the read operation destroys the currently stored state. In such cases, once data is read from a selected location in the ferroelectric layer, the refresh circuit buffers and rewrites the previously stored data back to the selected location from which the data was retrieved (typically performed with a DRAM). That is, as the data bits are stored within a stack, it can be necessary to rewrite (or not rewrite) the data bits when reading the data.

[0049] However, in further embodiments, the refresh circuit 158 can selectively operate in different modes, such that the refresh circuit 158 can operate to selectively rewrite or not rewrite data read from the register in response to a mode select (enable / disable) signal 159 from the associated control circuit. This is useful in various applications, such as power down events, detected attacks, one-time programming applications, encryption systems, etc. For example, in a first mode, the refresh circuit 158 is operable to automatically refresh the data in the FME after a read operation; and in a second mode, the refresh circuit 158 does not refresh the data in the FME after a read operation.

[0050] Figure 6 The construction of each cell 132 of the stack register presented herein as FTJ 160 is shown. The FTJ 160 is a two-terminal device having external conductive electrode layers 162, 164, an internal ferroelectric material (programming) layer 164, and an optional tunnel barrier layer 166. The tunnel barrier layer 168 is contemplated, but not necessarily required as a separate layer, and can be any suitable material, such as but not limited to a non-ferroelectric material, a dielectric material, etc.

[0051] By appropriate selection of the electrode materials, tunnel barrier, and ferroelectric layer, the resistance of the FTJ can be made dependent on the ferroelectric polarization orientation of the ferroelectric layer 166. In other words, the FTJ, such as FTJ 160, operates in a manner similar to a magnetic tunnel junction (MTJ), and will exhibit different resistances between the electrodes 162, 164 based on the programmed polarization of the ferroelectric layer 166. The difference in resistance will vary by construction, but the difference resistance values can be greater than 10 4 ohms.

[0052] Figure 7 The construction of each cell 132 of the stack register presented herein as FTJ 160 is shown. The FTJ 160 is a two-terminal device having external conductive electrode layers 162, 164, an internal ferroelectric material (programming) layer 164, and an optional tunnel barrier layer 166. The tunnel barrier layer 168 is contemplated, but not necessarily required as a separate layer, and can be any suitable material, such as but not limited to a non-ferroelectric material, a dielectric material, etc. Figure 3Another example configuration of each of the memory cells 132 in the memory array 130 is shown. Each FeRAM cell 170 is characterized as a 1T1C arrangement, although other configurations can be used. The FeRAM cell 170 includes at least one transistor 172 and at least one capacitor 174. Each transistor 172 is constructed using a base semiconductor substrate 176 having respective doped regions 178, 180 to form respective source and drain regions. As shown, a channel (CH) is formed between these respective regions. A gate structure 182 is disposed between the source region 178 and the drain region 180 adjacent to the channel region. The gate structure 182 includes a conductive gate 184 and an isolation region 186.

[0053] A capacitor structure 188 extends from the drain region 180 via a conductive path 190. The capacitor structure includes an upper electrode layer 192 and a lower electrode layer 194. A ferroelectric layer 196 is disposed between the electrode layers 190, 192. If desired, a tunneling layer (not shown separately) can also be disposed between the electrode layers. In this way, a control gate voltage applied to the electrode conductive gate 184 can be used to determine the electrical polarity of the ferroelectric layer 196, which relates to the amount of voltage needed to place the transistor from the source 178 to the drain 180 in a forward conductive state.

[0054] Figure 8 An FME memory cell element configured as a FeFET 200 is shown. The FeFET 200 includes a semiconductor substrate 202 in which doped regions 204, 206 are formed to provide respective source and drain regions. A gate structure 208 is disposed between the source region 204 and the drain region 206 to manage a channel (CH) therebetween. The gate structure 208 includes a ferroelectric layer 210 sandwiched between an isolation layer 212 and a conductive gate layer 214. Note that many different gate structures for FeFETs are known, including single layers of ferroelectric material, adding an insulating layer (as shown), adding a metallic layer, a laminate arrangement with multiple spaced apart ferroelectric layers, etc. Although Figure 6- Figure 7 The FTJ 160 and the FeRAM 170 of Figure 8 The FeFET 200 of

[0055] Figure 9 Another FME stack register 300 according to some embodiments is shown. The stack register 300 employs a hybrid configuration in which the stack register has different regions composed of different types of FMEs, such as Figure 6- Figure 8Those shown in the diagram. More specifically, the exemplary stack register 300 has a first range of cache lines 302 consisting of FTJ 160s, a second range of cache lines 304 consisting of FeRAM 180s, and a third range of cache lines 306 consisting of FeFET 200s. Other arrangements may be used.

[0056] Coupled to the stack register 300 is a controller 310. The controller 310 may be similar to the controllers discussed above and may include hardware or a programmable processor. Elements of the controller 310 include a data loader 312, a pointer 314, and state circuitry 316. The data loader 312 manages the loading (and migration, reading, and removal as desired) of data to the various cache lines. The pointer 314 provides pointing functionality, including tracking the addresses of the cache lines where various data values ​​(entries) reside. The pointer circuitry system may utilize one or more data structures in memory to track the location of various datasets in the stack register 300, as well as other control data such as aging, priority, and status. The state circuitry 316 further manages the contents of the cache lines, including managing overall capacity and marking data as obsolete.

[0057] In this way, controller 310 can utilize different regions of the stack register to store data based on the characteristics of the associated configuration of the stack register cache lines. For example, FTJ can provide a faster response but shorter persistence compared to FeFET, so shorter data durations can be provided to range 302 compared to range 306.

[0058] It should be understood that, such as Figure 9 The described circuit system utilizes stack registers to store virtually any type of information, including but not limited to program instructions, data values, and control parameters. Data transfer can occur at very high speeds, generating throughput at virtually any desired rate. Simultaneously, the NVM characteristics of the layers mean that the data rate can be adjusted, slowed down, or sped up as needed to meet the requirements of other aspects of the system. Each layer can store single bits, multiple bits, or portions of bits as required. In some cases, datasets can be promoted to higher levels or demoted to lower levels in the cache to transfer data from an FME with a first construction type to an FME with a different second construction type.

[0059] Figure 10 This is another system 320 according to some embodiments. System 320 may generally correspond to a main controller including a programmable processor 322, such as those applicable to the above. Figure 1- Figure 2The system described in the middle. Programmable processor 322 has one or more central processing units (CPUs) that operate to execute program instructions (e.g., firmware, software, applications, containers, programs, etc.) stored in memory. Without limitation, the program instructions can utilize input data, and can generate output data, both of which can be stored (along with the program instructions) at different locations, including the same location. The processors can be single-core, multi-core, distributed, hardware-accelerated, and so on.

[0060] Figure 10 Further shown is an array of memory locations that can be accessed by programmable processor 322. These include a first level (LI) cache 324, a second level (L2) cache 326, a third level (L3) cache 328, an SRAM-type cache 330, and a DRAM-type cache 332. The LI, L2, and L3 caches can operate as known in the art to provide a hierarchy of fast local memory for the processor. Each of these can be constructed of any suitable memory, including the FME cells in the stack registers described above. The SRAM-type cache 330 can be constructed of SRAM or FME cells in the stack register arrangement as described above. The DRAM-type cache 332 can similarly be constructed of DRAM or FME cells in the stack register arrangement as described above.

[0061] Any number of different types of program instructions, control data, and user data can be loaded and used in the various memory locations in Figure 10 As noted previously, in at least some embodiments, different forms of FME cells can construct the various memory locations, enabling different characteristics to be selected for different needs.

[0062] It will now be appreciated that various embodiments of the present disclosure can provide certain benefits over the prior art. The use of variously constructed FME cells in one or more stack registers can enable efficient management of data storage and retrieval needs. While the operating environment has been presented in the context of data storage applications including, but not limited to, SSDs, it will be appreciated that various embodiments can be incorporated into substantially any number of different applications and environments.

[0063] It will be appreciated that, although specific embodiments of the disclosure have been described herein for purposes of illustration, various modifications can be made of the detailed procedures and configurations described herein, particularly with regard to the structure and configuration of the individual components within the principles of the present disclosure, as indicated by the broad scope of the terms expressed in the claims that follow.

[0064] Further examples:

[0065] Example 1. A ferroelectric stack register memory, comprising: a first arrangement of ferroelectric memory cells (FMEs) arranged to provide a first number of cache lines adapted to respectively receive a corresponding first number of data entries from a processor; a second arrangement of FMEs arranged to provide a second number of cache lines adapted to respectively receive a corresponding second number of data entries from the processor, the second number of cache lines being different from the first number of cache lines; and a pointer mechanism configured to provide a pointer to each of the respective first and second numbers of cache lines based on a time sequence of operations of the processor.

[0066] Example 2. The memory of example 1, wherein the first number of cache lines are comprised of ferroelectric tunnel junction (FJT) memory cells.

[0067] Example 3. The memory of example 1, wherein the first number of cache lines are formed as ferroelectric random access memory (FeRAM) memory cells each having at least one transistor and at least one capacitor.

[0068] Example 4. The memory of example 3, wherein the at least one capacitor in each FeRAM memory cell has a ferroelectric layer.

[0069] Example 5. The memory of example 1, wherein the first number of cache lines are formed as ferroelectric field effect transistors (FeFETs).

[0070] Example 6. The memory of example 1, wherein the stack register is arranged as a plurality of ferroelectric layers separated by an intervening non-ferroelectric layer, the plurality of ferroelectric layers arranged as a stack having an input end and an output end, and wherein a read / write advancement circuit is adapted to advance data bits from the input end to the output end through each of the ferroelectric layers to fill the stack.

[0071] Example 7. The memory of example 1, wherein the processor selects between the first and second sets of cache lines in response to a type of data to be stored to the stack register.

[0072] Example 8. The memory of example 1, wherein the stack register comprises part of a data storage device having a main non-volatile memory (NVM) to store user data from a client device.

[0073] Example 9. The memory of Example 8, wherein the data storage device is a solid state drive (SSD), wherein the NVM is flash memory.

[0074] Example 10. The memory of Example 1, wherein the processor is characterized as a programmable processor that executes program instructions from memory, and at least some of the program instructions are stored in the stack register prior to their execution.

[0075] Example 11. A data storage device comprising: a non-volatile memory (NVM) characterized as a main memory storage for user data that is accessible by an external client device; a controller configured to transfer the user data between the NVM and the external client device in response to commands issued by the external client device; and a local memory configured to be used by the controller to support the transfer of the user data, the local memory characterized as a ferroelectric stack register memory comprising a first arrangement of ferroelectric memory cells (FMEs) having a first configuration, a second arrangement of FMEs having a second, different configuration, and a pointer mechanism configured to provide pointers to cache lines associated with each of the first and second arrangements of FMEs in response to inputs provided by the controller.

[0076] Example 12. The data storage device of Example 11, wherein the NVM comprises at least a selected one of flash memory or a rotatable magnetic recording medium.

[0077] Example 13. The data storage device of Example 11, wherein the controller comprises a programmable processor configured to execute program instructions stored in the stack register.

[0078] Example 14. The data storage device of Example 11, wherein the local memory further comprises read / write circuitry configured to read data from and write data to the stack register, and refresh circuitry configured to selectively refresh data to the stack register after a read operation in response to a mode select input from the controller.

[0079] Example 15. The data storage device of Example 11, wherein each of the first and second configurations is selected from FTJ, FeRAM, or FeFET.

[0080] Example 16. The data storage device of Example 11, wherein the controller stores a selected data set in the first arrangement of FMEs and subsequently transfers the selected data set to the second arrangement of FMEs.

[0081] Example 17. A method comprising: initiating communication between a controller and a ferroelectric stack register memory having a first arrangement of ferroelectric memory cells (FMEs) and a second arrangement of FMEs, the first arrangement of FMEs having a first configuration arranged to provide a first number of cache lines adapted to respectively receive a corresponding first number of data entries from a processor, the second arrangement of FMEs having a second, different configuration arranged to provide a second number of cache lines adapted to respectively receive a corresponding second number of data entries from the processor; using the controller to store a first data set to the first number of cache lines of the first arrangement and to store a second data set to the second number of cache lines of the second arrangement; and utilizing a pointer mechanism to provide a pointer to each of the respective first and second numbers of cache lines based on a time sequence of operation of the controller.

[0082] Example 18. The method of Example 17, further comprising using the controller to migrate the first data set to the second number of cache lines of the second arrangement and updating the pointer mechanism to reflect the migration.

[0083] Example 19. The method of Example 17, wherein each of the first and second configurations is selected from a different one of FTJ, FeRAM, or FeFET.

[0084] Example 20. The method of Example 17, wherein the stack register forms part of a data storage device having a host non-volatile memory (NVM) to store user data from a client device.

Claims

1. A ferroelectric stack register memory, comprising: A first arrangement of ferroelectric memory cells (FMEs) has a first configuration arranged to provide a first number of cache lines, the first number of cache lines being adapted to receive a corresponding first number of data entries from a processor. A second arrangement of the FME, the second arrangement having a different second configuration arranged to provide a second number of cache lines, the second number of cache lines being adapted to receive a corresponding second number of data entries from the processor respectively; as well as A pointer mechanism configured to provide pointers to each of a first and second number of cache lines based on a time sequence of operations of the processor.

2. The memory as claimed in claim 1, characterized in that, The first number of cache lines are composed of ferroelectric tunnel junction (FJT) memory cells.

3. The memory as claimed in claim 1, characterized in that, The first number of cache lines are formed as ferroelectric random access memory (FeRAM) cells, each having at least one transistor and at least one capacitor.

4. The memory as described in claim 3, characterized in that, The at least one capacitor in each FeRAM memory cell has a ferroelectric layer.

5. The memory as claimed in claim 1, characterized in that, The first number of cache lines are formed as ferroelectric field-effect transistors (FeFETs).

6. The memory as claimed in claim 1, characterized in that, The stack register is arranged as a plurality of ferroelectric layers separated by an intermediate non-ferroelectric layer, the plurality of ferroelectric layers being arranged as a stack with inputs and outputs, and wherein a read / write push circuit is adapted to progressively push data bits from the inputs to the outputs to each of the ferroelectric layers to fill the stack.

7. The memory as claimed in claim 1, characterized in that, The processor selects between a first number of cache lines and a second number of cache lines in response to the data type to be stored in the stack register.

8. The memory as claimed in claim 1, characterized in that, The stack registers form part of a data storage device having main non-volatile memory (NVM) for storing user data from client devices.

9. The memory as claimed in claim 8, characterized in that, The data storage device is a solid-state drive (SSD), where NVM is flash memory.

10. The memory as claimed in claim 1, characterized in that, The processor is characterized as a programmable processor that executes program instructions from memory, and at least some of the program instructions are stored in the stack register prior to its execution.

11. A data storage device, comprising: Non-volatile memory (NVM), characterized as main memory storage for user data that can be accessed by external client devices; A controller configured to transmit the user data between the NVM and the external client device in response to a command issued by the external client device; as well as A local memory, configured for use by the controller to support the transfer of the user data, is characterized as a ferroelectric stack register memory, comprising a first arrangement of ferroelectric memory cells (FMEs) having a first configuration, a second arrangement of FMEs having a different second configuration, and a pointer mechanism configured to provide pointers to cache lines associated with each of the first and second arrangements of the FMEs in response to input provided by the controller.

12. The data storage device as described in claim 11, characterized in that, The NVM includes at least one selected from flash memory or rotatable magnetic recording media.

13. The data storage device as described in claim 11, characterized in that, The controller includes a programmable processor configured to execute program instructions stored in the stack register.

14. The data storage device as described in claim 11, characterized in that, The local memory further includes a read / write circuitry and a refresh circuitry, the read / write circuitry being configured to read data from and write data to the stack register, and the refresh circuitry being configured to selectively refresh data to the stack register after a read operation in response to a mode selection input from the controller.

15. The data storage device as described in claim 11, characterized in that, Each of the first and second configurations is selected from FTJ, FeRAM, or FeFET.

16. The data storage device as described in claim 11, characterized in that, The controller stores the selected dataset in the first arrangement of the FME and then transfers the selected dataset to the second arrangement of the FME.

17. A method for managing data, comprising: Communication between the start controller and the ferroelectric stack register memory is initiated. The ferroelectric stack register memory has a first arrangement of ferroelectric memory cells (FMEs) and a second arrangement of FMEs. The first arrangement of FMEs has a first configuration arranged to provide a first number of cache lines, which are adapted to receive a corresponding first number of data entries from the processor. The second arrangement of FMEs has a different second configuration arranged to provide a second number of cache lines, which are adapted to receive a corresponding second number of data entries from the processor. The controller is used to store the first dataset into the first number of cache lines in the first arrangement, and to store the second dataset into the second number of cache lines in the second arrangement. as well as The pointer mechanism provides pointers to each of the corresponding first and second number of cache lines in a time sequence based on the operation of the controller.

18. The method of claim 17, further comprising using the controller to migrate the first dataset to the second number of cache lines in the second arrangement, and updating the pointer mechanism to reflect the migration.

19. The method as described in claim 17, characterized in that, Each of the first and second configurations is selected from a different one of FTJ, FeRAM, or FeFET.

20. The method as described in claim 17, characterized in that, The stack registers form part of a data storage device having main non-volatile memory (NVM) for storing user data from client devices.

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