Hardware devices and methods for memory management based on address monitoring
By monitoring the write address of the memory descriptor and ensuring that the register group is updated after the descriptor has been allocated, the problem of asynchronous descriptor configuration and register writing in the DMA controller is solved, thereby improving system efficiency and bandwidth utilization.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SUZHOU CENTEC COMM CO LTD
- Filing Date
- 2022-07-26
- Publication Date
- 2026-06-30
AI Technical Summary
In the prior art, the DMA controller has no control over the order of descriptor configuration and register write operations, which results in the descriptor being unusable when it is not ready, wasting time and bandwidth.
By monitoring the memory descriptor write addresses via the system bus, the register bank is updated after ensuring that the descriptors have been allocated, triggering the descriptor fetch operation, thus avoiding descriptor configuration and register bank configuration being out of sync.
This improves the efficiency of DMA in retrieving descriptors from registers, makes better use of bus bandwidth, reduces invalid data usage, and enhances the overall system processing capability.
Smart Images
Figure CN115248791B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of memory management technology, and more specifically, to a hardware device and method for memory management based on address monitoring. Background Technology
[0002] With the development of communication and computer technologies, high-speed and real-time data processing has become increasingly important. DMA (Direct Memory Access) technology allows the control of batch data transfers between memory and peripherals to bypass the CPU (Central Processing Unit) and be directly implemented and completed by the DMA controller. The CPU only needs to configure at the beginning of the transfer and read the descriptor for corresponding processing at the end. This greatly reduces the CPU's workload, allowing it to handle other tasks and improving system efficiency. For high-speed devices, this not only reduces CPU utilization but also significantly increases hardware throughput.
[0003] Based on their implementation, DMA controllers can be divided into register-based DMA controllers and descriptor-based DMA controllers. Both require providing some basic information, such as the source address, destination address, and transfer length, to initiate the transfer. In the descriptor-based DMA controller mechanism, existing technologies handle the following... Figure 1 As shown in the diagram, the CPU first needs to configure data in the memory storage space via the system bus. If the DMA controller is receiving data, this step is omitted. Next, the CPU needs to encapsulate the preset memory address for receiving data, or the address where the data is already stored in memory, along with other information (destination address, transfer length, etc.), into a descriptor according to a defined format, and store it in the descriptor storage space in memory via the system bus. After the descriptors are pre-allocated, the CPU writes to the registers in the DMA controller through the configuration bus interface to inform it of the number of allocated descriptors, thereby triggering the DMA controller's data transfer operation. The DMA controller begins to fetch descriptors from memory via the system bus and performs data transfer according to the descriptor's instructions. This can involve transferring data from memory to a peripheral device, or retrieving data from a peripheral device and storing it in memory. After the transfer is complete, the DMA controller needs to write the descriptors back to the descriptor storage space in memory via the system bus and generate an interrupt signal to the General Interrupt Controller (GIC). The CPU learns about the data transfer status through the interrupt and can then perform corresponding processing when it is idle.
[0004] In existing technologies, logically, the CPU first configures the descriptor, then writes to the DMA controller's registers via the I / O interface, triggering the DMA controller to retrieve the descriptor from the memory's descriptor storage space. However, in reality, because the order in which each software operation is completed by the CPU is uncontrollable, writing to memory and writing to registers are different operations, causing the register write to complete before the pre-allocated descriptor. This results in the DMA controller receiving the register write trigger and retrieving the descriptor from memory when the descriptor is not ready, or only partially ready. Consequently, the retrieved descriptor, upon entering the DMA controller, will be found to be unusable, requiring another retrieval from the same address. This wastes time and bandwidth. Summary of the Invention
[0005] The present invention aims to provide, for example, a hardware device and method for memory management based on address monitoring, which can save bus bandwidth and improve system efficiency.
[0006] The embodiments of the present invention can be implemented as follows:
[0007] In a first aspect, the present invention provides a hardware device for memory management based on address monitoring, including a CPU, a DMA controller, a memory, and a system bus. The CPU, the DMA controller, and the memory are all connected to the system bus. The DMA controller includes a register group, a monitoring module, and a processing module.
[0008] The CPU is used to encapsulate the pre-received data into a descriptor by the preset storage address in the data storage space of the memory or the storage address of the already stored data in the data storage space of the memory, and other data information, and to store the descriptor into the descriptor storage space of the memory through the system bus.
[0009] The system bus is used to monitor and record the write address signals of the descriptors in the memory;
[0010] The monitoring module is used to monitor the write address signals of the descriptors recorded on the system bus, determine the number of descriptors based on the monitored write address signals, and update the number of descriptors in the register group.
[0011] The processing module is used to retrieve the corresponding descriptor from the memory based on the number of descriptors updated in the register group, and write data received from the peripheral device into the memory or read data from the memory and send it to the peripheral device based on the retrieved descriptor.
[0012] In an optional implementation, the DMA controller has multiple channels, and the memory is allocated with base addresses corresponding to each channel. The first round of writing of descriptors in the memory starts from each base address, and the start address of the next round of writing is updated according to the end address of each round of storage. The descriptor extraction corresponding to a single data transfer event is performed by one channel of the DMA controller.
[0013] In an optional implementation, the monitoring module is used for:
[0014] The target address information is obtained based on the preset maximum data transfer volume and the write start address corresponding to the channel currently extracting the descriptor in the memory.
[0015] Monitor the write address signals of the descriptors recorded on the system bus and determine whether they match the target address information, and determine the number of descriptors based on the determination result.
[0016] In an optional implementation, the monitoring module is used for:
[0017] If, during the monitoring period, the write address signal of the descriptor recorded on the system bus does not match the target address information, the number of descriptors is determined based on the write start address, write address signal, and size of a single descriptor in the current round.
[0018] If, during the monitoring period, the write address signal of the descriptor recorded on the system bus matches the target address information, then the number of descriptors is determined to be the quotient of the preset maximum data transmission volume and the size of a single descriptor.
[0019] In an optional implementation, the processing module is further configured to, after the data corresponding to the descriptor extracted in the current round has been written or sent, write the extracted descriptor back to the descriptor storage space of the memory via the system bus.
[0020] The register group is also used to clear the number of descriptors updated in the current round to zero.
[0021] In an optional implementation, the other data information includes the destination address and transmission length.
[0022] In an optional implementation, the CPU is further configured to perform data or space processing based on the descriptors written back in the descriptor storage space of the memory after the data corresponding to the descriptor extracted in the current round has been written or sent.
[0023] Secondly, the present invention provides a method for memory management based on address monitoring, applied to the hardware device for memory management based on address monitoring described in any one of the above claims. The hardware device includes a CPU, a DMA controller, a memory, and a system bus. The CPU, DMA controller, and memory are all connected to the system bus. The DMA controller includes a register set, a monitoring module, and a processing module. The method includes:
[0024] The CPU encapsulates the pre-received data into a descriptor at a preset storage address in the data storage space of the memory or at the storage address of the already stored data in the data storage space of the memory, along with other data information, and stores the descriptor into the descriptor storage space of the memory via the system bus.
[0025] The system bus monitors and records the write address signals of the descriptors in the memory;
[0026] The monitoring module monitors the write address signals of the descriptors recorded on the system bus, determines the number of descriptors based on the monitored write address signals, and updates the number of descriptors in the register group.
[0027] The processing module retrieves the corresponding descriptor from the memory based on the number of descriptors updated in the register group, and writes data received from the peripheral device into the memory or reads data from the memory and sends it to the peripheral device based on the retrieved descriptor.
[0028] In an optional implementation, the step of the monitoring module monitoring the write address signals of descriptors recorded on the system bus and determining the number of descriptors based on the monitored write address signals includes:
[0029] The target address information is obtained based on the preset maximum data transfer volume and the write start address corresponding to the channel currently extracting the descriptor in the memory.
[0030] Monitor the write address signals of the descriptors recorded on the system bus and determine whether they match the target address information, and determine the number of descriptors based on the determination result.
[0031] In an optional implementation, the step of monitoring the write address signals of descriptors recorded on the system bus and determining whether they match the target address information, and determining the number of descriptors based on the determination result, includes:
[0032] If, during the monitoring period, the write address signal of the descriptor recorded on the system bus does not match the target address information, the number of descriptors is determined based on the write start address, write address signal, and size of a single descriptor in the current round.
[0033] If, during the monitoring period, the write address signal of the descriptor recorded on the system bus matches the target address information, then the number of descriptors is determined to be the quotient of the preset maximum data transmission volume and the size of a single descriptor.
[0034] The beneficial effects of the embodiments of the present invention include, for example:
[0035] This application provides a hardware device and method for memory management based on address monitoring. The CPU encapsulates the preset storage address of pre-received data or the storage address of already stored data in memory, along with other data information, into a descriptor, and stores the descriptor in memory via the system bus. The system bus monitors and records the write address signals of the descriptors in memory. The monitoring module of the DMA controller monitors the write address signals of the descriptors recorded on the system bus, determines the number of descriptors based on the monitored write address signals, and updates the descriptor count in the register set. The processing module retrieves the corresponding descriptor from memory based on the updated descriptor count and performs data writing or reading based on the descriptor.
[0036] This DMA controller can monitor memory descriptor write addresses via the system bus to determine the accurate descriptor allocation. It ensures that descriptors are correctly allocated before updating the register set and triggering a descriptor fetch. This avoids potential errors caused by asynchronous descriptor and register set configuration during CPU configuration, saves bus bandwidth, and improves system efficiency. Attached Figure Description
[0037] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0038] Figure 1 This is a schematic diagram of the structure of a hardware device in the prior art;
[0039] Figure 2 A schematic diagram of the structure of a hardware device for memory management based on address monitoring, provided in an embodiment of this application;
[0040] Figure 3 A flowchart illustrating a method for memory management based on address monitoring provided in this application embodiment;
[0041] Figure 4 for Figure 3 A flowchart of the sub-steps included in step S103. Detailed Implementation
[0042] As mentioned above, in the prior art, the order in which the CPU completes the configuration descriptor and write register operations is uncontrollable. This can lead to the write register being completed before the pre-allocated descriptor. Consequently, when the DMA controller receives the write register trigger, the descriptor may become unavailable after being retrieved from memory, requiring it to retrieve the descriptor from the same address again, thus wasting time and bandwidth.
[0043] To address the aforementioned problems, several solutions have been proposed in existing technologies. For example, one solution involves triggering a DMA (Distributed Memory Access) system to fetch descriptors from DDR for register writes. Upon receiving the descriptors, the DMA performs a validity check. For instance, if a burst transfer fetches n descriptors, and the i-th descriptor (i∈[1,n]) is invalid, then the burst transfer is valid up to the (i-1)-th descriptor, but invalid up to the nth descriptor. Once the last descriptor of the burst transfer is received, the DMA knows the number of valid descriptors in that burst. The DMA then fetches descriptors again, but the starting address is offset from the previous address by the space occupied by the valid descriptors in the current burst. This process continues until all pre-allocated descriptors are retrieved and are ultimately usable.
[0044] The advantage of this approach is that it can eventually retrieve a usable pre-allocated descriptor. However, its disadvantages are also obvious: it requires multiple retrievals, and a new retrieval request is not allowed before the last descriptor in a burst transfer has been retrieved. If no invalid descriptor is retrieved, this mechanism will significantly reduce the efficiency of descriptor retrieval because it cannot issue another retrieval request before all the data from the previous retrieval request has been returned, ultimately affecting DMA performance.
[0045] Alternatively, a second solution involves writing a value to the register, triggering DMA to fetch descriptors from DDR. Descriptor fetch requests can continue until the DMA receives the last descriptor. The starting address of the second fetch request is offset from the space occupied by the data requested in the first request, and the same applies to the third and fourth requests. The maximum number of requests that can be issued while some requests are incomplete depends on the system bus settings and is not specifically limited. If the first invalid descriptor appears, it's necessary to check how many requests are still incomplete. All descriptors from this invalid descriptor to the remaining incomplete requests are considered invalid. Descriptor fetch requests can still be issued at this point, but the starting address must be offset from the space occupied by the valid descriptors in the current burst transfer.
[0046] The advantage of this approach is that it can retrieve pre-allocated valid descriptors, and if an invalid descriptor is not found, a new fetch request can be initiated without waiting for the data from the previous fetch request, thus ensuring efficiency. However, the disadvantage is that if an invalid descriptor is found, all subsequent fetch requests are considered invalid, resulting in still relatively low efficiency.
[0047] Therefore, existing solutions all have many drawbacks. They all rely on recording the address of the first invalid descriptor after it has already occurred, and then restarting descriptor retrieval from that address in subsequent operations to ensure that a valid descriptor is eventually retrieved from each address. However, this comes at the cost of efficiency, with a portion of the bus bandwidth being occupied by invalid data, and it does not address the root cause of the problem of retrieving invalid descriptors.
[0048] Based on this, this application provides a memory management scheme based on address monitoring. The DMA controller can monitor the write addresses of memory descriptors through the system bus to obtain accurate descriptor allocation. It ensures that the descriptor has been allocated correctly before updating the register set and triggering the descriptor fetch operation. This avoids the possibility of errors caused by asynchronous descriptor configuration and data configuration during CPU configuration, saves bus bandwidth, and improves system efficiency.
[0049] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.
[0050] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.
[0051] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.
[0052] It should be noted that, where there is no conflict, the features in the embodiments of the present invention can be combined with each other.
[0053] Please see Figure 2This refers to the hardware device for memory management based on address monitoring provided in the embodiments of this application. This hardware device can be a computer device, a system chip, or other similar device.
[0054] The hardware includes a CPU, a DMA controller, memory, and a system bus. The CPU, DMA controller, and memory are all connected to the system bus. The DMA controller includes a register set, a monitoring module, and a processing module. The memory contains data storage space and descriptor storage space. The data storage space stores the actual data, while the descriptor storage space stores data descriptors, such as the data length and write address.
[0055] In this embodiment, the CPU encapsulates the preset storage address of the pre-received data in the data storage space of the memory or the storage address of the already stored data in the data storage space of the memory, and other data information into a descriptor, and stores the descriptor into the descriptor storage space of the memory through the system bus.
[0056] For example, when receiving data, the CPU can determine the preset storage address of the data to be received based on information such as the data length and the address information that can be written to in the current memory storage space. After determining the preset storage address, the CPU can encapsulate the preset storage address and other data information, such as the destination address and transmission length, into a descriptor according to a set format, and store the descriptor of the data to be received into the descriptor storage space of the memory via the system bus.
[0057] Furthermore, if data transmission is required, the CPU first configures and stores the data in the memory's data storage space via the system bus. The CPU can encapsulate the storage address of the data already stored in memory and other data information, such as the destination address and transmission length, into a descriptor according to a set format, and then store the stored data, i.e., the descriptor of the data to be sent, into the memory's descriptor storage space via the system bus.
[0058] During the process of the CPU writing descriptors to memory via the system bus, the system bus can monitor and record the write address signal of the descriptor in memory. The write address signal of the descriptor can indicate whether the location of the descriptor in the register has been successfully written.
[0059] The monitoring module in the DMA controller can monitor the write address signals of descriptors recorded on the system bus and determine the number of descriptors based on the monitored write address signals. For example, given the descriptor size, starting write address, and write address signals, the number of descriptors currently explicitly written to memory can be determined. The monitoring module can update the determined number of descriptors in the DMA register set to trigger a descriptor fetch operation.
[0060] The processing module in the DMA controller can be used to retrieve the corresponding descriptor from memory based on the number of descriptors updated in the register set, and write data received from the peripheral device into memory or read data from memory and send it to the peripheral device based on the retrieved descriptor.
[0061] At this point, the number of descriptors updated in the register set is the number of descriptors that have been successfully written to the registers, i.e., the number of valid descriptors.
[0062] When receiving data, the received data can be written into the memory from the peripheral device according to the valid descriptor associated with the pre-received data.
[0063] When sending data, the data to be sent can be read from the memory and sent to the peripheral device based on the valid descriptors associated with the data already stored in the memory.
[0064] In this embodiment, the number of descriptors updated in the DMA register set is obtained by monitoring the write address signals of descriptors stored in the registers by the CPU via the system bus. Based on these write address signals, it can be determined whether the location of the descriptor in the register has been successfully written. Through this hardware-active update method, when the register set is updated, it can be ensured that the value at the address corresponding to the descriptor in the register has been updated. The DMA then retrieves the descriptor from the register, and the retrieved descriptor is valid and usable. This method improves the efficiency of descriptor prefetching and makes efficient use of the bus bandwidth.
[0065] This solution effectively resolves the issue of unusable descriptors retrieved due to asynchrony between the CPU configuration register and the configuration descriptor. It reduces bandwidth consumption by invalid data, allowing more limited bandwidth to be used for transmitting other valid data in the system, thus improving overall system processing capabilities. It accurately identifies the CPU's descriptor allocation process, ensuring that descriptors are valid before being read, thereby improving the efficiency of DMA descriptor retrieval from registers.
[0066] In this embodiment, the DMA controller has multiple channels, and the memory is allocated with base addresses corresponding to each channel. The base address mentioned here is the base address for writing descriptors.
[0067] The first round of writing to descriptors in memory begins with storage from each base address, and the start address of the next round of writing is updated based on the end address of each round of storage. Descriptor retrieval for a single data transfer event is performed by a channel of the DMA controller.
[0068] In other words, among the multiple channels of the DMA controller, each channel processes the descriptor fetching sequentially. However, the fetching of the descriptor corresponding to a single data transfer event is performed by only a single channel.
[0069] In this embodiment, a preset maximum data transfer amount can be set according to the required frequency of updating the register group. This preset maximum data transfer amount refers to the maximum length of the descriptor in a single burst transfer. Monitoring the descriptor write address signal in the register and updating the register group based on this preset maximum data transfer amount can be achieved in the following way.
[0070] The monitoring module is used to obtain the target address information based on the preset maximum data transmission volume and the corresponding write start address in the register of the channel currently extracting the descriptor. It monitors the write address signals of the descriptors recorded on the system bus and determines whether they match the target address information. Based on the determination result, it determines the number of descriptors.
[0071] In this embodiment, the target address information can be obtained based on a preset maximum data transfer volume and a write start address. For example, if the write start address for the current round is the base address `baseDescAddr`, and the preset maximum data transfer volume is `burstSize` bytes, then the target address is `baseDescAddr + burstSize`.
[0072] Furthermore, if the write start address of the current round is not the base address, the target address needs to be obtained by adding the preset maximum data transfer amount to the write start address of the current round.
[0073] The monitoring module can determine whether the amount of data written to the descriptor in the memory has reached the preset maximum amount of data to be transferred by monitoring whether the write address signal of the descriptor recorded on the system bus matches the target address information.
[0074] Specifically, in this embodiment, the monitoring module can determine the number of descriptors based on the write start address, write address signal, and size of a single descriptor in the current round if the write address signal of the descriptor recorded on the system bus does not match the target address information during the monitoring period.
[0075] In this scenario, where no write address signal matching the target address information is detected within the monitoring cycle, a timeout logic will terminate this round of monitoring. If this round of monitoring terminates due to a timeout, the number of valid descriptors written to memory will be less than the number of descriptors corresponding to the preset maximum data transfer volume.
[0076] Specifically, the number of valid descriptors in memory can be obtained by subtracting the write start address from the currently monitored write address signal and dividing by the size of a single descriptor. This number is then updated in the register set. This allows the DMA to retrieve the corresponding number of valid descriptors from memory based on the specified number.
[0077] In another possible scenario, the monitoring module can be used to determine the number of descriptors as the quotient of the preset maximum data transfer amount and the size of a single descriptor if the write address signal of the descriptor recorded on the system bus matches the target address information during the monitoring period.
[0078] In this scenario, the DMA continuously monitors the write address signal of the descriptor on the system bus. If the write address signal does not match the target address information and the monitoring cycle has not ended, it continues monitoring and continuously counts the number of newly allocated descriptors in this round. If a write address signal matches the target address information, the DMA will actively update the register set. In the case of an address match and register set update, the number of descriptors updated in the register set is consistent with the number corresponding to the preset maximum data transfer volume.
[0079] Specifically, if the preset maximum data transmission volume is burstSize Byte and the size of a single descriptor is descSize Byte, then the number of descriptors updated in the current round is burstSize / descSize.
[0080] In this embodiment, the monitoring of descriptors in the memory is performed by setting a monitoring period as described above. Furthermore, by matching the write address signal of the descriptor with the target address information, the number of valid descriptors written can be accurately determined directly from the address information, thereby updating the register set. The DMA processing module can then retrieve the corresponding descriptors from the registers based on the updated number of descriptors.
[0081] Based on the above, in this embodiment, the processing module in the DMA controller is further configured to write back the extracted descriptor to the descriptor storage space of the memory via the system bus after the data corresponding to the descriptor extracted in the current round has been written or sent.
[0082] The register set is also used to clear the number of descriptors updated in the current round. After clearing the number of descriptors in the current round, the process returns to the step of monitoring the write address signals of descriptors in memory, and calculates the target address signal for the new round based on the previous round. Then, based on the write address signals of descriptors monitored by the system bus, the descriptors allocated in the new round are counted to prepare for the next register set update.
[0083] Specifically, in this embodiment, when the processing module reads data from or writes data to memory based on the number of descriptors updated in the register group, after a descriptor's data is successfully read or written, the descriptor corresponding to the updated data can be written back to the descriptor storage space in memory. Simultaneously, the register group is updated to subtract the number of descriptors written back in this instance. Once all data corresponding to the number of descriptors updated in the current round has been successfully read or written, the number of descriptors updated in the current round in the register group is cleared to zero.
[0084] Based on the above, the CPU is also used to perform data or space processing according to the descriptor written back in the memory descriptor storage space after the data corresponding to the descriptor extracted in the current round has been written or sent.
[0085] For example, after all the data corresponding to the descriptor has been written, the CPU can read the written data and perform data re-editing or other processing. After all the data corresponding to the descriptor has been sent, the CPU can release the memory units originally occupied by the data.
[0086] The address monitoring-based memory management scheme provided in this embodiment allows the CPU to encapsulate the preset storage address of pre-received data or the storage address of already stored data in memory, along with other data information, into a descriptor, and then store the descriptor in memory via the system bus. The system bus can monitor and record the write address signals of the descriptors in memory. The monitoring module of the DMA controller can monitor the write address signals of the descriptors recorded on the system bus, determine the number of descriptors based on the monitored write address signals, and update the number of descriptors in the register set. The processing module can retrieve the corresponding descriptors from memory based on the updated number of descriptors and perform data writing or data reading based on the descriptors.
[0087] This DMA controller can monitor the write addresses of memory descriptors via the system bus to determine the accurate descriptor allocation. It ensures that the descriptor is correctly allocated before updating the register set and triggering the descriptor removal operation. This avoids potential errors caused by asynchronous descriptor and data configuration during CPU configuration, saves bus bandwidth, and improves system efficiency.
[0088] Please see Figure 3 This application provides a method for memory management based on address monitoring, applicable to any of the hardware devices described above. The method includes the following steps:
[0089] S101, the CPU encapsulates the pre-received data into a descriptor by the preset storage address in the data storage space of the memory or the storage address of the already stored data in the data storage space of the memory, and other data information, and stores the descriptor into the descriptor storage space of the memory through the system bus.
[0090] S102, the system bus monitors and records the write address signals of the descriptors in the memory.
[0091] S103, the monitoring module monitors the write address signals of the descriptors recorded on the system bus, determines the number of descriptors based on the monitored write address signals, and updates the number of descriptors in the register group.
[0092] S104, the processing module retrieves the corresponding descriptor from the memory based on the number of descriptors updated in the register group, and writes the data received from the peripheral device into the memory or reads the data from the memory and sends it to the peripheral device based on the retrieved descriptor.
[0093] The address monitoring-based memory management method provided in this embodiment monitors the descriptor write addresses in the registers via the system bus. This allows the DMA controller to accurately obtain the descriptor allocation status. Only after ensuring that the descriptors have been properly allocated is the register set updated, and a descriptor fetch operation triggered. This avoids potential errors caused by asynchronous descriptor and register set configurations during CPU configuration, saves bus bandwidth, and improves system efficiency.
[0094] Specifically, the relevant details of the method provided in this embodiment can be found in the relevant descriptions of the above embodiments, and will not be repeated here.
[0095] In one possible implementation of the above, please refer to Figure 4 The step S103 above, in which the monitoring module monitors the write address signals of the descriptors recorded on the system bus and determines the number of descriptors based on the monitored write address signals, can be implemented in the following way:
[0096] S1031, the target address information is obtained in the memory according to the preset maximum amount of data to be transmitted and the write start address corresponding to the channel of the current descriptor extraction.
[0097] S1032, monitor the write address signal of the descriptor recorded on the system bus and determine whether it matches the target address information, and determine the number of descriptors based on the determination result.
[0098] In one possible implementation of the above, the step of determining the number of descriptors based on the judgment result can be implemented in the following way:
[0099] If, during the monitoring period, the write address signal of the descriptor recorded on the system bus does not match the target address information, the number of descriptors is determined based on the write start address, write address signal, and size of a single descriptor in the current round.
[0100] If, during the monitoring period, the write address signal of the descriptor recorded on the system bus matches the target address information, then the number of descriptors is determined to be the quotient of the preset maximum data transmission volume and the size of a single descriptor.
[0101] In summary, the hardware device and method for memory management based on address monitoring provided in this application embodiment include a CPU that encapsulates the preset storage address of pre-received data or the storage address of already stored data in memory, along with other data information, into a descriptor, and stores the descriptor in memory via the system bus. The system bus can monitor and record the write address signals of the descriptors in memory. The monitoring module of the DMA controller can monitor the write address signals of the descriptors recorded on the system bus, determine the number of descriptors based on the monitored write address signals, and update the number of descriptors in the register set. The processing module can retrieve the corresponding descriptor from memory based on the updated number of descriptors and perform data writing or data reading based on the descriptor.
[0102] This DMA controller can monitor memory descriptor write addresses via the system bus to determine the accurate descriptor allocation. It ensures that descriptors are correctly allocated before updating the register set and triggering a descriptor fetch. This avoids potential errors caused by asynchronous descriptor and register set configuration during CPU configuration, saves bus bandwidth, and improves system efficiency.
[0103] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.
Claims
1. A hardware device for memory management based on address monitoring, characterized in that, It includes a CPU, a DMA controller, a memory, and a system bus. The CPU, DMA controller, and memory are all connected to the system bus. The DMA controller includes a register set, a monitoring module, and a processing module. The CPU is used to encapsulate the pre-received data into a descriptor by the preset storage address in the data storage space of the memory or the storage address of the already stored data in the data storage space of the memory, and other data information, and to store the descriptor into the descriptor storage space of the memory through the system bus. The system bus is used to monitor and record the write address signals of the descriptors in the memory; The monitoring module is used to monitor the write address signals of the descriptors recorded on the system bus, determine the number of descriptors based on the monitored write address signals, and update the number of descriptors in the register group. The processing module is used to retrieve the corresponding descriptor from the memory based on the number of descriptors updated in the register group, and write data received from the peripheral device into the memory or read data from the memory and send it to the peripheral device based on the retrieved descriptor. The DMA controller has multiple channels, and the monitoring module is used to: obtain target address information in the memory according to the preset maximum data transfer volume and the write start address corresponding to the channel currently extracting the descriptor; Monitor the write address signals of the descriptors recorded on the system bus and determine whether they match the target address information, and determine the number of descriptors based on the determination result.
2. The hardware device for memory management based on address monitoring according to claim 1, characterized in that, The memory is allocated base addresses corresponding to each channel. The first round of writing of descriptors in the memory starts from each base address, and the start address of the next round of writing is updated according to the end address of each round of storage. The descriptor retrieval corresponding to a single data transfer event is performed by one channel of the DMA controller.
3. The hardware device for memory management based on address monitoring according to claim 2, characterized in that, The monitoring module is used for: If, during the monitoring period, the write address signal of the descriptor recorded on the system bus does not match the target address information, the number of descriptors is determined based on the write start address, write address signal, and size of a single descriptor in the current round. If, during the monitoring period, the write address signal of the descriptor recorded on the system bus matches the target address information, then the number of descriptors is determined to be the quotient of the preset maximum data transmission volume and the size of a single descriptor.
4. The hardware device for memory management based on address monitoring according to claim 1, characterized in that, The processing module is also used to write back the extracted descriptor to the descriptor storage space of the memory via the system bus after the data corresponding to the descriptor extracted in the current round has been written or sent. The register group is also used to clear the number of descriptors updated in the current round to zero.
5. The hardware device for memory management based on address monitoring according to claim 1, characterized in that, The other data information includes the destination address and transmission length.
6. The hardware device for memory management based on address monitoring according to claim 1, characterized in that, The CPU is also used to perform data or space processing based on the descriptors written back in the descriptor storage space of the memory after the data corresponding to the descriptor extracted in the current round has been written or sent.
7. A method for memory management based on address monitoring, characterized in that, The hardware device for memory management based on address monitoring as described in any one of claims 1-6, the hardware device comprising a CPU, a DMA controller, a memory, and a system bus, wherein the CPU, DMA controller, and memory are all connected to the system bus, and the DMA controller comprises a register set, a monitoring module, and a processing module, the method comprising: The CPU encapsulates the pre-received data into a descriptor at a preset storage address in the data storage space of the memory or at the storage address of the already stored data in the data storage space of the memory, along with other data information, and stores the descriptor into the descriptor storage space of the memory via the system bus. The system bus monitors and records the write address signals of the descriptors in the memory; The monitoring module monitors the write address signals of the descriptors recorded on the system bus, determines the number of descriptors based on the monitored write address signals, and updates the number of descriptors in the register group. The processing module retrieves the corresponding descriptor from the memory based on the updated number of descriptors in the register group, and writes data received from the peripheral device into the memory or reads data from the memory and sends it to the peripheral device based on the retrieved descriptor; the monitoring module monitors the write address signals of the descriptors recorded on the system bus, and determines the number of descriptors based on the monitored write address signals, including: The target address information is obtained in the memory based on the preset maximum data transfer volume and the write start address corresponding to the channel currently extracting the descriptor. Monitor the write address signals of the descriptors recorded on the system bus and determine whether they match the target address information, and determine the number of descriptors based on the determination result.
8. The method for memory management based on address monitoring according to claim 7, characterized in that, The step of monitoring the write address signals of descriptors recorded on the system bus and determining whether they match the target address information, and determining the number of descriptors based on the determination result, includes: If, during the monitoring period, the write address signal of the descriptor recorded on the system bus does not match the target address information, the number of descriptors is determined based on the write start address, write address signal, and size of a single descriptor in the current round. If, during the monitoring period, the write address signal of the descriptor recorded on the system bus matches the target address information, then the number of descriptors is determined to be the quotient of the preset maximum data transmission volume and the size of a single descriptor.