Method for forming semiconductor structure

Abstract

A method for forming a semiconductor structure includes: providing a substrate; forming a dielectric layer on the substrate; forming a patterned first mask layer on the dielectric layer; forming an initial second mask layer on the first mask layer, wherein the material of the initial second mask layer is different from the material of the first mask layer; etching the dielectric layer using the initial second mask layer and the first mask layer as masks to form an opening in the dielectric layer, and forming a second mask layer on the first mask layer, wherein the top corner of the second mask layer is rounded; and forming a conductive structure in the opening. The semiconductor structure formed by the method has improved performance.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art

[0002] At present, in the back end of line (BEOL) process of semiconductor devices, when manufacturing semiconductor integrated circuits, after the semiconductor device layer is formed, it is necessary to form a metal interconnection layer on the semiconductor device layer. Each metal interconnection layer includes metal interconnection lines and interlayer dielectric layers (ILD). This requires manufacturing trenches and connection holes (Via) in the interlayer dielectric layer, and then depositing metal in the trenches and connection holes. The deposited metal is the metal interconnection line.

[0003] However, the existing back-end process still needs to be improved. Summary of the invention

[0004] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure to improve the performance of the semiconductor structure.

[0005] In order to solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, including: providing a substrate; forming a dielectric layer on the substrate; forming a patterned first mask layer on the dielectric layer; forming an initial second mask layer on the first mask layer, the material of the initial second mask layer is different from the material of the first mask layer; etching the dielectric layer with the initial second mask layer and the first mask layer as masks to form an opening in the dielectric layer, and forming a second mask layer on the first mask layer, the top corners of the second mask layer are rounded; forming a conductive structure in the opening.

[0006] Optionally, when the dielectric layer is etched using the initial second mask layer and the first mask layer as masks, an etching rate of the initial second mask layer is greater than an etching rate of the first mask layer.

[0007] Optionally, the material of the initial second mask layer is the same as that of the dielectric layer.

[0008] Optionally, the material of the initial second mask layer is different from the material of the dielectric layer.

[0009] Optionally, when the dielectric layer is etched using the initial second mask layer and the first mask layer as masks, a difference between an etching rate of the initial second mask layer material and an etching rate of the dielectric layer material is within a preset range.

[0010] Optionally, before etching the dielectric layer using the initial second mask layer and the first mask layer as masks, the method further includes: forming a third mask layer on the initial second mask layer, wherein the material of the third mask layer is different from that of the initial second mask layer.

[0011] Optionally, the method for forming the first mask layer, the initial second mask layer and the third mask layer includes: forming a first mask material layer on a dielectric layer; forming a second mask material layer on the first mask material layer; forming a third mask material layer on the second mask material layer; forming a patterned photoresist layer on the third mask material layer; etching the third mask material layer, the second mask material layer and the first mask material layer using the patterned photoresist layer as a mask until the surface of the dielectric layer is exposed to form the first mask layer, the initial second mask layer and the third mask layer.

[0012] Optionally, the material of the third mask layer includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, titanium nitride, titanium oxide, aluminum nitride, silicon carbide nitride and silicon carbon nitride oxynitride.

[0013] Optionally, the thickness of the initial second mask layer is smaller than the thickness of the third mask layer.

[0014] Optionally, the process of etching the dielectric layer using the initial second mask layer and the first mask layer as masks includes a dry etching process; the etching gas of the dry etching process includes a fluorine-containing gas, and the fluorine-containing gas includes fluorine tetrachloride.

[0015] Optionally, the material of the initial second mask layer includes a dielectric material, and the dielectric material includes a combination of one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride and silicon carbon nitride oxynitride.

[0016] Optionally, the conductive structure includes: a barrier layer located on the surface of the opening and a conductive layer located on the surface of the barrier layer.

[0017] Optionally, the method for forming the conductive structure includes: forming a blocking material layer on the bottom surface and side wall surface of the opening, the side wall surface of the first mask layer, and the top surface and side wall surface of the second mask layer; forming a conductive material layer on the blocking material layer; and flattening the conductive material layer and the blocking material layer until the surface of the dielectric layer is exposed to form the conductive structure.

[0018] Optionally, the process of forming the barrier material layer includes a physical vapor deposition process or an atomic layer deposition process.

[0019] Optionally, the process of forming the conductive material layer includes an electroplating process or a physical vapor deposition process.

[0020] Optionally, the barrier layer is made of metal nitride, and the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.

[0021] Optionally, the material of the conductive layer is metal or metal nitride; the metal includes: a combination of one or more of copper, aluminum, tungsten, cobalt, nickel and tantalum; the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.

[0022] Optionally, the thickness of the first mask layer ranges from 120 angstroms to 300 angstroms.

[0023] Optionally, the material of the first mask layer is a combination of one or more of titanium nitride, titanium oxide and silicon nitride.

[0024] Optionally, the material of the dielectric layer includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride and silicon carbon nitride oxynitride.

[0025] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0026] The formation method of the technical solution of the present invention forms a patterned first mask layer on a dielectric layer, and then forms an initial second mask layer on the first mask layer, wherein the material of the initial second mask layer is different from the material of the first mask layer, and then etches the dielectric layer using the initial second mask layer and the first mask layer as masks to form an opening in the dielectric layer, and forms a second mask layer on the first mask layer, wherein the top corner of the second mask layer is rounded. The top corner of the second mask layer is rounded, so that when a conductive structure is subsequently formed in the opening, the material forming the conductive structure is not easy to accumulate at the top of the opening, so that the material forming the conductive structure is easy to enter the bottom of the opening, so that the formed conductive structure is denser and has better quality, thereby improving the conductive performance of the conductive structure.

[0027] Furthermore, when the material of the initial second mask layer is the same as the material of the dielectric layer, or when the material of the initial second mask layer is different from the material of the dielectric layer, the difference between the etching rate of the initial second mask layer material and the etching rate of the dielectric layer material is within a preset range, so that during the process of etching the dielectric layer, the initial second mask layer can be etched at the same time, so that the top corner of the second mask layer formed during the process of etching the dielectric layer is rounded.

[0028] Furthermore, a third mask layer is formed on the initial second mask layer, and the material of the third mask layer is different from that of the initial second mask layer. Thus, during the process of etching the dielectric layer, the third mask layer can protect the initial second mask layer, and avoid the situation where the initial second mask layer is completely consumed during the process of etching the dielectric layer, and the second mask layer with rounded top corners cannot be formed. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figures 1 to 3 is a schematic cross-sectional structural diagram of a semiconductor structure forming process in one embodiment;

[0030] Figures 4 to 9 It is a schematic cross-sectional structure diagram of the semiconductor structure forming process in an embodiment of the present invention. DETAILED DESCRIPTION

[0031] As described in the background art, the existing back-end process needs to be improved. Now, it is analyzed and explained in conjunction with specific embodiments.

[0032] Figures 1 to 3 It is a schematic cross-sectional structure diagram of a semiconductor structure forming process in one embodiment.

[0033] Please refer to Figure 1 , including: providing a substrate 100; forming a dielectric layer 101 on the substrate 100; and forming a patterned mask layer 102 on the dielectric layer 101.

[0034] Please refer to Figure 2 , the dielectric layer 101 is etched using the mask layer 102 as a mask until the surface of the substrate 100 is exposed, and an opening 103 is formed in the dielectric layer 101 .

[0035] Please refer to Figure 3 , a barrier material layer 104 is formed on the sidewall surface and the bottom surface of the opening 103 , and on the dielectric layer 101 .

[0036] After forming the barrier material layer 104 , the process further includes: forming a conductive layer (not shown) in the opening 103 .

[0037] During the formation of the semiconductor structure, when the barrier material layer 104 is formed on the sidewall surface and the bottom surface of the opening 103 and the dielectric layer 101, the material of the barrier material layer 104 includes titanium nitride or tantalum nitride, and the process of forming the barrier material layer 104 includes a physical vapor deposition process. The material of the conductive layer includes copper or tungsten, and the process of forming the conductive layer includes an electroplating process.

[0038] Since the top surface of the mask layer 102 is a flat surface, when depositing to form the blocking material layer 104, it is easy to preferentially deposit more materials of the blocking material layer 104 on the mask layer 102. After depositing more materials of the blocking material layer 104 on the mask layer 102, the materials of the blocking material layer 104 on the mask layer 102 will be sputtered and deposited on each other, so that the materials of the blocking material layer 104 are deposited in large quantities on the top of the opening 103, so that the size of the top of the opening 103 becomes smaller. When a conductive layer is subsequently formed on the blocking material layer 104 using an electroplating process, the amount of plating solution of the electroplating process that enters the bottom of the opening 103 is small, so that the formed conductive layer structure is loose and has holes, so that the conductive performance of the conductive layer is affected.

[0039] In order to solve the above problems, the technical solution of the present invention provides a method for forming a semiconductor structure, by first forming a patterned first mask layer on a dielectric layer, and then forming an initial second mask layer on the first mask layer, the material of the initial second mask layer is different from the material of the first mask layer, and then etching the dielectric layer with the initial second mask layer and the first mask layer as masks to form an opening in the dielectric layer, and forming a second mask layer on the first mask layer, the top corner of the second mask layer is rounded. The top corner of the second mask layer is rounded, so that when a conductive structure is subsequently formed in the opening, the material forming the conductive structure is not easy to accumulate at the top of the opening, so that the material forming the conductive structure is easy to enter the bottom of the opening, so that the formed conductive structure is more dense and of better quality, thereby improving the conductive performance of the conductive structure.

[0040] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0041] Figures 4 to 9 It is a schematic cross-sectional structure diagram of the semiconductor structure forming process in an embodiment of the present invention.

[0042] Please refer to Figure 4 , providing a substrate 200.

[0043] In this embodiment, the substrate 200 includes: a base (not shown); a device layer (not shown) located on the base, the device layer includes an isolation structure (not shown) and a device structure (not shown) located within the isolation structure, and the device structure includes a transistor, a diode, a triode, a capacitor, an inductor or a conductive structure, etc.

[0044] The material of the substrate is silicon.

[0045] In this embodiment, in other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multinary semiconductor material composed of group III-V elements, silicon on insulator (SOI) or germanium on insulator (GOI). Among them, the multinary semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

[0046] Please continue to refer to Figure 4 , a dielectric layer 201 is formed on the substrate 200.

[0047] The material of the dielectric layer 201 includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon oxycarbide nitride.

[0048] In this embodiment, the material of the dielectric layer 201 includes silicon oxide.

[0049] Next, a patterned first mask layer is formed on the dielectric layer 201 ; and an initial second mask layer is formed on the first mask layer, wherein the material of the initial second mask layer is different from that of the first mask layer.

[0050] In this embodiment, the method further includes: forming a third mask layer on the initial second mask layer, wherein a material of the third mask layer is different from a material of the initial second mask layer.

[0051] The formation process of the first mask layer, the initial second mask layer and the third mask layer can be found in Figure 5 and Figure 6 .

[0052] Please refer to Figure 5 , a first mask material layer 202 is formed on the dielectric layer 201 ; a second mask material layer 203 is formed on the first mask material layer 202 ; a third mask material layer 204 is formed on the second mask material layer 203 ; and a patterned photoresist layer 205 is formed on the third mask material layer 204 .

[0053] The first mask material layer 202 is used to subsequently form a first mask layer; the second mask material layer 203 is used to subsequently form a second mask layer; and the third mask material layer 204 is used to subsequently form a third mask layer.

[0054] The material of the first mask material layer 202 includes a combination of one or more of titanium nitride, titanium oxide and silicon nitride. The process of forming the first mask material layer 202 includes a chemical vapor deposition process or an atomic layer deposition process.

[0055] In this embodiment, the thickness of the first mask material layer 202 is in the range of 120 angstroms to 300 angstroms. The first mask material layer 202 in the above thickness range enables the first mask layer with good sidewall morphology and good dimensional accuracy to be accurately controlled when the first mask material layer 202 is subsequently etched to form the first mask layer, so that when the dielectric layer 201 is subsequently etched using the first mask layer and the initial second mask layer as masks, the size of the opening can be accurately controlled by the first mask layer.

[0056] The material of the second mask material layer 203 includes a dielectric material, and the dielectric material includes a combination of one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, and silicon carbonitride. The process of forming the second mask material layer 203 includes a chemical vapor deposition process or an atomic layer deposition process.

[0057] In this embodiment, the material of the second mask material layer 203 is the same as that of the dielectric layer 201. That is, the material of the second mask material layer 203 includes silicon oxide.

[0058] In other embodiments, the material of the second mask material layer is different from the material of the dielectric layer.

[0059] Therefore, when the dielectric layer is subsequently etched using the initial second mask layer and the first mask layer as masks, the difference between the etching rate of the initial second mask layer material and the etching rate of the dielectric layer material needs to be within a preset range to ensure that the initial second mask layer is consumed to a certain extent during the etching process of the dielectric layer, so that the top corners of the formed second mask layer are rounded.

[0060] The material of the third mask material layer 204 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, titanium nitride, titanium oxide, aluminum nitride, silicon carbonitride, and silicon carbonitride. The process of forming the third mask material layer 204 includes a chemical vapor deposition process or an atomic layer deposition process.

[0061] In this embodiment, the material of the third mask material layer 204 is different from the material of the second mask material layer 203, and the thickness of the third mask material layer 204 is less than the thickness of the second mask material layer 203. This ensures that after the first mask layer, the initial second mask layer and the third mask layer are subsequently formed, when the dielectric layer 201 is etched with the first mask layer, the initial second mask layer and the third mask layer, the third mask layer has sufficient thickness to protect the initial second mask layer from being completely consumed, so that the top corners of the formed second mask layer are rounded.

[0062] In other embodiments, the third mask material layer may not be formed. In this case, the second mask material layer is thicker to ensure that the initial second mask layer is not completely consumed during the etching of the dielectric layer, so that the top corners of the formed second mask layer are rounded.

[0063] Please refer to Figure 6 , using the patterned photoresist layer 205 as a mask, the third mask material layer 204 , the second mask material layer 203 and the first mask material layer 202 are etched until the surface of the dielectric layer 201 is exposed, thereby forming the first mask layer 206 , the initial second mask layer 207 and the third mask layer 208 .

[0064] The process of etching the third mask material layer 204 , the second mask material layer 203 and the first mask material layer 202 includes a dry etching process.

[0065] The dry etching process can form the first mask layer 206 , the initial second mask layer 207 and the third mask layer 208 with good sidewall morphology.

[0066] The patterned photoresist layer 205 is naturally consumed during the process of etching the third mask material layer 204 , the second mask material layer 203 and the first mask material layer 202 .

[0067] Please refer to Figure 7 The dielectric layer 201 is etched using the third mask layer 208, the initial second mask layer 207 and the first mask layer 206 as masks to form an opening 210 in the dielectric layer 201, and a second mask layer 209 is formed on the first mask layer 206, wherein the top corners of the second mask layer 209 are rounded.

[0068] The process of etching the dielectric layer 201 using the third mask layer 208, the initial second mask layer 207 and the first mask layer 206 as masks includes a dry etching process; the etching gas of the dry etching process includes a fluorine-containing gas, and the fluorine-containing gas includes fluorine tetrachloride.

[0069] The third mask layer 208 is completely consumed during the process of etching the dielectric layer 201. The thickness of the third mask layer 208 is greater than the thickness of the initial second mask layer 207, and the material of the third mask layer 208 is different from that of the initial second mask layer 207, so that during the process of etching the dielectric layer 201, the third mask layer 208 can protect the initial second mask layer 207, avoiding the situation that the initial second mask layer 207 is completely consumed during the process of etching the dielectric layer 201, and the second mask layer 209 with rounded top corners cannot be formed.

[0070] In this embodiment, the material of the initial second mask layer 207 is different from the material of the first mask layer 206, and the material of the initial second mask layer 207 is the same as the material of the dielectric layer 201, so that during the process of etching the dielectric layer 201, the initial second mask layer 207 can be etched at the same time, so that the top corner of the second mask layer 209 formed during the process of etching the dielectric layer 201 is rounded.

[0071] In other embodiments, the material of the initial second mask layer is different from the material of the first mask layer, and when the material of the initial second mask layer is different from the material of the dielectric layer, the difference between the etching rate of the initial second mask layer material and the etching rate of the dielectric layer material is within a preset range, so that during the process of etching the dielectric layer, the initial second mask layer can be etched at the same time, so that the top corner of the second mask layer formed during the process of etching the dielectric layer is rounded.

[0072] During the etching of the dielectric layer 201, the etching rate of the initial second mask layer 207 is greater than the etching rate of the first mask layer 206. Therefore, the first mask layer 206 can be less damaged during the etching of the dielectric layer 201, so that the first mask layer 206 can maintain good dimensional accuracy to form an opening 210 of a preset size.

[0073] In this embodiment, the opening 210 exposes the surface of the device structure in the substrate.

[0074] Next, a conductive structure is formed in the opening 210. The conductive structure includes: a barrier layer located on the surface of the opening 210 and a conductive layer located on the surface of the barrier layer. The formation process of the conductive structure can be found in Figure 8 and Fig. 9 .

[0075] Please refer to Figure 8 A barrier material layer 211 is formed on the bottom surface and sidewall surface of the opening 210 , the sidewall surface of the first mask layer 206 , and the top surface and sidewall surface of the second mask layer 209 ; and a conductive material layer 212 is formed on the barrier material layer 211 .

[0076] The material of the barrier material layer 211 includes metal nitride, and the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride. The process of forming the barrier material layer 211 includes a physical vapor deposition process or an atomic layer deposition process.

[0077] The material of the conductive material layer 212 includes metal or metal nitride; the metal includes one or more combinations of copper, aluminum, tungsten, cobalt, nickel and tantalum; the metal nitride includes one or more combinations of tantalum nitride and titanium nitride. The process of forming the conductive material layer 212 includes electroplating process or physical vapor deposition process.

[0078] Since the top corners of the second mask layer 209 are rounded, when the blocking material layer 211 is formed on the inner wall of the opening 210, the material forming the blocking material layer 211 is not easy to accumulate on the top of the opening 210, so that the material forming the conductive material layer 212 can easily enter the bottom of the opening 210, so that the formed conductive structure material is denser and of better quality, thereby improving the conductive performance of the conductive structure.

[0079] Please refer to Fig. 9 , planarizing the conductive material layer 212 and the barrier material layer 211 until the surface of the dielectric layer 201 is exposed to form the conductive structure.

[0080] The conductive structure includes a barrier layer 213 located on the bottom surface and sidewall surface of the opening 210 and a conductive layer 214 located on the surface of the barrier layer 213 .

[0081] In this embodiment, the process of planarizing the conductive material layer 212 and the barrier material layer 211 includes a chemical mechanical polishing process.

[0082] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; forming a dielectric layer on the substrate; forming a patterned first mask layer on the dielectric layer; forming an initial second mask layer on the first mask layer, wherein the material of the initial second mask layer is different from the material of the first mask layer; A third mask layer is formed on the initial second mask layer, wherein the material of the third mask layer is different from the material of the initial second mask layer, and the method for forming the first mask layer, the initial second mask layer and the third mask layer comprises: forming a first mask material layer on the dielectric layer; forming a second mask material layer on the first mask material layer; forming a third mask material layer on the second mask material layer; forming a patterned photoresist layer on the third mask material layer; etching the third mask material layer, the second mask material layer and the first mask material layer using the patterned photoresist layer as a mask until the surface of the dielectric layer is exposed, thereby forming the first mask layer, the initial second mask layer and the third mask layer; Using the third mask layer, the initial second mask layer and the first mask layer as masks, etching the dielectric layer to form an opening in the dielectric layer, and forming a second mask layer on the first mask layer, wherein the top corners of the second mask layer are rounded; A conductive structure is formed within the opening.

2. The method for forming a semiconductor structure according to claim 1, wherein: When the dielectric layer is etched using the initial second mask layer and the first mask layer as masks, an etching rate of the initial second mask layer is greater than an etching rate of the first mask layer.

3. The method for forming a semiconductor structure according to claim 2, wherein: The material of the initial second mask layer is the same as that of the dielectric layer.

4. The method for forming a semiconductor structure according to claim 2, wherein: The material of the initial second mask layer is different from that of the dielectric layer.

5. The method for forming a semiconductor structure according to claim 4, wherein: When the dielectric layer is etched using the initial second mask layer and the first mask layer as masks, the difference between the etching rate of the initial second mask layer material and the etching rate of the dielectric layer material is within a preset range.

6. The method for forming a semiconductor structure according to claim 1, wherein: The material of the third mask layer includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, titanium nitride, titanium oxide, aluminum nitride, silicon carbide nitride and silicon oxycarbide nitride.

7. The method for forming a semiconductor structure according to claim 1, wherein: The thickness of the initial second mask layer is smaller than the thickness of the third mask layer.

8. The method for forming a semiconductor structure according to claim 1, wherein: The process of etching the dielectric layer using the initial second mask layer and the first mask layer as masks comprises a dry etching process; the etching gas of the dry etching process comprises a fluorine-containing gas, and the fluorine-containing gas comprises fluorine tetrachloride.

9. The method for forming a semiconductor structure according to claim 1, wherein: The material of the initial second mask layer includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, and silicon carbonitride oxynitride.

10. The method for forming a semiconductor structure according to claim 1, wherein: The conductive structure comprises: a barrier layer located on the surface of the opening and a conductive layer located on the surface of the barrier layer.

11. The method for forming a semiconductor structure according to claim 10, wherein: The method for forming the conductive structure includes: forming a blocking material layer on the bottom surface and side wall surface of the opening, the side wall surface of the first mask layer, and the top surface and side wall surface of the second mask layer; forming a conductive material layer on the blocking material layer; and flattening the conductive material layer and the blocking material layer until the surface of the dielectric layer is exposed to form the conductive structure.

12. The method for forming a semiconductor structure according to claim 11, wherein: The process of forming the barrier material layer includes a physical vapor deposition process or an atomic layer deposition process.

13. The method for forming a semiconductor structure according to claim 11, wherein: The process of forming the conductive material layer includes an electroplating process or a physical vapor deposition process.

14. The method for forming a semiconductor structure according to claim 10, wherein: The barrier layer is made of metal nitride, and the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.

15. The method for forming a semiconductor structure according to claim 10, wherein: The conductive layer is made of metal or metal nitride; the metal includes one or more combinations of copper, aluminum, tungsten, cobalt, nickel and tantalum; the metal nitride includes one or more combinations of tantalum nitride and titanium nitride.

16. The method for forming a semiconductor structure according to claim 1, wherein: The thickness of the first mask layer ranges from 120 angstroms to 300 angstroms.

17. The method for forming a semiconductor structure according to claim 1, wherein: The material of the first mask layer is a combination of one or more of titanium nitride, titanium oxide and silicon nitride.

18. The method for forming a semiconductor structure according to claim 1, wherein: The material of the dielectric layer includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon oxycarbide nitride.

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