Semiconductor memory element and method of making the same

Abstract

A semiconductor memory device and a method of fabricating the same are disclosed. The semiconductor memory device includes a substrate having a conductor region formed thereon, an interlayer dielectric layer formed on the substrate, a conductive via electrically connected to the conductor region, wherein the conductive via includes a lower portion embedded in the interlayer dielectric layer and an upper portion protruding from a top surface of the interlayer dielectric layer, wherein the upper portion has a circular arc-shaped top surface, and a storage structure conformally covering the circular arc-shaped top surface.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor memory element and a method for manufacturing the same. Background Technology

[0002] Magnetic Random Access Memory (MRAM) is a non-volatile semiconductor memory that retains its stored data even after the power is turned off. In terms of performance, MRAM combines the high-speed read / write capabilities of Static Random Access Memory (SRAM) with the high integration density of Dynamic Random Access Memory (DRAM), and it can be rewritten virtually an unlimited number of times, making it a "full-featured" solid-state memory. Therefore, MRAM is poised to dominate the next generation of memory market.

[0003] MRAM typically includes peripheral circuitry and multiple magnetic storage cells. Each magnetic storage cell usually consists of a transistor and a magnetic tunnel junction (MTJ). The MTJ is located between two metal layers of the CMOS integrated circuit, for example, between a second and a third metal layer, with the two metal layers connected by a via.

[0004] Currently, the size of MTJ is limited by the shielding effect of the ion beam etching angle, and cannot be increased arbitrarily, which prevents further improvement of tunneling magnetoresistance (TMR). Summary of the Invention

[0005] The main objective of this invention is to provide a semiconductor memory element and a method for manufacturing the same, so as to overcome the shortcomings and disadvantages of the prior art.

[0006] The present invention provides a semiconductor memory element comprising a substrate having a conductor region thereon; an interlayer dielectric layer disposed on the substrate; a conductive via electrically connected to the conductor region, wherein the conductive via includes a lower portion embedded in the interlayer dielectric layer and an upper portion protruding from a top surface of the interlayer dielectric layer, wherein the upper portion has an arcuate top surface; and a memory structure conformally covering the arcuate top surface.

[0007] According to an embodiment of the present invention, the thickness of the lower part is greater than the thickness of the upper part.

[0008] According to an embodiment of the present invention, the interlayer dielectric layer is a tetraethoxysilane (TEOS) silicon oxide layer.

[0009] According to an embodiment of the present invention, the semiconductor memory element further includes an etch stop layer disposed between the interlayer dielectric layer and the substrate.

[0010] According to an embodiment of the present invention, the storage structure includes a magnetic tunneling junction stack.

[0011] According to an embodiment of the present invention, the conductive via includes a tungsten metal layer.

[0012] According to an embodiment of the present invention, the conductive via has a barrier layer between the tungsten metal layer and the interlayer dielectric layer.

[0013] Another aspect of the present invention provides a semiconductor memory element, comprising a substrate having a conductor region thereon; an interlayer dielectric layer disposed on the substrate; a conductive via electrically connected to the conductor region, wherein the conductive via includes a lower portion embedded in the interlayer dielectric layer and an upper portion protruding from a top surface of the interlayer dielectric layer, wherein the upper portion has a flat top surface and a rounded corner surface between the flat top surface and a sidewall surface of the upper portion; and a storage structure conformally covering the rounded corner surface.

[0014] According to an embodiment of the present invention, the thickness of the lower part is greater than the thickness of the upper part.

[0015] According to an embodiment of the present invention, the interlayer dielectric layer is a tetraethoxysilane (TEOS) silicon oxide layer.

[0016] According to an embodiment of the present invention, the semiconductor memory element further includes an etch stop layer disposed between the interlayer dielectric layer and the substrate.

[0017] According to an embodiment of the present invention, the storage structure includes a magnetic tunneling junction stack.

[0018] According to an embodiment of the present invention, the conductive via includes a tungsten metal layer.

[0019] According to an embodiment of the present invention, the conductive via has a barrier layer between the tungsten metal layer and the interlayer dielectric layer.

[0020] Another aspect of the present invention provides a method for forming a semiconductor memory element, comprising: providing a substrate having a conductor region thereon; forming an interlayer dielectric layer on the substrate; forming a conductive via in the interlayer dielectric layer, wherein the conductive via is electrically connected to the conductor region; performing a first etching process on the interlayer dielectric layer such that an upper portion of the conductive via protrudes from a top surface of the interlayer dielectric layer and a lower portion of the conductive via is embedded in the interlayer dielectric layer; performing a second etching process on the upper portion of the conductive via to trim the upper portion; and forming a memory structure conformally covering the upper portion of the conductive via.

[0021] According to an embodiment of the present invention, the thickness of the lower part is greater than the thickness of the upper part.

[0022] According to an embodiment of the present invention, the interlayer dielectric layer is a tetraethoxysilane (TEOS) silicon oxide layer.

[0023] According to an embodiment of the present invention, the method further includes: forming an etch stop layer between the interlayer dielectric layer and the substrate.

[0024] According to an embodiment of the present invention, after the second etching process is performed on the upper part of the conductive via, the upper part has an arc-shaped top surface.

[0025] According to an embodiment of the present invention, after the second etching is performed on the upper part of the conductive via, the upper part has a flat top surface and a rounded corner surface between the flat top surface and a side wall surface of the upper part. Attached Figure Description

[0026] Figures 1 to 5 This is a schematic diagram illustrating a method for forming a semiconductor memory element according to an embodiment of the present invention;

[0027] Figures 6 to 10 This is a schematic diagram illustrating a method for forming a semiconductor memory element according to another embodiment of the present invention.

[0028] Explanation of main component symbols

[0029] 1, 2 Semiconductor memory elements

[0030] 20 Conductive Through Holes

[0031] 20U upper

[0032] 20L lower part

[0033] 30 Storage Structure

[0034] 100 base

[0035] 110 Conductor Region

[0036] 120 dielectric layer

[0037] 130 Etching Stop Layer

[0038] 140 interlayer dielectric layers

[0039] 201 Tungsten metal layer

[0040] 202 Barrier Layer

[0041] 300 stacked structure

[0042] 301 Lower Electrode Layer

[0043] 302 Magnetic Tunneling Stack

[0044] 303 Upper Electrode Layer

[0045] PR photoresist pattern

[0046] S1~S7 Top surface Detailed Implementation

[0047] In the following description, details will be illustrated with reference to the accompanying drawings, which also form part of the detailed description of the specification, and which are depicted in a manner that describes specific examples in which the embodiments may be practiced. The embodiments described below are described in sufficient detail to enable those skilled in the art to implement them.

[0048] Of course, other embodiments may be adopted, or any structural, logical, and electrical changes may be made without departing from the embodiments described herein. Therefore, the following detailed description should not be regarded as limiting; rather, the embodiments included therein will be defined by the appended claims.

[0049] Figures 1 to 5 This is a schematic diagram illustrating a method for forming a semiconductor memory element 1 according to an embodiment of the present invention. Figure 1 As shown, a substrate 100, such as a silicon substrate, is first provided, on which a conductive region 110 is disposed. For example, the conductive region 110 may be a copper metal layer disposed in a dielectric layer 120, but is not limited thereto. According to an embodiment of the present invention, the dielectric layer 120 may be a low dielectric constant material layer, for example, its dielectric constant may be less than 2.5, but is not limited thereto. An inter-layer dielectric layer 140 is formed on the substrate 100. According to an embodiment of the present invention, the inter-layer dielectric layer 140 may be a tetraethylorthosilicate (TEOS) silicon oxide layer.

[0050] According to an embodiment of the present invention, an etch stop layer 130 may be additionally formed between the interlayer dielectric layer 140 and the substrate 100, for example, a nitrogen-doped silicon nitride layer, but not limited thereto.

[0051] According to an embodiment of the present invention, a conductive via 20 is then formed in the interlayer dielectric layer 140. According to an embodiment of the present invention, the conductive via 20 is electrically connected to the conductor region 110. At this time, the top surface S1 of the conductive via 20 and the top surface S2 of the interlayer dielectric layer 140 are flush. According to an embodiment of the present invention, the conductive via 20 may include a tungsten metal layer 201. Furthermore, the conductive via 20 may have a barrier layer 202 between the tungsten metal layer 201 and the interlayer dielectric layer 140, for example, titanium nitride, but is not limited thereto.

[0052] Methods for forming conductive vias 20 may include lithography, etching, chemical vapor deposition (CVD), and chemical mechanical polishing (CMP) processes.

[0053] like Figure 2 As shown, a first etching process, such as a dry etching process, is then performed on the interlayer dielectric layer 140 to remove a portion of the interlayer dielectric layer 140, thereby causing an upper part 20U of the conductive via 20 to protrude from the top surface S3 of the interlayer dielectric layer 140, and causing a lower part 20L of the conductive via 20 to be embedded in the interlayer dielectric layer 140.

[0054] like Figure 3 As shown, a second etching process, such as a dry etching process, is then performed on the upper portion 20U of the conductive via 20 to refine the upper portion 20U. According to an embodiment of the present invention, after performing the aforementioned second etching process on the upper portion 20U of the conductive via 20, the upper portion 20U has an arc-shaped top surface S4. According to an embodiment of the present invention, the thickness of the lower portion 20L of the conductive via 20 can be greater than the thickness of the upper portion 20U.

[0055] like Figure 4As shown, next, a lower electrode layer 301, a magnetic tunneling junction stack 302, and an upper electrode layer 303 are sequentially deposited on the top surface S3 of the interlayer dielectric layer 140 and the upper portion 20U of the conductive via 20. The lower electrode layer 301, the magnetic tunneling junction stack 302, and the upper electrode layer 303 constitute a stacked structure 300. According to an embodiment of the present invention, the lower electrode layer 301 may be, for example, tantalum nitride, and the upper electrode layer 303 may be, for example, titanium nitride, but is not limited thereto. According to an embodiment of the present invention, the magnetic tunneling junction stack 302 may include a reference layer, a channel layer, and a free layer, but is not limited thereto. The reference layer and the free layer may contain magnetic materials, and the channel layer may contain insulating materials, but is not limited thereto.

[0056] like Figure 5 As shown, a photolithography process is then performed to form a photoresist pattern PR on the conductive via 20. Next, an etching process, such as anisotropic dry etching, is used to etch the stacked structure 300 not covered by the photoresist pattern PR, thereby forming the memory structure 30, which conformally covers the upper portion 20U of the conductive via 20. Subsequent steps may include low-dielectric-constant material layer deposition and back-end metallization processes, which are well-known techniques and will not be described further.

[0057] Figures 6 to 10 This is a schematic diagram illustrating a method for forming a semiconductor memory element 2 according to another embodiment of the present invention. Figure 6 As shown, a substrate 100, such as a silicon substrate, is also provided, on which a conductive region 110 is disposed. For example, the conductive region 110 may be a copper metal layer disposed in a dielectric layer 120, but is not limited thereto. According to an embodiment of the present invention, the dielectric layer 120 may be a low dielectric constant material layer, for example, its dielectric constant may be less than 2.5, but is not limited thereto. An interlayer dielectric layer 140 is formed on the substrate 100. According to an embodiment of the present invention, the interlayer dielectric layer 140 may be a TEOS silicon oxide layer.

[0058] According to an embodiment of the present invention, an etch stop layer 130 may be additionally formed between the interlayer dielectric layer 140 and the substrate 100, for example, a nitrogen-doped silicon nitride layer, but not limited thereto.

[0059] According to an embodiment of the present invention, a conductive via 20 is then formed in the interlayer dielectric layer 140. According to an embodiment of the present invention, the conductive via 20 is electrically connected to the conductor region 110. At this time, the top surface S1 of the conductive via 20 and the top surface S2 of the interlayer dielectric layer 140 are flush. According to an embodiment of the present invention, the conductive via 20 may include a tungsten metal layer 201. Furthermore, the conductive via 20 may have a barrier layer 202 between the tungsten metal layer 201 and the interlayer dielectric layer 140, for example, titanium nitride, but is not limited thereto.

[0060] like Figure 7 As shown, a first etching process, such as a dry etching process, is then performed on the interlayer dielectric layer 140 to remove a portion of the interlayer dielectric layer 140, thereby causing an upper part 20U of the conductive via 20 to protrude from the top surface S3 of the interlayer dielectric layer 140, and causing a lower part 20L of the conductive via 20 to be embedded in the interlayer dielectric layer 140.

[0061] like Figure 8 As shown, a second etching process, such as a dry etching process, is then performed on the upper portion 20U of the conductive via 20 to refine the upper portion 20U. According to an embodiment of the present invention, after performing the aforementioned second etching process on the upper portion 20U of the conductive via 20, the upper portion 20U has a flat top surface S5 and a rounded corner surface S6 located between the flat top surface S5 and a side wall surface S7 of the upper portion 20U. According to an embodiment of the present invention, the thickness of the lower portion 20L of the conductive via 20 can be greater than the thickness of the upper portion 20U.

[0062] like Figure 9 As shown, next, a lower electrode layer 301, a magnetic tunneling junction stack 302, and an upper electrode layer 303 are sequentially deposited on the top surface S3 of the interlayer dielectric layer 140 and the upper portion 20U of the conductive via 20. The lower electrode layer 301, the magnetic tunneling junction stack 302, and the upper electrode layer 303 constitute a stacked structure 300. According to an embodiment of the present invention, the lower electrode layer 301 may be, for example, tantalum nitride, and the upper electrode layer 303 may be, for example, titanium nitride, but is not limited thereto. According to an embodiment of the present invention, the magnetic tunneling junction stack 302 may include a reference layer, a channel layer, and a free layer, but is not limited thereto. The reference layer and the free layer may contain magnetic materials, and the channel layer may contain insulating materials, but is not limited thereto.

[0063] like Figure 10 As shown, a photolithography process is then performed to form a photoresist pattern PR on the conductive via 20. Next, an etching process, such as anisotropic dry etching, is used to etch the stacked structure 300 not covered by the photoresist pattern PR, thereby forming the memory structure 30, which conformally covers the upper portion 20U of the conductive via 20. Subsequent steps may include low-dielectric-constant material layer deposition and back-end metallization processes, which are well-known techniques and will not be described further.

[0064] This invention uses a secondary etching process to trim the upper part 20U of the conductive via 20, resulting in an arc-shaped top surface S4 on the upper part 20U. Figure 3 ) or has a flat top surface S5 and a rounded corner surface S6 between the flat top surface S5 and the side wall surface S7 of the upper 20U. Figure 8The subsequent storage structure 30 conformally covers the upper part 20U of the conductive via 20, which can increase the overlap area between the magnetic tunneling junction stack 302 and the conductive via 20, thereby improving the tunneling magnetoresistance (TMR).

[0065] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A semiconductor memory element, characterized in that, Include: A substrate on which a conductor region is provided; An interlayer dielectric layer is disposed on the substrate; A conductive via, electrically connected to the conductor region, wherein the conductive via includes a lower portion embedded in the interlayer dielectric layer and an upper portion protruding from the top surface of the interlayer dielectric layer, wherein the upper portion has an arc-shaped top surface, and wherein the maximum width of the upper portion in the cross-sectional structure of the semiconductor memory element is not greater than the width of the lower portion. as well as A storage structure includes a lower electrode layer, a magnetic tunneling junction stack, and an upper electrode layer sequentially and conformally covering the arc-shaped top surface, wherein the lower electrode layer directly contacts the top surface of the interlayer dielectric layer and the upper arc-shaped top surface, the sidewalls of the lower electrode layer are flush with the sidewalls of the magnetic tunneling junction stack and the upper electrode layer, and a portion of the top surface of the interlayer dielectric layer is located between the sidewall of the lower electrode layer and the upper portion of the conductive via.

2. The semiconductor memory element according to claim 1, wherein, The thickness of the lower part is greater than the thickness of the upper part.

3. The semiconductor memory element according to claim 1, wherein, The interlayer dielectric layer is a tetraethoxysilane (TEOS) silicon oxide layer.

4. The semiconductor memory element according to claim 1, wherein, Also includes: An etch stop layer is disposed between the interlayer dielectric layer and the substrate.

5. The semiconductor memory element according to claim 1, wherein, The storage structure includes a magnetic tunneling junction stack.

6. The semiconductor memory element according to claim 1, wherein, The conductive via contains a tungsten metal layer.

7. The semiconductor memory element according to claim 6, wherein, The conductive via has a barrier layer between the tungsten metal layer and the interlayer dielectric layer.

8. A semiconductor memory element, characterized in that, include: A substrate on which a conductor region is provided; An interlayer dielectric layer is disposed on the substrate; A conductive via, electrically connected to the conductor region, wherein the conductive via includes a lower portion embedded in the interlayer dielectric layer and an upper portion protruding from the top surface of the interlayer dielectric layer, wherein the upper portion has a flat top surface and a rounded corner surface between the flat top surface and the sidewall surface of the upper portion, wherein the maximum width of the upper portion in the cross-sectional structure of the semiconductor memory element is not greater than the width of the lower portion. as well as A storage structure includes a lower electrode layer, a magnetic tunneling junction stack, and an upper electrode layer sequentially and conformally covering the rounded corner surface, wherein the lower electrode layer directly contacts the top surface of the interlayer dielectric layer and the upper rounded corner surface of the conductive via, the sidewalls of the lower electrode layer are flush with the sidewalls of the magnetic tunneling junction stack and the upper electrode layer, and a portion of the top surface of the interlayer dielectric layer is located between the sidewall of the lower electrode layer and the upper portion of the conductive via.

9. The semiconductor memory element according to claim 8, wherein, The thickness of the lower part is greater than the thickness of the upper part.

10. The semiconductor memory element according to claim 8, wherein, The interlayer dielectric layer is a tetraethoxysilane (TEOS) silicon oxide layer.

11. The semiconductor memory element according to claim 8, wherein, Also includes: An etch stop layer is disposed between the interlayer dielectric layer and the substrate.

12. The semiconductor memory element according to claim 8, wherein, The storage structure includes a magnetic tunneling junction stack.

13. The semiconductor memory element according to claim 8, wherein, The conductive via includes a tungsten metal layer.

14. The semiconductor memory element according to claim 13, wherein, The conductive via has a barrier layer between the tungsten metal layer and the interlayer dielectric layer.

15. A method of forming a semiconductor memory element, comprising: A substrate is provided on which a conductor region is provided; An interlayer dielectric layer is formed on the substrate; Conductive vias are formed in the interlayer dielectric layer, wherein the conductive vias are electrically connected to the conductor region; A first etching process is performed on the interlayer dielectric layer, so that the upper part of the conductive via protrudes from the top surface of the interlayer dielectric layer, and the lower part of the conductive via is embedded in the interlayer dielectric layer. A second etching process is performed on the upper portion of the conductive via to refine the upper portion, wherein the maximum width of the upper portion in the cross-sectional structure of the semiconductor memory element is not greater than the width of the lower portion; and A storage structure is formed comprising a lower electrode layer, a magnetic tunneling junction stack, and an upper electrode layer sequentially and conformally covering the upper portion of the conductive via, wherein the lower electrode layer directly contacts the top surface of the interlayer dielectric layer and the top surface of the upper portion of the conductive via, the sidewalls of the lower electrode layer are flush with the sidewalls of the magnetic tunneling junction stack and the upper electrode layer, and a portion of the top surface of the interlayer dielectric layer is located between the sidewall of the lower electrode layer and the upper portion of the conductive via. Wherein, after the second etching process is performed on the upper part of the conductive via, the upper part has an arc-shaped top surface.

16. The method according to claim 15, wherein, The thickness of the lower part is greater than the thickness of the upper part.

17. The method according to claim 15, wherein, The interlayer dielectric layer is a tetraethoxysilane (TEOS) silicon oxide layer.

18. The method according to claim 15, wherein, Also includes: An etch stop layer is formed between the interlayer dielectric layer and the substrate.

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