Electronic Devices

Abstract

An electronic device includes: a substrate, a plurality of pixels, a plurality of data lines, an amplifier, and a current source. The plurality of pixels and the plurality of data lines are disposed on the substrate. The amplifier and the current source are coupled to one of the plurality of data lines, wherein at least a portion of the data line forms a conduction path. One of the plurality of pixels is coupled to the data line at a first node, the first node is located on the conduction path, and a first current flowing from the first node to the amplifier is different from a second current flowing from the first node to the current source.

Description

Technical Field

[0001] The present disclosure relates to electronic devices, and more particularly to electronic devices with a mild IR-drop phenomenon. Background Art

[0002] Image sensors including active pixel sensors are now widely used in electronic devices. In an image sensor, a plurality of pixels are coupled to a readout circuit, and data from each pixel is read by the readout circuit. Generally speaking, the readout circuit includes an amplifier and a companion current source. In addition, there is a resistance of a signal line between the output terminal of the pixel and the input terminal of the amplifier. Therefore, the output data voltage of the pixel will experience a severe voltage drop (IR-drop) at the input terminal of the amplifier.

[0003] Therefore, an electronic device with a more minor voltage drop phenomenon is needed. Summary of the invention

[0004] An embodiment of the present disclosure provides an electronic device. The electronic device includes: a substrate, a plurality of pixels, a plurality of data lines, an amplifier, and a current source. The plurality of pixels and the plurality of data lines are arranged on the substrate. The amplifier and the current source are coupled to one of the plurality of data lines, wherein at least a portion of the data line forms a conduction path. One of the plurality of pixels is coupled to the data line at a first node, the first node is located on the conduction path, and a first current flowing from the first node to the amplifier is different from a second current flowing from the first node to the current source.

[0005] Another embodiment of the present disclosure provides an electronic device. The electronic device includes: a substrate, a plurality of pixels, a plurality of data lines, a plurality of companion lines, an amplifier, and a current source. The amplifier is coupled to one of the plurality of data lines, and the current source is coupled to one of the plurality of companion lines. One of the plurality of pixels is coupled to the data line through a first node, and is coupled to the companion line through the first node and a second node, and a first current flowing from the first node to the amplifier is different from a second current flowing from the first node to the current source. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] In order to make the above-mentioned objects, features and advantages of the present invention more clearly understood, the specific embodiments of the present invention are described in detail below in conjunction with the accompanying drawings, wherein:

[0007] Figure 1A FIG. 4 is a schematic diagram of an electronic device according to an embodiment of the present disclosure.

[0008] Figure 1B Based on Figure 1A Schematic diagram of a pixel and its corresponding amplifier according to an embodiment.

[0009] Figure 1C Based on Figure 1B The voltage V BE and V Data The relationship diagram between .

[0010] Figures 1D to 1F Based on Figure 1A A partial schematic diagram of an electronic device of an embodiment.

[0011] Figure 1G is the output data voltage V of the pixel according to the embodiment of the present disclosure Data Schematic diagram of the voltage at the input of the amplifier.

[0012] Figures 1H-1K It is a partial schematic diagram of an electronic device according to some embodiments of the present disclosure.

[0013] Figure 2A FIG. 4 is a schematic diagram of an electronic device according to another embodiment of the present disclosure.

[0014] Figure 2B Based on Figure 2A Schematic diagram of a pixel and its corresponding amplifier according to an embodiment.

[0015] FIG. 2C to FIG. 2E FIG. 1 is a partial schematic diagram of an electronic device according to the embodiment of FIG. 1 .

[0016] Figure 2F is the output data voltage V of the pixel according to an embodiment of the present disclosure Data Schematic diagram of the voltage at the amplifier input.

[0017] Figure 2G to Figure 2J Schematic diagram of a portion of an electronic device according to different embodiments of the present disclosure. DETAILED DESCRIPTION

[0018] The following description is made for the purpose of illustrating the general principles of the present disclosure and is not to be construed in a limiting sense. The scope of the present disclosure is determined by reference to the appended claims.

[0019] In the following detailed description, for the purpose of explanation, numerous specific details and embodiments are set forth in order to provide a thorough understanding of the present disclosure. The use of similar and / or corresponding numbers in the drawings of different embodiments does not imply any association between the different embodiments.

[0020] In addition, in this specification, relative spatial expressions are used. For example, "below", "bottom", "above" or "top" are used to describe the position of one element relative to another element. It should be understood that if the device is turned upside down, the "lower" element will become a "higher" element.

[0021] It should be understood that although the terms first, second, third, etc. may be used herein to describe various components, assemblies, regions, layers, parts, and / or parts, these components, assemblies, regions, layers, parts, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, part, or part from another element, component, region, layer, or part. Therefore, a first component, component, region, layer, part, or part in the specification may be referred to as a second component, component, region, layer, part, or part in the claims without departing from the teachings of the present disclosure.

[0022] It should be understood that this description of the exemplary embodiments is intended to be read in conjunction with the accompanying drawings, which are considered part of the entire written description. The drawings are not drawn to scale. In addition, in order to simplify the drawings, structures and devices are shown schematically.

[0023] The terms "approximately," "about," and "substantially" generally mean that a value is within + / -20% of the stated value, more typically within + / -10%, + / -5%, + / -3%, + / -2%, + / -1%, or + / -0.5% of the stated value. The stated values ​​of the present disclosure are approximate. Even if not specifically stated, the nominal value still includes the meaning of "approximately," "approximately," or "substantially."

[0024] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It should be understood that in each case, terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with the relevant technology of the present disclosure and the background or context of the present disclosure, and unless so defined, should not be interpreted in an idealized or overly formal manner.

[0025] In addition, in some embodiments of the present disclosure, unless otherwise explicitly stated, terms such as "connected" and "interconnected" regarding attachment, coupling, etc. refer to a relationship in which structures are fixed or attached to each other directly or indirectly through intermediate structures (e.g., electrical connections), as well as removable or rigid attachments or relationships.

[0026] Figure 1A FIG. 4 is a schematic diagram of an electronic device according to an embodiment of the present disclosure. Figure 1B Based on Figure 1A Schematic diagram of a pixel and its corresponding amplifier of an embodiment.

[0027] In one embodiment, the electronic device 100 may include an image sensor. In some embodiments, the electronic device 100 may be an X-ray detector, a fingerprint sensor, a smart TV, a smart phone, a tablet computer, a desktop computer, a laptop computer, a surveillance camera, a digital camera, a digital video camera, etc., but the present disclosure is not limited thereto.

[0028] The electronic device 100 includes a substrate 110, a pixel array 120, a plurality of read lines 130, a plurality of data lines 135, a driving circuit 140, a readout circuit 150, and a current source component 160. The pixel array 120, the read lines 130, and the data lines 135 are disposed on the substrate 110. The pixel array 120 may be a two-dimensional array of pixels 121 having X columns and Y rows (X and Y are positive integers greater than 1). The readout circuit 150 and the current source component 160 are disposed in edge regions 170 and / or 180, respectively, as shown in FIG. Figure 1A For ease of explanation, Figure 1B The pixel 121 shown in FIG. 1 includes a 2T-APS (2-transistor-active pixel sensor) circuit, but the present disclosure is not limited thereto. It should be noted that the circuit of the pixel 121 can be implemented by any other known or newly developed circuit structure in the art.

[0029] There are Y read lines 130 and X data lines 135. The row selection signals transmitted by the read lines 130 are labeled Read 1 to Read Y, respectively, and the data transmitted by the data lines 135 are labeled Data 1 to Data X. The read lines 130 can be regarded as row selection lines controlled by the driving circuit 140. For example, the driving circuit 140 will sequentially enable one read line 130 (i.e., one row), and the data of the pixels coupled to the enabled read line 130 can be read by the readout circuit 150 through the data line 135.

[0030] Please refer to Figure 1B , the pixel 121 includes transistors M2 to M3, and a photodiode PD, but is not limited thereto. The transistor M1 connected between the pixel 121 and the data line 135 may be a row selection transistor controlled by a row selection signal Read n (n is an integer from 1 to Y). The transistor M2 may be a source follower coupled to a voltage source Vdd, and the transistor M3 may be a reset transistor. When the reset signal Reset is in a low logic state and the row selection signal Read n is in a high logic state, the transistor M1 is turned on, so that the data at the node P is transmitted to the node N1 through the data line 135. The transistor M1. The node N1 corresponding to the pixel 121 is located on the corresponding data line 135 and is coupled between the amplifier 151 and the current source 161.

[0031] like Figure 1B As shown, the current I D Through transistors M2 and M1, the current I D Divided into current I amp and current I cs Two currents, Iamp represents the current flowing from the node N1 into the amplifier 151, I cs represents the current flowing from the node N1 to the current source 161. For example, assuming that the pixel 121 is coupled to the nth read line 130 (ie, the pixel 121 is in the nth row), the current I amp Through the resistor R data2 And the resistor R data1 Flows into the input terminal of the amplifier 151. It should be noted that the signal lines in the electronic device 100 each have their own resistance. If the length of the signal line increases, the resistance of the signal line will increase accordingly. data1 It can refer to the equivalent resistance between the input terminal of the amplifier 151 and the node N1 corresponding to the pixel 121 coupled to the first read line 130 (ie, the pixel 121 is in the first row), and the resistance R data2 It can refer to the equivalent resistance between the nodes N1 corresponding to the pixels 121 of two adjacent rows. In other words, when calculating the resistance between the node N1 corresponding to the pixels 121 of the Nth row and the node N1 corresponding to the pixels 121 of the first row, there will be (N-1) resistors R data2 For ease of understanding, although Figure 1B The pixel 121 in the nth row has only one resistor R data2 As a representation.

[0032] In addition, the resistor R data3 It may refer to the resistance between the node N1 corresponding to the pixel 121 of the last row and the current source 161. Similarly, for ease of understanding, although the pixel 121 in 1B represents the pixel 121 of the nth row, the node N1 and the resistance R data3 There is no resistor R between data2 .

[0033] In the present disclosure, because the input terminal of the amplifier 151 has a very high input impedance, the current I flowing into the input terminal amp Very low, for example, about 20pA (i.e. 2x10 -11 A). Current I amp is defined as the input bias current of the amplifier 151. The amplifier 151 may be a non-inverting closed loop configuration, such as Figure 1B As shown, the other input terminal of the amplifier 151 is coupled to the reference voltage V ref , but the present disclosure is not limited thereto.

[0034] In addition, the current source 161 can provide a more stable current I CS , with a range of 10 -6 A to 10 -5 A(10-6 A≤Ics≤10 - 5 A). If the current I CS 5μA (i.e. 5x10 -6 A), current I amp is 20pA (i.e. 2x10 -11 A), then the current I amp With current I CS The ratio (I amp / I CS ) is 0.0004% (i.e. 4x10 -6 ). It should be noted that the ratio I amp / I CS The ratio I amp / I CS Can be equal to or less than 0.0015% (0 amp / I CS ≤0.0015%). Therefore, with the current I CS Compared with the current I amp can be ignored. Therefore, it can be concluded that the current I D and I CS Basically the same.

[0035] Specifically, in this embodiment, the node N1 can be a data voltage V Data First, the data line 135 is entered. At least a portion of the data line 135 between the amplifier 151 and the current source 161 forms a conduction path, which can be the shortest path to establish an electrical connection between the amplifier 151 and the current source 161. The node N1 is located on the conduction path, and the current I from the node N1 to the amplifier 151 amp is less than the current I from the node N1 to the current source 161 CS .

[0036] For the partial conduction path from node N1 to the input of amplifier 151, since the current I amp is very small, and the voltage V1 at the node N1 and the voltage V2 at the node N2 (ie, the input terminal of the amplifier 151) are substantially the same.

[0037] For the other part of the conduction path from node N1 to current source 161, since the current I CS cannot be ignored because the current flowing through the resistor R data3 The current I CS An IR-drop phenomenon will occur, causing the voltage V1 at the node N1 to be greater than the voltage V5 at the node N5. The current source 161 is coupled between the node N5 and a ground terminal, and the ground terminal has a ground voltage substantially equal to 0 or a predetermined reference voltage.​

[0038] Please refer to Figure 1B Specifically, when the row selection signal Read n is in a high logic state, the transistor M1 is turned on. Therefore, the current I D flows through the drain and source of transistor M2. At this time, the data voltage VData of the node N1 can be expressed by formulas (1) and (2):

[0039]

[0040]

[0041] Where V BE Represents the voltage at node BE; V P Represents the voltage at node P; V th represents the threshold voltage of transistor M2; μ represents the mobility of transistor M2; W and L represent the width and length of transistor M2 respectively; C ox represents the capacitance per unit area of ​​transistor M2. At this time, the data voltage V Data Depends on voltage V BE and current I CS , where the voltage V BE and V Data The relationship between Figure 1C shown.

[0042] When the row selection signal Read n is in a low logic state, the transistor M1 is turned off. Therefore, the current I CS The data voltage V Data Discharge to ground voltage.

[0043] Figures 1D to 1F Based on Figure 1A A partial schematic diagram of an electronic device according to an embodiment. Figure 1G is the output data voltage V of the pixel according to the embodiment of the present disclosure Data Schematic diagram of the voltage at the input of the amplifier. Figure 1A and Figure 1D to Figure 1G .

[0044] In the first scenario, please refer to Figure 1D When the row selection signal Read 1 is in a high logic state, the transistor M1 corresponding to the pixel 121 in the first row is turned on. Therefore, the data voltage V Data will be transmitted to the node N1 corresponding to the pixel 121 on the data line 135. For the pixel 121 located in the first row, the current I amp Through the resistor R data1 flows into the amplifier 151. In addition, the current ICS Through (Y-1) resistors R data2 and a resistor R data3 flows into the current source 161. If the output data voltage V Data The waveform is Figure 1G The waveform shown at position ① in FIG. 1 is as follows: the waveform of the voltage at the input terminal of the amplifier 151 is as follows: Figure 1G The waveform shown in position ② in the figure. That is, because the current I flowing into the amplifier 151 amp is very small, so the output data voltage V of pixel 121 Data can be transmitted to amplifier 151 without severe voltage drop.

[0045] In the second scenario, please refer to Figure 1E When the row selection signal Read n (n is a positive integer greater than 1 and less than Y) is in a high logic state, the transistor M1 corresponding to the pixel 121 located in the nth row is turned on. Data is transmitted to the node N1 on the data line 135 corresponding to the pixel 121. As the distance between the node N1 and the input terminal of the amplifier 151 becomes longer, the current I amp Through (n-1) resistors R data2 and resistor R data1 flows into the amplifier 151. In addition, the current I CS Through the remaining resistor R data2 and a resistor R data3 flows into the current source 161. It should be noted that, because the current I amp Very small, current I amp The voltage drop caused by can be substantially negligible. If the output data voltage V Data The waveform is Figure 1G The waveform shown in position ① in the figure, the voltage waveform at the input end of the amplifier 151 is Figure 1G Therefore, the output data voltage V of pixel 121 is Data can be transmitted to amplifier 151 without severe voltage drop.

[0046] In the third scenario, please refer to Figure 1F When the row selection signal Read Y is in a high logic state, only the transistor M1 corresponding to the pixel 121 located in the Yth row (ie, the last row) is turned on. Therefore, the data voltage V Data will be transmitted to the node N1 on the data line 135 corresponding to the pixel 121. Because there are (Y-1) pixels between the amplifier 151 and the pixel 121 located in the Yth row, the current I ampThrough (Y-1) resistors R data2 and resistor R data1 Flows into the amplifier 151. In addition, there is no other pixel between the pixel 121 and the current source 161, and the current I cs Through a resistor R data3 flows into the current source 161. It should be noted that, because the current I amp Very small, current I amp The voltage drop caused by this can be ignored. If the output data voltage V Data The waveform is as Figure 1G The waveform shown in position ①, the voltage waveform at the input end of the amplifier 151 is Figure 1G That is, the output data voltage V of the pixel 121 is Data can be transmitted to amplifier 151 without severe voltage drop.

[0047] Figures 1H-1K It is a partial schematic diagram of an electronic device according to some embodiments of the present disclosure.

[0048] like Figure 1A and Figure 1H As shown, the amplifier 151 and the current source 161 coupled to the same data line are arranged at opposite ends of the data line (e.g., in opposite edge regions 170 and 180 of the substrate 110). For example, the amplifier 151 coupled to the adjacent data line 135 is disposed in the top edge region 170 of the substrate 110, and the current source 161 coupled to the adjacent data line 135 is disposed in the bottom edge region 180 of the substrate 110.

[0049] exist Fig. 1I In the embodiment, the amplifier 151 and the current source 161 coupled to the same data line are arranged in the same edge region 170 of the substrate 110. In addition, the data lines 135 may each have a U-shape and correspond to the readout switches (ie, Figure 1B The transistor M1) is coupled to at least one U-shaped data line.

[0050] like Figure 1JAs shown, the amplifier 151 and the current source 161 coupled to the same data line 135 are arranged at opposite ends of the data line 135 (e.g., in opposite edge regions 170 and 180 of the substrate 110). However, the amplifier 151 and the current source 161 coupled to adjacent data lines 135 have different arrangements. For example, for the left data line 135, the amplifier 151 is disposed in the top edge region 170 of the substrate 110, and the current source 161 is disposed in the bottom edge region 180 of the substrate 110. For the right data line 135, the amplifier 151 is disposed in the bottom edge region 180 of the substrate 110, and the current source 161 is disposed in the top edge region 170 of the substrate 110.

[0051] exist Figure 1K In the embodiment, the amplifier 151 and the current source 161 coupled to the same data line 135 are arranged in the same edge region 170 or 180 of the substrate 110. However, the amplifier 151 and the current source 161 coupled to the adjacent data line 135 may have a different arrangement. In addition, the data line may have a U-shape, and the readout switch (i.e. Figure 1B The transistor M1 in the substrate 110 is coupled to at least one U-shaped data line 135. For example, for the left data line 135, the amplifier 151 and the current source 161 are disposed in the top edge region 170 of the substrate 110. For the right data line 135, the amplifier 151 and the current source 161 are disposed in the bottom edge region 180 of the substrate 110.

[0052] Figure 2A FIG. 4 is a schematic diagram of an electronic device according to another embodiment of the present disclosure.

[0053] Figure 2A The electronic device 200 and Figure 1A The electronic device 200 is similar to the electronic device 100 in FIG. The differences between the electronic devices 200 and 100 include: (1) the companion line 236 is adjacent to the data line 235; (2) another switch transistor is added between the pixel 221 and the added companion line 236; and (3) the current source 252 is coupled to the companion line 236. The details of the above differences will be described in the following embodiments. It should be noted that the present embodiment does not limit the positions of the current source 252 and the amplifier 251. In some embodiments, the current source 252 can be changed to be coupled to the data line 235, and the amplifier 251 can be coupled to the companion line 236.

[0054] In one embodiment, a plurality of amplifiers 251 and a plurality of current sources 252 are provided in the readout circuit 250, such as Figure 2A In addition, the current source 252 is coupled to the corresponding companion line 236. It should be noted that, Figure 2AThe arrangement of the amplifier 251 and the current source 252 is for the convenience of description and is one of the various arrangements disclosed in the present invention. Other arrangements will be described in the following embodiments.

[0055] Figure 2B Based on Figure 2A Schematic diagram of a pixel and its corresponding amplifier according to an embodiment.

[0056] Figure 2B Similar to Figure 1B , the difference is Figure 2B The additional transistor M4 indicates that the pixel 221 can be implemented using a 2T-APS circuit, but the present disclosure is not limited thereto. Figure 2B In the embodiment, transistor M4 is a switch transistor, which is coupled to transistor M1 at node N1, and the control terminal of transistor M4 can also be controlled by the same row selection signal Read n, but the present disclosure is not limited thereto. In some embodiments, transistor M1 and transistor M4 are controlled by two different signals. More specifically, the control terminal of transistor M1 can be controlled by the row selection signal Read n, and the control terminal of transistor M4 can be controlled by another control signal. It should be noted that in Figure 2A , the pixel 221 can be coupled to its corresponding data line 235 through the transistor M1 and the node N1, and coupled to its corresponding companion line 236 through the two transistors M1 and M4 and the two nodes N1 and N3. For example, if the row selection signal Read n is in a high logic state, the transistors M1 and M4 are turned on, and the data of the node P is transmitted to the node N1 through the transistor M1, and the data of the node P is transmitted to the node N3 through the transistors M1 and M4. The node N1 is coupled to the data line 235, and the node N3 is coupled to the companion line 236.

[0057] Similar to the previous embodiment, in this embodiment, the node N1 may be a data voltage V Data First, it enters the place of data line 235. The part of data line 235 between amplifier 251 and node N1, the connection path between node N1 and node N3, and the part of companion line 236 between current source 252 and node N3 form a conduction path, which can be the shortest path for electrical connection between amplifier 251 and current source 252. Node N1 is located in the conduction path, and the current I from node N1 to amplifier 251 amp is less than the current I from the node N1 to the current source 252 CS .

[0058] FIG. 2C to FIG. 2E FIG. 1 is a partial schematic diagram of an electronic device according to the embodiment of FIG. 1 . Figure 2F is the output data voltage V of the pixel according to an embodiment of the present disclosure DataSchematic diagram of the voltage at the amplifier input.

[0059] Please refer to Figures 2A to 2F In the first scenario, please refer to Figure 2C When the row selection signal Read 1 is in a high logic state, the transistors M1 and M4 corresponding to the pixels 221 in the first row are turned on. Therefore, the data voltage V Data is transmitted to the node N1 located on the data line 235, and is transmitted to the output node N3 located on the companion line 236. Meanwhile, the pixels 221 in other rows are not coupled to the data line 235 and the companion line 236. Since there are no other pixels between the amplifier 251 and the pixel 221, the current I amp Through the resistor R data1 flows into the amplifier 251. In addition, the current I cs Through the resistor R data3 Flows into the current source 252. As described in the previous embodiment, the current I flowing into the amplifier 251 amp is much smaller than the current I flowing into the current source 252 cs , and the current I amp The voltage drop caused by this can be ignored. If the output data voltage V Data The waveform is as Figure 2F As shown in position ① in FIG. 1 , the voltage waveform at the input end of the amplifier 251 is as follows: Figure 2F Therefore, the output data voltage V Data can be transmitted to amplifier 251 without severe voltage drop.

[0060] In the second scenario, please refer to Figure 2D When the row selection signal Read n (n is a positive integer greater than 1 and less than Y) is in a high logic state, the transistors M1 and M4 corresponding to the pixels 221 in the nth row are turned on. Therefore, the data voltage V Data is transmitted to the node N1 on the data line 235 and to the node N3 on the companion line 236. Meanwhile, the pixels 221 in other rows are not coupled to the data line 235 and the companion line 236. Because there are (n-1) pixels between the amplifier 251 and the pixel 221 in the nth row, the current I amp Through (n-1) resistors R data2 and resistor R data1 flows into the amplifier 251. In addition, the current I cs Through (n-1) resistors R data2 and a resistor R data3 flows into the current source 252. It should be noted that, because the current I flowing into the amplifier 151amp is very small, so the current I amp The voltage drop caused by this can be ignored. If the output data voltage V Data The waveform is as Figure 2F As shown in position ① in FIG. 1 , the voltage waveform at the input end of the amplifier 251 is as follows: Figure 2F Therefore, the output data voltage V of pixel 221 is Data can be transmitted to amplifier 251 without severe voltage drop.

[0061] In the third scenario, please refer to Figure 2E When the row selection signal Read Y is in a high logic state, the transistors M1 and M4 of the pixel 221 located in the Yth row (ie, the last row) are turned on. Therefore, the data voltage V Data is transmitted to the node N1 on the data line 235 and to the node N3 on the companion line 236. Meanwhile, the pixels 221 in other rows are not coupled to the data line 235 and the companion line 236. Because there are (Y-1) pixels between the amplifier 251 and the pixel 221 in the Yth row, the current I amp Through (Y-1) resistors R data2 and resistor R data1 Flows into the amplifier 251. In addition, the current I from the pixel 221 cs Through (Y-1) resistors R data2 and resistor R data3 flows into the current source 252. It should be noted that, because the current I flowing into the amplifier 151 amp is very small, so the current I amp The voltage drop caused by this can be ignored. If the output data voltage V Data The waveform is as Figure 2F As shown in position ① in FIG. 1 , the voltage waveform at the input end of the amplifier 251 is as follows: Figure 2F Therefore, the output data voltage V Data can be transmitted to amplifier 251 without severe voltage drop.

[0062] Figure 2G to Figure 2J Schematic diagram of a portion of an electronic device according to different embodiments of the present disclosure.

[0063] exist Figure 2GIn the embodiment, the amplifier 251 coupled to the data line 235 and the current source 252 coupled to the companion line 236 are arranged in separate areas (e.g., in opposite edge areas 270 and 280 of the substrate 210). For example, the amplifier 251 coupled to the left data line 235 and the right data line 235 is disposed in the top edge area 270 of the substrate 210, and the current source 252 coupled to the left companion line 236 and the right companion line 236 is disposed in the bottom edge area 280 of the substrate 210.

[0064] exist Figure 2H , the amplifier 251 coupled to the data line 235 and the current source 252 coupled to the companion line 236 are arranged in the same edge region 270 of the substrate 210. For example, the amplifier 251 coupled to the left data line 235 and the right data line 235 are disposed in the upper edge region 270 of the substrate 210, and the current source 252 coupled to the left companion line 236 and the right companion line 236 are also disposed in the upper edge region 270 of the substrate 210. Alternatively, in some embodiments, the amplifier 251 coupled to the data line 235 and the current source 252 coupled to the companion line 236 are disposed in the bottom edge region (not shown) of the substrate 210.

[0065] exist Fig.2I , the amplifier 251 coupled to one data line 235 and the current source 252 coupled to one companion line 236 may be arranged separately (e.g., in opposite edge regions 270 and 280 of the substrate 210). However, the amplifier 251 coupled to the adjacent data line 235 and the current source 252 coupled to the adjacent companion line 236 may have different arrangements. For example, for the left data line 235 and the left companion line 236, the amplifier 251 is disposed in the top edge region 270 of the substrate 210, and the current source 252 is disposed in the bottom edge region 280 of the substrate 210. For the right data line 235 and the right companion line 236, the amplifier 251 is disposed in the bottom edge region 280 of the substrate 210, and the current source 252 is disposed in the top edge region 270 of the substrate 210.

[0066] exist Figure 2J , an amplifier 251 coupled to one data line 235 and a current source 252 coupled to a companion line 236 are arranged in the same edge region 270 of the substrate 210. However, the amplifier 251 coupled to an adjacent data line 235 and the current source 252 coupled to an adjacent companion line 236 may have a different arrangement. For example, for the left data line 235 and the left companion line 236, the amplifier 251 and the current source 252 are arranged in the top edge region 270 of the substrate 210. For the right data line 235 and the right companion line 236, the amplifier 251 and the current source 252 are arranged in the bottom edge region 280 of the substrate 210.

[0067] In summary, some embodiments of the present disclosure provide an electronic device that can significantly reduce IR drop by bifurcating the path from the pixel to the amplifier and the path from the pixel to the current source. Therefore, very little current flows to the input terminal of the amplifier, so the output data voltage of the pixel can be transmitted to the amplifier without severe IR drop.

[0068] Although the present disclosure has been described by way of examples and embodiments, it should be understood that those skilled in the art may make various combinations, changes, substitutions and alterations to the present disclosure without departing from the spirit and scope of the present disclosure. In addition, the scope of the present disclosure is not limited to the processes, machines, manufactures, compositions, devices, methods and steps in the specific embodiments described in the specification. Those skilled in the art will appreciate that existing or developing processes, machines, manufactures, compositions, devices, methods and steps may be performed in the aforementioned embodiments as long as they can obtain substantially the same results based on some embodiments of the present disclosure. Therefore, the scope of the present disclosure includes the aforementioned processes, machines, manufactures, compositions, devices, methods and steps. In addition, each of the attached claims constitutes a separate embodiment, and the scope of the present disclosure also includes each combination of the attached claims and embodiments.

Claims

1. An electronic device, characterized in that: The electronic device comprises: a substrate; A plurality of pixels are disposed on the substrate; A plurality of data lines are disposed on the substrate; and an amplifier and a current source, coupled to one of the plurality of data lines, wherein at least a portion of the data line forms a conduction path; wherein one of the plurality of pixels is coupled to the data line at a first node, the first node is located on the conduction path, and a first current flowing from the first node to the amplifier is different from a second current flowing from the first node to the current source; The ratio of the first current to the second current is equal to or less than 0.0015%.

2. The electronic device according to claim 1, wherein: At least a portion of the data line is between the amplifier and the current source.

3. The electronic device according to claim 1, wherein: The substrate includes a first edge region and a second edge region opposite to each other, and the amplifier and the current source are arranged in at least one of the first edge region and the second edge region.

4. The electronic device as claimed in claim 3, characterized in that: The amplifier and the current source are arranged in different edge areas.

5. The electronic device according to claim 1, wherein: The electronic device further includes another one of the plurality of data lines, another current source and another amplifier. The other current source and the other amplifier are coupled to the other data line.

6. The electronic device as claimed in claim 5, characterized in that: The arrangement of the other current source and the other amplifier is different from that of the current source and the amplifier.

7. The electronic device as claimed in claim 1, characterized in that: The data line has a U shape.

8. The electronic device as claimed in claim 1, wherein: The pixel includes a plurality of transistors and a photodiode.

9. The electronic device as claimed in claim 1, wherein: The electronic device further comprises: A plurality of readout lines are disposed on the substrate; and A row selection transistor is coupled between the pixel and the data line, wherein a row selection signal is transmitted through one of the plurality of data lines, and the row selection transistor is controlled by the row selection signal.

10. An electronic device, characterized in that: The electronic device comprises: a substrate; A plurality of pixels are disposed on the substrate; A plurality of data lines are arranged on the substrate; A plurality of accompanying lines are disposed on the substrate; an amplifier coupled to one of the plurality of data lines; and a current source coupled to one of the plurality of companion lines, wherein one of the plurality of pixels is coupled to the data line via a first node and coupled to the companion line via the first node and a second node, and a first current flowing from the first node to the amplifier is different from a second current flowing from the first node to the current source; The ratio of the first current to the second current is equal to or less than 0.0015%.

11. The electronic device according to claim 10, wherein: A portion of the data line between the amplifier and the first node, a connection path between the first node and the second node, and a portion of the companion line between the current source and the second node form a conductive path, and the first node is located on the conductive path.

12. The electronic device according to claim 10, wherein: The electronic device further comprises: a row selection transistor coupled between the pixel and the data line, wherein the row selection transistor is controlled by a row selection signal; and A switch transistor is coupled to the row selection transistor at the first node, wherein the switch transistor is controlled by the row selection signal.

13. The electronic device according to claim 12, wherein: The electronic device further comprises: A plurality of readout lines are disposed on the substrate, wherein the row selection signal is transmitted by one of the plurality of readout lines.

14. The electronic device according to claim 10, wherein: The electronic device further comprises: a row of selection transistors coupled between the pixel and the data line; and A switch transistor is coupled to the row selection transistor at the first node, wherein the row selection transistor and the switch transistor are controlled by two different signals.

15. The electronic device according to claim 10, wherein: The pixel includes a plurality of transistors and a photodiode.

16. The electronic device as claimed in claim 10, characterized in that: The electronic device further includes: another one of the plurality of data lines, another one of the plurality of companion lines, another current source and another amplifier, wherein the another amplifier is coupled to the another data line, and the another current source is coupled to the another companion line.

17. The electronic device as claimed in claim 10, characterized in that: The substrate includes a first edge region and a second edge region opposite to each other, and the amplifier and the current source are arranged in at least one of the first edge region and the second edge region.

18. The electronic device as claimed in claim 17, wherein: The amplifier and the current source are arranged in different edge areas.

Images