Column analog-to-digital converter and its local counting method

Abstract

The present disclosure provides a column analog-to-digital converter and a local counting method. The column analog-to-digital converter includes a plurality of analog-to-digital converters connected in parallel. Each of the analog-to-digital converters includes a comparator and a counting circuit. The comparator compares a ramp voltage with one of a plurality of column signals to generate a comparator output signal. The counting circuit generates a local clock according to a base clock and a comparator output signal through a voltage-controlled oscillator of the counting circuit, counts the base clock and the local clock respectively to generate a first counting output and a second counting output, and combines the first counting output with the second counting output to generate a counting output.

Description

Technical Field

[0001] The present invention relates to an image sensor, and more particularly, to a column analog-to-digital converter (column ADC) and a local counting method thereof. Background Art

[0002] Conventional CMOS image sensors (CIS) generally use column analog-to-digital converters (CADC). CADC is usually composed of multiple successive-approximation register analog-to-digital converters (SAR ADC) or multiple single-slope analog-to-digital converters (single-slope ADC). Each single-slope ADC receives a column signal corresponding to a pixel column, and multiple single-slope ADCs share a digital-to-analog converter (DAC), a high-speed clock generator, and a readout amplifier.

[0003] Single slope ADC uses a counter to count the output length of the signal generated by comparing the ramp voltage with the column signal as the output of the ADC. Therefore, the resolution of the ADC depends on the available counting time and the counting frequency. However, the counting frequency is usually limited by the load of the clock tree, which increases the counting time of the ADC at high resolution. In addition, due to the high counting frequency, the CADC counter faces a serious challenge of power consumption.

[0004] Since Correlated Double Sampling (CDS) and High Dynamic Range Imaging (HDR) are widely used in applications such as touch, image sensing, and fingerprint recognition, the available counting time is reduced. In addition, the frame rate is limited by the conversion time of the ADC.

[0005] Prior art uses phase delay to increase the resolution of the ADC without increasing the counting frequency. For example, 3 phase delays are added to the least significant bit (LSB) of a high-speed clock. That is, the half cycle of bit [0] is cut into four equal parts to increase the resolution of the ADC by 2 bits. However, the phase delay of the LSB is usually generated by a delay-locked loop (DLL) or a phase-locked loop (PLL), which will increase the layout area and power consumption. In addition, different phase delays require path balancing in the layout to avoid increasing the differential nonlinearity (DNL) of the ADC, but it will increase the difficulty of layout design.

[0006] Another prior art uses a local delay line to generate multiple phases in LSB, and a logic circuit determines in which phase the transition time of the input signal is located, so as to output a corresponding binary code according to the determination result. However, it requires an additional correction circuit to eliminate the PVT variation characteristics. Summary of the invention

[0007] The present invention provides a column analog-to-digital converter (CADC) having a local counting method capable of performing local counting according to a comparator output signal so as to improve counting resolution and perform self-compensation without a correction circuit.

[0008] An embodiment of the present invention provides a column analog-to-digital converter. The column analog-to-digital converter includes a plurality of analog-to-digital converters connected in parallel. Each of the analog-to-digital converters receives a ramp voltage, one of a plurality of column signals, and a base clock to generate a count output. Each of the analog-to-digital converters includes a comparator and a counting circuit. The comparator is configured to compare the ramp voltage with one of a plurality of column signals to generate a comparator output signal. The counting circuit is configured to generate a local clock according to the base clock and the comparator output signal through a voltage-controlled oscillator (VCO) of the counting circuit, count the base clock and the local clock respectively to generate a first count output and a second count output, and combine the first count output with the second count output to generate a count output.

[0009] An embodiment of the present invention provides a local counting method. A column analog-to-digital converter includes a plurality of analog-to-digital converters connected in parallel. The local counting method of each analog-to-digital converter includes the following. Each analog-to-digital converter compares a ramp voltage with one of the column signals to generate a comparator output signal. A voltage-controlled oscillator of each analog-to-digital converter generates a local clock according to a base clock and a comparator output signal. Each analog-to-digital converter counts the base clock and the local clock respectively to generate a first count output and a second count output. Each analog-to-digital converter combines the first count output with the second count output to generate a count output.

[0010] According to the above, in an embodiment of the present invention, in order to cope with the frequency limitations caused by timing violations and longer wires and reduce system complexity, an embodiment of the present invention provides a column analog-to-digital converter (CADC) with a local counting method, which is capable of performing local counting based on a comparator output signal so as to improve the counting resolution and perform self-compensation without a correction circuit.

[0011] In order to make the above features and advantages of the present invention more easily understood, embodiments accompanied by drawings are described in detail as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and together with the description serve to explain the principles of the invention.

[0013] Figure 1 is a schematic diagram showing a column analog-to-digital converter according to an embodiment of the present invention.

[0014] Figure 2 is a circuit block diagram showing a counting circuit according to an embodiment of the present invention.

[0015] Figure 3 is a circuit block diagram showing a voltage controlled oscillator according to an embodiment of the present invention.

[0016] Figure 4A is a timing diagram illustrating local counting according to an embodiment of the present invention.

[0017] Figure 4B is a timing diagram illustrating local counting according to an embodiment of the present invention.

[0018] Figure 5A is a timing diagram illustrating local counting according to another embodiment of the present invention.

[0019] Figure 5B is a timing diagram illustrating local counting according to another embodiment of the present invention.

[0020] Figure 6is a timing diagram illustrating local counting according to another embodiment of the present invention.

[0021] FIG. 7A to FIG. 7D is a timing diagram illustrating local counting according to another embodiment of the present invention.

[0022] Figure 8 is a timing diagram illustrating local counting according to another embodiment of the present invention.

[0023] Fig. 9 is a timing diagram illustrating local counting according to another embodiment of the present invention.

[0024] Fig.10 is a flow chart illustrating a local counting method according to an embodiment of the present invention.

[0025] Description of Figure Numbers

[0026] 00, 01, 10, 11: logic;

[0027] 100: column analog-to-digital converter;

[0028] 110_1, 110_2, 110_3, 110_N: analog-to-digital converter;

[0029] 120: digital-to-analog converter;

[0030] 130: readout amplifier;

[0031] 140_1: Comparator;

[0032] 150_1: counting circuit;

[0033] 160_1: voltage controlled oscillator;

[0034] 210: main counting circuit;

[0035] 220: local counting circuit;

[0036] 230: edge detector;

[0037] 240: counter;

[0038] 310: Ring oscillator;

[0039] 320: frequency divider;

[0040] 330: trigger;

[0041] 340: Multiplexer;

[0042] 1010, S1020: step;

[0043] CLKB: base clock;

[0044] CLKL1, CLKL2, CLKL3, CLKLN: local clock;

[0045] CLKL1_D: divided local clock;

[0046] CLKL1_I: initial local clock;

[0047] CMP1, CMP2, CMP3, CMPN: comparator output signals;

[0048] CNTEN: counting enable signal;

[0049] CO1, CO2, CO3, CON: counting output;

[0050] CO1A, CO2A, CO3A, CONA: first counting output;

[0051] CO1B, CO2B, CO3B, CONB: second counting output;

[0052] CS1, CS2, CS3, CSN: column signals;

[0053] DCEN: Duty cycle enable signal;

[0054] DOUT: output;

[0055] f1: first frequency;

[0056] f2: second frequency;

[0057] f3: third frequency;

[0058] T1: first cycle;

[0059] T2: second cycle;

[0060] T21, T22, T23: second cycle;

[0061] T31, T32, T33: the third cycle;

[0062] TCMP1: duration;

[0063] V1: initial value;

[0064] VF: final value;

[0065] VI: initial value;

[0066] VLC: local count value;

[0067] VM: median value;

[0068] VM1: first median value;

[0069] VM2: second median value;

[0070] VRAMP: ramp voltage. DETAILED DESCRIPTION

[0071] Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the specification to refer to the same or similar parts.

[0072] refer to Figure 1 , the column analog-to-digital converter 100 includes a plurality of analog-to-digital converters 110_1 to 110_N connected in parallel, a digital-to-analog converter 120, and a readout amplifier 130. The digital-to-analog converter 120 generates a ramp voltage VRAMP. The analog-to-digital converters 110_1 to 110_N receive the ramp voltage VRAMP, the column signals CS1 to CSN, and the base clock CLKB to generate count outputs CO1 to CON. The column signals CS1 to CSN are provided by corresponding pixel columns of an image sensor (such as a CMOS image sensor). The base clock CLKB may come from a conventional VCO, PLL, or DLL. The readout amplifier 130 receives and reads the count outputs C01 to CON (data) to generate an output DOUT (logic), and the output DOUT may be provided to a bit line of a memory. The implementation of the digital-to-analog converter 120 and the readout amplifier 130 is not limited in a particular manner.

[0073] Given the analog-to-digital converter 110_1 as an example, the analog-to-digital converter 110_1 includes a comparator 140_1 and a counting circuit 150_1, and the counting circuit 150_1 includes a built-in voltage-controlled oscillator (VCO) 160_1. The comparator 140_1 compares the ramp voltage VRAMP with the column signal CS1 to generate a comparator output signal CMP1. Thereafter, the counting circuit 150_1 generates a local clock CLKL1 according to the base clock CLKB and the comparator output signal CMP1 through the voltage-controlled oscillator 160_1, counts the base clock CLKB to generate a first counting output CO1A, counts the local clock CLKL1 to generate a second counting output CO1B, and combines the first counting output CO1A with the second counting output CO1B to generate a counting output CO1. The implementation of the comparator 140_1 is not limited.

[0074] In addition, since the analog-to-digital converters 110_2 to 110_N are repeated in columns and are similar to the analog-to-digital converter 110_1, the details of the corresponding comparator output signals CMP2 to CMPN, the local clocks CLKL2 to CLKLN, the first counting outputs CO2A to CONA, and the second counting outputs CO2B to CONB are not repeated.

[0075] Figure 2 According to an embodiment of the present invention Figure 1 The circuit blocks of the counting circuit 150_1 are shown in FIG. Figure 2 In the embodiment of the present invention, the counting circuit 150_1 includes a main counting circuit 210 and a local counting circuit 220. The main counting circuit 210 counts the base clock CLKB to generate a first counting output CO1A before both the base clock CLKB and the comparator output signal CMP1 are enabled. The local counting circuit 220 counts the local clock CLKL1 to generate a second counting output CO1B after both the base clock CLKB and the comparator output signal CMP1 are enabled. The relevant timing will be described later. Due to the addition of the local counting circuit 220, this architecture effectively improves the resolution of CADC. For example, if the first counting output CO1A provided by the main counting circuit 210 is 10 bits and the second counting output CO1B provided by the local counting circuit 220 is 1 bit, then the resolution of CADC will be improved to 11 bits. If the first counting output CO1A provided by the main counting circuit 210 is 10 bits and the second counting output CO1B provided by the local counting circuit 220 is 2 bits, then the resolution of CADC will be improved to 12 bits.

[0076] The local counting circuit 220 includes an edge detector 230, a voltage-controlled oscillator 160_1, and a counter 240. The edge detector 230 detects the transition of the base clock CLKB and the comparator output signal COMP1 to generate a duty cycle enable signal DCEN and a count enable signal CNTEN. Specifically, the edge detector 230 may generate the duty cycle enable signal DCEN and the count enable signal CNTEN according to the rising edge or falling edge of the base clock CLKB and the comparator output signal COMP1 depending on the design requirements. When the voltage-controlled oscillator 160_1 is enabled according to the duty cycle enable signal DCEN and the count enable signal CNTEN, the voltage-controlled oscillator 160_1 generates the local clock CLKL1. When the counter 240 is enabled according to the count enable signal CNTEN, the counter 240 counts the local clock CLKL to generate a second count output CO1B.

[0077] Figure 3 According to an embodiment of the present invention Figure 1 and Figure 2 The circuit blocks of the voltage controlled oscillator 160_1 are shown in FIG. Figure 3 , the voltage controlled oscillator 160_1 includes a ring oscillator 310 and a frequency divider 320. The ring oscillator 310 includes a plurality of inverters, and generates an initial local clock CLKL1_I according to the number of inverters and a delay time. The frequency divider 320 includes a flip-flop 330 and a multiplexer 340. The flip-flop 330 divides the initial local clock CLKL1_I to generate a divided local clock CLKL1_D, and the multiplexer 340 selects the initial local clock CLKL1_I or the divided local clock CLKL1_D as the local clock CLKL1 according to the count enable signal CNTEN. In detail, the number of stages of the flip-flop 330 of the frequency divider 320 is not limited, so that the frequency of the initial local clock CLKL1_I can be divided by 2 N It should be noted that since the local counting circuit 220 is a digital circuit, scaling is advantageous in the logic processing.

[0078] Figure 4A and Figure 4B is a timing diagram showing local counting according to an embodiment of the present invention. Figure 4A and Figure 4B When the counter 240 is enabled according to the counting enable signal CNTEN, the step of the counter 240 counting the local clock CLKL1 to generate the second counting output CO1B may include the following.

[0079] During the first cycle T1 of the base clock CLKB and when the base clock CLKB and the comparator output signal CMP1 are both enabled, the voltage controlled oscillator 160_1 provides the local clock CLKL1 having the first frequency f1 to the counter 240. The first frequency f1 is as follows: Figure 4A and Figure 4B The counter 240 receives the local clock CLKL1 having the first frequency f1 and counts the local clock CLKL1 to generate a local count value VLC, and sequentially increases the local count value VLC from an initial value VI corresponding to the counted local clock CLKL1 having the first frequency f1 until the base clock CLKB is disabled, to generate an intermediate value VM of the local count value VLC.

[0080] During the second cycle T2 of the base clock CLKB, and when the base clock CLKB and the comparator output signal CMP1 are both enabled, the voltage controlled oscillator 160_1 provides the local clock CLKL1 having the second frequency f2 to the counter 240. The second frequency f2 is as follows: Figure 4A and Figure 4B0.5×local frequency shown in . The counter 240 receives the local clock CLKL1 having the second frequency f2 and counts the local clock CLKL1, and sequentially decreases the local count value VLC from the intermediate value VM corresponding to the counted local clock CLKL1 having the second frequency f2 until the base clock CLKB is disabled, to generate a final value VF of the local count value VLC. In this embodiment, the first frequency f1 is twice as large as the second frequency f2.

[0081] Subsequently, the counter 240 compares the final value VF of the local count value VLC with the initial value VI of the local count value VLC to generate a second count output CO1B. Figure 4A As shown in FIG. 1 , when the final value VF is greater than the initial value VI, the second counting output CO1B will be logic 0. Figure 4B As shown in FIG. 1 , when the final value VF is less than the initial value VI, the second count output CO1B will be logic 1. In some embodiments, when the final value VF is greater than the initial value VI, the second count output CO1B will be logic 1. And when the final value VF is less than the initial value VI, the second count output CO1B will be logic 0. The present invention does not limit the corresponding relationship between the logic value and the comparison result.

[0082] In this way, it is necessary to determine whether the timing of enabling the comparator output signal CMP1 is before or after half of the duty cycle of the first period T1. Figure 4A As shown in FIG. 1 , the timing of enabling the comparator output signal CMP1 is before half of the duty cycle of the first cycle T1 , and as shown in FIG. Figure 4B As shown, the timing of enabling the comparator output signal CMP1 is after half of the duty cycle of the first period T1. In other words, in this embodiment, the resolution of CADC is increased by one bit.

[0083] It should be noted that in this embodiment, Figure 4A and Figure 4B As shown in FIG. 1 , the base clock CLKB is enabled at a positive duty cycle, but in another embodiment, as shown in FIG. Figure 5A and Figure 5B As shown in FIG. 8 , the base clock CLKB can be enabled in a negative duty cycle.

[0084] Figure 6 is a timing diagram showing a local count with positive counts and negative counts in one cycle according to another embodiment of the present invention. Figure 6 When the counter 240 is enabled according to the counting enable signal CNTEN, the step of the counter 240 counting the local clock CLKL1 to generate the second counting output CO1B may include the following.

[0085] During the first cycle T1 of the base clock CLKB and when the base clock CLKB and the comparator output signal CMP1 are both enabled, the voltage controlled oscillator 160_1 provides the local clock CLKL1 having the first frequency f1 to the counter 240. The first frequency f1 is as follows: Figure 6 The counter 240 receives the local clock CLKL1 having the first frequency f1 and counts the local clock CLKL1 to generate a local count value VLC, and sequentially increases the local count value VLC from an initial value VI corresponding to the counted local clock CLKL1 having the first frequency f1 until the base clock CLKB is disabled, to generate an intermediate value VM of the local count value VLC.

[0086] When the base clock CLKB is disabled, the voltage controlled oscillator 160_1 immediately provides the local clock CLK1 having the second frequency f2 to the counter 240. The second frequency f2 is as follows: Figure 6 0.5×local frequency shown in . The counter 240 receives the local clock CLKL1 having the second frequency f2 and counts the local clock CLKL1, and sequentially decreases the local count value VLC from the intermediate value VM corresponding to the counted local clock CLKL1 having the second frequency f2 until the first cycle T1 of the base clock CLKB ends to generate a final value VF of the local count value VLC. In this embodiment, the first frequency f1 is twice as large as the second frequency f2.

[0087] Subsequently, the counter 240 compares the final value VF of the local count value VLC with the initial value VI of the local count value VLC to generate a second count output CO1B. Figure 6 As shown in FIG. 1 , when the final value VF is less than the initial value VI, the second count output CO1B will be a logic 1. And when the final value VF is greater than the initial value VI (not shown), the second count output CO1B will be a logic 0. It is worth noting that Figure 4A and Figure 4B Compared with the embodiment, Figure 6 This embodiment is suitable for low frequency applications.

[0088] FIG. 7A to FIG. 7D FIG. 4 is a timing diagram showing a local count with an additional 2-bit resolution according to another embodiment of the present invention. Fig. 7A When the counter 240 is enabled according to the counting enable signal CNTEN, the step of the counter 240 counting the local clock CLKL1 to generate the second counting output CO1B may include the following.

[0089] During the first cycle T1 of the base clock CLKB and when the base clock CLKB and the comparator output signal CMP1 are both enabled, the voltage controlled oscillator 160_1 provides the local clock CLKL1 having the first frequency f1 to the counter 240. The first frequency f1 is as follows: Fig. 7A The counter 240 receives the local clock CLKL1 having the first frequency f1 and counts the local clock CLKL1 to generate a local count value VLC, and sequentially increases the local count value VLC from an initial value VI corresponding to the counted local clock CLKL1 having the first frequency f1 until the base clock CLKB is disabled, to generate an intermediate value VM of the local count value VLC.

[0090] During the second cycle T21, the second cycle T22 and the second cycle T23 after the first cycle T1 of the base clock CLKB, and when the base clock CLKB and the comparator output signal CMP1 are both enabled, the voltage controlled oscillator 160_1 provides the local clock CLKL1 having the third frequency f3 to the counter 240. The third frequency f3 is as shown in FIG. Fig. 7A The counter 240 receives the local clock CLKL1 having the third frequency f3 and counts the local clock CLKL1, and sequentially decreases the local count value VLC from the intermediate value VM corresponding to the counted local clock CLKL1 having the third frequency f3 until the second cycle T23 ends. In this embodiment, the first frequency f1 is four times greater than the third frequency f3.

[0091] Then, when the local count value VLC is just less than or equal to the initial value VI as the second count output CO1B, the counter 240 adopts the logic value. For example, in this embodiment, when the local count value VLC is equal to or less than the initial value VI as the second count output CO1B, the counter 240 adopts the logic value. Figure 7B When the local count value VLC is less than the initial value V1 in the second period T23 corresponding to the logic 01 shown in FIG. Figure 7C When the local count value VLC is less than the initial value V1 in the second period T22 corresponding to the logic 10 shown in FIG. 1 , the second count output CO1B will be logic 10. Fig.7D When the local count value VLC is just less than the initial value VI within the second cycle T21 corresponding to the logic 11 shown in FIG. 1 , the second count output CO1B will be logic 11. As mentioned, since the logic value must be determined as logic 00 because logic 01, logic 10, and logic 11 have not yet been adopted, the cycle corresponding to logic 00 can be omitted while the local count value VLC is still greater than the initial value VI until the end of the second cycle T23, as shown in FIG. Fig. 7AThe present invention does not limit the corresponding relationship between the logic value and the second period T21, the second period T22 and the second period T23.

[0092] In this way, the timing of enabling the comparator output signal CMP1 will inevitably be determined. It should be noted that the duty cycle of the first cycle T1 is divided into four parts corresponding to logic 00, logic 01, logic 10 and logic 11 respectively. In this embodiment, the timing of enabling the comparator output signal CMP1 in the first part of the duty cycle of the first cycle T1 is Fig. 7A The timing of enabling the comparator output signal CMP1 in the second portion of the duty cycle of the first period T1 corresponds to the logic 00 shown in FIG. Figure 7B The timing of enabling the comparator output signal CMP1 in the third portion of the duty cycle of the first period T1 corresponds to the logic 01 shown in FIG. Figure 7C The timing of enabling the comparator output signal CMP1 in the fourth portion of the duty cycle of the first period T1 is consistent with the timing of enabling the comparator output signal CMP1 in the fourth portion of the duty cycle of the first period T1. Fig.7D In other words, in this embodiment, the resolution of CADC is increased by two bits.

[0093] Figure 8 FIG. 4 is a timing diagram showing a local count with an additional 2-bit resolution according to another embodiment of the present invention. Figure 8 When the counter 240 is enabled according to the counting enable signal CNTEN, the step of the counter 240 counting the local clock CLKL1 to generate the second counting output CO1B may include the following.

[0094] During the first cycle T1 of the base clock CLKB and when the base clock CLKB and the comparator output signal CMP1 are both enabled, the voltage controlled oscillator 160_1 provides the local clock CLKL1 having the first frequency f1 to the counter 240. The first frequency f1 is as shown in Figure 8 The counter 240 receives the local clock CLKL1 having the first frequency f1 and counts the local clock CLKL1 to generate a local count value VLC, and sequentially increases the local count value VLC from an initial value VI corresponding to the counted local clock CLKL1 having the first frequency f1 until the base clock CLKB is disabled, to generate an intermediate value VM of the local count value VLC.

[0095] Subsequently, the counter 240 supplements the intermediate value VM of the local count value VLC before the second cycle T21 , the second cycle T22 , and the second cycle T23 of the base clock CLKB to obtain a one's complement of the intermediate value VM of the local count value VLC.

[0096] During the second cycle T21, the second cycle T22 and the second cycle T23 after the first cycle T1 of the base clock CLKB, and when the base clock CLKB and the comparator output signal CMP1 are both enabled, the voltage controlled oscillator 160_1 provides the local clock CLKL1 having the third frequency f3 to the counter 240. The third frequency f3 is as shown in FIG. Figure 8 The counter 240 receives the local clock CLKL1 having the third frequency f3 and counts the local clock CLKL1, and sequentially increases the local count value VLC from the intermediate value VM corresponding to the counted local clock CLKL1 having the third frequency f3 until the second period T23 ends. In this embodiment, the first frequency f1 is four times greater than the third frequency f3.

[0097] Then, when the local count value VLC is just greater than or equal to the initial value VI as the second count output CO1B, the counter 240 adopts the logic value. FIG. 7A to FIG. 7D Similarly, the relationship between the logic value and the second period T21, the second period T22 and the second period T23 is not repeated. Therefore, in this embodiment, the resolution of CADC is increased by two bits in the same counting direction.

[0098] Fig. 9 FIG. 4 is a timing diagram showing a local count with an additional 2-bit resolution according to another embodiment of the present invention. Fig. 9 When the counter 240 is enabled according to the counting enable signal CNTEN, the step of the counter 240 counting the local clock CLKL1 to generate the second counting output CO1B may include the following.

[0099] During the first cycle T1 of the base clock CLKB and when the base clock CLKB and the comparator output signal CMP1 are both enabled, the voltage controlled oscillator 160_1 provides the local clock CLKL1 having the first frequency f1 to the counter 240. The first frequency f1 is as shown in Fig. 9 The counter 240 receives the local clock CLKL1 having the first frequency f1 and counts the local clock CLKL1 to generate a local count value VLC, and sequentially increases the local count value VLC from an initial value VI corresponding to the counted local clock CLKL1 having the first frequency f1 until the base clock CLKB is disabled, to generate a first intermediate value VM1 of the local count value VLC.

[0100] During the second cycle T21, the second cycle T22 and the second cycle T23 after the first cycle T1 of the base clock CLKB, and when the base clock CLKB and the comparator output signal CMP1 are both enabled, the voltage controlled oscillator 160_1 provides the local clock CLKL1 having the third frequency f3 to the counter 240. The third frequency f3 is as shown in FIG. Fig. 9 The counter 240 receives the local clock CLKL1 having the third frequency f3 and counts the local clock CLKL1, and sequentially decreases the local count value VLC from the second intermediate value VM2 corresponding to the counted local clock CLKL1 having the third frequency f3 until the second period T23 ends. In this embodiment, the first frequency f1 is four times greater than the third frequency f3.

[0101] During the third periods T31, T32 and T33 after the second periods T21, T22 and T23 of the base clock CLKB, and when both the base clock CLKB and the comparator output signal CMP1 are enabled, the voltage controlled oscillator 160_1 provides the local clock CLKL1 having the third frequency f3 to the counter 240. The third frequency f3 is as shown in FIG. Fig. 9 The counter 240 receives and counts the local clock CLKL1 having the third frequency f3, and sequentially increases the local count value VLC from the second intermediate value VM2 corresponding to the counted local clock CLKL1 having the third frequency f3 until the third period T33 ends.

[0102] Then, when the local count value VLC is just greater than or equal to the initial value VI as the second count output CO1B, the counter 240 adopts the logic value. FIG. 7A to FIG. 7D Similarly, the relationship between the logic value and the second period T31, the second period T32 and the second period T33 is not repeated. Therefore, in this embodiment, the resolution of CADC is increased by two bits by multi-sampling, thereby reducing the quantization error.

[0103] Fig.10A flow chart of a local counting method according to one of the exemplary embodiments of the present disclosure is shown. The column analog-to-digital converter includes a plurality of analog-to-digital converters connected in parallel. The local counting method of each analog-to-digital converter includes the following. In step 1010, each analog-to-digital converter compares a ramp voltage with one of the column signals to generate a comparator output signal. Subsequently, in step S1020, a voltage-controlled oscillator of the analog-to-digital converter generates a local clock based on a base clock and a comparator output signal. The analog-to-digital converter counts the base clock and the local clock respectively to generate a first count output and a second count output. The analog-to-digital converter combines the first count output with the second count output to generate a count output.

[0104] According to the above, in an embodiment of the present invention, in order to cope with the frequency limitations caused by timing violations and longer wires and reduce system complexity, an embodiment of the present invention provides a column analog-to-digital converter (CADC) with a local counting method, which is capable of performing local counting based on a comparator output signal without a correction circuit so as to improve the counting resolution, perform self-compensation, and improve PVT variations.

[0105] It will be apparent to those skilled in the art that various modifications and changes may be made to the structure of the present invention without departing from the scope or spirit of the present invention. In view of the foregoing, it is desired that the present invention covers modifications and changes of the present invention, provided that the modifications and changes are within the scope of the appended claims and their equivalents.

Claims

1. A column analog-to-digital converter, comprising a plurality of analog-to-digital converters connected in parallel, wherein each of the analog-to-digital converters comprises: a comparator configured to compare the ramp voltage with one of the plurality of column signals to generate a comparator output signal; as well as A counting circuit is configured to generate a local clock according to a basic clock and the comparator output signal through a voltage-controlled oscillator of the counting circuit, count the basic clock and the local clock respectively to generate a first counting output and a second counting output, and combine the first counting output and the second counting output to generate a counting output.

2. The column analog-to-digital converter according to claim 1, further comprising: a digital-to-analog converter configured to generate the ramp voltage; as well as A sense amplifier is configured to receive the count output generated by each of the analog-to-digital converters to generate an output.

3. The column analog-to-digital converter according to claim 1, wherein the counting circuit comprises: a main counting circuit configured to count the base clock to generate the first counting output before both the base clock and the comparator output signal are enabled; The local counting circuit is configured to count the local clock to generate the second counting output after the base clock and the comparator output signal are both enabled.

4. The column analog-to-digital converter of claim 3 , wherein the local counting circuit comprises: an edge detector configured to detect transition times of the base clock and the comparator output signal to generate a duty cycle enable signal and a count enable signal; The voltage controlled oscillator is configured to generate the local clock when the voltage controlled oscillator is enabled according to the duty cycle enable signal; as well as The counter is configured to count the local clock to generate the second count output when the counter is enabled according to the count enable signal.

5. The column analog-to-digital converter of claim 4 , wherein the voltage controlled oscillator comprises: a ring oscillator including a plurality of inverters configured to generate an initial local clock according to the number and delay time of the inverters; and The frequency divider includes a trigger and a multiplexer, wherein the trigger divides the initial local clock to generate a divided local clock, and the multiplexer selects the initial local clock or the divided local clock as the local clock according to the counting enable signal.

6. The column analog-to-digital converter according to claim 4 , wherein when the counter is enabled according to the count enable signal, the step of the counter counting the local clock to generate the second count output comprises: During a first cycle of the base clock, and when the base clock and the comparator output signal are both enabled, the voltage controlled oscillator provides the local clock having a first frequency, the counter receives the local clock having the first frequency and counts the local clock, and sequentially increases a local count value from an initial value corresponding to the counted local clock having the first frequency until the base clock is disabled, so as to generate an intermediate value of the local count value; During a second cycle of the base clock and when the base clock and the comparator output signal are both enabled, the voltage controlled oscillator provides the local clock having a second frequency, the counter receives the local clock having the second frequency and counts the local clock, and sequentially decreases the local count value from the intermediate value corresponding to the counted local clock having the second frequency until the base clock is disabled to generate a final value of the local count value, wherein the first frequency is greater than the second frequency; as well as The counter compares the final value of the local count value with the initial value of the local count value to generate the second count output.

7. The column analog-to-digital converter according to claim 4, wherein when the counter is enabled according to the count enable signal, the step of the counter counting the local clock to generate the second count output comprises: During a first cycle of the base clock, and when the base clock and the comparator output signal are both enabled, the voltage controlled oscillator provides the local clock having a first frequency, the counter receives the local clock having the first frequency and counts the local clock, and sequentially increases the local count value from an initial value corresponding to the counted local clock having the first frequency until the base clock is disabled, so as to generate an intermediate value of the local count value; When the base clock is disabled, the voltage-controlled oscillator immediately provides the local clock having a second frequency, the counter receives the local clock having the second frequency and counts the local clock, and sequentially decreases the local count value from the intermediate value corresponding to the counted local clock having the second frequency until the first cycle of the base clock ends to generate a final value of the local count value, wherein the first frequency is greater than the second frequency; as well as The counter compares the final value of the local count value with the initial value of the local count value to generate the second count output.

8. The column analog-to-digital converter according to claim 4 , wherein when the counter is enabled according to the count enable signal, the step of the counter counting the local clock to generate the second count output comprises: During a first cycle of the base clock, and when the base clock and the comparator output signal are both enabled, the voltage controlled oscillator provides the local clock having a first frequency, the counter receives the local clock having the first frequency and counts the local clock, and sequentially increases the local count value from an initial value corresponding to the counted local clock having the first frequency until the base clock is disabled, so as to generate an intermediate value of the local count value; During a plurality of second cycles after the first cycle of the base clock, and when the base clock and the comparator output signal are both enabled, the voltage controlled oscillator provides the local clock having a third frequency, the counter receives the local clock having the third frequency and counts the local clock, and sequentially decreases the local count value from the intermediate value corresponding to the counted local clock having the third frequency until the plurality of second cycles of the base clock are finished, wherein the first frequency is greater than the third frequency; as well as When the local count value is just less than or equal to the initial value as the second count output, the counter adopts a logic value corresponding to one of the plurality of second cycles of the base clock.

9. The column analog-to-digital converter according to claim 4, wherein when the counter is enabled according to the count enable signal, the step of the counter counting the local clock to generate the second count output comprises: During a first cycle of the base clock, and when the base clock and the comparator output signal are both enabled, the voltage controlled oscillator provides the local clock having a first frequency, the counter receives the local clock having the first frequency and counts the local clock, and sequentially increases the local count value from an initial value corresponding to the counted local clock having the first frequency until the base clock is disabled, so as to generate an intermediate value of the local count value; Before a plurality of second cycles of the base clock, taking the complement of the intermediate value of the local count value to obtain a one's complement of the intermediate value of the local count value; During the plurality of second cycles after the first cycle of the base clock, and when the base clock and the comparator output signal are both enabled, the voltage controlled oscillator provides the local clock having a third frequency, the counter receives the local clock having the third frequency and counts the local clock, and sequentially increases the local count value from the one's complement of the intermediate value corresponding to the counted local clock having the third frequency until the plurality of second cycles of the base clock are finished, wherein the first frequency is greater than the third frequency; as well as When the local count value is just greater than or equal to the initial value as the second count output, the counter adopts a logic value corresponding to one of the plurality of second cycles of the base clock.

10. The column analog-to-digital converter according to claim 4, wherein when the counter is enabled according to the count enable signal, the step of the counter counting the local clock to generate the second count output comprises: During a first cycle of the base clock, and when the base clock and the comparator output signal are both enabled, the voltage controlled oscillator provides the local clock having a first frequency, the counter receives the local clock having the first frequency and counts the local clock, and sequentially increases the local count value from an initial value corresponding to the counted local clock having the first frequency until the base clock is disabled, so as to generate a first intermediate value of the local count value; During a plurality of second cycles after the first cycle of the base clock, and when the base clock and the comparator output signal are both enabled, the voltage controlled oscillator provides the local clock having a third frequency, the counter receives the local clock having the third frequency and counts the local clock, and sequentially decreases the local count value from the first intermediate value corresponding to the counted local clock having the third frequency until the plurality of second cycles of the base clock are completed to generate a second intermediate value of the local count value; During a plurality of third cycles after the plurality of second cycles of the base clock, and when the base clock and the comparator output signal are both enabled, the voltage controlled oscillator provides the local clock having the third frequency, the counter receives the local clock having the third frequency and counts the local clock, and sequentially increases the local count value from the second intermediate value corresponding to the counted local clock having the third frequency until the plurality of third cycles of the base clock are finished, wherein the first frequency is greater than the third frequency; as well as When the local count value is just greater than or equal to the initial value as the second count output, the counter adopts a logic value corresponding to one of the plurality of third cycles of the base clock.

11. A local counting method, applicable to a column analog-to-digital converter comprising a plurality of analog-to-digital converters connected in parallel, wherein the local counting method comprises: comparing the ramp voltage with one of the plurality of column signals to generate a comparator output signal; generating a local clock by a voltage controlled oscillator of each analog-to-digital converter according to a base clock and the comparator output signal; Counting the base clock and the local clock respectively to generate a first count output and a second count output; as well as The first count output and the second count output are combined to generate the count output.

12. The local counting method according to claim 11, further comprising: generating the ramp voltage; as well as The count output produced by each of the analog-to-digital converters is received and read to produce an output.

13. The local counting method according to claim 11, further comprising: counting the base clock to generate the first count output before both the base clock and the comparator output signal are enabled; as well as The local clock is counted to generate the second count output after both the base clock and the comparator output signal are enabled.

14. The local counting method according to claim 13, wherein the step of counting the local clock to generate the second count output after both the base clock and the comparator output signal are enabled comprises: Detecting the transition time of the basic clock and the comparator output signal to generate a duty cycle enable signal and a count enable signal; generating the local clock according to the duty cycle enable signal and the count enable signal; as well as When the counter is enabled according to the count enable signal, the local clock is counted to generate the second count output.

15. The local counting method according to claim 14, wherein the step of generating the local clock according to the duty cycle enable signal and the count enable signal comprises: Generate an initial local clock according to the number and delay time of inverters; as well as The initial local clock is divided to generate a divided local clock, and the initial local clock or the divided local clock is selected as the local clock according to the counting enable signal.

16. The local counting method according to claim 11, wherein the step of counting the local clock according to the counting enable signal to generate the second counting output comprises: During a first cycle of the base clock and when the base clock and the comparator output signal are both enabled, providing the local clock having a first frequency, receiving the local clock having the first frequency and counting the local clock, and sequentially increasing the local count value from an initial value corresponding to the counted local clock having the first frequency until the base clock is disabled to generate an intermediate value of the local count value; During a second cycle of the base clock and when the base clock and the comparator output signal are both enabled, providing the local clock having a second frequency, receiving the local clock having the second frequency and counting the local clock, and sequentially decreasing the local count value from the intermediate value corresponding to the counted local clock having the second frequency until the base clock is disabled to generate a final value of the local count value, wherein the first frequency is greater than the second frequency; as well as The final value of the local count value is compared to the initial value of the local count value to generate the second count output.

17. The local counting method according to claim 14, wherein the step of counting the local clock according to the counting enable signal to generate the second counting output comprises: During a first cycle of the base clock and when the base clock and the comparator output signal are both enabled, providing the local clock having a first frequency, receiving the local clock having the first frequency and counting the local clock, and sequentially increasing the local count value from an initial value corresponding to the counted local clock having the first frequency until the base clock is disabled to generate an intermediate value of the local count value; When the base clock is disabled, immediately providing the local clock having a second frequency, receiving the local clock having the second frequency and counting the local clock, and sequentially decreasing the local count value from the intermediate value corresponding to the counted local clock having the second frequency until the first cycle of the base clock ends to generate a final value of the local count value, wherein the first frequency is greater than the second frequency; as well as The final value of the local count value is compared to the initial value of the local count value to generate the second count output.

18. The local counting method according to claim 14, wherein the step of counting the local clock according to the counting enable signal to generate the second counting output comprises: During a first cycle of the base clock and when the base clock and the comparator output signal are both enabled, providing the local clock having a first frequency, receiving the local clock having the first frequency and counting the local clock, and sequentially increasing the local count value from an initial value corresponding to the counted local clock having the first frequency until the base clock is disabled to generate an intermediate value of the local count value; During a plurality of second cycles after the first cycle of the base clock, and when the base clock and the comparator output signal are both enabled, providing the local clock having a third frequency, receiving the local clock having the third frequency and counting the local clock, and sequentially decreasing the local count value from the intermediate value corresponding to the counted local clock having the third frequency until the plurality of second cycles of the base clock are finished, wherein the first frequency is greater than the third frequency; as well as When the local count value is just less than or equal to the initial value as the second count output, a logic value corresponding to one of the plurality of second cycles of the base clock is adopted.

19. The local counting method according to claim 14, wherein the step of counting the local clock according to the counting enable signal to generate the second counting output comprises: During a first cycle of the base clock and when the base clock and the comparator output signal are both enabled, providing the local clock having a first frequency, receiving the local clock having the first frequency and counting the local clock, and sequentially increasing the local count value from an initial value corresponding to the counted local clock having the first frequency until the base clock is disabled to generate an intermediate value of the local count value; Before a plurality of second cycles of the base clock, taking the complement of the intermediate value of the local count value to obtain a one's complement of the intermediate value of the local count value; providing the local clock having a third frequency during the plurality of second cycles after the first cycle of the base clock and when the base clock and the comparator output signal are both enabled, receiving the local clock having the third frequency and counting the local clock, and sequentially increasing the local count value from the one's complement of the intermediate value corresponding to the counted local clock having the third frequency until the plurality of second cycles of the base clock are finished, wherein the first frequency is greater than the third frequency; as well as When the local count value is just greater than or equal to the initial value as the second count output, a logic value corresponding to one of the plurality of second cycles of the base clock is adopted.

20. The local counting method according to claim 14, wherein the step of counting the local clock according to the counting enable signal to generate the second counting output comprises: During a first cycle of the base clock and when the base clock and the comparator output signal are both enabled, providing the local clock having a first frequency, receiving the local clock having the first frequency and counting the local clock, and sequentially increasing the local count value from an initial value corresponding to the counted local clock having the first frequency until the base clock is disabled to generate a first intermediate value of the local count value; During a plurality of second cycles after the first cycle of the base clock, and when the base clock and the comparator output signal are both enabled, providing the local clock having a third frequency, receiving the local clock having the third frequency and counting the local clock, and sequentially decreasing the local count value from the first intermediate value corresponding to the counted local clock having the third frequency until the plurality of second cycles of the base clock are finished, to generate a second intermediate value of the local count value; providing the local clock having the third frequency during a plurality of third cycles after the plurality of second cycles of the base clock and when the base clock and the comparator output signal are both enabled, receiving the local clock having the third frequency and counting the local clock, and sequentially increasing the local count value from the second intermediate value corresponding to the counted local clock having the third frequency until the plurality of third cycles of the base clock are completed, wherein the first frequency is greater than the third frequency; as well as When the local count value is just greater than or equal to the initial value as the second count output, a logic value corresponding to one of the plurality of third cycles of the base clock is adopted.

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