Bonding Structure of Semiconductor Device, Method for Manufacturing the Same, and Semiconductor Device

Abstract

The present application relates to a bonding structure of a semiconductor device, a manufacturing method thereof, and a semiconductor device. The bonding structure includes: a first substrate; a second substrate; a bonding ring located between the first substrate and the second substrate, which includes a first bonding layer and a second bonding layer, and the resistance of the first bonding layer changes before and after bonding connection; a conductive layer located on a side of the first substrate facing the second substrate, which includes at least two separate conductive lines, one end of each conductive line is electrically connected to the first bonding layer, and the other end is electrically connected to a resistance detection pad. The bonding structure of the semiconductor device according to the present application can monitor the bonding quality of the bonding process online, and has a high degree of automation.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit manufacturing, and particularly to a bonding structure of a semiconductor device, a manufacturing method thereof, and a semiconductor device. Background Art

[0002] Wafer-level bonding is an important process step in MEMS (Micro Electromechanical System) technology. Its main functions are to provide good mechanical protection for the structures on the wafer and to enable the sealing step to be carried out under certain gas atmosphere or vacuum requirements. Among them, aluminum-germanium bonding is a relatively common form in wafer-level bonding. On the one hand, aluminum-germanium bonding is compatible with the CMOS (Complementary Metal Oxide Semiconductor) process and has no heavy metal ion pollution; on the other hand, the materials used in aluminum-germanium bonding have low costs and are suitable for consumer devices.

[0003] The main evaluation parameters of the bonding process include bonding strength and airtightness. Regarding the existing evaluation means of the bonding process, on the one hand, after dicing into bare dies, the bonding strength is measured by push-pull force measurement, and the airtightness of the device bonding is checked by rough inspection and fine inspection; on the other hand, by detecting the fusion degree of the two media in the bonding area with an infrared microscope, the bonding quality can be evaluated to a certain extent.

[0004] However, push-pull force measurement and airtightness inspection are mainly used to measure the bonding strength and airtightness, which are destructive detection methods. The tests need to be carried out after dicing the wafer into bare dies, and are applicable to the debugging stage of the bonding process and cannot perform online monitoring of the bonding process. In addition, infrared microscope detection uses the penetration ability of infrared rays to detect the aluminum-germanium fusion degree of the bonding interface through the silicon wafer. Although it can be used for online monitoring of the bonding process, it requires that the wafer cannot be low-resistance heavily doped, both sides of the bonding medium surface cannot be all metals, and the wafer must be thinned to less than 200 μm, otherwise the infrared rays cannot penetrate. In addition, all infrared microscope detections are manual operations, cannot be automated, have too low efficiency and cannot be quantified. Summary of the Invention

[0005] Based on the above defects in the prior art, the purpose of the present application is to provide a bonding structure of a semiconductor device and a manufacturing method thereof, which can online monitor the bonding quality of the bonding process and have a high degree of automation.

[0006] For this reason, the present application provides the following technical solutions.

[0007] The present application provides a bonding structure of a semiconductor device, and the bonding structure includes:

[0008] A first substrate;

[0009] A second substrate;

[0010] A bonding ring located between the first substrate and the second substrate, which includes a first bonding layer and a second bonding layer, and the resistance of the first bonding layer changes before and after bonding connection;

[0011] A conductive layer located on the side of the first substrate facing the second substrate, which includes at least two separated conductive lines, one end of each conductive line is electrically connected to the first bonding layer, and the other end is electrically connected to a resistance detection pad.

[0012] In at least one embodiment, it further includes a first dielectric layer, the first dielectric layer is located on the side of the conductive layer facing the second substrate, and the first bonding layer is located on the side of the first dielectric layer facing the second substrate.

[0013] In at least one embodiment, the conductive layer is partially exposed from the first dielectric layer to form at least two of the resistance detection pads, and the at least two resistance detection pads are respectively and electrically connected to the at least two conductive lines.

[0014] In at least one embodiment, at least two conductive vias are formed in the first dielectric layer, and the first bonding layer is respectively and electrically connected to the at least two conductive lines through the at least two conductive vias.

[0015] In at least one embodiment, it further includes a second dielectric layer, and the second bonding layer is located on the side of the second dielectric layer facing the first substrate.

[0016] In at least one embodiment, the first bonding layer is annular, there are four conductive vias, and the connection points of the four conductive vias and the first bonding layer divide the first bonding layer into four equal-length segments.

[0017] In at least one embodiment, a dam structure is formed on the first dielectric layer or the second dielectric layer, and the dam structure is used to limit the distance between the first dielectric layer and the second dielectric layer during bonding.

[0018] In at least one embodiment, the material of the first bonding layer includes at least one of the following: germanium, silicon, tin; the material of the second bonding layer includes at least one of the following: aluminum, gold, copper.

[0019] The present application also provides a manufacturing method of a bonding structure of a semiconductor device, and the manufacturing method includes:

[0020] The manufacturing method includes:

[0021] Providing a first substrate, and forming a conductive layer on the first substrate; wherein the conductive layer includes at least two conductive lines and at least two resistance detection pads that are separately arranged;

[0022] A first bonding layer is formed on a side of the conductive layer away from the first substrate; wherein the first bonding layer is electrically connected to the at least two resistance detection pads via the at least two conductive lines;

[0023] Providing a second substrate, and forming a second bonding layer on the second substrate;

[0024] The first bonding layer and the second bonding layer are bonded to form the bonding structure.

[0025] In at least one embodiment, the manufacturing method further includes: first forming a first dielectric layer on the conductive layer, etching the first dielectric layer to form at least two conductive through holes, and then forming the first bonding layer on the first dielectric layer;

[0026] Wherein, the first bonding layer is electrically connected to the at least two conductive lines via the at least two conductive through holes.

[0027] In at least one embodiment, the manufacturing method further includes: etching the first dielectric layer so that the conductive layer is partially exposed from the first dielectric layer to form the at least two resistance detection pads.

[0028] In at least one embodiment, the manufacturing method further includes: first forming a second dielectric layer on the second substrate, and then forming the second bonding layer on the second dielectric layer.

[0029] In at least one embodiment, etching the first dielectric layer to form at least two conductive vias includes: etching the first dielectric layer to form four conductive vias;

[0030] Wherein, the connection points between the four conductive vias and the first bonding layer divide the first bonding layer into four sections of equal length.

[0031] In at least one embodiment, the manufacturing method further comprises:

[0032] Detect the resistance change of the first bonding layer, and determine whether the bonding performance meets the preset requirements based on the detection result.

[0033] In at least one embodiment, detecting the change in resistance of the first bonding layer and judging whether the bonding performance meets preset requirements according to the detection result includes:

[0034] Before and after the bonding connection, the resistance of the first bonding layer is detected respectively, the resistance change value is calculated, and the resistance change value is compared with a preset expected range of the resistance change value. If the resistance change value is within the expected range of the resistance change value, it is determined that the bonding performance meets the preset requirements.

[0035] In at least one embodiment, the manufacturing method further includes:

[0036] Before performing the bonding connection, a dam structure is formed on the first dielectric layer or the second dielectric layer;

[0037] Wherein, the dam structure is used to limit the distance between the first dielectric layer and the second dielectric layer during the bonding connection.

[0038] The present application also provides a semiconductor device, and the semiconductor device includes the bonding structure described in any of the above embodiments. Beneficial effects

[0039] According to the bonding structure of the semiconductor device provided by the present application, by providing a first dielectric layer and a conductive layer, at least two resistance detection pads are formed by partially exposing the conductive layer, and the first bonding layer is connected to the at least two resistance detection pads through conductive vias. Combining the characteristic that the resistance of the first bonding layer changes after bonding, the change in the resistance of the first bonding layer before and after bonding can be detected through the resistance detection pads to determine whether the bonding performance meets the preset requirements. Generally, the degree of automation is high, the bonding quality of the bonding process can be monitored online, and the melting degree of the bonding can be quantified by resistance. In addition, the bonding structure is also applicable to the bonding quality monitoring of the case where the wafer has low resistance and heavy doping or both sides of the bonding dielectric surface are all metal, and the applicable range is wider. Description of the drawings

[0040] Figure 1 A schematic diagram showing the bonding structure of the semiconductor device of the present application is shown.

[0041] Figure 2 A top view showing the bonding structure of the semiconductor device of the present application is shown.

[0042] Figure 3 A flowchart showing the manufacturing method of the bonding structure of the semiconductor device of the present application is shown.

[0043] Figures 4a to 4j A manufacturing process diagram showing the bonding structure of the semiconductor device of the present application is shown.

[0044] Description of the reference numerals

[0045] 1. First substrate;

[0046] 2. Conductive layer; 21. Conductive circuit; 22. Resistance detection pad;

[0047] 3. The first dielectric layer;

[0048] 4. The first bonding layer; 41. Germanium material layer; 42. Titanium material layer;

[0049] 5. Conductive vias; 6. The third dielectric layer;

[0050] 10. The second substrate; 20. The second dielectric layer; 30. The second bonding layer; 40. The damascene structure. Detailed implementation manners

[0051] The exemplary embodiments disclosed in the present application will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific implementation manners set forth herein. On the contrary, these embodiments are provided so that the present application can be more thoroughly understood and the scope of the present application can be completely conveyed to those skilled in the art.

[0052] In the following description, numerous specific details are given to provide a more thorough understanding of the present application. However, it is obvious to those skilled in the art that the present application can be implemented without one or more of these details. In other instances, in order to avoid confusion with the present application, some well-known technical features are not described; that is, not all features of the actual embodiments are described here, and the well-known functions and structures are not described in detail.

[0053] In the drawings, for clarity, the dimensions of layers, regions, elements and their relative dimensions may be exaggerated. The same reference numerals denote the same elements throughout.

[0054] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or portions, these elements, components, regions, layers and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or portion from another element, component, region, layer or portion. Thus, without departing from the teachings of the present application, the first element, component, region, layer or portion discussed below may be referred to as the second element, component, region, layer or portion. And when discussing the second element, component, region, layer or portion, it does not imply that there must be a first element, component, region, layer or portion in the present application.

[0055] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. are used herein for convenience in describing the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms are intended to include different orientations of the device in use and operation. For example, if the device in the figures is flipped, then an element or feature described as "under" or "beneath" or "below" another element or feature will be oriented "above" the other element or feature. Thus, the exemplary terms "under" and "below" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0056] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present application. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0057] In order to thoroughly understand the present application, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present application. The preferred embodiments of the present application are described in detail below, but in addition to these detailed descriptions, the present application may also have other implementation methods.

[0058] According to the following Figures 1 to 2 The bonding structure of the semiconductor device according to the present application is described in detail.

[0059] In this embodiment, if Figure 1 and Figure 2 As shown, the bonding structure of the semiconductor device of the present application includes a first substrate 1 , a conductive layer 2 , a first dielectric layer 3 , a first bonding layer 4 , a second substrate 10 , a second dielectric layer 20 and a second bonding layer 30 .

[0060] like Figure 1 and Figure 2 As shown, the conductive layer 2 is located on the side of the first substrate 1 facing the second substrate 10, the first dielectric layer 3 is formed on the side of the conductive layer 2 facing the second substrate 10, and the first bonding layer 4 is located on the side of the first dielectric layer 3 facing the second substrate 10. Among them, the conductive layer 2 includes four conductive lines 21 arranged separately, the conductive layer 2 is partially exposed from the first dielectric layer 3 to form four resistance detection pads 22, four separate conductive through holes 5 are arranged through the first dielectric layer 3, the first bonding layer 4 is connected to the four conductive through holes 5, each conductive through hole 5 is correspondingly conductively connected to a conductive line 21, and each conductive line 21 is conductively connected to the corresponding resistance detection pad 22. It should be noted that the purpose of setting the resistance detection pad 22 is to detect the resistance of the first bonding layer 4, and the number thereof can be set to at least two, not limited to four, and can also be two, three, five or more. Correspondingly, the number of the conductive through holes 5 and the conductive lines 21 can also be two, three, five or more.

[0061] In addition, it should be understood that the first dielectric layer 3 is not necessarily provided, and the first bonding layer 4 can also be directly formed on the side of the conductive layer 2 facing away from the first substrate 1 without providing the first dielectric layer 3. In this case, the conductive line 21 of the conductive layer 2 can be directly connected to the first bonding layer 4 without passing through the conductive through hole 5.

[0062] like Figure 1 and Figure 2As shown, the second dielectric layer 20 is formed on the side of the second substrate 10 facing the first substrate 1, and the second bonding layer 30 is formed on the side of the second dielectric layer 20 facing the first substrate 1. The first bonding layer 4 and the second bonding layer 30 are bonded to form a bonding ring. It can be understood that the first bonding layer 4 and the second bonding layer 30 can have the same shape to facilitate bonding. At the same time, it can be understood that the second dielectric layer 20 is not necessarily provided, and the second bonding layer 30 can be directly provided on the second substrate 10.

[0063] According to the bonding structure of the semiconductor device of the present application, by providing a resistance detection pad 22 electrically connected to the first bonding layer 4, the change in the resistance of the first bonding layer 4 before and after bonding can be detected through the resistance detection pad 22 to determine whether the bonding performance of the bonding connection meets the preset requirements. Generally, the degree of automation is high, the bonding quality of the bonding process can be monitored online, and the melting degree of the bonding can be quantified by resistance. In addition, this bonding structure is also applicable to the bonding quality monitoring of the case where the wafer has low resistance and heavy doping or the bonding dielectric surfaces on both sides are all metal, and the applicable range is wider. It should be particularly noted that detecting the resistance of the first bonding layer 4 refers to detecting the resistance value or resistivity of the first bonding layer 4.

[0064] Specifically, for the change in the resistance of the first bonding layer 4 before and after bonding, during the process debugging and R & D stage, the expected range of the resistance change value of the first bonding layer 4 when the bonding process meets the requirements can be calibrated, and then during the actual production stage, the actual resistance change value of the first bonding layer 4 before and after bonding can be detected and compared with the above-calibrated expected range of the resistance change value, so as to be able to confirm online whether the bonding quality of the bonding process meets the requirements.

[0065] In this embodiment, as Figure 2 shown, the first bonding layer 4 is generally square, and the four conductive vias 5 are located at the four corners of the square. In this way, the four conductive vias 5 divide the first bonding layer 4 into four resistance strips, forming a Wheatstone bridge structure. Further, since the lengths of the four resistance strips are equal, after bonding is completed, the uniformity of the bonding connection can be judged by detecting the output of the Wheatstone bridge structure. Specifically, since the lengths of the four resistance strips are equal, that is, theoretically the resistances of the four resistance strips are basically equal, then if the bonding is completely uniform, the output of the Wheatstone bridge structure can be zero. Generally speaking, that is, the smaller the output of the Wheatstone bridge structure, the more uniform the bonding connection. It should be understood that the first bonding layer 4 is not limited to a square shape, and the first bonding layer 4 can be formed into a complete ring of any shape (such as a circle). Correspondingly, in order to be able to judge the uniformity of the bonding according to the Wheatstone bridge structure, the connection between the four conductive vias 5 and the first bonding layer 4 should divide the first bonding layer 4 into four segments with equal lengths.

[0066] In this embodiment, asFigure 2 As shown, the four resistor detection pads 22 can be arranged in pairs side by side, and the four resistor detection pads 22 can be located on the same side of the bonding structure, which is convenient for both manufacturing and electrical connection during resistor testing.

[0067] In this embodiment, as Figure 1 and Figure 2 shown, the bonding structure further includes a retaining wall structure 40, and the retaining wall structure 40 is formed on the side of the second dielectric layer 20 facing the first substrate 1. Among them, the retaining wall structure 40 is formed into a square shape adapted to the square-shaped second bonding layer 30, and the retaining wall structure 40 is provided on both the inner and outer sides of the second bonding layer 30. The retaining wall structure 40 is used to limit the distance between the first dielectric layer 3 and the second dielectric layer 20 during bonding. It should be understood that the height of the retaining wall structure 40 should be set to be less than the sum of the heights of the first bonding layer 4 and the second bonding layer 30 before bonding, so as to realize the bonding connection between the first bonding layer 4 and the second bonding layer 30. However, the height of the retaining wall structure 40 cannot be set too small, otherwise the first bonding layer 4 and the second bonding layer 30 will be over-fused, affecting the bonding performance. In short, the height of the retaining wall structure 40 can be reasonably set according to actual needs.

[0068] It should be added that the retaining wall structure 40 is not limited to being formed on the second dielectric layer 20, and can also be formed on the side of the first dielectric layer 3 facing the second substrate 10. In addition, the shape of the retaining wall structure 40 is not limited to being adapted to the first bonding layer 4 or the second bonding layer 30, and can also be independently set to any suitable shape. The retaining wall structure 40 is not limited to being provided on both the inner and outer sides of the second bonding layer 30, and can also be provided on only one side. In short, as long as the distance between the first dielectric layer 3 and the second dielectric layer 20 can be limited during bonding.

[0069] In this embodiment, the material of the first bonding layer 4 can include at least one of the following: germanium, silicon, tin; the material of the second bonding layer 30 includes at least one of the following: aluminum, gold, copper. Preferably, the material of the first bonding layer 4 includes germanium, and the material of the second bonding layer includes aluminum.

[0070] In this embodiment, as Figure 1 shown, the first bonding layer 4 includes a germanium material layer 41 and a titanium material layer 42. The titanium material layer 42 is located between the germanium material layer 41 and the first dielectric layer 3. By providing the titanium material layer 42, it is beneficial to adhere the germanium material layer 41 to the first dielectric layer 3.

[0071] In this embodiment, other layers can also be provided between the first substrate 1 and the conductive layer 2, such as Figure 1 the third dielectric layer 6 shown in. It should be understood that the bonding structure of the present application can also include other layer structures not shown in the figure.

[0072] Next, according to Figures 3 to 4j a detailed description will be given of the manufacturing method of the bonding structure of the semiconductor device according to the present application.

[0073] As Figure 3 shown, the manufacturing method of the bonding structure of the semiconductor device includes:

[0074] Step S1: Provide a first substrate and form a conductive layer on the first substrate; wherein, the conductive layer includes at least two conductive lines and at least two resistance detection pads that are separately arranged;

[0075] Step S2: Form a first bonding layer on the side of the conductive layer facing away from the first substrate; wherein, the first bonding layer is electrically connected to the at least two resistance detection pads through the at least two conductive lines in a corresponding manner;

[0076] Step S3: Provide a second substrate and form a second bonding layer on the second substrate;

[0077] Step S4: Bond and connect the first bonding layer and the second bonding layer to form a bonding structure.

[0078] Among them, it should be understood that the manufacturing method of the bonding structure of the present application is not limited to the order of the above steps S1 to S4. Without affecting the manufacturing, the order of the above steps can be swapped. For example, step S3 can be carried out before step S1.

[0079] Optionally, in step S2, first form a first dielectric layer on the conductive layer, etch the first dielectric layer to form at least two conductive vias, and then form a first bonding layer on the first dielectric layer; wherein, the first bonding layer is electrically connected to the at least two conductive lines through the at least two conductive vias in a corresponding manner. Further preferably, etch the first dielectric layer to form four conductive vias, and the connection parts of the four conductive vias and the first bonding layer divide the first bonding layer into four equal-length segments, so that a Wheatstone bridge structure can be formed. After bonding and connecting, the uniformity of the bonding connection can be judged by detecting the output of the Wheatstone bridge structure.

[0080] Further optionally, in step S2, etch the first dielectric layer so that part of the conductive layer is exposed from the first dielectric layer to form at least two resistance detection pads.

[0081] Further optionally, in step S3, first form a second dielectric layer on the second substrate, and then form a second bonding layer on the second dielectric layer.

[0082] Further optionally, before step S4, form a dam structure on the first dielectric layer or the second dielectric layer; wherein, the dam structure is used to limit the distance between the first dielectric layer and the second dielectric layer during the bonding connection.

[0083] Further, the manufacturing method further includes: detecting the change in the resistance of the first bonding layer, and judging whether the bonding performance meets the preset requirements according to the detection result. Specifically, the resistance of the first bonding layer is detected before and after the bonding connection respectively, the resistance change value is calculated, and the resistance change value is compared with the expected range of the preset resistance change value. If the resistance change value is within the expected range of the resistance change value, it is determined that the bonding performance meets the preset requirements.

[0084] Figures 4a to 4j shows a specific manufacturing process of the bonding structure of the semiconductor device of the present application. As Figures 4a to 4c shown, first, a third dielectric layer 6 (for example, an oxide layer) is deposited and formed on the first substrate 1, then a conductive layer 2 is deposited and formed on the third dielectric layer 6, and a first dielectric layer 3 (for example, an oxide layer) is deposited and formed on the conductive layer 2. Among them, the conductive layer 2 includes at least two conductive lines arranged separately.

[0085] As Figure 4d shown, the first dielectric layer 3 is etched and a conductive material (for example, tungsten) is deposited to form a conductive through hole 5. After completion, a planarization process can be performed. Among them, there are at least two conductive through holes 5, and the conductive through holes 5 are conductively connected to the corresponding conductive lines.

[0086] As Figure 4e shown, at the position corresponding to the conductive through hole 5 on the first dielectric layer 3, a first bonding layer 4 is deposited and etched. Among them, the first bonding layer 4 may include a germanium material layer 41 and a titanium material layer 42, and of course, other materials may also be included.

[0087] As Figure 4f shown, the first dielectric layer 3 is etched so that the conductive layer 2 is partially exposed from the first dielectric layer 3 to form a resistance detection pad 22. Among them, the number of the resistance detection pads 22 is at least two, and the resistance detection pads are conductively connected to the corresponding conductive lines.

[0088] As Figures 4g to 4h shown, a second dielectric layer 20 (for example, an oxide layer) and a second bonding layer 30 are sequentially deposited and formed on the second substrate 10. Among them, the material of the second bonding layer 30 may include aluminum, and of course, other materials may also be included.

[0089] As Figure 4i shown, a barrier structure 40 is further deposited and etched on the second dielectric layer 20, and the barrier structure 40 is formed on both the inner and outer sides of the second bonding layer 30. Among them, the barrier structure 40 may be an oxide layer. Of course, the present application is not limited thereto, and the barrier structure 40 may also be formed on the first dielectric layer 3.

[0090] Finally, as Figure 4j shown, through the first bonding layer 4 and the second bonding layer 30, the Figure 4f structure formed inFigure 4i The structures formed therein are bonded to form a final bonding structure.

[0091] In the above process, preferably, four conductive vias 5 are formed in the first dielectric layer 3, the first bonding layer 4 is formed in a ring shape, and the connection points of the four conductive vias 5 and the first bonding layer 4 divide the first bonding layer 4 into four equal-length segments.

[0092] Furthermore, the manufacturing method of the present application further includes: detecting the change in the resistance of the first bonding layer 3, and judging whether the bonding performance meets the preset requirements according to the detection result. Specifically, the resistance (resistance value or resistivity) of the first bonding layer 3 is detected before and after the bonding connection respectively, the resistance change value is calculated, and the resistance change value is compared with the expected range of the preset resistance change value. If the resistance change value is within the expected range of the resistance change value, it is judged that the bonding performance meets the preset requirements, otherwise it is judged that the bonding performance does not meet the preset requirements.

[0093] The present application also provides a semiconductor device, which includes the bonding structure of the semiconductor device described in any of the above embodiments.

[0094] It should be understood that the above embodiments are all exemplary and do not cover all possible embodiments included in the claims. Without departing from the scope of the present application, various deformations and changes can be made on the basis of the above embodiments. Similarly, the technical features of the above embodiments can be arbitrarily combined to form other embodiments of the present application that may not be clearly described. Therefore, the above embodiments only represent several embodiments of the present application and do not limit the protection scope of the present application.

Claims

1. A bonding structure of a semiconductor device, characterized in that, The bonding structure includes: A first substrate; A second substrate; A bonding ring located between the first substrate and the second substrate, which includes a first bonding layer and a second bonding layer, and the resistance of the first bonding layer changes before and after bonding connection; A conductive layer deposited on one side of the first substrate facing the second substrate, which includes at least two separated conductive lines and at least two resistance detection pads, one end of each conductive line is electrically connected to the first bonding layer, and the other end is electrically connected to the resistance detection pad; A first dielectric layer located on one side of the conductive layer facing the second substrate, and the first bonding layer is located on one side of the first dielectric layer facing the second substrate; Wherein, the first bonding layer includes a germanium material layer and a titanium material layer, and the titanium material layer is located between the germanium material layer and the first dielectric layer.

2. The bonding structure according to claim 1, wherein The conductive layer is partially exposed from the first dielectric layer to form at least two of the resistance detection pads, and the at least two resistance detection pads are respectively and electrically connected to the at least two conductive lines.

3. The bonding structure according to claim 1, wherein At least two conductive vias are formed in the first dielectric layer, and the first bonding layer is respectively and electrically connected to the at least two conductive lines through the at least two conductive vias.

4. The bonding structure according to claim 1, wherein It further includes a second dielectric layer, and the second bonding layer is located on one side of the second dielectric layer facing the first substrate.

5. The bonding structure according to claim 3, characterized in that The first bonding layer is annular, there are four conductive vias, and the connection points of the four conductive vias and the first bonding layer divide the first bonding layer into four equal-length segments.

6. The bonding structure according to claim 4, wherein, A dam structure is formed on the first dielectric layer or the second dielectric layer, and the dam structure is used to limit the distance between the first dielectric layer and the second dielectric layer during bonding.

7. The bonding structure according to claim 1, characterized in that, The material of the first bonding layer includes at least one of the following: germanium, silicon, tin; the material of the second bonding layer includes at least one of the following: aluminum, gold, copper.

8. A method for manufacturing a bonding structure of a semiconductor device, characterized in that, The manufacturing method includes: Providing a first substrate and depositing and forming a conductive layer on the first substrate; wherein, the conductive layer includes at least two separated conductive lines and at least two resistance detection pads; Forming a first dielectric layer on the conductive layer; Forming a first bonding layer on the first dielectric layer; wherein, the first bonding layer is respectively and electrically connected to the at least two resistance detection pads through the at least two conductive lines; the first bonding layer includes a germanium material layer and a titanium material layer, and the titanium material layer is located between the germanium material layer and the first dielectric layer; Providing a second substrate and forming a second bonding layer on the second substrate; Bonding and connecting the first bonding layer and the second bonding layer to form the bonding structure.

9. The manufacturing method according to claim 8, characterized in that, After forming the first dielectric layer on the conductive layer, the manufacturing method further includes: etching the first dielectric layer to form at least two conductive vias, and then forming the first bonding layer on the first dielectric layer; Wherein, the first bonding layer is respectively and electrically connected to the at least two conductive lines through the at least two conductive vias.

10. The manufacturing method according to claim 9, characterized in that, The manufacturing method further includes: etching the first dielectric layer so that the conductive layer is partially exposed from the first dielectric layer to form the at least two resistance detection pads.

11. The manufacturing method according to claim 9, characterized in that, The manufacturing method further includes: first forming a second dielectric layer on the second substrate, and then forming the second bonding layer on the second dielectric layer.

12. The manufacturing method according to claim 9, characterized in that, Etching the first dielectric layer to form at least two conductive vias includes: etching the first dielectric layer to form four conductive vias; Wherein, the connection parts of the four conductive vias and the first bonding layer divide the first bonding layer into four segments with equal lengths.

13. The manufacturing method according to claim 8, characterized in that, The manufacturing method further includes: Detecting the resistance change of the first bonding layer, and judging whether the bonding performance meets the preset requirements according to the detection result.

14. The manufacturing method according to claim 13, characterized in that, The detecting the resistance change of the first bonding layer and judging whether the bonding performance meets the preset requirements according to the detection result includes: Detecting the resistance of the first bonding layer before and after the bonding connection respectively, calculating the resistance change value, comparing the resistance change value with the expected range of the preset resistance change value, and if the resistance change value is within the expected range of the resistance change value, it is judged that the bonding performance meets the preset requirements.

15. The manufacturing method according to claim 11, characterized in that, The manufacturing method further includes: Before the bonding connection, forming a dam structure on the first dielectric layer or the second dielectric layer; Wherein, the dam structure is used to limit the distance between the first dielectric layer and the second dielectric layer during the bonding connection.

16. A semiconductor device, characterized in that, The semiconductor device includes the bonding structure according to any one of claims 1 to 7.

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