Chip testing circuit, chip and testing equipment

Abstract

The present invention relates to a chip test circuit, a chip and a test device. The chip test circuit includes: a signal input terminal connected to a chip to be detected for accessing a signal to be detected; a plurality of signal output terminals for outputting the signal to be detected; a switch module connected between the signal input terminal and the signal output terminals; the switch module includes: at least one switch module, which includes a plurality of switch branches, and the number of switch branches matches the number of signal output terminals; the switch branch includes: a first end of the switch branch is electrically connected to the signal input terminal; a second end of the switch branch is correspondingly connected to the signal output terminal one by one; a switch unit connected between the first end and the second end of the switch branch; wherein, the switch unit is configured to selectively conduct according to the type of the signal to be detected to transmit the signal to be detected to the signal output terminal. The above chip test circuit can improve the bandwidth of signal transmission, improve the test efficiency, and at the same time can meet the requirements of various signal test conditions.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and particularly to a chip test circuit, a chip and a test device. Background Art

[0002] With the enrichment of chip functions, the internal test requirements of chips are gradually increasing. Correspondingly, the number of signals to be transmitted between the chip and the test device is increasing. The test device with multi-channel input meets the requirement of simultaneously measuring multiple signals. For example, during the test of the SPI (Serial Peripheral Interface) bus of a chip, it is necessary to simultaneously test the clock signal, the data signal and the chip select signal, but the required test speed is not high. However, in some cases, only one signal needs to be tested, and a high test speed is required, such as testing the USB bus signal. Summary of the Invention

[0003] The purpose of the embodiments of the present application is to provide a chip test circuit, a chip and a test device, which can improve the bandwidth of signal transmission, further improve the test efficiency, and at the same time can meet the requirements of various signal test conditions.

[0004] Based on this, in the first aspect, a chip test circuit is provided, including: a signal input end, which is connected to the chip to be detected and is used for accessing the signal to be detected; a plurality of signal output ends, which are used for outputting the signal to be detected; a switch module, which is connected between the signal input end and the signal output ends; the switch module includes: at least one switch module, the switch module includes a plurality of switch branches, and the number of switch branches matches the number of signal output ends; the switch branch includes: a first end of the switch branch, which is electrically connected to the signal input end; a second end of the switch branch, which is connected to the signal output ends in a one-to-one correspondence; a switch unit, which is connected between the first end and the second end of the switch branch; wherein, the switch unit is configured to selectively conduct according to the type of the signal to be detected to transmit the signal to be detected to the signal output ends.

[0005] In one embodiment, the types of the signals to be detected include high-speed signals and low-speed signals.

[0006] In one embodiment, when the signal to be detected is a high-speed signal, at least 2 of the plurality of switch branches are conducted.

[0007] In one embodiment, the chip test circuit further includes: a plurality of sample and hold circuits, which are arranged between the second end of the switch branch and the signal output ends, and the clock phases of each sample and hold circuit are different.

[0008] In one embodiment, the switch module includes 1 switch module, and each switch module includes M switch branches, which are respectively the switch branches of level 1 to level M, where M≥2.

[0009] In one embodiment, the switch module includes N switch modules, and each switch module includes M switch branches, namely the 1st to Mth switch branches, where M≥N≥2.

[0010] In one embodiment, the second ends of the switch branches of the same level in the switch module are electrically connected.

[0011] In one embodiment, when the types of signals to be detected are different, at least two switch branches of the switch module accessing the high-speed signal are turned on, one switch branch of the other switch modules is turned on, and the switch branches of the same level in each switch module are not turned on simultaneously.

[0012] In one embodiment, when the type of signal to be detected is a low-speed signal, at least one switch branch of each switch module is turned on, and the switch branches of the same level in each switch module are not turned on simultaneously.

[0013] In one embodiment, the switch unit converts the signal to be detected from a voltage signal into a current signal.

[0014] In one embodiment, the switch unit further includes a bandwidth limiter for limiting the bandwidth range of the switch unit.

[0015] In a second aspect, there is provided a chip including the chip test circuit of any of the embodiments.

[0016] In a third aspect, there is provided a test device including a power supply and the test circuit of any of the embodiments, and the power supply is used to provide a working voltage and / or a working current for the test circuit.

[0017] The above chip test circuit can improve the bandwidth of signal transmission, further improve the test efficiency, and at the same time meet the requirements of various signal test conditions by setting a plurality of switch branches and a plurality of signal output terminals. Description of the Drawings

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0019] Figure 1 It is a circuit element diagram of the chip test circuit in one embodiment;

[0020] Figure 2 It is a circuit element diagram of the chip test circuit in another embodiment;

[0021] Figure 3Circuit element diagram of a chip test circuit in another embodiment;

[0022] Figure 4 Circuit element diagram of a chip test circuit in another embodiment;

[0023] Figure 5 Functional block diagram of a switch unit in an embodiment;

[0024] Figure 6 is Figure 5 Specific circuit element diagram of the switch unit shown;

[0025] Figure 7 is Figure 6 Specific circuit element diagram of the medium bandwidth limiter in Detailed implementation manners

[0026] For ease of understanding this application, the following will describe this application more comprehensively with reference to relevant accompanying drawings. Embodiments of this application are given in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided so that the disclosure of this application is more thorough and comprehensive.

[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used in the description of this application herein are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0028] It can be understood that the terms "first", "second", etc. used in this application can be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element. For example, without departing from the scope of this application, a first resistor can be called a second resistor, and similarly, a second resistor can be called a first resistor. Both the first resistor and the second resistor are resistors, but they are not the same resistor.

[0029] It can be understood that for "connection" in the following embodiments, if there is an electrical signal or data transfer between the connected circuits, modules, units, etc., it should be understood as "electrical connection", "communication connection", etc.

[0030] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising", "including" or "having", etc. specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof.

[0031] Refer to Figure 1 , Figure 1 which shows a circuit element diagram of a chip test circuit in an embodiment. Refer to Figure 1 , the chip test circuit includes a signal input terminal 10, a switch module 20, and a plurality of signal output terminals 30. The signal input terminal 10 is connected to the chip to be detected and is used to access the signal to be detected. The plurality of signal output terminals 30 are used to output the signal to be detected for further processing of the signal to be detected. The switch module 20 is connected between the signal input terminal 10 and the signal output terminals 30; the switch module 20 includes at least one switch module 210, and the switch module includes a plurality of switch branches, and the number of switch branches matches the number of signal output terminals; the switch branch includes: a first end of the switch branch, electrically connected to the signal input terminal; a second end of the switch branch, corresponding to and connected to the signal output terminal one by one; a switch unit, connected between the first end and the second end of the switch branch, controlling the conduction and disconnection of the switch branch; wherein, the switch unit is configured to selectively conduct according to the type of the signal to be detected to transmit the signal to be detected to the signal output terminal. It can be understood that the signal to be detected can be a digital signal or an analog signal, which is not limited herein.

[0032] Specifically, the chip test circuit includes: a signal input terminal 10; the plurality of signal output terminals 30 include a first signal output terminal 311, a second signal output terminal 312, a third signal output terminal 313, and a fourth signal output terminal 314; the switch module 210 includes a first switch branch 211, a second switch branch 212, a third switch branch 213, and a fourth switch branch 214, wherein, the first end of the first switch branch is electrically connected to the signal input terminal 10, and the second end of the first switch branch is electrically connected to the first signal output terminal 311; the first end of the second switch branch is electrically connected to the signal input terminal 10, and the second end of the second switch branch is electrically connected to the second signal output terminal 312; the first end of the third switch branch is electrically connected to the signal input terminal 10, and the second end of the third switch branch is electrically connected to the third signal output terminal 313; the first end of the fourth switch branch is electrically connected to the signal input terminal 10, and the second end of the fourth switch branch is electrically connected to the fourth signal output terminal 314. A switch unit is further provided on each switch branch, which are respectively the switch unit 211a provided on the first switch branch, the switch unit 212a provided on the second switch branch, the switch unit 213a provided on the third switch branch, and the switch unit 214a provided on the fourth switch branch. When the switch unit conducts, the switch branch where the switch unit is located conducts, and vice versa. When the switch unit disconnects, the switch branch where the switch unit is located shuts off. Therefore, the switch unit can control the conduction and disconnection of the switch branch. It should be noted that Figure 1Only for exemplary illustration, the test circuit includes a first switch branch 211, a second switch branch 212, a third switch branch 213, and a fourth switch branch 214, and is connected to a first signal output terminal 311, a second signal output terminal 312, a third signal output terminal 313, and a fourth signal output terminal 314 in one-to-one correspondence, but this is not a limitation on the present application. Those skilled in the art can set the number of switch branches and the number of signal output terminals according to actual situations.

[0033] Specifically, the switch unit is configured to selectively conduct according to the type of the signal to be detected to transmit the signal to be detected to the signal output terminal. In some embodiments, as Figure 1 shown, after the signal input terminal 10 accesses the signal to be detected, the switch units 211a, 212a, 213a, 214a in the first switch branch 211, the second switch branch 212, the third switch branch 213, and the fourth switch branch 214 are simultaneously conducted, that is, the first switch branch 211, the second switch branch 212, the third switch branch 213, and the fourth switch branch 214 are conducted, and then the signal to be detected is simultaneously output to the corresponding first signal output terminal 311, second signal output terminal 312, third signal output terminal 313, and fourth signal output terminal 314 through the first switch branch 211, the second switch branch 212, the third switch branch 213, and the fourth switch branch 214 respectively.

[0034] Optionally, the characteristics of each switch unit are the same. In this way, after the signal to be detected passes through the first switch branch 211, the second switch branch 212, the third switch branch 213, and the fourth switch branch 214, the signal remains unchanged, that is, the signals output by the first signal output terminal 311, the second signal output terminal 312, the third signal output terminal 313, and the fourth signal output terminal 314 are the same, and are the same as the signal to be detected accessed by the signal input terminal, which is the same signal. For example, if the type of the switch unit is a high-speed type, the highest frequency allowed to pass through each switch unit is the same; if the type of the switch unit is a high-precision type, the leakage current when the signal passes through each switch unit is the same; if the type of the switch unit is a high-voltage type, the maximum voltage value of the signal allowed to pass through the switch unit is the same; if the type of the switch unit is a large-current type, the maximum current value of the signal allowed to pass through the switch unit is the same.

[0035] In this way, by setting multiple switch branches and corresponding multiple signal output terminals, and then transmitting to the external circuit, the chip test circuit can improve the bandwidth of signal transmission and further improve the test efficiency.

[0036] Optionally, the chip test circuit further includes a plurality of sample-and-hold circuits 40, which are arranged between the second end of the switch branch and the signal output terminal 30 and are used for sampling the signal to be detected. And the clock phases of each sample-and-hold circuit are different. Specifically, as Figure 2As shown in the figure, the multiple sample-and-hold circuits 40 include a first sample-and-hold circuit 41, a second sample-and-hold circuit 42, a third sample-and-hold circuit 43, and a fourth sample-and-hold circuit 44. Among them, the first sample-and-hold circuit 41 is disposed between the second end of the first switch branch and the first signal output terminal 311, the second sample-and-hold circuit 42 is disposed between the second end of the second switch branch and the second signal output terminal 312, the third sample-and-hold circuit 43 is disposed between the third switch branch and the third signal output terminal 313, and the fourth sample-and-hold circuit 44 is disposed between the second end of the fourth switch branch and the fourth signal output terminal 314. In this way, the sample-and-hold circuit 40 is equivalent to sampling the same signal to be detected at different times, achieving a four-fold sampling rate, improving the signal bandwidth and the data sampling rate.

[0037] In some other embodiments, after the signal input terminal 10 accesses the signal to be detected, some switch branches of the multiple switch branches of the switch module 210 are turned on, that is, the switch units of some switch branches among the first switch branch 211, the second switch branch 212, the third switch branch 213, and the fourth switch branch 213 are turned on. For example, the switch unit 211a of the first switch branch 211 is turned on, that is, the first switch branch 211 is turned on, and the other switch units remain off, then the signal to be detected is output from the first switch branch 211 to the first signal output terminal 311. Or the first switch branch 211 and the second switch branch 212 are turned on, and the other switch units remain off, then the signal to be detected is output from the first switch branch 211 to the first signal output terminal 311, and is output from the second switch branch 212 to the second signal output terminal 312.

[0038] In this way, by setting multiple switch branches and corresponding multiple signal output terminals, the chip test circuit can configure multiple output modes, such as the multi-output mode in which the multiple signal output terminals output the same signal to be detected or the single-output mode in which a single signal output terminal outputs the signal to be detected as described above.

[0039] Since the types of signals to be detected include high-speed signals and low-speed signals. Usually, for high-speed signals, such as USB signals, HDMI signals, etc., the required test speed is higher than that of low-speed signals. The low-speed signals can be SPI signals, CAN (Controller Area Network) signals, etc. Therefore, in order to achieve better test results, for example, when testing high-speed signals, the multi-output mode can be adopted to facilitate the next acquisition and processing, improve the overall sampling rate, so that higher-frequency signals can be observed, and further improve the test efficiency; while when testing low-speed signals, the single-output mode can be adopted for this test circuit. In this way, the same test circuit can meet the requirements of multiple signal test conditions.

[0040] Figure 3The circuit element diagram of the chip test circuit in another embodiment is shown. Refer to Figure 3, the chip test circuit includes a first signal input terminal 110 and a second signal input terminal 120; the multiple signal output terminals are respectively a first signal output terminal 321, a second signal output terminal 322, a third signal output terminal 323, and a fourth signal output terminal 324. The switch module 20 includes a first switch module 220 and a second switch module 230. Among them, the first switch module 220 is connected between the first signal input terminal 110 and the multiple signal output terminals 30, and the second switch module 230 is connected between the second signal input terminal 120 and the multiple signal output terminals 30. Specifically, the first switch module 220 includes first to fourth stage switch branches, namely a first switch branch 221, a second switch branch 222, a third switch branch 223, and a fourth switch branch 224. Among them, the first end of the first switch branch is electrically connected to the first signal input terminal 110, and the second end of the first switch branch is electrically connected to the first signal output terminal 321; the first end of the second switch branch is electrically connected to the first signal input terminal 110, and the second end of the second switch branch is electrically connected to the second signal output terminal 322; the first end of the third switch branch is electrically connected to the first signal input terminal 110, and the second end of the third switch branch is electrically connected to the third signal output terminal 323; the first end of the fourth switch branch is electrically connected to the first signal input terminal 110, and the second end of the fourth switch branch is electrically connected to the fourth signal output terminal 324. Similarly, the second switch module 230 also includes first to fourth stage switch branches, namely a first switch branch 231, a second switch branch 232, a third switch branch 233, and a fourth switch branch 234. Among them, the first end of the first switch branch is electrically connected to the second signal input terminal 120, and the second end of the first switch branch is electrically connected to the first signal output terminal 321; the first end of the second switch branch is electrically connected to the second signal input terminal 120, and the second end of the second switch branch is electrically connected to the second signal output terminal 322; the first end of the third switch branch is electrically connected to the second signal input terminal 120, and the second end of the third switch branch is electrically connected to the third signal output terminal 323; the first end of the fourth switch branch is electrically connected to the second signal input terminal 120, and the second end of the fourth switch branch is electrically connected to the fourth signal output terminal 324. Thus, the second ends of the switch branches of the same stage of the switch module are electrically connected and are electrically connected to the corresponding signal output terminals. In addition, a switch unit is provided on each switch branch. The first switch module 220 includes a switch unit 221a provided on the first switch branch, a switch unit 222a provided on the second switch branch, a switch unit 223a provided on the third switch branch, and a switch unit 224a provided on the fourth switch branch. The second switch module 230 includes a switch unit 231a provided on the first switch branch, a switch unit 232a provided on the second switch branch, a switch unit 233a provided on the third switch branch, and a switch unit 234a provided on the fourth switch branch.When the switching unit is turned on, the switching branch where the switching unit is located is turned on. Conversely, when the switching unit is turned off, the switching branch where the switching unit is located is turned off. Therefore, the switching unit can control the conduction and disconnection of the switching branch where it is located.

[0041] It can be understood that Figure 3 only the switching module 20 is exemplarily shown to include a first switching module 220 and a second switching module 230. The first switching module 220 and the second switching module 230 respectively include first to fourth order switching branches, namely a first switching branch, a second switching branch, a third switching branch, and a fourth switching branch, and are respectively connected to a first signal output terminal, a second signal output terminal, a third signal output terminal, and a fourth signal output terminal in a one-to-one correspondence. However, this is not a limitation to the present application. Those skilled in the art can set the number of switching modules, the number of switching branches, and the number of signal output terminals according to actual situations.

[0042] Next, it will be combined with Figure 3 to detail that the switching unit is configured to selectively conduct according to the type of the signal to be detected to transmit the signal to be detected to the signal output terminal. In some embodiments, if the signal to be detected is a high-speed signal, at least two of the multiple switching branches of the switching module accessing the high-speed signal are turned on.

[0043] Exemplarily, when two signals to be detected are externally provided, namely a first signal to be detected and a second signal to be detected, the first signal to be detected is connected to the first signal input terminal 110, and the second signal to be detected is connected to the second signal input terminal 120. Considering the type of the signal to be detected, if the first signal to be detected and the second signal to be detected are both high-speed signals, the switching unit can be configured as follows: the switching units 221a and 222a in the first switching branch 221 and the second switching branch 222 of the first switching module 220 are turned on, that is, the first switching branch 221 and the second switching branch 222 of the first switching module 220 are turned on. Therefore, the first signal to be detected is output from the first switching branch 221 and the second switching branch 222 to the first signal output terminal 321 and the second signal output terminal 322. And the switching units 233a and 234a in the third switching branch 233 and the fourth switching branch 234 of the second switching module 120 are turned on, that is, the third switching branch 233 and the fourth switching branch 234 are turned on. Therefore, the second signal to be detected is output from the third switching branch 233 and the fourth switching branch 234 to the third signal output terminal 323 and the fourth signal output terminal 324.

[0044] When the types of signals to be detected are different, at least two switching branches of the switching module for accessing high-speed signals are turned on, one switching branch of other switching modules is turned on, and the same-level switching branches of each switching module are not turned on simultaneously. Exemplarily, for example, the first signal to be detected is a low-speed signal, and the second signal to be detected is a high-speed signal. When the first signal input terminal 110 accesses the first signal to be detected and the second signal input terminal 120 accesses the second signal to be detected, the switching unit can be configured as follows: the switching unit 221a of the first switching branch 221 of the first switching module 220 is turned on, that is, the first switching branch 221 of the first switching module 220 is turned on, and the first signal to be detected is output from the first switching branch 221 to the first signal output terminal 321. And at least two of the switching units 232a, 233a, 234a in the second switching branch 232, the third switching branch 233, and the fourth switching branch 234 of the second switching module 230 are turned on. For example, the switching units 232a and 233a are turned on, that is, the second switching branch 232 and the third switching branch 233 are turned on. Therefore, the second signal to be detected is output from the second switching branch 232 and the third switching branch 233 to the second signal output terminal 322 and the third signal output terminal 323. Of course, in order to further increase the bandwidth of high-speed signal transmission and optimize the test efficiency, the switching unit can also be configured as follows: the switching unit 221a of the first switching branch 221 of the first switching module 220 is turned on, that is, the first switching branch 221 of the first switching module 220 is turned on, and the first signal to be detected is output from the first switching branch 221 to the first signal output terminal 321. And the switching units 232a, 233a, 234a in the second switching branch 232, the third switching branch 233, and the fourth switching branch 234 of the second switching module 230 are turned on, that is, the second switching branch 232, the third switching branch 233, and the fourth switching branch 234 are all turned on. Therefore, the second signal to be detected is output from the second switching branch 232, the third switching branch 233, and the fourth switching branch 234 to the second signal output terminal 322, the third signal output terminal 323, and the fourth signal output terminal 324.

[0045] In this way, by setting multiple switching branches and corresponding multiple signal output terminals, the chip test circuit can configure multiple output modes, can meet the requirements of various signal test conditions, can also increase the bandwidth of signal transmission, and further optimize the test efficiency.

[0046] To meet multiple output modes, in some embodiments, when the switching module includes one switching module, the switching module can be provided with M switching branches, which are respectively the first to Mth level switching branches, where M≥2, Figure 1 taking the illustrated embodiment as an example. In other embodiments, when the switching module includes N switching modules, each switching module includes M switching branches, which are respectively the first to Mth level switching branches, where M≥N≥2, Figure 3Take the illustrated embodiment as an example.

[0047] Specifically, when the switch module includes N switch modules, the second ends of the switch branches of the same-level switch branches of the switch modules are electrically connected. The following will be combined with Figure 4 Taking the chip test circuit including 4 switch modules, and each switch module including 1 to 4 levels of switch branches as an example, the chip test circuit will be specifically described.

[0048] As Figure 4 The illustrated chip test circuit includes a first signal input terminal 130, a second signal input terminal 140, a third signal input terminal 150, and a fourth signal input terminal 160; a plurality of signal output terminals 30 are respectively a first signal output terminal 331, a second signal output terminal 332, a third signal output terminal 333, and a fourth signal output terminal 334; the switch module 20 includes a first switch module 240, a second switch module 250, a third switch module 260, and a fourth switch module 270. Among them, the first switch module 240 is connected between the first signal input terminal 130 and the plurality of signal output terminals 30, the second switch module 250 is connected between the second signal input terminal 140 and the plurality of signal output terminals 30, the third switch module 260 is connected between the third signal input terminal 150 and the plurality of signal output terminals 30, and the fourth switch module 160 is connected between the fourth signal input terminal 160 and the plurality of signal output terminals 30. Specifically, each switch module respectively includes first to fourth levels of switch branches, namely a first switch branch, a second switch branch, a third switch branch, and a fourth switch branch. Among them, the second ends of the switch branches of the same-level switch branches of the switch module are electrically connected, that is, the first end of each switch branch is connected to the corresponding signal input terminal, and the second end of the first switch branch is electrically connected to the first signal output terminal, the second end of the second switch branch is electrically connected to the second signal output terminal, the second end of the third switch branch is electrically connected to the third signal output terminal, and the second end of the fourth switch branch is electrically connected to the fourth signal output terminal.

[0049] Specifically, when the signal to be detected is a high-speed signal, such as a USB bus signal, the signal to be detected is input to the first signal input terminal 130. The switch units in the first switch branch, the second switch branch, the third switch branch, and the fourth switch branch are simultaneously turned on, that is, the first switch branch 241, the second switch branch 242, the third switch branch 243, and the fourth switch branch 244 are turned on. Then the signal to be detected is simultaneously output to the corresponding first signal output terminal 331, second signal output terminal 332, third signal output terminal 333, and fourth signal output terminal 334 through the first switch branch 241, the second switch branch 242, the third switch branch 243, and the fourth switch branch 244 respectively. In this way, the bandwidth of signal transmission can be improved, and the test efficiency can be further improved. When the signal to be detected is a low-speed signal, such as testing an SPI signal, during this process, it is necessary to test the clock, data, and chip select signals simultaneously, but the required test speed is not high. Therefore, at least one switch branch of each switch module is turned on, and the switch branches of the same level of the switch module are not turned on simultaneously. The test clock, data, and chip select signals are input to the first signal input terminal 130, the second signal input terminal 140, and the third signal input terminal 150 respectively. For example, the first switch branch 241 of the first switch module 240 is turned on, the second switch branch 252 of the second switch module 250 is turned on, and the third switch branch 263 of the third switch module 260 is turned on, so as to transmit the test clock, data, and chip select signals to the first signal output terminal 331, the second signal output terminal 332, and the third signal output terminal 333 respectively.

[0050] Based on the above technical solution, the switch unit converts the signal to be detected from a voltage signal into a current signal. Optionally, the switch unit uses a cross-point switch to transmit the signal. In this way, the bandwidth of signal transmission can be further improved.

[0051] Figure 5 is a functional block diagram of a switch unit provided by an embodiment. Refer to Figure 5 , the switch unit includes a first follower 510, a second follower 520, and a transconductance amplifier 530. Among them, the input terminal of the first follower 510 is connected to the first end of the switch branch to access the differential voltage VIP. The output terminal of the first follower 510 is connected to the first input terminal of the transconductance amplifier 530. The input terminal of the second follower 520 is connected to the first end of the switch branch to access the differential voltage VIN. The output terminal of the second follower 520 is connected to the second input terminal of the transconductance amplifier 530. The first output terminal and the second output terminal of the transconductance amplifier 530 are connected to the second end of the switch branch to output the differential currents ION and IOP.

[0052] Among them, the first follower 510 and the second follower 520 have a high input impedance, a low output impedance, and a voltage gain approximately equal to 1, and have a driving effect on the subsequent transconductance amplifier 530.

[0053] Specifically, Figure 6 it is Figure 5 the specific circuit element diagram of the switch unit shown. Refer to Figure 6 , the first follower 510 includes a first resistor R1, a first triode Q1, a second triode Q2, a first current source I1, and a second current source I2. One end of the first resistor R1 is connected to the constant voltage power supply VCC, the other end of the first resistor R1 is connected to the collector of the first triode Q1, the base of the first triode Q1 is connected to the input end of the first follower 510, the emitter of the first triode Q1 is connected to the emitter of the second triode Q2 and grounded through the first current source I1, the collector of the second triode Q2 is connected to the constant voltage power supply VCC through the second current source I2, the collector and the base of the second triode Q2 are connected, and are also connected to the output end of the first follower 510.

[0054] The second follower 520 includes a second resistor R2, a third triode Q3, a fourth triode Q4, a third current source I3, and a fourth current source I4. One end of the second resistor R2 is connected to the constant voltage power supply VCC, the other end of the second resistor R2 is connected to the collector of the third triode Q3, the base of the third triode Q3 is connected to the input end of the second follower 520, the emitter of the third triode Q3 is connected to the emitter of the fourth triode Q4 and grounded through the third current source I3, the collector of the fourth triode Q4 is connected to the constant voltage power supply VCC through the fourth current source I4, the collector and the base of the fourth triode Q4 are connected, and are also connected to the output end of the second follower 520.

[0055] The current of the above-mentioned second current source I2 is set to be half of the first current source I1. Similarly, the current of the fourth current source I4 is set to be half of the third current source I3. Such a setting makes the output voltage of the first follower 510 and the second follower 520 the same as the input voltage, which can improve the ability to suppress common-mode signals.

[0056] The transconductance amplifier 530 is used to convert the input differential voltage signal into a current signal for output. Specifically, the transconductance amplifier 530 includes a fifth transistor Q5, a sixth transistor Q6, a fifth current source I5, a sixth current source I6, a third resistor R3, and a first capacitor C1. Among them, the base of the fifth transistor Q5 is connected to the first input terminal of the transconductance amplifier 530, the collector of the fifth transistor Q5 is connected to the first output terminal of the transconductance amplifier 530, and the emitter of the transconductance amplifier 530 is grounded through the fifth current source I5. The base of the sixth transistor Q6 is connected to the second input terminal of the transconductance amplifier 530, the collector of the sixth transistor Q6 is connected to the second output terminal of the transconductance amplifier 530, and the emitter of the sixth transistor Q6 is grounded through the sixth current source I6. At the same time, the third resistor R3 and the first capacitor C1 are connected in parallel between the emitter of the fifth transistor Q5 and the emitter of the sixth transistor Q6.

[0057] In the above transconductance amplifier 530, the fifth transistor Q5 and the sixth transistor Q6 serve as common-emitter amplifiers, the fifth current source I5 and the sixth current source I6 serve as amplifier tail current sources, and the third resistor R3 serves as an emitter resistor to control the transconductance value of the transconductance amplifier 530 and achieve bandwidth adjustment. At the same time, the first capacitor C1 serves as a high-frequency compensation capacitor, which can improve the bandwidth of the switching unit.

[0058] In this way, when the enable terminals of the first current source I1, the second current source I2, the third current source I3, the fourth current source I4, the fifth current source I5, and the sixth current source I6 are connected to control signals, the first current source I1, the second current source I2, the third current source I3, the fourth current source I4, the fifth current source I5, and the sixth current source I6 are turned on, so that the first follower 510, the second follower 520, and the transconductance amplifier 530 work, and the switching unit is turned on.

[0059] In some embodiments, the switching unit further includes a bandwidth limiter 540 for limiting the bandwidth range of the switching unit. Specifically, the bandwidth limiter 540 is disposed between the output terminal of the first follower 510 and the output terminal of the second follower 520. When the switching unit is turned off, turning on the bandwidth limiter 540 can improve the high-frequency isolation of the switching unit.

[0060] As Figure 7 shown, the bandwidth limiter 540 includes a switch K, a second capacitor C2, and a third capacitor C3. One end of the second capacitor C2 is connected to the output terminal of the first follower 510, the other end of the second capacitor C2 is connected to the first end of the third capacitor C3 through the switch K, and the other end of the third capacitor C3 is connected to the output terminal of the second follower 520.

[0061] When the bandwidth limiter 540 is turned on, close the switch K. The two ends of the bandwidth limiter 540 are equivalent to a capacitor Cs, and its capacitance value is:

[0062]

[0063] Since the outputs of the above-mentioned first follower 510 and second follower 520 have an impedance value R0, the range of the bandwidth f of the switch unit will be limited to within, that is, the bandwidth

[0064] It can be understood that the bandwidth limiter can also adopt other forms. For example, the bandwidth controller adopts the form of a switch K0. When the switch unit is in the off state, the switch K0 is closed to short-circuit the output end of the first follower and the output end of the second follower, which can greatly improve the isolation degree of the switch unit.

[0065] The above circuit can be applied to chips and test equipment such as oscilloscopes or similar equipment. In some embodiments, the test equipment further includes a power supply for providing a working voltage and / or working current for the test circuit so that the test circuit can work normally.

[0066] In the description of this specification, the description with reference to terms such as "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or features described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic description of the above terms does not necessarily refer to the same embodiment or example.

[0067] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0068] The above-described embodiments only represent several implementation manners of the present invention. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several deformations and improvements can still be made, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the invention patent should be subject to the appended claims.

Claims

1. A chip test circuit, characterized in that, Comprising: A signal input terminal, which is connected to the chip to be detected and is used for accessing the signal to be detected; A plurality of signal output terminals, which are used for outputting the signal to be detected; A switch module, which is connected between the signal input terminal and the signal output terminals; The switch module includes: At least one switch module, the switch module includes a plurality of switch branches, and the number of the switch branches matches the number of the signal output terminals; The switch branch includes: The first end of the switch branch, which is electrically connected to the signal input terminal; The second end of the switch branch, which is connected to the signal output terminals in one-to-one correspondence; A switch unit, which is connected between the first end and the second end of the switch branch; Wherein, the switch unit is configured to selectively conduct according to the type of the signal to be detected to transmit the signal to be detected to the signal output terminals; The first ends of the respective branches of different switch modules are connected to the signal input terminals corresponding to their respective switch modules, and the second ends of the switch branches of the same level of the switch module are electrically connected.

2. The chip test circuit according to claim 1, wherein The types of the signals to be detected include high-speed signals and low-speed signals.

3. The chip test circuit according to claim 2, wherein When the signal to be detected is the high-speed signal, at least 2 of the plurality of switch branches are conducted.

4. The chip test circuit according to claim 1, wherein The chip test circuit further includes: a plurality of sample-and-hold circuits, which are arranged between the second end of the switch branch and the signal output terminals, and the clock phases of each of the sample-and-hold circuits are different.

5. The chip test circuit according to claim 2, wherein When the switch module includes 1 switch module, each switch module includes M switch branches, which are respectively the 1st to Mth level switch branches, wherein M≥2; When the switch module includes N switch modules, each switch module includes M switch branches, which are respectively the 1st to Mth level switch branches, wherein M≥N≥2.

6. The chip test circuit according to claim 5, wherein When the types of the signals to be detected are different, at least 2 switch branches of the switch module accessing the high-speed signal are conducted, 1 switch branch of the other switch modules is conducted, and the switch branches of the same level of each switch module are not conducted simultaneously.

7. The chip test circuit according to claim 5, wherein When the type of the signal to be detected is the low-speed signal, at least 1 switch branch of each switch module is conducted, and the switch branches of the same level of each switch module are not conducted simultaneously.

8. The chip test circuit according to claim 1, wherein The switch unit further includes a bandwidth limiter, which is used for limiting the bandwidth range of the switch unit.

9. A chip, characterized in that, Including the chip test circuit according to any one of claims 1-8.

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