Data processing method, device, input / output expansion unit, and controller

Abstract

The present invention discloses a data processing method, device, input / output expansion unit and controller, belonging to the technical field of data processing. The present invention obtains original conversion data corresponding to an input analog signal; converts the original conversion data into reference process data; obtains a calibration proportionality coefficient corresponding to the reference process data; and obtains multiple groups of target data according to the reference process data and the calibration proportionality coefficient; determines a target display jitter value range according to the multiple groups of target data; and generates a target display value corresponding to each group of target data according to the target display jitter value range, and displays the target display value, thereby realizing high-speed acquisition of multiple analog signal input ranges, and simultaneously generating a target display value according to the target display jitter value range, ensuring that the acquisition and display result is within a relatively small jitter range, being able to balance high-efficiency acquisition and stability, and enabling the user to monitor a stable result.

Description

Technical Field

[0001] The present invention relates to the technical field of data processing, and particularly to a data processing method, device, input / output expansion unit and controller. Background Art

[0002] In the analog acquisition input / output (I / O) expansion system of a programmable logic controller (PLC), the analog acquisition I / O expansion unit usually needs to adapt to the backplane expansion bus to complete analog-to-digital conversion within a high-speed control cycle and upload the conversion result to the central processing unit (CPU) basic unit as the input feedback for the CPU basic unit to issue the next control instruction. In this control process, the higher the rate at which the analog acquisition I / O expansion unit completes analog-to-digital conversion and uploads the conversion result to the CPU basic unit, the higher the control synchronization of the control system. The analog acquisition I / O expansion unit is designed based on analog-to-digital converter device technology, and nowadays, the analog-to-digital converter device technology determines that such devices have the characteristic that while the output rate is increased, the effective resolution decreases, resulting in increased conversion value jitter. Therefore, existing products often have the phenomenon that when high-speed acquisition is performed, the displayed value of the acquisition result continuously jitters, resulting in customers being unable to intuitively observe the stable monitoring result of the monitored analog signal.

[0003] The above content is only used to assist in understanding the technical solution of the present invention, and does not represent an admission that the above content is prior art. Summary of the Invention

[0004] The main purpose of the present invention is to provide a data processing method, device, input / output expansion unit and controller, aiming to solve the technical problem in the prior art that the displayed value of the acquisition result jitters greatly, resulting in customers being unable to observe the stable monitoring result.

[0005] To achieve the above purpose, the present invention provides a data processing method, and the data processing method includes the following steps:

[0006] Obtain the original conversion data corresponding to the input analog signal;

[0007] Convert the original conversion data into reference process data;

[0008] Obtain the calibration scale factor corresponding to the reference process data; and

[0009] Obtain multiple groups of target data according to the reference process data and the calibration scale factor;

[0010] Determine the target display jitter value range according to multiple groups of the target data; and

[0011] Generate target display values corresponding to each group of target data according to the described target display jitter value range, and display the target display values.

[0012] Optionally, the obtaining of the original conversion data corresponding to the input analog signal includes:

[0013] Obtain the analog quantity corresponding to the input analog signal;

[0014] Determine the available resolution bits and reference voltage of the analog-to-digital converter; and

[0015] Obtain the original conversion data according to the analog quantity, the available resolution bits, and the reference voltage.

[0016] Optionally, the converting the original conversion data into reference process data includes:

[0017] Determine the data jitter range of the original conversion data;

[0018] Obtain process data according to the original conversion data, the data jitter range, and the target data offset bits; and

[0019] Obtain reference process data according to the process data and a preset offset.

[0020] Optionally, before obtaining the process data according to the original conversion data, the data jitter range, and the target data offset bits, it further includes:

[0021] Obtain the input range corresponding to the input analog signal;

[0022] Determine the effective resolution bits according to the input range and the preset data resolution; and

[0023] Determine the target data offset bits according to the effective resolution bits.

[0024] Optionally, before obtaining the calibration scale factor corresponding to the reference process data, it further includes:

[0025] Obtain the upper limit of the calibration write value under the input condition of the upper limit of the input range corresponding to the analog signal for the reference process data, and the lower limit of the calibration write value under the input condition of the lower limit of the input range corresponding to the analog signal; and

[0026] Calculate the calibration scale factor according to the preset data resolution, the upper limit of the calibration write value, and the lower limit of the calibration write value.

[0027] Optionally, the obtaining of the target data according to the reference process data and the calibration scale factor includes:

[0028] The target data is obtained based on the reference process data, the lower limit of the calibrated write value, and the calibrated proportionality coefficient.

[0029] Optionally, the multiple sets of target data are at least two sets of continuously read data;

[0030] Determining the target display jitter value range according to multiple sets of the target data includes:

[0031] Determining a reference display jitter value range according to multiple sets of the target data; and

[0032] Performing a rounding process on the reference display jitter value range to obtain the target display jitter value range

[0033] In addition, to achieve the above object, the present invention also provides a data processing device, which includes: a memory, a processor, and a data processing program stored on the memory and running on the processor, and the data processing program is configured to implement the data processing method as described above.

[0034] In addition, to achieve the above object, the present invention also provides an input / output expansion unit, which includes: a plurality of switch circuits, an analog-to-digital converter chip, a multi-channel high-speed isolator chip, and the data processing device as described above, which are connected in sequence. Each switch circuit includes a DIP switch and a resistor connected to each other. One end of the DIP switch is connected to the positive input terminal of the differential voltage current, and one end of the resistor is connected to the negative input terminal of the differential voltage current. One end of the DIP switch is also connected to the analog-to-digital converter chip, and one end of the resistor is also connected to the analog-to-digital converter chip.

[0035] In addition, to achieve the above object, the present invention also provides a controller, which includes: a processor basic unit and a plurality of input / output expansion units as described above. The microprocessor inside the input / output expansion unit receives the control instructions issued by the processor basic unit through the backplane expansion bus.

[0036] The present invention obtains original conversion data corresponding to an input analog signal; converts the original conversion data into reference process data; obtains a calibration scale factor corresponding to the reference process data; and obtains multiple groups of target data according to the reference process data and the calibration scale factor; determines a target display jitter value range according to the multiple groups of target data; and generates a target display value corresponding to each group of target data according to the target display jitter value range, and displays the target display value, thereby realizing high-speed acquisition of multiple analog signal input ranges, and generating a target display value according to the target display jitter value range, ensuring that the acquisition and display results are within a smaller jitter range, being able to take into account both efficient acquisition and stability, and enabling users to monitor stable results. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 It is a structural diagram of a data processing device in a hardware operating environment involved in an embodiment of the present invention;

[0038] Figure 2 It is a flowchart of a first embodiment of a data processing method of the present invention;

[0039] Figure 3 This is a schematic diagram of the structure of an analog acquisition I / O expansion system according to an embodiment of a data processing method of the present invention;

[0040] Figure 4 A schematic diagram of an analog acquisition electrical function module inside an analog acquisition I / O expansion unit according to an embodiment of a data processing method of the present invention;

[0041] Figure 5 It is a flowchart of a second embodiment of a data processing method of the present invention;

[0042] Figure 6 FIG. 4 is a flow chart of a third embodiment of a data processing method according to the present invention.

[0043] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0044] It should be understood that the specific embodiments described herein are only used to explain the present invention, and are not used to limit the present invention.

[0045] Reference Figure 1 , Figure 1 The present invention is a schematic diagram of the data processing device structure of the hardware operating environment involved in the embodiment of the present invention.

[0046] like Figure 1As shown in the figure, the data processing device may include: a processor 1001, such as a Central Processing Unit (CPU), a communication bus 1002, a user interface 1003, a network interface 1004, and a memory 1005. Among them, the communication bus 1002 is used to implement the connection and communication between these components. The user interface 1003 may include a display screen (Display), an input unit such as a keyboard (Keyboard). Optionally, the user interface 1003 may further include a standard wired interface and a wireless interface. The network interface 1004 may optionally include a standard wired interface and a wireless interface (such as a Wireless-Fidelity (Wi-Fi) interface). The memory 1005 may be a high-speed Random Access Memory (RAM) or a stable Non-Volatile Memory (NVM), such as a disk memory. Optionally, the memory 1005 may also be a storage device independent of the aforementioned processor 1001.

[0047] Those skilled in the art can understand that Figure 1 the structure shown in the figure does not constitute a limitation on the data processing device, and it may include more or fewer components than shown in the figure, or combine some components, or have different component arrangements.

[0048] As Figure 1 shown, in the memory 1005 as a storage medium, there may be included an operating system, a network communication module, a user interface module, and a data processing program.

[0049] In Figure 1 the data processing device shown in the figure, the network interface 1004 is mainly used for data communication with a network server; the user interface 1003 is mainly used for data interaction with a user; the processor 1001 and the memory 1005 in the data processing device of the present invention may be provided in the data processing device. The data processing device calls the data processing program stored in the memory 1005 through the processor 1001 and executes the data processing method provided by the embodiments of the present invention.

[0050] The embodiments of the present invention provide a data processing method. Referring to Figure 2 , Figure 2 it is a schematic flowchart of the first embodiment of a data processing method of the present invention.

[0051] In this embodiment, the data processing method includes the following steps:

[0052] Step S10: Obtain the original conversion data corresponding to the input analog signal.

[0053] In this embodiment, the execution subject of this embodiment may be the data processing device, which has functions such as data processing, data communication, and program running. The data processing device may be a chip such as a microprocessor unit (MPU). Of course, it may also be other devices with similar functions, and this embodiment is not limited thereto. For the convenience of description, this embodiment is described by taking the data processing device as an example.

[0054] It should be noted that in the analog acquisition I / O expansion system of the PLC, the analog acquisition I / O expansion unit usually needs to adapt to the backplane expansion bus to complete analog-to-digital conversion within a high-speed control cycle and upload the conversion result to the CPU basic unit as the input feedback for the CPU basic unit to issue the next control instruction. In this control process, the higher the rate at which the analog acquisition I / O expansion unit completes analog-to-digital conversion and uploads the conversion result to the CPU basic unit, the higher the control synchronization of the control system. The analog acquisition I / O expansion unit is designed based on analog-to-digital converter device technology. Nowadays, the analog-to-digital converter device technology determines that such devices have the characteristics that while the output rate is increased, the effective resolution decreases, resulting in increased jitter of the conversion value. Therefore, existing products often have the phenomenon that the displayed value of the acquisition result jitters continuously during high-speed acquisition, resulting in customers being unable to intuitively observe the stable monitoring result of the monitored analog signal. The current solution will greatly exacerbate the jitter of the displayed value in the case of high-speed resolution acquisition and cannot achieve both.

[0055] In this embodiment, to solve the above technical problems, a design method is provided that is based on a simple hardware circuit and adds corresponding software algorithms to the process data after analog-to-digital conversion of the analog acquisition. It realizes high-speed acquisition of all 6 types of analog signal input ranges (0 - 5V; 1 - 5V; 0 - 10V; (-10) - 10V; 4 - 20mA; 0 - 20mA), multiple (high, medium, low) resolution acquisitions, and at the same time can ensure that the jitter range of the acquisition display result is within ±1 LSB. Specifically, it can be realized in the following way.

[0056] In the specific implementation, in this embodiment, first Figure 3 the analog acquisition I / O expansion system of this embodiment is described. As Figure 3 shown, the analog acquisition I / O expansion system in this embodiment consists of a main control CPU basic unit 100 and multiple analog acquisition I / O expansion units ( Figure 3The analog acquisition I / O expansion units shown in the figure (analog acquisition I / O expansion unit 201, analog acquisition I / O expansion unit 202, …, analog acquisition I / O expansion unit 20n). In this system, the analog acquisition I / O expansion units (201 to 20n) will receive high-speed control commands sent from the main control CPU basic unit 100 via the backplane expansion bus. The cycle interval of this high-speed control command can be, for example, 0.5 ms. When the MPU1 inside the analog acquisition I / O expansion units (201 to 20n) in this system receives this high-speed control command, it will control the analog acquisition electrical function module inside the analog acquisition I / O expansion unit to perform acquisition response, complete single-channel analog acquisition of the corresponding range for the analog voltage and circuit signals output by the external customer site industrial transmitter 6 within the cycle interval of the high-speed control command, and upload the acquisition results to the main control CPU basic unit 100 via the backplane expansion bus 3. The main control CPU basic unit 100 includes an MPU1 and a CAN transceiver 2, and each analog acquisition I / O expansion unit includes an MPU1, a high-speed isolator 4, and an analog acquisition electrical function module 5.

[0057] Further, in this embodiment, in combination with Figure 4 the analog acquisition electrical function module inside the analog acquisition I / O expansion unit will be described. As Figure 4 shown, the analog acquisition electrical function module inside the analog acquisition I / O expansion unit includes a single MPU chip 1, a single 24-bit analog / digital converter chip 9 that supports 4-channel differential voltage input, a single EEPROM chip 11, 4 1-bit DIP switches 7, 4 250Ω resistors 8, and a single multi-channel high-speed isolator chip 10. During the entire process of analog voltage and current signal acquisition, the analog acquisition I / O expansion unit ( Figure 1The MPU chips within the numbers 201 to 20n) serve as the main body for receiving the high-speed control commands issued by the master CPU basic unit through the backplane expansion bus. Also, within the interval between the high-speed control commands issued by the master CPU basic unit, the MPU chips perform the following functions: 1. Through the Serial Peripheral Interface (SPI), obtain the 24-bit raw conversion data (process data A) after a single conversion from the analog-to-digital converter (ADC) chip. Subsequently, the process of converting process data A into process data B will also be completed through the internal software code. After obtaining process data B, the development engineer will complete the corresponding product calibration according to the maximum product resolution design target. During normal use, when there is an analog voltage or current input within any analog input range, the software algorithm within the MPU will calculate the corresponding process data C for the corresponding analog input signal through the corresponding algorithm formula. At the same time, the software algorithm within the MPU will also perform a rounding operation on process data C. If there are multiple resolution design requirements, the program within the MPU will also perform a proportional reduction process of 1 / 2 or 2 / 3 on process data C to achieve the performance of multiple design requirements with a product acquisition resolution of 6000 or 8000 LSB. Finally, the processed process data C corresponding to the product acquisition resolution requirements will be uploaded as the customer display value to the master CPU basic unit through the backplane expansion bus. During the product calibration operation, the MPU needs to complete the operation of writing the calibration value into the EEPROM through the I2C interface. A single Electrically Erasable Programmable Read Only Memory (EEPROM) chip mainly provides the function of power-off retention for the calibration fixed write value upper limit C2 and the calibration fixed write value lower limit C1. A single 4-channel 24-bit analog-to-digital converter chip needs to match the MPU control requirements to complete a single analog-to-digital conversion at high speed and send the 24-bit raw conversion data after the single analog-to-digital conversion to the MPU through the SPI interface between it and the MPU.When it is in the case of analog current input, the 1-bit dip switch corresponding to the channel should be turned on, and the analog current signal is converted into the corresponding sampling voltage range through the 250Ω resistor of the corresponding input channel. Here, the sampling voltage range corresponding to the 4-20mA input range is set to 1-5V; the sampling voltage range corresponding to the 0-20mA input range is 0-5V; a single multi-channel high-speed isolator chip mainly provides analog / digital isolation design for the serial peripheral interface SPI interface signal between the ADC chip and the MPU, so that the analog input signal of the product meets the requirements of corresponding safety regulations. At the same time, reducing the influence of the analog loop noise on the transmission of the serial peripheral interface SPI signal achieves the design purpose of improving the high-speed transmission stability of the serial peripheral interface SPI signal of the product in a high-frequency noise environment. At the same time, in order to meet the design requirement of completing a single analog / digital conversion within the high-speed backplane expansion bus high-speed control cycle of 0.5ms, the working mode of the ADC chip adopted in the design should be set to the working mode with a single analog / digital conversion time within 300us.

[0058] In a specific implementation, in this embodiment, after receiving the input analog signal, the original conversion data is obtained through analog / digital conversion by the ADC chip. The original conversion data is the original digital quantity data without any processing. Among them, the input analog signal can be voltage or current. The specific process of the above analog / digital conversion can be obtained according to the following formula:

[0059]

[0060] Among them, A is the original conversion data, Vadc: the differential input voltage of the voltage acquisition pin of the ADC device, that is, the analog quantity corresponding to the input analog signal. In this embodiment, the above calculation is carried out under ideal conditions, without considering the total non-adjustable error of the ADC device and the influence of the change of the ADC power supply voltage. N is the number of bits of the resolvable resolution of the ADC device. In this embodiment, a 24-bit ADC device is adopted. Of course, other bits can also be adopted according to the actual situation. Vref: Here is the analog / digital conversion reference voltage inside the ADC device. In this embodiment, it can be set to 2.5V.

[0061] Step S20: Convert the original conversion data into reference process data.

[0062] In a specific implementation, after obtaining the above original conversion data, in this embodiment, the original conversion data will be data-converted to obtain the reference process data. Specifically, in this embodiment, the original conversion data can be shifted left by six bits and then subtracted by a fixed offset to obtain the reference process data.

[0063] Step S30: Obtain the calibration scale factor corresponding to the reference process data.

[0064] In this embodiment, in order to reduce the large jitter of the final data display value, data calibration is first performed. After the calibration is completed, the calibration scale factor corresponding to the reference process data can be obtained in this embodiment. This calibration scale factor has the jitter result characteristics of all the reference process data, and the calibration scale factor can be obtained by looking up a table.

[0065] Step S40: Obtain the target data according to the reference process data and the calibration scale factor.

[0066] In a specific implementation, after obtaining the reference process data and the calibration scale factor, the target data can be calculated by combining the reference process data and the calibration scale factor. The target data is the display value corresponding to the input analog signal. For example, it is the display value under any voltage input within the input range of 1 - 5V.

[0067] Step S50: Determine the target display jitter value range according to multiple groups of the target data.

[0068] Step S60: Generate the target display values corresponding to each group of the target data according to the target display jitter value range, and display the target display values.

[0069] In a specific implementation, if the target data is to jitter, at least 2 consecutive calculations of the target data need to be completed. Therefore, in this embodiment, multiple groups of target data corresponding to the input analog signal are obtained through the above calculation process. These multiple groups of target data are at least two continuously read data. In this embodiment, two groups of target data are taken as an example for illustration. Assume that the target data obtained for the first time is the reference process data read for the first time ± (positive and negative jitters of the reference process data - C1) * K, and the target data obtained for the second time is the reference process data read for the second time ± (positive and negative jitters of the reference process data - C1) * K. Combining the above relational expressions, the maximum jitter value of the target data and the maximum jitter range K of two consecutive data readings of the process data B can be obtained. Here, K is the calibration scale factor. Finally, the reference display jitter value range can be obtained through the above relational expressions. Then, in this embodiment, the jitter value range is further rounded to obtain the target display jitter value range, which not only meets the design goal performance of the maximum acquisition resolution but also ensures that the jitter range of the display value at the customer site meets the design requirements. For example, assume that the obtained display jitter value range is -1.137 LSB. After rounding, it is -1 LSB, that is, the jitter range of the final display value at the customer site is within ±1 LSB.

[0070] In this embodiment, the original conversion data corresponding to the input analog signal is obtained; the original conversion data is converted into reference process data; the calibration scale factor corresponding to the reference process data is obtained; and multiple sets of target data are obtained according to the reference process data and the calibration scale factor; the target display jitter value range is determined according to the multiple sets of target data; and the target display value corresponding to each set of target data is generated according to the target display jitter value range, and the target display value is displayed, realizing high-speed acquisition of various analog signal input ranges, and at the same time generating the target display value according to the target display jitter value range, ensuring that the acquisition and display results are within a small jitter range, being able to balance high-efficiency acquisition and stability, and enabling the user to monitor stable results.

[0071] Reference Figure 5 , Figure 5 is a schematic flowchart of the second embodiment of a data processing method of the present invention.

[0072] Based on the above first embodiment, in the data processing method of this embodiment, the step S20 specifically includes:

[0073] Step S201: Determine the data jitter range of the original conversion data.

[0074] In specific implementation, after obtaining the original conversion data, in this embodiment, the data jitter range corresponding to the original conversion data can be obtained based on analog signals with different input ranges (such as 1V to 5V), as shown in Table 1 specifically.

[0075] Table 1:

[0076]

[0077]

[0078] From Table 1, the decimal calculation results of the original conversion data when the input is 1V and 5V can be obtained, as well as the negative jitter range and positive jitter range of the low 7-bit data of the calculation results of the corresponding original conversion data.

[0079] Step S202: Obtain process data according to the original conversion data, the data jitter range, and the target data offset bits.

[0080] Step S203: Obtain reference process data according to the process data and a preset offset.

[0081] In a specific implementation, the process data can be calculated based on the original conversion data, the data jitter range, and the target data offset bits. Then, the reference process data can be obtained by combining the preset offset and the process data. The reference process data is the process data that conforms to the 16-bit digital quantity data interaction format between the internal MPU and the ADC chip of the analog acquisition I / O expansion unit, and its range should be: a decimal number greater than 0 and less than 65535. Since the decimal calculation result of the process data A is 24-bit data, first, it is shifted left by 6 bits in software, and then the obtained 18-bit data is subtracted by the fixed offset of 106000. Finally, the process data B is adjusted to the range of 0 to 65535, and considering that the lower 7 bits of the process data A have positive and negative jitter characteristics, specifically, it can be obtained according to the following formula:

[0082]

[0083] Where B is the reference process data, A is the original conversion data, the positive and negative jitter of the lower 7 bits of data is the data jitter range, 2^ 6 is the target data offset bits, Offset is the preset offset, the preset offset can be set to 106000 LSB, and it can also be set to other values according to actual needs. This embodiment does not limit this.

[0084] In this embodiment, the input range of 1V to 5V should be designed considering the maximum resolution target of 12000 LSB. 1V to 5V is the input range corresponding to the analog signal, the preset resolution is 12000 LSB, and the effective resolution bits can be obtained according to the following formula:

[0085]

[0086] Where 1V and 5V are the input ranges, 12000 is the preset resolution. Through the above calculation, it can be obtained that N needs to satisfy being greater than 17.2 bits. In order to meet the 1 - 5V input acquisition range with the maximum resolution target of 12000 LSB, the original data after single analog / digital conversion needs to be rounded, that is, rounded to 18 bits. Therefore, the effective resolution bits can be obtained as 18 bits. Also, since the ADC chip obtains 24-bit original conversion data as the original conversion data for single analog / digital conversion, the target data offset bits can finally be obtained as 6 bits.

[0087] In this embodiment, the data jitter range of the original conversion data is determined; the input range corresponding to the input analog signal is obtained; the effective resolution bits are determined according to the input range and the preset data resolution; the target data offset bits are determined according to the effective resolution bits; the process data is obtained according to the original conversion data, the data jitter range and the target data offset bits; and the reference process data is obtained according to the process data and the preset offset. In this way, more accurate reference process data can be obtained.

[0088] Reference Figure 6 , Figure 6 is a schematic flowchart of the third embodiment of a data processing method of the present invention.

[0089] Based on the above first embodiment, the third embodiment of a data processing method of the present invention is proposed.

[0090] In this embodiment, before the step S30, it further includes:

[0091] Step S301: Obtain the upper calibration write value under the input condition of the upper limit of the input range corresponding to the analog signal for the reference process data, and the lower calibration write value under the input condition of the lower limit of the input range corresponding to the analog signal.

[0092] In specific implementation, in this embodiment, the reference process data is calibrated. Specifically, calibration can be performed according to the upper calibration write value under the input condition of the upper limit of the input range corresponding to the analog signal and the lower calibration write value under the input condition of the lower limit of the input range corresponding to the analog signal, as shown in Table 2 specifically.

[0093] Table 2:

[0094]

[0095] Step S302: Calculate the calibration proportionality coefficient according to the preset data resolution, the upper calibration write value, and the lower calibration write value.

[0096] In specific implementation, the calculation formula of the calibration proportionality coefficient is the calibration proportionality coefficient where 12000 is the preset resolution, C2 is the upper calibration write value, and C1 is the lower calibration write value. Multiple calibration proportionality coefficients K are calculated through the above formula. For example, when C2 is the calibration minimum value and negative jitter occurs, and C1 is the calibration minimum value and negative jitter occurs, K = 0.572; when C2 is the calibration maximum value and negative jitter occurs and C1 is the calibration minimum value, K = 0.571. Multiple calibration proportionality coefficients can be obtained through various different combinations of C1 and C2, which will not be elaborated in this embodiment.

[0097] Further, after determining the calibration proportionality coefficient, in this embodiment, the target data can be obtained based on the reference process data, the lower limit of the calibration write value, and the calibration proportionality coefficient. The calculation formula is as follows:

[0098] C = (Data B - C1 when input is arbitrary) * K

[0099] Where C is the target data, Data B when input is arbitrary, i.e., the reference process data, C1 is the lower limit of the calibration write value, and K is the calibration proportionality coefficient.

[0100] In this embodiment, by obtaining the upper limit of the calibration write value under the input condition of the upper limit of the input range corresponding to the analog signal for the reference process data, and the lower limit of the calibration write value under the input condition of the lower limit of the input range corresponding to the analog signal; calculating the calibration proportionality coefficient according to the preset data resolution, the upper limit of the calibration write value, and the lower limit of the calibration write value, and then obtaining the target data based on the reference process data, the lower limit of the calibration write value, and the calibration proportionality coefficient, it is ensured that while the target data meets the design goal performance of the maximum acquisition resolution, the jitter range of the display value at the customer site also meets the design requirements.

[0101] In addition, an input / output expansion unit is proposed in an embodiment of the present invention. The input / output expansion unit includes: a plurality of switch circuits, an analog-to-digital converter chip, a multi-channel high-speed isolator chip, and a data processing device as described above, which are connected in sequence. Each switch circuit includes a DIP switch and a resistor connected to each other. One end of the DIP switch is connected to the positive input terminal of the differential voltage current, one end of the resistor is connected to the negative input terminal of the differential voltage current, one end of the DIP switch is also connected to the analog-to-digital converter chip, and one end of the resistor is also connected to the analog-to-digital converter chip.

[0102] In addition, a controller is proposed in an embodiment of the present invention. The controller includes: a processor basic unit and a plurality of input / output expansion units as described above. The microprocessor inside the input / output expansion unit receives the control instructions issued by the processor basic unit through the backplane expansion bus.

[0103] Since this storage medium adopts all the technical solutions of the above-mentioned all embodiments, it has at least all the beneficial effects brought by the technical solutions of the above-mentioned embodiments, which will not be elaborated here one by one.

[0104] It should be understood that the above is only for illustration and does not constitute any limitation to the technical solution of the present invention. In specific applications, those skilled in the art can set according to needs, and the present invention does not limit this.

[0105] It should be noted that the above-described work process is only illustrative and does not limit the scope of protection of the present invention. In actual applications, those skilled in the art can select some or all of them according to actual needs to achieve the purpose of the solution of this embodiment, and no limitation is made here.

[0106] In addition, for the technical details not described in detail in this embodiment, reference can be made to the data processing method provided in any embodiment of the present invention, and details will not be repeated here.

[0107] In addition, it should be noted that in this article, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or system including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or further includes elements inherent to such process, method, article or system. Without more limitations, the element defined by the statement "including one..." does not exclude the existence of additional identical elements in the process, method, article or system including that element.

[0108] The serial numbers of the above embodiments of the present invention are only for description and do not represent the advantages or disadvantages of the embodiments.

[0109] Through the description of the above embodiments, those skilled in the art can clearly understand that the above-described embodiment methods can be implemented by means of software plus a necessary general hardware platform. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. The computer software product is stored in a storage medium (such as a read-only memory (ROM) / RAM, magnetic disk, optical disk), and includes several instructions for causing a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in various embodiments of the present invention.

[0110] The above is only the preferred embodiment of the present invention, and does not limit the patent scope of the present invention accordingly. Any equivalent structure or equivalent process transformation made by using the content of the specification and drawings of the present invention, or directly or indirectly applied in other related technical fields, shall be equally included in the patent protection scope of the present invention.

Claims

1. A data processing method, characterized in that, The data processing method includes: Obtaining original conversion data corresponding to an input analog signal; Determining the data jitter range of the original conversion data; Obtaining process data based on the original conversion data, the data jitter range, and a target data offset bit number; and Obtaining reference process data based on the process data and a preset offset; Obtaining a calibration scale factor corresponding to the reference process data; and Obtaining multiple sets of target data based on the reference process data and the calibration scale factor; Determining a target display jitter value range based on the multiple sets of target data; and Generating target display values corresponding to the multiple sets of target data according to the target display jitter value range and displaying the target display values; Before obtaining the process data based on the original conversion data, the data jitter range, and the target data offset bit number, it further includes: Obtaining an input range corresponding to the input analog signal; Determining an effective resolution bit number according to the input range and a preset data resolution; and Determining the target data offset bit number according to the effective resolution bit number.

2. The data processing method according to claim 1, wherein The obtaining of the original conversion data corresponding to the input analog signal includes: Obtaining an analog quantity corresponding to the input analog signal; Determining an available resolution bit number and a reference voltage of an analog-to-digital converter; and Obtaining the original conversion data based on the analog quantity, the available resolution bit number, and the reference voltage.

3. The data processing method according to claim 1, wherein Before obtaining the calibration scale factor corresponding to the reference process data, it further includes: Obtaining an upper calibration write value limit under the input condition of the upper limit of the input range corresponding to the analog signal for the reference process data, and a lower calibration write value limit under the input condition of the lower limit of the input range corresponding to the analog signal; and Calculating the calibration scale factor according to the preset data resolution, the upper calibration write value limit, and the lower calibration write value limit.

4. The data processing method according to claim 3, characterized in that, The obtaining of the target data based on the reference process data and the calibration scale factor includes: Obtaining the target data based on the reference process data, the lower calibration write value limit, and the calibration scale factor.

5. The data processing method according to any one of claims 1 to 4, characterized in that The multiple sets of target data are at least two sets of continuously read data; The determining of the target display jitter value range based on the multiple sets of target data includes: Determining a reference display jitter value range based on the multiple sets of target data; and Performing a rounding process on the reference display jitter value range to obtain the target display jitter value range.

6. A data processing device, characterized in that, The data processing device includes: a memory, a processor, and a data processing program stored on the memory and running on the processor, and the data processing program is configured to implement the data processing method according to any one of claims 1 to 5.

7. An input / output expansion unit, characterized in that The input / output expansion unit includes: a plurality of switch circuits connected in sequence, an analog / digital converter chip, a multi-channel high-speed isolator chip, and the data processing device as described in claim 6. Each of the switch circuits includes a DIP switch and a resistor connected to each other. One end of the DIP switch is connected to the positive input terminal of the differential voltage current, one end of the resistor is connected to the negative input terminal of the differential voltage current, one end of the DIP switch is further connected to the analog / digital converter chip, and one end of the resistor is further connected to the analog / digital converter chip.

8. A controller, characterized in that, The controller includes: a processor basic unit and a plurality of input / output expansion units as described in claim 7. The microprocessor inside the input / output expansion unit receives the control instructions issued by the processor basic unit through the backplane expansion bus.

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