Protection address determination method and circuit, protection method and circuit, and device

Abstract

The present disclosure relates to a hammer protection address determination method, a hammer protection address determination circuit, a hammer protection method, a hammer protection circuit, and an electronic device, and relates to the field of integrated circuit technology. The hammer protection address determination circuit includes: a comparison module for obtaining a current hammer damaged address when a hammer protection instruction is detected, and comparing the current hammer damaged address with a protected historical hammer damaged address; a selection determination module for determining a preset address in an array as a hammer protection address if the current hammer damaged address is the same as the historical hammer damaged address; and determining the current hammer damaged address as a hammer protection address if the current hammer damaged address is different from the historical hammer damaged address. The present disclosure provides a method for avoiding resource waste during hammer damaged address protection.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to a hammer protection address determination method, a hammer protection address determination circuit, a hammer protection method, a hammer protection circuit, and an electronic device. Background Art

[0002] In the application field of integrated circuits, the memory capacity in a memory chip is usually divided into multiple arrays for manufacturing, and the memory contains multiple logic arrays.

[0003] In practice, some arrays are vulnerable to row hammer attacks (bit flip attacks). Bit flip attacks exploit the interaction of electrons between adjacent memory cells, causing a cell's value to become erroneous after a sufficient number of accesses. These attacks are also known as hammer attacks. The addresses affected by the hammer attack are called hammer-damaged addresses.

[0004] For some arrays, the internal hammer-damaged addresses will be protected multiple times, resulting in a waste of internal resources.

[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field. Summary of the Invention

[0006] The purpose of the present disclosure is to provide a hammer protection address determination method, a hammer protection address determination circuit, a hammer protection method, a hammer protection circuit and an electronic device, so as to provide a method for avoiding resource waste in the process of hammer damaged address protection.

[0007] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by practice of the present disclosure.

[0008] According to a first aspect of the present disclosure, there is provided a hammer protection address determination circuit, comprising:

[0009] A comparison module is used to obtain a current hammer damaged address when a hammer protection instruction is detected, and compare the current hammer damaged address with a protected historical hammer damaged address;

[0010] A selection and determination module is used to determine the preset address in the array as the hammer protection address if the current hammer damaged address is the same as the historical hammer damaged address; if the current hammer damaged address is different from the historical hammer damaged address, determine the current hammer damaged address as the hammer protection address.

[0011] Optionally, also include:

[0012] A hammer damaged address determination module is used to determine an attack address in the array and determine a current hammer damaged address based on the attack address;

[0013] The hammer damaged address determination module is connected to the comparison module and is configured to provide the comparison module with the current hammer damaged address.

[0014] Optionally, the comparison module is used to compare the current hammer damaged address with the historical hammer damaged address; if the current hammer damaged address is the same as the historical hammer damaged address, a first signal is output; if the current hammer damaged address is different from the historical hammer damaged address, a second signal is output.

[0015] Optionally, also include:

[0016] A preset address providing module, used for providing a preset address;

[0017] The preset address is a redundant address in the array and / or a boundary address close to the redundant address.

[0018] Optionally, the preset address providing module and the hammer damaged address determining module are respectively connected to the selection determining module;

[0019] The selection and determination module is used to output the preset address provided by the preset address providing module when the output of the comparison module is the first signal; and to output the current hammer damaged address provided by the hammer damaged address determination module when the output of the comparison module is the second signal.

[0020] Optionally, the selection and determination module includes a first multiplexer; wherein,

[0021] The control end of the first multiplexer is connected to the output end of the comparison module, the first input end of the first multiplexer is connected to the output end of the hammer damaged address determination module, and the second input end of the first multiplexer is connected to the preset address providing module.

[0022] Optionally, the selection and determination module further includes a second multiplexer; wherein,

[0023] The control end of the second multiplexer is connected to the hammer enable signal provided by the hammer monitoring module, the first input end of the second multiplexer is connected to the output end of the first multiplexer, and the second input end of the second multiplexer is connected to the array address providing module;

[0024] The array address providing module is used to provide an address in the array.

[0025] Optionally, the hammer monitoring module includes a first NAND gate, a second NAND gate and a NOT gate; wherein,

[0026] The input end of the first NAND gate is connected to the activation instruction and the output signal of the second NAND gate;

[0027] The input end of the second NAND gate is connected to the refresh instruction and the output signal of the first NAND gate;

[0028] The input end of the NOT gate is connected to the output end of the first NAND gate, and the output end of the NOT gate outputs the hammering enable signal.

[0029] Optionally, the array address providing module is further configured to be connected to an input end of the hammer damaged address determining module.

[0030] Optionally, the hammer damaged address determination module includes a counting unit, a grabbing unit and a determination unit; wherein,

[0031] The counting unit is used to count the number of activation instructions and refresh instructions that appear in the array within a preset time;

[0032] The capture unit is used to determine the attack address in the array according to the statistically obtained number of activation instructions and the number of refresh instructions, and latch the attack address;

[0033] The determining unit is configured to determine the current hammer damaged address according to the latched attack address.

[0034] Optionally, the capture unit includes a connected comparator and a latch; wherein,

[0035] The comparator is used to compare the input activation instruction number and the refresh instruction number, so as to determine the address in the array whose access number exceeds a preset condition as the attack address;

[0036] The latch is used to latch the attack address determined by the comparator.

[0037] Optionally, the determining unit includes an operator; wherein,

[0038] The operator is used to perform addition and / or subtraction operations on the attack address to determine an address adjacent to the attack address in the array as the current hammer damaged address.

[0039] Optionally, the comparison module includes a plurality of latches, a plurality of XOR gates and an AND gate; wherein,

[0040] One XOR gate corresponds to one latch;

[0041] The input end of the XOR gate is connected to the output end of the latch and the output end of the hammer damaged address determination module, and the output end of the XOR gate is connected to the input end of the AND gate;

[0042] The AND gate is used to output the first signal when the current hammer damaged address is the same as the historical hammer damaged address; and output the second signal when the current hammer damaged address is different from the historical hammer damaged address.

[0043] According to a second aspect of the present disclosure, a method for determining a hammer protection address is provided, comprising:

[0044] When a hammer protection instruction is detected, a current hammer damaged address is obtained, and the current hammer damaged address is compared with a protected historical hammer damaged address;

[0045] If the current hammer damaged address is the same as the historical hammer damaged address, then determining the preset address in the array as the hammer protection address;

[0046] If the current hammer damaged address is different from the historical hammer damaged address, the current hammer damaged address is determined as the hammer protection address.

[0047] Optionally, before obtaining the current hammer-damaged address, the method further includes:

[0048] An attack address in the array is determined, and a current hammer damaged address is determined based on the attack address.

[0049] Optionally, determining the attack address in the array includes:

[0050] An address in the array whose access times exceed a preset condition is determined as the attack address.

[0051] Optionally, determining the current hammering damaged address according to the attack address includes:

[0052] An address adjacent to the attack address in the array is determined as the current hammer damaged address.

[0053] Optionally, the preset address is a redundant address in the array and / or a boundary address close to the redundant address.

[0054] According to a third aspect of the present disclosure, there is provided a hammer protection circuit comprising a refresh circuit and the above-mentioned hammer protection address determination circuit;

[0055] The output end of the hammer protection address determination circuit is connected to the input end of the refresh circuit, and the refresh circuit is used to perform a refresh operation on the hammer protection address output by the hammer protection address determination circuit.

[0056] According to a fourth aspect of the present disclosure, there is provided a hammer protection method, comprising:

[0057] Determine the hammer protection address according to the above-mentioned hammer protection address determination method;

[0058] The hammer protection address is refreshed and protected.

[0059] According to a fifth aspect of the present disclosure, there is provided an electronic device, including:

[0060] multiple arrays;

[0061] A plurality of array control units, each of which is provided with the above-mentioned hammer protection address determination circuit;

[0062] One array control unit corresponds to one array.

[0063] Optionally, the hammer monitoring module in the hammer protection address determination circuit is provided outside the array control unit;

[0064] A plurality of array control units share one hammer monitoring module.

[0065] The technical solution provided by the present disclosure may have the following beneficial effects:

[0066] The hammer protection address determination circuit provided in the exemplary embodiment of the present disclosure compares the current hammer damaged address and the historical hammer damaged address through a comparison module, and determines the current hammer damaged address as the hammer protection address only when the current hammer damaged address and the historical hammer damaged address are different; when the current hammer damaged address and the historical hammer damaged address are the same, the preset address is determined as the hammer protection address, thereby avoiding repeated protection of the hammer damaged address and avoiding protection of meaningless addresses, thereby improving resource utilization.

[0067] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0068] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort. In the drawings:

[0069] Figure 1 Schematically shows a schematic diagram of an internal array structure of a dynamic random access memory according to an exemplary embodiment of the present disclosure;

[0070] Figure 2 Schematically shows a block diagram of a hammer protection address determination circuit according to an exemplary embodiment of the present disclosure;

[0071] Figure 3 Schematically shows a structural diagram of a hammer protection address determination circuit according to an exemplary embodiment of the present disclosure;

[0072] Figure 4 Schematically shows a schematic diagram of a hammer-damaged address location according to an exemplary embodiment of the present disclosure;

[0073] Figure 5 Schematically shows another schematic diagram of the location of a hammer-damaged address according to an exemplary embodiment of the present disclosure;

[0074] Figure 6 Schematically shows a circuit structure diagram of a comparison module according to an exemplary embodiment of the present disclosure;

[0075] Figure 7 Schematically shows a structural diagram of another hammer protection address determination circuit according to an exemplary embodiment of the present disclosure;

[0076] Figure 8 Schematically shows a circuit structure diagram of a hammer damaged address determination module according to an exemplary embodiment of the present disclosure;

[0077] Figure 9 Schematically shows a circuit structure diagram of a hammer monitoring module according to an exemplary embodiment of the present disclosure;

[0078] Figure 10 Schematically shows Figure 9 The schematic diagram of the signal waveform corresponding to the circuit of the hammer monitoring module shown;

[0079] Figure 11 A flowchart of a method for determining a hammer protection address according to an exemplary embodiment of the present disclosure is schematically shown;

[0080] Figure 12 A flowchart of a hammer protection method according to an exemplary embodiment of the present disclosure is schematically shown;

[0081] Figure 13 The figure schematically shows a structural diagram of an electronic device according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0082] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the drawings represent like or similar parts, and thus repetitive description thereof will be omitted.

[0083] In addition, the described features, structures or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure can be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. can be adopted. In other cases, well-known structures, methods, devices, implementations, materials or operations are not shown or described in detail to avoid obscuring various aspects of the present disclosure.

[0084] The blocks shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically separate entities. Specifically, these functional entities may be implemented in software, or in one or more software-hardened modules, or in different networks and / or processor devices and / or microcontroller devices.

[0085] Inside the chip, memory data is written into a matrix in bits. Each unit is called a CELL. By specifying a row and a column, you can accurately locate a CELL. This is the basic principle of memory chip addressing.

[0086] This array is typically referred to as a memory chip's bank, also known as a logical bank. Due to manufacturing limitations, this array cannot be made too large, so memory chips are typically manufactured by dividing the memory capacity into several banks. As chip capacity continues to increase, the number of logical banks also increases.

[0087] Reference Figure 1, shows a schematic diagram of the internal array structure of a dynamic random-access memory (DRAM). Figure 1 In this example, the DRAM has 16 banks, designated BANK0 through BANK15. BANK0 through BANK3 form the first bank group (Bank Group 0); BANK4 through BANK7 form the second bank group (Bank Group 1); BANK8 through BANK11 form the third bank group (Bank Group 2); and BANK12 through BANK15 form the fourth bank group (Bank Group 3).

[0088] Sixteen array control units 110 and a hammer monitoring module 120 are provided on the external circuits of the four array groups, namely the first array group, the second array group, the third array group and the fourth array group. BankCtrl0-BankCtrl15 in the figure represent the 16 array control units 110, and BankCtrl0 is connected to BANK0 for controlling BANK0; BankCtrl1 is connected to BANK1 for controlling BANK1; and so on, BankCtrl15 is connected to BANK15 for controlling BANK15.

[0089] Furthermore, the hammer monitoring module 120 in the external circuit is connected to the 16 array control units 110. Upon detecting a hammer protection command, it simultaneously provides a hammer protection enable signal RH_EN to all 16 array control units 110. Upon receiving the hammer protection enable signal RH_EN, each of the 16 array control units 110 provides hammer-damaged addresses and inputs them to the corresponding arrays 130 for protection, preventing bit flips at these addresses.

[0090] In actual applications, some cells in the array may be subject to multiple hammer attacks, causing one or more addresses in the array to be repeatedly and unnecessarily protected under the hammer protection enable signal RH_EN, resulting in a waste of internal DRAM resources. For example, if the interval between two consecutive protections for a certain address is short, even if it is subjected to multiple hammer attacks, the probability of a bit flip is very small, and repeatedly protecting this address is simply a waste of resources.

[0091] Based on this, an exemplary embodiment of the present disclosure provides a hammer protection address determination circuit. Figure 2 The hammer protection address determination circuit 200 includes: a comparison module 220 and a selection determination module 240; wherein,

[0092] The comparison module 220 is used to obtain the current hammer damaged address when a hammer protection instruction is detected, and compare the current hammer damaged address with the protected historical hammer damaged address.

[0093] As shown above, in actual applications, the hammer monitoring module 120 is usually set in the external circuit to monitor the hammer protection instruction and provide the hammer protection enable signal RH_EN to multiple array control units 110. After receiving the hammer protection enable signal RH_EN, the array control unit 110 will obtain the current hammer damaged address.

[0094] Reference Figure 3 The current hammer damaged address is determined by the hammer damaged address determination module 310. Specifically, the hammer damaged address determination module 310 can be used to determine the attack address in the array and determine the current hammer damaged address according to the attack address.

[0095] In the exemplary embodiments of the present disclosure, an attack address refers to a frequently accessed address in the array. Due to the frequent access of the attack address, the attack address may affect adjacent addresses and even cause bit flips due to the mutual influence of electrons. To prevent bit flips from occurring, it is necessary to determine the current hammer-damaged address that may be attacked in advance based on the attack address so that refresh protection can be applied to the current hammer-damaged address before a bit flip occurs due to the attack.

[0096] In the exemplary embodiment of the present disclosure, the hammer damaged address determination module 310 is connected to the comparison module 220 , and the hammer damaged address determination module 310 can provide the comparison module 220 with the current hammer damaged address.

[0097] Every time a hammer attack occurs, the hammer damaged address determination module 310 will determine a hammer damaged address that needs to be protected and provide it to the comparison module 220. The comparison module 220 will store these protected historical hammer damaged addresses and compare them with the current hammer damaged address provided later.

[0098] It should be noted that the current hammer damaged address here is mainly to distinguish it from the historical hammer damaged address, and refers to the hammer damaged address determined before the hammer protection is performed under the current hammer protection instruction.

[0099] In practical applications, an address adjacent to the attack address can be determined as the current hammering damaged address based on actual circumstances. In the exemplary embodiment of the present disclosure, an address immediately adjacent to the attack address can be determined as the current hammering damaged address, or an adjacent address that is one address away from the attack address can be determined as the current hammering damaged address, etc., and the exemplary embodiment of the present disclosure does not specifically limit this.

[0100] Reference Figure 4 and Figure 5 As shown, in Figure 4 In the example, the first address 401 is a frequently accessed address, and the second address 402 and the third address 403 are hammer damaged addresses adjacent to the first address 401 and may be affected by the first address 401 and may have bit flips. Figure 5 In the example, if the first address 401 is repaired by the fourth address 501, the fifth address 502 and the sixth address 503 adjacent to the fourth address 501 will become hammer damaged addresses. In other words, the address repaired by the attack address will become a new attack address, and the addresses adjacent to the new attack address will also become hammer damaged addresses, which also has the risk of bit flipping.

[0101] In an exemplary embodiment of the present disclosure, in the process of determining an attack address, an address in the array whose access times exceed a preset condition may be determined as an attack address.

[0102] In actual applications, the preset condition can be determined according to actual needs. For example, the preset condition can be a condition that the number of accesses within two adjacent refresh intervals exceeds the preset number of accesses. In adjacent refresh intervals, if the number of accesses to a certain address exceeds the preset number of accesses, the address is considered to be an attack address, and its adjacent addresses may be hammered by the attack address and undergo bit flipping. The preset number of accesses can be, for example, 150-1500 times or other times. For example, in two adjacent refresh intervals, if the number of accesses to a certain address in the array exceeds the above-mentioned 1500 times, the address is determined to be an attack address. It should be noted that the preset condition can also be other conditions, and the exemplary embodiments of the present disclosure do not specifically limit this.

[0103] After the comparison module 220 compares the current hammer damaged address with the protected historical hammer damaged address, it can output a comparison result, for example, the same result or a different result.

[0104] The selection and determination module 240 can be used to determine the preset address in the array as the hammer protection address if the current hammer damaged address is the same as the historical hammer damaged address; if the current hammer damaged address is different from the historical hammer damaged address, determine the current hammer damaged address as the hammer protection address.

[0105] In an exemplary embodiment of the present disclosure, Figure 3 As shown, the preset address is provided by the preset address providing module 330, and the preset address providing module 330 provides the address in the array where it is located.

[0106] Specifically, the preset address may be a redundant address in the array, or a boundary address close to the redundant address.

[0107] In reality, an array contains both normal addresses and redundant addresses, with the redundant addresses used to repair damaged normal addresses. Typically, during the address refresh protection process, the normal addresses are refreshed first, followed by the redundant addresses. This creates the possibility of data loss due to untimely redundant address refreshes. Therefore, in an exemplary embodiment of the present disclosure, the redundant address is determined as a preset address. This allows the redundant address to be refreshed when the current hammer-damaged address is the same as the historical hammer-damaged address. This avoids the waste of resources caused by repeatedly refreshing the same hammer-damaged address and reduces the probability of data loss at the redundant address.

[0108] In addition, the boundary address close to the redundant address, that is, the address at the junction of the normal address and the redundant address, is usually an address that is prone to bit flipping. Therefore, when the current hammer-damaged address is the same as the historical hammer-damaged address, refreshing the boundary address can also achieve the purpose of saving resources and improving resource utilization.

[0109] In an exemplary embodiment of the present disclosure, when the current hammer damaged address is different from the historical hammer damaged address, the current hammer damaged address is determined as the hammer protection address and protected to prevent bit flipping.

[0110] In practical applications, there are usually two types of arrays: the target array that is subject to hammer attacks and the non-target array that is not subject to hammer attacks. For the target array, there are real attack addresses that are frequently accessed many times. The corresponding hammer-damaged addresses can be determined based on these real attack addresses.

[0111] In other words, the target array can provide a valid hammer-damaged address for protection. However, the non-target array does not contain any truly frequently accessed attack addresses. Therefore, driven by the hammer protection enable signal RH_EN, the non-target array can only provide a meaningless hammer-damaged address. Protecting this meaningless hammer-damaged address is wasteful; if this situation accumulates within the DRAM, it will significantly waste internal DRAM resources.

[0112] In the exemplary embodiment of the present disclosure, for a non-target array, the current hammer-damaged address determined by the hammer-damaged address determination module 310 is generally an initial reset address, which is equivalent to an empty address. After the initial reset address is input into the comparison module 220, since there is also an empty address similar to the initial reset address in the comparison module 220, the two empty addresses will be determined by the comparison module 220 as the same address. Therefore, for the non-target array, a preset address with practical significance is ultimately provided as the hammer protection address, thereby avoiding the waste of resources caused by protecting addresses with no practical significance, and also having the effect of improving resource utilization.

[0113] The hammer protection address determination circuit provided in the exemplary embodiment of the present disclosure compares the current hammer damaged address and the historical hammer damaged address through a comparison module, and determines the current hammer damaged address as the hammer protection address only when the current hammer damaged address and the historical hammer damaged address are different; when the current hammer damaged address and the historical hammer damaged address are the same, the preset address is determined as the hammer protection address, thereby avoiding repeated protection of the hammer damaged address and avoiding protection of meaningless addresses, thereby improving resource utilization.

[0114] The following is a detailed description of the internal structure of each module involved in the above-mentioned hammer protection address determination circuit:

[0115] In the exemplary embodiment of the present disclosure, the comparison module 220 is primarily used to compare the current hammer damaged address with the historical hammer damaged address; if the current hammer damaged address is the same as the historical hammer damaged address, a first signal is output; if the current hammer damaged address is different from the historical hammer damaged address, a second signal is output. The first signal and the second signal are different signals. For example, when the first signal is a high level 1 signal, the second signal is a low level 0 signal; when the first signal is a low level 0 signal, the second signal is a high level 1 signal, thereby achieving the purpose of distinguishing.

[0116] Reference Figure 6As shown, the comparison module 220 may include multiple latches 221, multiple XOR gates 222 and an AND gate 223; wherein, one latch 221 corresponds to one XOR gate 222, and the input end of the XOR gate 222 is connected to the output end of the latch 221 and the output end of the hammer damaged address determination module 310, and the output end of the XOR gate 222 is connected to the input end of the AND gate 223.

[0117] The AND gate 223 is configured to output a first signal when the current hammer damaged address is the same as the historical hammer damaged address; and output a second signal when the current hammer damaged address is different from the historical hammer damaged address.

[0118] In actual applications, if the current hammer-damaged address input from the hammer-damaged address determination module 310 is different from the historical hammer-damaged addresses stored in the multiple latches 221, the above addresses will all output a high-level 1 signal after passing through the XOR gate 222. For the AND gate 223, when all its inputs are high-level 1 signals, the output of the AND gate 223 is also a high-level 1 signal, which is equivalent to the output of the comparison module 220 being a high-level 1 signal.

[0119] In actual applications, if the current hammer-damaged address input from the hammer-damaged address determination module 310 is the same as the historical hammer-damaged address stored in one of the latches 221, the two addresses will output a low-level 0 signal after passing through the aforementioned XOR gate 222. For the AND gate 223, as long as one of the inputs is a low-level 0 signal, the output of the AND gate 223 is a low-level 0 signal, which is equivalent to the comparison module 220 outputting a low-level 0 signal.

[0120] above Figure 6 The comparison module 220 is shown as an example in which, when the current hammer damage address is the same as the historical hammer damage address, the first signal output is a low-level 0 signal; and when the current hammer damage address is different from the historical hammer damage address, the second signal output is a high-level 1 signal. In actual applications, there are also examples in which, when the current hammer damage address is the same as the historical hammer damage address, the first signal output is a high-level 1 signal; and when the current hammer damage address is different from the historical hammer damage address, the second signal output is a low-level 0 signal, which are not listed here one by one.

[0121] In actual applications, the selection determination module 240 can be determined according to actual needs. In the exemplary embodiment of the present disclosure, refer to Figure 3As shown, the selection and determination module 240 may include a first multiplexer 241 and a second multiplexer 242, wherein the control end of the first multiplexer 241 is connected to the output end of the comparison module 220, the first input end of the first multiplexer 241 is connected to the output end of the hammer damaged address determination module 310, and the second input end of the first multiplexer 241 is connected to the preset address providing module 330.

[0122] In actual applications, when the first signal output by the comparison module 220 is a high-level 1 signal and the second signal is a low-level 0 signal, it is equivalent to outputting a high-level 1 signal when the current hammer damaged address is the same as the historical hammer damaged address, and outputting a low-level 0 signal when the current hammer damaged address is different from the historical hammer damaged address. In order for the first multiplexer 241 to output the current hammer damaged address when the comparison module 220 outputs a low-level 0 signal, the first input terminal connected to the output terminal of the hammer damaged address determination module 310 needs to be a 0 input terminal, and the second input terminal connected to the preset address providing module 330 needs to be a 1 input terminal, as shown in FIG. Figure 3 shown.

[0123] On the contrary, when the first signal output by the comparison module 220 is a low-level 0 signal and the second signal is a high-level 1 signal, it is equivalent to outputting a low-level 0 signal when the current hammer damaged address is the same as the historical hammer damaged address, and outputting a high-level 1 signal when the current hammer damaged address is different from the historical hammer damaged address. In order for the first multiplexer 241 to output the current hammer damaged address when the comparison module 220 outputs a high-level 1 signal, the first input terminal connected to the output terminal of the hammer damaged address determination module 310 needs to be a 1 input terminal, and the second input terminal connected to the preset address providing module 330 needs to be a 0 input terminal, as shown in FIG. Figure 7 shown.

[0124] In the exemplary embodiment of the present disclosure, the control terminal of the second multiplexer 242 is connected to the hammer enable signal provided by the hammer monitoring module 120, the first input terminal of the second multiplexer 242 is connected to the output terminal of the first multiplexer 241, and the second input terminal of the second multiplexer 242 is connected to the array address providing module 350. The array address providing module 350 is used to provide addresses in the array.

[0125] In actual application, when the hammer enable signal acts on the second multiplexer 242, if the signal output from the output end of the first multiplexer 242 is to be output, the first input end of the second multiplexer 242 needs to be the same level signal as the hammer enable signal.

[0126] When the hammer enable signal is a high enable signal, the first input terminal of the second multiplexer 242 is a 1 input terminal, and the second input terminal of the second multiplexer 242 is a 0 input terminal, so that when there is no hammer enable signal, the second multiplexer 242 can normally output the address in the array to facilitate conventional memory access operations, such as Figure 3 shown.

[0127] When the hammer enable signal is a low enable signal, the first input terminal of the second multiplexer 242 is a 0 input terminal, and the second input terminal of the second multiplexer 242 is a 1 input terminal, so that when there is no hammer enable signal, the second multiplexer 242 can normally output the address in the array to facilitate conventional memory access operations, such as Figure 7 shown.

[0128] In practical applications, the hammer damaged address determination module 310 can be determined according to specific preset conditions. Figure 8 As shown, the hammer-damaged address determination module 310 may include a counting unit 311, a capture unit 313, and a determination unit 315. The counting unit 311 is configured to count the number of activation instructions and refresh instructions that appear in the array within a preset time. The counting unit 311 includes multiple counters. The inputs of the counting unit 311 are connected to activation instructions and refresh instructions. The counting unit 311 can calculate the number of activation instructions between two refresh instructions and send the counted number to the capture unit 313.

[0129] Capture unit 313 is used to determine an attack address in the array based on the number of activation instructions and refresh instructions counted by counting unit 311, and latch the attack address. Specifically, the attack address is determined based on a preset condition. For example, if the preset condition is that an address in the array that has been accessed more than 1500 times between two adjacent refresh instructions is an attack address, that is, an address that has received more than 1500 activation instructions between two adjacent refresh instructions is an attack address. Capture unit 313 can then determine the attack address based on the counted number of activation instructions and refresh instructions, and send the determined attack address to determination unit 315.

[0130] In actual applications, the capture unit may include a connected comparator and a latch; wherein the comparator can be used to compare the number of activation instructions and the number of refresh instructions input to determine the address in the array that has been accessed more than a preset condition as the attack address; the latch can be used to latch the attack address determined by the comparator and provide it to the determination unit 315 according to actual needs.

[0131] In an exemplary embodiment of the present disclosure, the determination unit 315 is configured to determine the current hammer-damaged address based on the latched attack address. Typically, the hammer-damaged address affected by the attack address is an address adjacent to the attack address. Therefore, in an exemplary embodiment of the present disclosure, the determination unit 315 may include an arithmetic unit configured to perform addition and / or subtraction operations on the attack address to determine an address adjacent to the attack address in the array as the current hammer-damaged address.

[0132] As shown above, the hammer monitoring module 120 is provided on the external circuit of the array, and the hammer monitoring module 120 is used to provide the array with a hammer protection enable signal RH_EN when a hammer protection instruction is detected. Figure 9 As shown, the hammer monitoring module 120 includes a first NAND gate 122, a second NAND gate 124 and a NOT gate 126; wherein, the input end of the first NAND gate 122 is connected to the activation instruction and the output signal of the second NAND gate 124; the input end of the second NAND gate 124 is connected to the refresh instruction and the output signal of the first NAND gate 122; the input end of the NOT gate 126 is connected to the output end of the first NAND gate 122, and the output end of the NOT gate 126 outputs the hammer enable signal.

[0133] Reference Figure 10 As shown, when the signal is a low enable signal, when the activation instruction input to the input end of the first NAND gate 122 generates the signal ACT_CMD, the first NAND gate 122 generates a high-level 1 signal. After the high-level 1 signal passes through the NOT gate 126, it generates a hammer enable signal. If the refresh instruction input end of the second NAND gate 124 generates a low-level 0 signal REF_CMD, the second NAND gate 124 will output a high-level 1 signal. At this time, the activation instruction ACT_CMD is also a high-level 1 signal. After these two high-level 1 signals are input to the first NAND gate 122, the first NAND gate 122 will generate a low-level 0 signal, resulting in the signal output from the NOT gate 126 being a high-level 1 signal, achieving the effect of turning off the hammer enable signal RH_EN. In other words, the hammer enable signal RH_EN acts between adjacent activation instructions and refresh instructions. After the activation instruction triggers the hammer enable signal, as long as a refresh instruction is generated, the hammer enable signal will terminate.

[0134] In practical applications, the preset address providing module 330 may be a latch that pre-latches the preset address in the corresponding array, and is connected to the first multiplexer 241 to provide the preset address.

[0135] In practical applications, the array address providing module 350 is used to identify and provide addresses in the array. In the exemplary embodiment of the present disclosure, the array address providing module 350 is connected to the hammer damaged address determining module 310 and the second multiplexer 242 .

[0136] In addition, if Figure 3 As shown, the hammer protection address determination circuit provided in the exemplary embodiment of the present disclosure further includes a row address decoder 370, the input end of which is connected to the output end of the second multiplexer 242, and is used to decode the address output by the second multiplexer 242. Finally, the decoded address is input into the array and refresh protected in the array.

[0137] The exemplary embodiment of the present disclosure also provides a method for determining a hammer protection address. Figure 11 The hammer protection address determination method may specifically include the following steps:

[0138] Step S112: when a hammer protection instruction is detected, obtaining a current hammer damaged address, and comparing the current hammer damaged address with a protected historical hammer damaged address;

[0139] Step S114: If the current hammer-damaged address is the same as the historical hammer-damaged address, the preset address in the target array is determined as the hammer protection address;

[0140] Step S116: If the current hammer damaged address is different from the historical hammer damaged address, the current hammer damaged address is determined as the hammer protection address.

[0141] In some embodiments of the present disclosure, before obtaining the current hammer damaged address, the hammer protection address determination method may further include: determining an attack address in the array, and determining the current hammer damaged address according to the attack address.

[0142] In some embodiments of the present disclosure, determining the attack address in the array may include: determining an address in the array whose access times exceed a preset condition as the attack address.

[0143] In some embodiments of the present disclosure, determining the current hammer damaged address according to the attack address may include: determining an address adjacent to the attack address in the array as the current hammer damaged address.

[0144] In some embodiments of the present disclosure, the preset address may be a redundant address in the array and / or a boundary address close to the redundant address.

[0145] The hammer protection address determination method provided by the exemplary embodiment of the present disclosure can compare the current hammer-damaged address with the historical hammer-damaged address that has been protected when a hammer protection instruction is detected. If the two addresses are the same, the preset address is determined as the hammer protection address for protection; if the two addresses are different, the current hammer-damaged address is determined as the hammer protection address for protection. This can avoid repeatedly protecting the same hammer-damaged address multiple times, and by determining the preset address as the hammer protection address, addresses that would normally be ignored can be protected, thereby improving the practicality of hammer address protection, reducing unnecessary data waste, and improving data utilization.

[0146] The specific details of each step in the above-mentioned hammer protection address determination method have been described in detail in the corresponding hammer protection address determination circuit, so they will not be repeated here.

[0147] The exemplary embodiments of the present disclosure further provide a hammer protection circuit, comprising a refresh circuit and the aforementioned hammer protection address determination circuit. The output of the hammer protection address determination circuit is connected to the input of the refresh circuit, and the refresh circuit is configured to perform a refresh operation on the hammer protection address output by the hammer protection address determination circuit. The hammer protection address determined by the hammer protection address determination circuit can be refresh protected in the refresh circuit. The refresh circuit primarily performs a refresh read operation on the hammer protection address. In practical applications, reference can be made to conventional circuits for performing refresh operations, and the specific structure of the refresh circuit is not particularly limited herein.

[0148] In the exemplary embodiment of the present disclosure, the specific structural form of the hammer protection address determination circuit in the hammer protection circuit has been described in detail in the above embodiment, and thus will not be repeated here.

[0149] The exemplary embodiment of the present disclosure also provides a hammer protection method, referring to Figure 12 The hammer protection method may specifically include the following steps:

[0150] Step S121: determining a hammer protection address according to the above-mentioned hammer protection address determination method;

[0151] Step S123: Refresh protection on the hammer protection address.

[0152] The specific details of each step in the above-mentioned hammer protection method have been described in detail in the corresponding hammer protection address determination method and hammer protection circuit, so they will not be repeated here.

[0153] The exemplary embodiment of the present disclosure further provides an electronic device, Figure 13As shown, the electronic device may include: multiple arrays 1310 and multiple array control units 1330, with one array control unit 1330 corresponding to each array 1310. Each array control unit 1330 is provided with the aforementioned hammer protection address determination circuit, which is used to determine the hammer protection address in the corresponding array 1310. The specific structural details of the hammer protection address determination circuit have been described in detail in the above embodiment and will not be repeated here.

[0154] It should be noted that the hammer monitoring module 120 in the above-mentioned hammer protection address determination circuit is set outside the array control unit 1330; and multiple array control units 1330 share one hammer monitoring module 120, which is used to provide the array control unit 1330 with a hammer protection enable signal RH_EN.

[0155] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using a software program, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present disclosure is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that can be integrated with one or more media. The available medium can be a magnetic medium (for example, a floppy disk, a hard disk, a tape), an optical medium (for example, a DVD), or a semiconductor medium (for example, a solid state disk (SSD)). In the embodiment of the present disclosure, the computer may include the device described above.

[0156] Although the present disclosure is described herein in conjunction with various embodiments, in the process of implementing the disclosure for which protection is sought, those skilled in the art may understand and implement other variations of the disclosed embodiments by reviewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude multiple components. A single processor or other unit may implement several functions listed in the claims. The fact that certain measures are recorded in mutually different dependent claims does not mean that these measures cannot be combined to produce good results.

[0157] Although the present disclosure has been described with reference to specific features and embodiments thereof, it will be apparent that various modifications and combinations may be made thereto without departing from the spirit and scope of the present disclosure. Accordingly, this specification and the drawings are merely illustrative of the present disclosure as defined by the appended claims and are deemed to cover any and all modifications, variations, combinations or equivalents within the scope of the present disclosure. Obviously, those skilled in the art may make various modifications and variations to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, the present disclosure is intended to encompass such modifications and variations if they fall within the scope of the claims of the present disclosure and their equivalents.

Claims

1. A hammer protection address determination circuit, characterized in that: include: A comparison module is used to obtain a current hammer damaged address when a hammer protection instruction is detected, and compare the current hammer damaged address with a protected historical hammer damaged address; A preset address providing module, configured to provide a preset address; wherein the preset address is a redundant address in the array and / or a boundary address close to the redundant address; A selection and determination module is used to determine the preset address in the array as the hammer protection address if the current hammer damaged address is the same as the historical hammer damaged address; if the current hammer damaged address is different from the historical hammer damaged address, determine the current hammer damaged address as the hammer protection address.

2. The hammer protection address determination circuit according to claim 1, characterized in that: Also includes: A hammer damaged address determination module is used to determine an attack address in the array and determine a current hammer damaged address based on the attack address; The hammer damaged address determination module is connected to the comparison module and is configured to provide the comparison module with the current hammer damaged address.

3. The hammer protection address determination circuit according to claim 2, characterized in that: The comparison module is used to compare the current hammer damaged address with the historical hammer damaged address; if the current hammer damaged address is the same as the historical hammer damaged address, a first signal is output; if the current hammer damaged address is different from the historical hammer damaged address, a second signal is output.

4. The hammer protection address determination circuit according to claim 3, characterized in that: The preset address providing module and the hammer damaged address determining module are respectively connected to the selection determining module; The selection and determination module is configured to output the preset address provided by the preset address providing module when the output of the comparison module is the first signal; When the output of the comparison module is the second signal, the current hammer damaged address provided by the hammer damaged address determination module is output.

5. The hammer protection address determination circuit according to claim 4, characterized in that: The selection and determination module includes a first multiplexer; wherein, The control end of the first multiplexer is connected to the output end of the comparison module, the first input end of the first multiplexer is connected to the output end of the hammer damaged address determination module, and the second input end of the first multiplexer is connected to the preset address providing module.

6. The hammer protection address determination circuit according to claim 5, characterized in that: The selection and determination module also includes a second multiplexer; wherein, The control end of the second multiplexer is connected to the hammer enable signal provided by the hammer monitoring module, the first input end of the second multiplexer is connected to the output end of the first multiplexer, and the second input end of the second multiplexer is connected to the array address providing module; The array address providing module is used to provide an address in the array.

7. The hammer protection address determination circuit according to claim 6, characterized in that: The hammer monitoring module includes a first NAND gate, a second NAND gate and a NOT gate; wherein, The input end of the first NAND gate is connected to the activation instruction and the output signal of the second NAND gate; The input end of the second NAND gate is connected to the refresh instruction and the output signal of the first NAND gate; The input end of the NOT gate is connected to the output end of the first NAND gate, and the output end of the NOT gate outputs the hammering enable signal.

8. The hammer protection address determination circuit according to claim 6, characterized in that: The array address providing module is further configured to be connected to an input end of the hammer damaged address determining module.

9. The hammer protection address determination circuit according to any one of claims 2 to 8, characterized in that: The hammer damaged address determination module includes a counting unit, a grabbing unit and a determination unit; wherein, The counting unit is used to count the number of activation instructions and refresh instructions that appear in the array within a preset time; The capture unit is used to determine the attack address in the array according to the statistically obtained number of activation instructions and the number of refresh instructions, and latch the attack address; The determining unit is configured to determine the current hammer damaged address according to the latched attack address.

10. The hammer protection address determination circuit according to claim 9, characterized in that: The capture unit includes a connected comparator and a latch; wherein, The comparator is used to compare the input activation instruction number and the refresh instruction number, so as to determine the address in the array whose access number exceeds a preset condition as the attack address; The latch is used to latch the attack address determined by the comparator.

11. The hammer protection address determination circuit according to claim 9, characterized in that: The determining unit includes an operator; wherein, The operator is used to perform addition and / or subtraction operations on the attack address to determine an address adjacent to the attack address in the array as the current hammer damaged address.

12. The hammer protection address determination circuit according to claim 3, characterized in that: The comparison module includes a plurality of latches, a plurality of XOR gates and an AND gate; wherein, One XOR gate corresponds to one latch; The input end of the XOR gate is connected to the output end of the latch and the output end of the hammer damaged address determination module, and the output end of the XOR gate is connected to the input end of the AND gate; The AND gate is used to output the first signal when the current hammer damaged address is the same as the historical hammer damaged address; and output the second signal when the current hammer damaged address is different from the historical hammer damaged address.

13. A method for determining a hammer protection address, characterized in that: include: When a hammer protection instruction is detected, a current hammer damaged address is obtained, and the current hammer damaged address is compared with a protected historical hammer damaged address; If the current hammer damaged address is the same as the historical hammer damaged address, a preset address in the array is determined as the hammer protection address, wherein the preset address is a redundant address in the array and / or a boundary address close to the redundant address; If the current hammer damaged address is different from the historical hammer damaged address, the current hammer damaged address is determined as the hammer protection address.

14. The method for determining a hammer protection address according to claim 13, wherein: Before obtaining the current hammer damaged address, the method further includes: An attack address in the array is determined, and a current hammer damaged address is determined based on the attack address.

15. A hammer protection circuit, characterized in that: comprising a refresh circuit and a hammer protection address determination circuit according to any one of claims 1 to 12; The output end of the hammer protection address determination circuit is connected to the input end of the refresh circuit, and the refresh circuit is used to perform a refresh operation on the hammer protection address output by the hammer protection address determination circuit.

16. A hammer protection method, characterized in that: include: Determining a hammer protection address according to the hammer protection address determination method according to any one of claims 13-14; The hammer protection address is refreshed and protected.

17. An electronic device, characterized in that: include: multiple arrays; A plurality of array control units, each of which is provided with a hammer protection address determination circuit according to any one of claims 1 to 12; One array control unit corresponds to one array.

18. The electronic device according to claim 17, wherein: The hammer monitoring module in the hammer protection address determination circuit is arranged outside the array control unit; A plurality of array control units share one hammer monitoring module.

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