Unique chip identifiers exploiting unclonable characteristics of on-chip resistive memory arrays

Abstract

A semiconductor device is disclosed, comprising a plurality of two-terminal resistive switching devices (420), wherein electrodes (322) in contact with a resistive switching layer (324) have a root mean square surface roughness (425, 427) greater than 2 nm, and the correlation coefficient of the intrinsic characteristics of two resistive switching devices is in the range of -0.1 to 0.1. The random physical characteristics of the resistive switching devices on the semiconductor chip can be used to generate unique data for electronic identification of the semiconductor chip, to verify communication with the semiconductor chip, or to generate encryption keys.

Description

[0001] This case is a divisional application. The parent application was filed on April 6, 2021, with the invention title "Unique Chip Identifier Utilizing the Unclonable Characteristics of On-Chip Resistive Memory Arrays" and application number 2021800066064.

[0002] Cross-reference to related applications

[0003] This patent application claims the benefit of priority to U.S. Provisional Application No. 63 / 005879, filed April 6, 2020, entitled “Resistive Random Access Device, System, and Manufacturing Technique,” ​​the entire contents of which are incorporated herein by reference for all purposes. Technical Field

[0004] This disclosure generally relates to two-terminal resistor-switched memories, and as an exemplary example, uses the random characteristics of resistor-switching devices to uniquely identify chips. Background Technology

[0005] Resistive switched memories (RSMs) represent a cutting-edge innovation in the field of integrated circuit technology. While various RSM technologies are still under development, numerous technical concepts have been demonstrated and are in one or more validation phases to prove or refute related theories or technologies. In the near future, RSM technology is expected to demonstrate strong evidence of a significant advantage over competing technologies in the semiconductor electronics industry.

[0006] Proposals have been made to practically apply resistive switching technology to memory applications in electronic devices. For example, resistive switching elements are often considered, at least in part, a viable alternative in theory to metal-oxide-semiconductor (MOS) type memory transistors used for electronic storage of digital information. For instance, resistive switching memory devices offer several potential technological advantages over non-volatile flash memory MOS type transistors.

[0007] In view of the above, the assignee of this disclosure continues to develop and dedicate himself to the practical application of resistive switching technology. Summary of the Invention

[0008] The following is a simplified summary of the invention to provide a basic understanding of certain aspects of this specification. This summary is not a broad overview of the specification. It is intended neither to define the key or essential elements of the specification, nor to describe the scope of any particular embodiment or any scope of the claims. Its purpose is to present some concepts of the specification in a simplified form as a prelude to the specific embodiments presented in this disclosure.

[0009] Embodiments of this disclosure provide methods for generating unique data for resistive switching devices using the physical characteristics of these devices. This unique data can be used for various purposes related to electronic identification. As an example, data generated from the physical characteristics of resistive switching devices on a semiconductor chip can be used to form a unique identifier sequence for that semiconductor chip.

[0010] In further embodiments, this disclosure provides physical characteristics of resistive switching devices that may have or can be manufactured to have random or substantially random characteristics. Furthermore, these physical characteristics can produce different measurable unique characteristics between adjacent resistive switching devices (or other suitable groups) on an array, between different resistive switching devices on a semiconductor die, between different resistive switching devices on one or more wafers, or combinations of such groups. Additionally, physical characteristics are provided to produce consistent measurements of a given resistive switching device or group of devices through multiple measurements under different temperatures or different operating conditions. Therefore, the unique data generated by these measurements can be reliably reproduced over multiple measurement cycles under various operating conditions. As disclosed herein, this further achieves a very low error rate when reproducing the unique identifier sequence derived from the resistive switching device.

[0011] Another embodiment discloses a variety of measurable unique characteristics of a resistive switching device that can be used to generate unique identifier data. Examples include the raw leakage current of a device or a group of devices, the raw resistance of a device, the raw switching speed of a device, the raw programming voltage of a device, the differential programming speed of multiple groups of devices, the differential programming voltage of multiple groups of devices, and other examples disclosed herein, or that may be known in the art, or that are reasonably conveyed to those skilled in the art by the context provided herein.

[0012] In a further embodiment, the measurement process used to generate identifier data from the resistive switching device can be permanentized to minimize or avoid errors when regenerating the identifier data. For example, a measurement process based partly or entirely on program events of the resistive switching device may include a process for permanentizing the program events for the resistive switching device. As an example, after the measurement process that associates identifier data with program events of the resistive switching device, a programming process suitable for forming a one-time programmable resistive switching device can be utilized. Even over multiple read cycles, making the resistive switching device one-time programmable contributes to a longer lifespan when recalling the identifier data associated with the measurement process, even across a wide temperature range and other conditions (e.g., electromagnetic radiation at X-ray or gamma frequencies) that may interfere with the program events of the resistive switching device.

[0013] In another embodiment, an electronic device is disclosed that facilitates the generation of unique (e.g., distinctive) identifier data for a semiconductor chip post-manufacturing. Unique identifier data can be derived through measurable processes associated with the random or substantially random physical characteristics of resistive switching devices manufactured within the semiconductor chip. In some embodiments, the electronic device may facilitate selection among multiple measurable processes of the resistive switching devices to generate identifier data for the semiconductor chip. In other embodiments, the electronic device may facilitate selection of a subset of resistive switching devices on the semiconductor chip for use in measurable processes. In further embodiments, the electronic device may facilitate specifying different subsets of the array of resistive switching devices for different purposes (including rewritable nonvolatile memory, one-time programmable (non-rewritable) memory, or identifier devices for generating identifier data for the semiconductor chip). In a further embodiment, the electronic device may provide a combination of the aforementioned processes. By allowing post-manufacturing selection of a portion of the array to generate identifier data, the identifier data can be opaque even to the semiconductor chip manufacturer, thereby providing subsequent users (e.g., purchasers, licensees, sub-licensees, etc.) with a high degree of security regarding the identifier data and preventing unauthorized access, unauthorized intrusion, cloning, etc.

[0014] The following description and accompanying drawings illustrate certain exemplary aspects of this specification. However, these aspects only indicate some of the various ways in which the principles of this specification can be used. Other advantages and novel features of this specification will become apparent from the following detailed description when considered in conjunction with the accompanying drawings. Attached Figure Description

[0015] Various aspects or features of this disclosure are described with reference to the accompanying drawings, wherein similar reference numerals are always used to refer to similar elements. Numerous specific details are set forth in this specification to provide a thorough understanding of this disclosure. However, it should be understood that certain aspects of this disclosure may be practiced without these specific details, or using other methods, components, materials, etc. In other instances, known structures and apparatuses are shown in block diagram form to facilitate the description of this disclosure.

[0016] Figure 1 A block diagram of an example electronic device is shown in one embodiment, providing control over a process for generating resistor switch (RS) device identifier data;

[0017] Figure 2 An embodiment is shown that can be derived from Figure 1 A view of an example subset of an array of electronic devices controlled externally by an RS device;

[0018] Figure 3A block diagram showing an example RS device layer stack structure and the surface roughness of the layers in the stack structure in a further disclosed embodiment is shown.

[0019] Figure 4 A block diagram illustrating exemplary adjacent RS devices of the array and variations in the surface roughness of the layers is shown in another embodiment.

[0020] Figure 4A A close-up of an example surface roughness between layers of the RS device in a further embodiment is shown;

[0021] Figure 4B and Figure 4C An example RS device according to one or more disclosed embodiments is shown, along with filament formation and deformation;

[0022] Figure 5 An example Hamming distance distribution between a set of RS devices within a die in an embodiment is shown;

[0023] Figure 6 An example diagram illustrating the cross-correlation of a 256-bit identifier sequence formed by an RS device according to a further disclosed embodiment is shown;

[0024] Figure 7 Example graphs showing the bit error rates of multiple read operations at different temperatures according to other embodiments disclosed herein;

[0025] Figure 8 An example graph is shown comparing the entropy measure of identifier data generated by the RS device with existing benchmarks;

[0026] Figure 9 A schematic diagram of a set of RS devices is shown in one embodiment, illustrating a differential process that helps generate unique identifier bit data.

[0027] Figure 10 An example schematic diagram of multiple sets of RS devices for a differential process to generate identifier bit data is shown in a further embodiment;

[0028] Figure 11 An example schematic diagram of multiple RS devices for a differential process of generating identifier bit data is shown in yet another embodiment.

[0029] Figure 12 An example schematic diagram of multiple sets of RS devices for a differential process of generating identifier bit data according to a further embodiment is shown;

[0030] Figure 13 A flowchart of an example method for generating identifier data via intrinsic current leakage of an RS device is shown in one or more embodiments;

[0031] Figure 14 and Figure 14A A flowchart of an example method for generating identifier data based on the physical characteristics of an RS device, according to a further embodiment, is shown.

[0032] Figure 15 A flowchart of an example method for generating an identifier sequence via an intrinsic programming voltage of an RS device is shown in another embodiment;

[0033] Figure 16 and Figure 16A A flowchart is shown in an alternative or additional embodiment of an example method for generating identifier data via a programming voltage of an RS device;

[0034] Figure 17 A flowchart of an example method for forming identifier data via the intrinsic programming speed of an RS device is shown in a further embodiment;

[0035] Figure 18 and Figure 18A A flowchart is shown for an example method of forming identifier data via intrinsic RS programming speed in an alternative or additional embodiment;

[0036] Figure 19 A flowchart of an example method for generating identifier data via differential procedural events of multiple sets of RS devices is shown in the embodiment;

[0037] Figure 20 and Figure 20A A flowchart of an example method for generating identifier data via differential procedural events of multiple sets of RS devices is shown in one embodiment.

[0038] Figure 21 and Figure 21A A flowchart illustrates an example method for extending the lifespan of RS device identifier data using one-time programmable programming.

[0039] Figure 22 A block diagram of an example electronic operating environment according to certain embodiments presented herein is shown;

[0040] Figure 23 A block diagram of an example computing environment for implementing one or more of the disclosed embodiments is shown. Detailed Implementation

[0041] introduction

[0042] One or more embodiments of this disclosure utilize the random or essentially random physical properties of nanoscale resistive switching devices to generate data. The random properties of resistive switching devices are typically random, and therefore this randomness can be used to generate data with little correlation between multiple such devices (e.g., see below). Figure 6 Therefore, this data can be used for applications requiring unique or distinctive identification, such as identification and licensing applications related to devices (e.g., a semiconductor die, also referred to herein as a semiconductor chip, or a semiconductor wafer, a set or more sets of dies, a set or more sets of wafers, an electronic device containing semiconductor dies, etc.). Furthermore, highly unrelated data can also be used for security applications, such as random number generation, encryption key generation, etc.

[0043] Furthermore, the various embodiments disclose methods for generating high-entropy data sequences that meet or exceed scientific criteria for randomness (e.g., see below). Figure 5 and Figure 8 The resistive switching device process is comparable to high-quality encrypted random number sources. Furthermore, the switching device process for generating data sequences can be selected from intrinsic resistive switching devices (e.g., devices that have not been previously programmed and are original or initial devices after fabrication) that best utilize the nanoscale, non-cloning physical properties of resistive switching devices. This achieves a high degree of decoupling between devices on a die (within a die), between dies on a wafer (between dies), and between wafers in the fabrication facility, thereby minimizing the possibility that a data sequence generated from a resistive switching device on a single die will repeat with other devices on the same die or with other resistive switching devices on a given wafer or different wafers.

[0044] Furthermore, the disclosed resistive switching devices can be constructed between electromagnetically impermeable metal lines on a semiconductor die (e.g., between opaque back-end wiring structures that cover a significant portion of the electromagnetic imaging spectrum, visible light, ultraviolet light, infrared light, etc.), which exacerbates the difficulties involved in unauthorized side-channel access techniques such as unauthorized device-layer microscopy. In one or more additional embodiments, some of the disclosed sequence generation processes can be made permanent through a one-time programmable process, thereby allowing reliable rereading of the sequence over a very large number of read cycles to reliably and accurately reproduce previously generated data sequences, resulting in extremely low bit error rates (e.g., see below). Figure 7In a further embodiment, the disclosed process for generating uncorrelated data sequences may involve a process compatible with the operation of resistive switching devices, thereby allowing the selection of a set of resistive switching devices from any suitable subset of the resistive switching devices on the chip post-manufacturing. Systems and methods are also provided to provide control outputs related to the selection of resistive switching devices, data sequence process selection, and process configuration in connection with the generation of physically unclonable data sequences disclosed herein to a user of the manufactured chip. Various other embodiments will become apparent based on the disclosure herein and the associated drawings.

[0045] As used herein, the term “substantially” and other related terms or degrees (e.g., almost, approximately, substantially, etc.) are intended to have the meaning explicitly stated in connection with their use herein, or the meaning that a person skilled in the art could reasonably infer, or a reasonable variation in a particular quality or quantity that a person skilled in the art could understand by referring to the entire specification (including the knowledge of a person skilled in the art and the material incorporated herein by reference). For example, the term degree can refer to reasonable manufacturing tolerances that a manufacturing apparatus can achieve a particular quality or quantity. Thus, as a specific example without limitation, for an element of a resistive switching device explicitly identified as having a size of about 50 angstroms (A), the relative term “about” can refer to a reasonable variation of about 50 A that a person skilled in the art would expect to achieve with commercial manufacturing equipment, industrial manufacturing equipment, laboratory manufacturing equipment, etc., and is not limited to a mathematically precise quantity (or quality). In other examples, the term degree can refer to a variation of + / - 0.3%, + / - 0.5%, or + / - 0.10% of an explicitly stated value, which is appropriate for a person skilled in the art to achieve the stated function or feature of the element disclosed herein. In other examples, the term "degree" may refer to any appropriate variation in quality or quantity that would be appropriate for implementing one or more explicitly disclosed functions or features of the disclosed elements. Therefore, this specification is by no means limited to the specific quality and quantity disclosed herein, but includes all variations of the specific quality or quantity reasonably communicated to a person skilled in the art through the context of this disclosure.

[0046] As the name suggests, a two-terminal resistive switching device has two terminals or electrodes. In this document, the terms "electrode" and "terminal" are used interchangeably; furthermore, two-terminal resistive switching devices include non-volatile two-terminal storage devices and volatile two-terminal switching devices. Typically, the first electrode of a two-terminal resistive switching device is referred to as the "upper electrode" (TE), and the second electrode is referred to as the "lower electrode" (BE). However, it is understood that the electrodes of a two-terminal resistive switching device can be arranged in any suitable configuration, including a horizontal arrangement where the components of the storage cell are (essentially) side-by-side rather than overlapping. Between the TE and BE of a two-terminal resistive switching device there is typically an intermediate layer, resistive switching medium (RSM), or resistive switching layer (RSL), sometimes referred to as a switching layer; however, such devices are not limited to these layers. For example, as disclosed herein, disclosed in publications incorporated herein by reference, as commonly understood and used in the art, or reasonably conveyed to those skilled in the art by the context provided herein and in supplemental or incorporated publications that complement or supplement the common understanding in the art, one or more barrier layers, adhesive layers, ion-conducting layers, seed layers, particle source layers, etc., may be contained between or adjacent to one or more TE, BE, or intermediate layers consistent with proper operation of such a device.

[0047] Generally, the composition of the memory cells in each device may vary, with different components, materials, or deposition processes selected to achieve desired characteristics (e.g., stoichiometry / non-stoichiometry, volatile / non-volatile, on / off current ratio, switching time, read time, memory endurance, program / erase cycle time, etc.). An example of a filament-based device may include: a conductive layer, such as a metal, metal alloy, or metal nitride (e.g., including TiN, TaN, TiW, or other suitable metal compounds); an optional interface layer (e.g., a doped p-type (or n-type) silicon-containing (Si) layer (e.g., p-type or n-type Si-containing layer, p-type or n-type polycrystalline silicon, p-type or n-type polycrystalline SiGe, etc.)); a resistive switching layer (RSL); and an active metal layer capable of being ionized. Under appropriate conditions, the active metal layer can provide filament-forming ions to the RSL. In this embodiment, conductive filaments (e.g., formed by ions) can pass through at least a subset of the RSL, which is beneficial for conductivity. As an example, the resistance of a filament-based device can be determined by the tunneling resistance between the filament and the conductive layer. A memory cell with this characteristic can be described as a filament-based device.

[0048] For example, an RSL (also known in the art as a resistive switching medium (RSM)) may include an undoped amorphous silicon layer, a semiconductor layer with inherent properties, or a stoichiometric or nonstoichiometric silicon nitride (e.g., SiN, Si3N4, SiN...). x (etc.), low-valent silicon oxides (e.g., SiO2) x(where x is between 0.1 and 2), low-valent silicon nitrides, metal oxides, metal nitrides, non-stoichiometric silicon compounds, etc. Other examples of materials suitable for RSL may include Si. x Ge y O z (where x, y, and z are appropriate positive numbers), silicon oxide (e.g., SiO2). N (where N is an appropriate positive number), silicon nitride oxide, undoped amorphous Si (a-Si), amorphous SiGe (a-SiGe), TaO B (where B is a suitable positive number), HfO C (where C is a suitable positive number), TiO D (where D is an appropriate number), Al2O E (where E is an appropriate positive number) etc., nitrides (e.g., AlN, SiN) or appropriate combinations thereof.

[0049] In some embodiments, an RSL (non-volatile RSL) used as part of a non-volatile memory device may include a substantial number (e.g., compared to a volatile selector device) of material holes or defects to trap neutral metal particles within the RSL (e.g., at low voltages). A large number of holes or defects can facilitate the formation of a thick and stable structure of neutral metal particles. In such a structure, these trapped particles can maintain the non-volatile memory device in a low-resistance state without external stimuli (e.g., electricity), thereby achieving non-volatile operation. In other embodiments, an RSL (volatile RSL) for a volatile selector device may have very few material holes or defects to trap particles. Due to the presence of a small number of particles trapping holes / defects, the conductive filaments formed in such an RSL can be very thin (e.g., one to several particle widths, depending on the field strength, particle material, or RSL material, or a suitable combination thereof) and unstable without a suitablely high external stimuli (e.g., electric field, voltage, current, Joule heating, or a suitable combination thereof). Furthermore, particles with high surface energy and good diffusivity within the RSL can be selected. This results in the conductive filament being able to form rapidly in response to appropriate stimuli and also being easily deformable, for example, in response to external stimuli reduced to a deformation amount (which can be lower than the amount of external stimuli associated with the formation of the volatile conductive filament, for example, in response to the current flowing through the selector device; see U.S. Patent No. 9,633,724B2, the entire contents of which are incorporated herein by reference and used for all purposes). It should be noted that the volatile RSL and conductive filament used for the selector device can have different electrical properties than the conductive filament and non-volatile RSL of a non-volatile storage device. For example, the selector device RSL can in particular have a higher material resistance and can have a higher on / off current ratio, etc.

[0050] The active metal layer for the filament-based memory cell may particularly include silver (Ag), gold (Au), titanium (Ti), titanium nitride (TiN), or other suitable compounds of titanium, nickel (Ni), copper (Cu), aluminum (Al), chromium (Cr), tantalum (Ta), iron (Fe), manganese (Mn), tungsten (W), vanadium (V), cobalt (Co), platinum (Pt), hafnium (Hf), and palladium (Pd), etc. In some aspects of the present disclosure, other suitable conductive materials and stoichiometric or non-stoichiometric compounds, nitrides, oxides, alloys, mixtures, or combinations thereof or similar materials may be used for the active metal layer. Further, in at least one embodiment, non-stoichiometric compounds, e.g., non-stoichiometric metal oxides / metal-oxygen or metal nitrides / metal-nitrogen (e.g., AlO x , AlN x , CuO x , CuN x , AgO x , AgN x , etc., where x is a suitable positive number depending on the metal compound or a numerical range such as 0 < x < 2, 0 < x < 3, 0 < x < 4 or other numerical values / numerical ranges that may have different values for different non-stoichiometric compounds), or other suitable metal compounds may be used for the active metal layer.

[0051] In one or more embodiments, the disclosed filament resistive switching device may include an active metal layer that includes a metal-nitrogen selected from the group consisting of TiN x , TaN x , AlN x , CuN x , WN x , and AgN x , where x is a positive number (or range of numbers) that may vary depending on the metal-nitrogen material. In a further embodiment, the active metal layer may include a metal-oxygen selected from the group consisting of TiO x , TaO x , AlO x , CuO x , WO x , and AgO x , where x is also a positive number (or range of numbers) that may vary depending on the metal-oxygen material. In other embodiments, the active metal layer may include a metal-oxygen-nitrogen selected from the group consisting of TiO a N b , AlO a N b , CuO a N b , WO a N b , and AgOa N b The group consists of metals oxygen-nitrogen, where a and b are appropriate positive / digital ranges. The disclosed filament resistive switching device may further include a switching layer comprising elements selected from SiO₂. y AlN y TiO y TaO y AlO y CuO y TiN x TiN y TaN x TaN y SiO x SiN y AlN x CuN x CuN y AgN x AgN y TiO x TaO x AlO x CuO x AgO x and AgO y The switching materials in the group consist of positive numbers (or ranges), where x and y are positive numbers (or ranges), and y is greater than x. Various combinations described above are contemplated and envisioned within the scope of embodiments of the present invention.

[0052] In one example, the disclosed filamentary resistive switching device includes: a particle donor layer (e.g., containing an active metal layer) comprising a stoichiometric or non-stoichiometric metal compound (or mixture); and a resistive switching layer. In an alternative embodiment of this example, the particle donor layer comprises a metal-nitrogen:MN x (For example, AgN) x TiN x AlN x (etc.), the resistive switching layer contains metal-nitrogen: MN y (For example, AgO) y TiO y AlO y (etc.), where y and x are positive numbers (or ranges), and in some cases y is greater than x. In an alternative embodiment of this example, the particle donor layer comprises metal-oxygen:MO x (For example, AgO) x TiO x AlO x (etc.), the resistive switching layer contains metal-oxygen: MO y (For example, AgO) y TiO yAlO y (etc.), where y and x are positive numbers (or ranges), and in some cases y is greater than x. In another alternative, the metallic compound of the particle donor layer is MN. x (e.g. AgN) x TiN x AlN x (etc.), the resistor switch layer is freely selectable by MO y (For example, AgO) y TiO y AlO y (etc.) and SiO y The group consists of x and y, which are typically non-stoichiometric values, or, in further embodiments, the opposite.

[0053] As used herein, variables such as x, y, a, b, etc., representing values ​​or ratios of one element to another (or other) element in a compound or mixture may have different values ​​(or ranges) applicable to each compound / mixture and are not intended to represent identical or similar values ​​or ratios between compounds. A mixture may refer to non-stoichiometric materials containing free elements (e.g., metal-rich nitrides or oxides (metal oxides / nitrides containing free metal atoms), metal-poor nitrides or oxides (metal oxides / nitrides containing free oxygen / nitrogen atoms)), and other combinations of elements that do not form conventional stoichiometric compounds as understood in the art. Some details relating to embodiments of this disclosure can be found in the following U.S. patent applications assigned to the assignee of this patent application: U.S. Patent Application No. 11 / 875541, filed October 19, 2007, and U.S. Patent Application No. 12 / 575921, filed October 8, 2009; the entire contents of each of these patent applications are incorporated herein by reference, except elsewhere, and are used for all purposes.

[0054] It should be understood that the various embodiments described herein can utilize a variety of memory cell technologies with different physical characteristics. These physical characteristics can be associated with one or more manufacturing processes and can have a random or substantially random characteristic that reduces or avoids replication or duplication between manufactured memory cells (even if the memory cells are manufactured using the same process). As an example, in one embodiment, one or more layers of the disclosed resistive switching device can have a root mean square (RMS) surface roughness greater than 0.2 nm (e.g., see below). Figure 4AThe surface roughness is at most approximately 10.0 nm. This leads to random or near-random variations in layer thickness, including unpredictable variations in the physical properties of such devices. In some theoretical models, RMS surface roughness affects the geometry of the resistive switching material layer, resulting in random or substantially random variations in resistive switching device characteristics (e.g., intrinsic or primitive (e.g., at manufacturing time) current conductance, programming voltage, differential programming voltage, programming speed, differential programming speed, and other characteristics disclosed herein). As a further example, different resistive switching memory cells and cell technologies can have different discrete programmable resistors, different associated program / erase voltages, and other different characteristics. In one embodiment, a resistive switching memory device (device size between approximately 50 nanometers (nm) and approximately 130 nm wide (e.g., approximately 100 nm, approximately 56 nm, approximately 75 nm, approximately 128 nm, etc.)) produced by a 28 nm lithography process can be adapted to achieve the random physical properties disclosed herein. In other embodiments, a 22nm lithography process that produces device dimensions between 40nm and 100nm widths (e.g., about 44nm width, about 60nm width, about 66nm width, about 88nm width, etc.) can achieve random physical properties.

[0055] During manufacturing, the disclosed resistive switching device may possess intrinsic physical characteristics resulting from the manufacturing process used to produce the resistive switching device. These intrinsic physical characteristics may have inherent random or substantially random characteristics that vary between resistive switching devices in a group of such devices (e.g., see below). Figure 4 , Figure 4A , Figure 4B and Figure 4C Furthermore, the intrinsic physical characteristics of devices, dies, wafers, etc., can vary between devices on a single die and between devices on one or more wafers. Therefore, minimal correlation of intrinsic physical characteristics between devices, dies, wafers, etc., can produce minimal correlation between the operational processes of devices, dies, wafers, etc., and the data derived from such processes. For example, the intrinsic resistance of a resistive switching layer (RSL) can depend at least in part on these uncorrelated physical characteristics and can vary between devices, even for adjacent devices in a single array on a single die (and, as previously mentioned, between multiple dies, wafers, etc.). Moreover, the current flowing through the RSL in its intrinsically unprogrammed state, the programming voltage in its intrinsically unprogrammed state, the programming speed in its intrinsically unprogrammed state, the differential programming voltage / current / speed in its intrinsically unprogrammed state, etc., can vary between resistive switching devices. The processes disclosed herein for forming resistive switching devices and utilizing the random or substantially random physically unclonable characteristics of resistive switching devices can provide excellent sequences of uncorrelated data.

[0056] As used herein, the terms “intrinsic,” “original,” “initial,” etc., refer to post-manufacturing but pre-commercialization operations on resistive switching devices on semiconductor dies. Intrinsic (and similar terms) does not, in particular, exclude some or all post-manufacturing operations such as quality testing or other verification procedures performed by the manufacturer, or even some pre-commercialization operations performed by non-manufacturer entities, such as testing to ensure the chip meets the manufacturer’s quality specifications, chip setup or configuration procedures (e.g., defining one-time programmable memory or identifier memory in a resistive switching memory array; see below). Figure 1 and Figure 2 Typically, as used herein, a resistive switching device is in its intrinsic state if it has not received a stimulus as described herein or known in the art suitable for forming a conductive filament within the resistive switching device and changing the resistive switching device from a resistive state to a conductive state (e.g., electrical, thermal, magnetic, or similar stimuli known in the art, and suitable combinations thereof).

[0057] Some embodiments of this disclosure may employ a bipolar switching device that exhibits a first switching response (e.g., programming to one of a set of program states) to an electrical signal of a first polarity and a second switching response (e.g., erasing to an erase state) to an electrical signal of a second polarity. For example, the bipolar switching device contrasts with a unipolar device, which exhibits a first switching response (e.g., programming) and a second switching response (e.g., erasing) to electrical signals having the same polarity but different amplitudes.

[0058] In various embodiments, the filament-based resistive switching device can operate in a bipolar manner, exhibiting different responses to external stimuli of different polarities (or directions, energy flows, energy source orientation, etc.). For a volatile filament-based selector device, as an exemplary example, in response to a first polarity stimulus exceeding a first threshold voltage (or a set of voltages), the filament selector device can change from a first resistive state to a second resistive state. Furthermore, in response to a second polarity stimulus exceeding a second threshold voltage, the filament selector device can change from the first state to a third state. In some embodiments, the third state can be substantially the same as the first state, having the same or similar measurable unique characteristics (e.g., conductivity, etc.), having the same or similar threshold stimulus magnitude (although opposite in polarity or direction), etc. In other embodiments, the third state can differ from the second state based on measurable characteristics (e.g., different conductivity values ​​in response to reverse polarity compared to positive polarity) or based on the threshold stimulus associated with the transition from the first state (e.g., different positive voltage magnitude required to transition to the second state compared to the negative voltage magnitude required to transition to the third state).

[0059] For bipolar operation of a memory cell based on a non-volatile filament, in response to an appropriate programming voltage applied to the memory cell, a conductive path, or filament, is formed through the non-volatile RSL. Specifically, upon application of the programming voltage, metal ions are generated from the active metal layer and migrate to the non-volatile RSL layer. The metal ions can occupy holes or defects within the non-volatile RSL layer. In some embodiments, after the bias voltage is removed, the metal ions become neutral metal particles and are trapped in holes or defects within the non-volatile RSL layer. When a sufficient number of particles are trapped, a filament is formed, and the memory cell switches from a relatively high-resistance state to a relatively low-resistance state.

[0060] In some disclosed embodiments, the completion of the conductive filament may involve only a small number of particles (e.g., atoms, ions, conductive compounds, etc.) or even fewer particles of the conductive material. As a specific example, in some embodiments, electrically continuous conductive filaments can be established at the boundary of the switching layer by positions of 1 to 3 atoms, and the repositioning of one or more of these atoms may disrupt the electrical continuity. Because the ratio between completed and incomplete filaments is extremely small, it is very difficult (if not impossible) for an unauthorized side channel to attempt to read bits of the memory (e.g., by high-intensity microscopy), as it is difficult to image such small particles and determine whether their positions are sufficient to establish electrical continuity. Furthermore, the disclosed resistive switching devices can be formed between metal lines on a semiconductor chip (e.g., between back-end wiring layers). The density of the metal wiring layers further obstructs the visibility of the resistive switching devices, preventing conventional side-channel techniques from benefiting.

[0061] Once a conductive filament is formed, the trapped conductive particles provide a conductive path or filament through the non-volatile RSL layer, and the resistance is typically determined by the tunneling resistance between one or more of these particles and the conductive material of the adjacent non-volatile RSL layer. In some resistive switching devices, an erasure process can be performed to at least partially deform the conductive filament, thereby returning the memory cell from a low-resistance state to a high-resistance state. More specifically, when an erase bias voltage is applied, metal particles trapped in holes or defects in the non-volatile RSL become mobile ions and migrate back to the active metal layer, or separate within the RSL (or a combination of the foregoing), thereby disrupting the conductivity of the conductive filament through the RSL layer. In the context of memory, this state change can be associated with the individual states of binary bits. For an array of multiple memory cells, words, bytes, pages, blocks, etc., of the memory cells can be programmed or erased to represent 0s or 1s of binary information, and binary information is efficiently stored by maintaining these states over time. In various embodiments, multi-level information (e.g., multiple bits) can be stored in such memory cells.

[0062] Where no particular memory cell technology or program / erase voltage is specified for any aspect and embodiment herein, as is known to those skilled in the art, or as may be known to those skilled in the art from the context provided herein, these aspects and embodiments are intended to encompass any suitable memory cell technology and operate with a program / erase voltage applicable to that technology. It should also be understood that embodiments including alternative memory cell technologies or changes in signal levels known to those skilled in the art are considered within the scope of this disclosure where replacing a different memory cell technology requires circuit modifications known to those skilled in the art, or where changes to operating signal levels known to those skilled in the art are required.

[0063] As described above, applying a programming voltage (also known as a “programming pulse”) to one of the electrodes of a dual-terminal memory can cause the formation of a conductive filament in the intermediate layer (e.g., RSL). Conventionally, and as generally described herein, the TE receives the programming pulse and the BE is grounded (or maintained at a lower voltage or opposite polarity compared to the programming pulse), but this is not intended to limit all embodiments. Conversely, applying an “erase pulse” to one electrode (typically a pulse of opposite polarity as a programming pulse or a pulse applied to the opposite electrode as a programming pulse) can disrupt the continuity of the filament, for example, by driving the metal particles or other material forming the filament back to the active metal source. The characteristics of the conductive filament, and its presence or absence, affect the electrical characteristics of the dual-terminal memory cell; for example, when the conductive filament is present, the resistance between the two terminals is reduced and / or the conductance between the two terminals is increased, contrary to its absence.

[0064] A read pulse can be asserted after a programming or erasing pulse. The amplitude of the read pulse is typically lower than that of the programming or erasing pulse and is usually insufficient to affect the conductive filament and / or change the state of the dual-ended memory cell. By applying a read pulse to one of the electrodes of the dual-ended memory, the current (e.g., I0) is measured when compared with a predetermined threshold current. on This can indicate the conductivity state of a dual-ended memory cell. A threshold current can be preset based on expected current values ​​under different states of a dual-ended memory device applicable to a given dual-ended memory technology (e.g., high-resistance state current; currents in one or more low-resistance states, etc.). For example, the cell's conductivity is greater when a conductive filament has been formed (e.g., in response to the application of a programming pulse) and in response to the measured current (e.g., I) of a read pulse. on The reading will be larger. On the other hand, when the conductive filament is removed (e.g., in response to the application of an erase pulse), the cell's resistance is higher because the intermediate layer has a relatively high resistance, and therefore the cell's conductance is lower, resulting in a lower measurement current (e.g., I) read in response to the read pulse. offThe conductivity will be lower. Conventionally, when a conductive filament is formed, the memory cell is referred to as being in a high-conductivity "on state". When the conductive filament is absent, the memory cell is referred to as being in a "off state". Memory cells in the on or off state can be logically mapped to binary values, such as "1" and "0". It should be understood that the conventions or associated logical binary mappings used herein related to the state of a cell are not intended to be limiting, as other conventions, including the opposite conventions, can be used in conjunction with the disclosed subject matter. The techniques described in detail herein are illustrated in conjunction with single-cell (SLC) memory; however, it should be understood that the disclosed techniques can also be used with multi-cell (MLC) memory, where a single memory cell can retain a set of measurable and unique states representing multiple bits of information.

[0065] Digital information can be stored on such devices by mapping it to the non-volatile resistive states of dual-ended memory cells. Electronic devices containing many of these dual-ended memory cells can also store large amounts of data. High-density arrays are configured to contain as many memory cells as possible within a given chip space, thereby maximizing the data storage capacity of the memory chip or system-on-a-chip device.

[0066] Two common conventions are used for two-terminal memories (e.g., cross-switch arrays) formed at metal line intersections within a wafer. The first convention is a 1T1R memory array, where each memory cell is isolated from the electrical effects of surrounding circuitry (e.g., current, including leakage path current) by an associated transistor. The second convention is a 1TnR memory array (where n is a positive number greater than 1), where a group of multiple memory cells is isolated from the electrical effects of surrounding circuitry by one (or more) transistors. In the 1T1R context, individual memory cells can be configured to have high current suppression between memory cells, thus significantly reducing the leakage path current of the 1T1R memory array. In the 1TnR context, many individual memory cells with a high device density in a given amount of silicon space can be connected to a single transistor with a much lower density. Therefore, the 1TnR context favors higher bit density of resistive memory cells on a semiconductor chip.

[0067] Overview

[0068] Figure 1A block diagram of an example integrated circuit device 100 of an electronic device according to one or more embodiments of the present disclosure is shown. The integrated circuit device 100 includes an array of memories 105. The array of memories 105 may include a resistive switching device 110, an identifier memory 120, and an one-time programmable (OTP) memory 130. In various embodiments, the resistive switching device 110 may include a non-volatile two-terminal resistive switching memory device, a volatile two-terminal resistive switching device, or a combination of a non-volatile two-terminal resistive switching memory device and a volatile two-terminal resistive switching device (e.g., used as a selector device for non-volatile memory, or used independently as a volatile latch, switch, etc.). In some embodiments, the array of memories 105 may include other memory cell technologies, such as phase-change memory, oxygen-vacancy memory, magnetic memory, conductive bridge memory, etc.

[0069] The identifier memory 120 may also be referred to herein as fingerprint memory, non-clonable memory, random sequence memory, etc. The identifier memory 120 and OTP memory 130 may be memory structures separate from the array of memory 105 (e.g., located outside the array of memory 105 on a semiconductor chip), or may be at least partially contained within the array of memory 105 (e.g., one array in a set of arrays containing the array of memory 105, a block, one or more blocks, or a set of pages in the array, or other suitable arrangement). In one or more embodiments, the identifier memory 120 and OTP memory 130 may have a fixed size / number of memory cells and may be pre-allocated within the integrated circuit device 100. In other embodiments, the identifier memory 120 and OTP memory 130 may have variable size or controllable location after manufacturing. For example, the number of memory cells allocated to the identifier memory 120 or OTP memory 130 may be dynamically increased or decreased by a controller 160. As an exemplary example, but without limitation, the array of memory 105 may have a fixed amount of memory (e.g., 65 megabytes, or other suitable value), and a first subset of the fixed amount of memory (e.g., 4 megabytes, or any other suitable value from zero to a fixed amount) may be allocated to identifier memory 120, and a second subset of the fixed amount of memory (e.g., 8 megabytes, or any other suitable value from zero to a fixed amount) may be allocated to OTP memory 130. In this example, if identifier memory 620 is not fully used to generate identifier data sequence data, a portion of the first subset (e.g., 2 megabytes, etc.) may be allocated back to resistive switching device 110, and a third subset of resistive switching device 110 (e.g., 4 megabytes, or other suitable value) may be allocated from resistive switching device 110 to OTP memory 130 if more OTP is required. Any other suitable reallocation based on the experience of those skilled in the art or as apparent from the context provided herein is considered to be within the scope of this disclosure and may also be provided by controller 160. However, in some embodiments, if the memory has already been used for fingerprint identification (identifier sequence data) or programmed as OTP data, it can be prevented from being redistributed back to general-purpose memory (or another form of memory).

[0070] The integrated circuit device 100 also shows an input 140 and an output 150. In some embodiments, the input 140 may include data to be stored in the resistor switching device 110, the identifier memory 120, or the OTP memory 130 (or provide a path to that data). The output 150 may output the data stored in the resistor switching device 110, the identifier memory 120, or the OTP memory 130. In some embodiments, the output 150 may output data generated by calculations using the data stored in the identifier memory 120, or, in a further embodiment, may output data generated by such calculations stored in the resistor switching device 110 or the OTP memory 130.

[0071] Figure 1 A novel mechanism is provided to output control over the generation of physically unclonable identifier sequences post-manufacturing. Generating identifier sequence data using static random access memory (SRAM) encounters considerably high bit error rates (BER), ranging from 3% to 15% depending on the implementation. To reduce the BER associated with generating SRAM identifier sequences, complex circuitry is incorporated into the SRAM bits during manufacturing. This permanently fixes the SRAM bits that can be used to generate the identifier sequence and further increases the significant hardware overhead on the semiconductor die. The disclosed resistive switching device can generate identifier sequence data with extremely low BER (e.g., see below). Figure 7 Therefore, the embodiments disclosed herein provide circuitry and processes for memory operations (e.g., for storing data, reading data, rewriting data, etc.) of resistive switching devices, and extend these to the generation of identifier sequence data. In such embodiments, the resistive switching device for memory operations, identifier data, or OTP storage does not need to be fixed at manufacturing time, but can be dynamically exposed after manufacturing for selection and reconfiguration (e.g., via controller 160).

[0072] In addition to the foregoing, the disclosed resistive switching device possesses excellent characteristics for generating identifier data sequences. These characteristics include high entropy, as described below. Figure 6 and Figure 8 As shown, this addresses the inherent difficulties in generating random or fundamentally random numbers, low BER, reverse engineering, or illegal side-channel data access, as well as fast sensing times. For example, a bit sequence of 128 or 256 identifier bits (also referred to herein as physically non-clonable (or PUF) bits) can be formed by 128 or 256 resistive switching devices (as described herein) or 128 or 256 groups of multiple such resistive switching devices (as described herein in the generation of differential identifier bits). The high randomness in generating identifier bits minimizes non-random patterns between sequence bits (multiple resistive switching devices / multiple groups of such devices), thereby reducing or avoiding false rejection rates. Furthermore, high randomness minimizes the impact of a single die (internal HD; Figure 5 The Hamming distance values ​​for multiple read operations on the identifier sequence on the resistive switching device are used to provide an ideal Gaussian distribution of the Hamming distance values ​​between multiple dies of the resistive switching device, thereby improving the safety margin. This can increase the total number of semiconductor chips that can obtain a unique identifier sequence with a given sequence bit length, and even have a high safety margin (e.g., defined by the number of unique bits between the individual sequences used to identify a single die).

[0073] In one or more embodiments, the operable controller 160 performs memory operations on the array of RS devices 105. For example, in one embodiment, the operable controller 160 performs sensing operations related to generating identifier data bits from one (or a group of) resistive switching devices assigned to identifier device 120. Examples of sensing operations related to generating identifier bits may include intrinsic current (intrinsic current of an unprogrammed resistive switching device, also known as leakage current), intrinsic resistance of the resistive switching device, detection of program events, detection of the rate or timing of program events, programming voltage, program current, on-state (programming) resistance, erase voltage or current, delay frequency, parasitic resistance or capacitance, minimum pulse width for programming or erasing, etc., or suitable combinations thereof. In other embodiments, in a further embodiment, the operable controller 160 performs programming operations related to generating identifier data bits from one or more resistive switching devices assigned to identifier device 120. Examples of such programming operations include intrinsic programming voltage, intrinsic programming speed, intrinsic program current, etc. In other embodiments, the controller 160 may be configured to implement differential operations related to generating identifier bits from multiple resistive switching devices. Differential operations that can be used to generate identifier bits according to aspects of this disclosure may include differential programming speed, differential intrinsic programming voltage, differential intrinsic (leakage) current, differential intrinsic resistance, differential on-state resistance, differential erase voltage or current, differential delay frequency, differential parasitic resistance or capacitance, differential program or erase minimum pulse width, or suitable combinations thereof (e.g., see below). Figures 9 to 12 ).

[0074] In other embodiments, the operable controller 160 selectively performs one-time programmable operations on selected identifier devices 120 to present a permanent identifier bit sequence generated using program events (e.g., intrinsic programming voltage, intrinsic programming speed, differential programming speed, differential programming voltage, etc.). In additional embodiments, as described herein, the operable controller 160 establishes one or more threshold metrics (e.g., current metric, resistance metric, programming voltage metric, programming speed metric, etc.) to define identifier bit values ​​(e.g., logic levels; "0" and "1" bits in a binary context) through sensing or programmable operations performed on the identifier devices 120. As an exemplary example, if the operating characteristic selected for generating identifier bit data is intrinsic leakage current, a current value threshold (or a small range of values) can be selected (e.g., 500 nA or any other suitable value or range), and resistive switching devices above the current value threshold can be assigned a "1" identifier bit value, while devices below the current value threshold can be assigned a "0" identifier bit value. In other embodiments, a range of thresholds with smaller and larger thresholds can be utilized (e.g., a smaller threshold of 400 nA and a larger threshold of 600 nA, or any other suitable range of thresholds or values). In one embodiment, devices with intrinsic current below 400 nA can be assigned a "0" identifier bit value; devices with intrinsic current above 600 nA can be assigned a "1" identifier bit value, and devices between 400 nA and 600 nA can be discarded. In one embodiment, further read operations can use a 500 nA threshold to regenerate the "0" and "1" bit values. According to embodiments of this disclosure, using lower and higher initial thresholds can increase sensing margin and reduce bit error rate.

[0075] It should be understood that appropriate thresholds or a set of thresholds can be established for other resistive switching device operating characteristics selected to generate identifier bit information. As another (non-limiting) exemplary example, logic level 0 can be associated with a programming voltage of 2 volts or higher, and logic level 1 can be associated with a programming voltage of 1.8 volts or lower. As previously stated, other appropriate thresholds can be used to define the logic level values ​​of the identifier bits disclosed herein. In some embodiments, when a large number of resistive switching devices are sensed as part of generating identifier bits, threshold voltages, currents, pulse widths, etc., can be selected such that approximately half of the devices are associated with logic level 0 and the other half with logic level 1. In some embodiments, threshold setting can be performed manually via controller 160; in other embodiments, default threshold settings can be set during semiconductor chip initialization.

[0076] In a further embodiment, the operational characteristics or program events used to generate the identifier bit sequence can be selected to have the same or substantially the same measurements over time, multiple read cycles, and the temperature range common to semiconductor chips. This results in a very low bit error rate for the disclosed identifier bit sequence (e.g., see below). Figure 7 As an exemplary example, the intrinsic leakage current (or other physically non-clonable characteristic) of a resistive switching device measured for the first time on day 1 at room temperature can be measured as the same or substantially the same at 100 degrees Celsius five years later after 1 million read operations (e.g., relative to a constant intrinsic leakage current threshold). The value of the resistive switching device can be determined according to the requirements of controller 160. As another exemplary example, to determine the resistance of the resistive switching device, a current source can be applied to the resistive switching device, the voltage drop measured, and the resistance calculated. Other techniques known in the art or reasonably conveyed to those skilled in the art for measuring or determining the physical characteristics of resistive switching devices are considered to be within the scope of this disclosure.

[0077] In addition to the foregoing, controller 160 can be configured to define an arrangement or sequence of resistive switching devices (or multiple sets of resistive switching devices) to create a multi-bit sequence of identifier bits. As an exemplary example, resistive switching devices 0:7 can be read and assigned to bits 0:7 of the bit sequence. In other embodiments, the bit sequence does not need to be derived from resistive switching devices arranged in a specific order. As an example, devices 15, 90, 7, 21, 50, 2, 37, 19 can be read from a sequence of resistive switching devices and assigned to bits 0:7 of the output bit string, respectively. Larger bit strings can be of any selected length. For example, bit strings of 64 bits, 256 bits, 1024 bits, 64 kilobits, or any other suitable subset of identifier devices 120 up to all identifier devices 120 (which may include all arrays of RS devices 105 in at least some embodiments) can be used for the bit string. As another non-limiting example, for a 256-bit identifier sequence, controller 160 can define the order of identifier devices 120 / multiple sets of identifier devices 120 to correspond to a 256-bit sequence. The controller 160 can then sort the identifier bit values ​​(e.g., logic levels, ...) generated from the identifier devices 120 / multiple sets of identifier devices 120 according to device order, thereby creating a 256-bit identifier sequence. As a specific example, in the case of selecting a row of 256 resistive switching devices in the array to generate the identifier sequence, the identifier bit values ​​of the 256 resistive switching devices can be arranged in the order of their physical positions in that row; however, this is only an exemplary example, and any other suitable arrangement or order can be implemented by the controller 160 as an alternative or supplement.

[0078] As is evident from the entire disclosure, any suitable number of bits can be assigned to the identifier bits, thus enabling the operable controller 160 to determine which identifier bits from the identifier device 120 contribute to the identifier data: 64 bits, 1,000 bits, 64,000 bits, or any other suitable subset of the array of RS devices 105 up to the entire array including RS devices 105. In one or more embodiments, the controller 160 may be implemented on the array of RS devices 105. Figures 13 to 21A Methods 1300 to 2100.

[0079] In one or more additional embodiments, controller 160 is operable to store data in resistive switching device 110 or OTP device 130. For example, controller 160 may receive an input data word to be stored from input 140. In some embodiments, controller 160 may combine the input data word with an identifier data sequence stored at / generated by identifier device 120 to produce an output data word. The output data word may be stored in resistive switching device 110. The input word may be optionally deleted. Subsequently, to recreate the input data, the output data word stored in resistive switching device 110 may be combined with the identifier data sequence (optionally calculated on the fly by controller 160), and the recreated input data word may be output via output 150. In various embodiments, such input data word may be a password, document, encryption key, or any other suitable data to be securely stored. Initial randomness testing using the various embodiments disclosed herein for generating identifier data has been successful. In a randomness test NIST SP800-22, embodiments based on applying a voltage or current drive signal to identifier device 120 passed all 15 subtests. Similarly, another randomness test using the NIST SP800-90B, based on a similar embodiment with applied voltage or current drive signals, passed all subtests. In the randomness test, 100 bitstreams were tested using the NIST SP 800-90B at 1 Mb / bitstream and a total of 300 Mb, and all randomness subtests were passed.

[0080] Figure 2 A block diagram of an example array of resistor switch (RS) devices 205 according to an alternative or additional embodiment of the present disclosure is shown. In one embodiment, the array of RS devices 205 may be substantially similar to the array of memory 105 described above. However, the array of RS devices 205 is not limited to the description given above, and in some embodiments may include other features or functions besides those described above or those that replace those described above.

[0081] The array of RS devices 205 can be divided into subsets as shown in optional block 210. Although in Figure 2The example array of RS devices 205 shown illustrates various sizes and locations of optional blocks 210; however, it should be understood that these sizes and locations are merely exemplary. Furthermore, the term "block" is not intended to limit the number, location, layout, or spatial orientation of groups of resistive switching devices that can be assigned to optional block 210. Rather, the term "block" is intended only to indicate an optional grouping of any suitable subset of resistive switching devices within the array of RS devices 205, depending solely on the physical constraints of the circuit layout (if any) that can be established when manufacturing the semiconductor die containing the array of RS devices 205 and operational access to a group of resistive switching devices. However, in the case where bit-addressable two-ended resistive switching devices are used within the array of RS devices 205, such constraints are not required, and in this embodiment, any suitable selection, grouping, association, etc., of resistive switching devices can be defined as optional block 210 by controller 160. For example, in at least one embodiment, a discontinuous group of resistive switching devices can be defined as optional block 210 (e.g., optional block 210A and optional block 210B can be defined as a single optional block 210AB). In another example, a group of resistive switching devices defining a non-rectangular or even irregularly shaped region (e.g., a shapeless region) can be defined as optional block 210 in other embodiments. Suitable combinations of the foregoing can be implemented in other embodiments.

[0082] Controller 160 can receive input from a selected resistive switching device (e.g., via the above). Figure 1 Input 140 (or via another command path not described) is used to assign them as a group. Selection can include any suitable number of resistive switching devices, including groups of regular or irregular shapes, shapeless groups, continuous and discontinuous resistive switching devices, or suitable combinations of the aforementioned groups. Therefore, although... Figure 2 A rectangular block of identifier devices 120 within the array of RS devices 205 is shown; however, it should be understood that, alternatively, different subsets of the array of RS devices 205 may be defined as identifier devices 120. Similarly, controller 160 may receive input for selected one-time programmable (OTP) devices 130. Although the grouping of TOP devices 130 is shown within a rectangular space, similar to identifier devices 120, irregular, shapeless, and non-contiguous groups of OTP devices 130 may also be selected and defined by controller 160 as OTP devices 130. Controller 160 may also receive resistive switch storage devices (e.g., as described above) for one or more selectable blocks 210. Figure 1 The grouping selection of the resistive switching device 110, or the grouping selection of volatile resistive switching devices for one or more optional blocks 210 included in the manufacture.

[0083] In various embodiments, controller 160 may facilitate defining optional blocks 210 during a setup procedure prior to post-manufacturing operation. In some embodiments, controller 160 may facilitate defining or redefining optional blocks after operation of the array of RS devices 205. For example, in one or more embodiments, the pre-operation grouping of devices serving as identifier device 120, OTP device 130, or resistor switch device 110 may be modified during the lifetime of the chip or electronic device containing the array of RS devices 205, and where the physical constraints of the resistive switching devices for the array of RS devices 205 allow. Generally, devices programmed for OTP operation to store data as OTP data are typically not erasable and therefore cannot be reused for non-OTP operation. However, this depends on the technical capabilities of the resistive switching devices for the array of RS devices 205; for example, in at least one embodiment, controller 160 may implement such re-indication where the use of the OTP device can be changed after OTP programming. As disclosed herein, or as reasonably conveyed to those skilled in the art through the context provided herein, where physical limitations permit, the devices can be redefined using a selection command at controller 160 to identify device 120, OTP device 130, and resistor switch device 110, thereby redefining a subset of the array of RS devices 205 for switching, memory, identification, or OTP operation.

[0084] The embodiment where controller 160 helps define a user-selected subset of the array of RS device 205 for identifier device 120 further enhances the security of the identifier sequence generated by identifier device 120, making unauthorized access to such identifier sequence more difficult. This is because a fixed set of bits within the array of RS device 205 used to generate identifier data does not add additional ambiguity to the physical location containing (or generating) the identifier data. Therefore, a hacker intending to illegally obtain identifier data can perform an unauthorized side-channel read operation on a precise portion of the array of RS device 205, for example, using a high-intensity microscope (e.g., using high-magnification electromagnetic techniques, whether visible, infrared, or ultraviolet, to image the physical properties of the identifier bits to see if they are programmed or unprogrammed). Compromising chip security does not even require the chip itself to succeed; some unauthorized intrusion operations only require identifier data to impersonate the chip associated with the identifier data. In this case, the hacker does not even care whether a portion of the array of RS device 205 is physically damaged during side-channel access (or even whether a large portion of the chip is damaged); as long as the identifier data is accurately extracted, the unauthorized intrusion is successful. Conversely, when the portion of the resistive switching device assigned to identifier device 120 is unknown, unauthorized access techniques cannot target the precise subset of bits containing identifier data. Therefore, even the manufacturer's layout of the array of manufactured RS devices 205 is insufficient to determine which bits contain identifier data; even the chip manufacturer itself may not know this information. Furthermore, if some bits in the array of RS devices 205 contain a portion of identifier data, destroying those bits effectively destroys the identifier data, thereby effectively deterring unauthorized access attempts. Therefore, providing controller 160 with the ability to select identifier bits 120 after manufacturing, particularly allowing selection of identifier bits of different sizes and positions within the array of RS devices 205, non-contiguous sets of identifier bits, and even irregularly shaped or shapeless sets of identifier bits, significantly increases the difficulty associated with unauthorized access to identifier data generated by the array of RS devices 205 as described herein.

[0085] Figure 3A block diagram of an example resistive switching device stack 300 according to a further embodiment of the present disclosure is shown. Note that the device stack 300 and the elements shown therein (as well as other integrated circuit device diagrams included herein) are not drawn to scale but are merely representative examples. The device stack 300 includes a substrate 302. The substrate 302 can provide a basis for implementing integrated circuit manufacturing processes to form the physical components of the device contained within the device stack 300. In one embodiment, the substrate 302 may be silicon (Si) or a silicon oxide material (e.g., SiO2, ...), but is not limited thereto, and in other embodiments may comprise any suitable substrate material.

[0086] Various embodiments of this disclosure may optionally be provided Figure 3 One or more layers, not shown, are fabricated on or above substrate 302. Such layers may include layers of integrated circuit devices, such as electronic devices, mechanical devices, electromechanical devices, etc. In one or more embodiments, such devices may be formed as part of a front-end manufacturing technique, which may include manufacturing techniques for forming devices within or at least partially within substrate 302, but this disclosure is not limited to such embodiments. Furthermore, in a further embodiment, one or more layers covering substrate 302 may be formed using back-end manufacturing techniques. Such layers may include metal layers (e.g., metal x-1 layers, x-2 layers…xn layers, where n is an appropriate integer), dielectric layers, etc., or appropriate combinations of the foregoing layers located beneath the insulating / dielectric layer 304. In one embodiment, according to multi-die bonding techniques known in the art, one or more additional substrates, similar to substrate 302 and optionally containing integrated circuit devices or layers formed on additional substrates, may be bonded to substrate 302 and located beneath the insulating / dielectric layer 304.

[0087] like Figure 3 As shown, the insulating / dielectric layer 304 is located on the substrate 302 and on any optional layer formed between the substrate 302 and the insulating / dielectric layer 304. A metal layer, such as the metal "x" layer 306, is disposed on the insulating / dielectric layer 304. x can be a suitable integer greater than zero. In one embodiment, the metal "x" layer 306 can be a back metal layer, but this disclosure is not limited to this embodiment.

[0088] An insulator 308 is formed on a metal "x" layer 306, which includes spatially spaced conductive electrodes 310 (or conductive plugs). Separate devices 320, such as resistive switching devices (e.g., resistive switch storage devices, volatile resistive switch devices, or a combination of resistive switch storage devices and volatile resistive switch devices), are covered on the conductive electrodes 310. The bottom conductive layer 322 of the separate devices 320 is in electrical contact (in some embodiments, physical contact) with the respective upper surfaces of the conductive electrodes 310 and portions of the upper surface of the insulator 308. In some embodiments, one or more additional layers (e.g., adhesion layers, diffusion barrier layers, seed layers, ion conductor layers, etc., or suitable combinations thereof) may be located between the insulator 308 and the bottom conductive layer 322.

[0089] A resistive switching layer 324 is formed on (and optionally in physical contact with) the conductive layer 322. The resistive switching layer 324 is shown as having an intrinsic surface roughness 325 formed at the boundary of the conductive electrode 310 as the lower surface of the resistive switching layer 324. The intrinsic surface roughness 325 can be defined by grain boundaries of atomic / molecular particles forming the (upper) surface of the conductive electrode 310, the (lower) surface of the resistive switching layer 324, or a combination of the aforementioned surfaces. Atomic / molecular particles or multiple groups of such particles (also referred to as atomic / molecular "grains") can form an irregular surface structure in the surface of the resistive switching layer 324. In one embodiment, the distribution of the manufactured particles can result in an RMS surface roughness greater than 0.2 nm on the surface of the resistive switching layer 324 (e.g., see below). Figure 4A ).although Figure 3 Not shown in the text (however, see below) Figure 4B and Figure 4C However, the upper surface of the resistive switch layer 324 can also have an RMS surface roughness greater than 0.2 nm. In one embodiment, the upper and lower surfaces can have a maximum RMS surface roughness of no more than 10 nm. In a further embodiment, the RMS surface roughness of the upper and lower surfaces of the resistive switch layer 324 can be in the range between 0.2 nm and 10 nm, or any suitable value or range therebetween (e.g., 0.2 nm to 5 nm; 0.5 nm to 5 nm; 0.75 nm to 3 nm, etc.). This can result in a variation in the thickness of the resistive switch layer 324 throughout its entire volume (measured from the upper surface to the lower surface). Furthermore, the location, orientation, size, and distribution of grain boundaries within the resistive switch layer 324 are generally random or substantially random processes, resulting in uncorrelated surface roughnesses on the switch layer surfaces of the individual separate devices 320 (e.g., see below). Figure 4 ).

[0090] A particle donor layer 326 is disposed on the resistive switch layer 324. The particle donor layer 326 may contain conductive particles diffused within the resistive switch layer 324, and may also be referred to herein as a metal layer, an active metal layer, etc. As disclosed herein or as is known in the art, or reasonably conveyed to those skilled in the art through the context provided herein, the particle donor layer 326 may include suitable materials for an active metal layer or a particle donor layer. Furthermore, a conductive layer 328 may be disposed on the metal layer 326. In one embodiment, the conductive layer 328 may be a metal "x+1" layer bonded to the metal "x" layer 306 as part of a downstream metal wiring. However, the conductive layer 328 is not limited thereto and may be a doped silicon layer, a doped silicon-germanium layer, a metal-containing layer (e.g., a conductive metal compound, alloy, mixture, etc.), or other suitable conductive layers disposed between downstream metal wirings of an integrated circuit device. In at least one embodiment, one or more layers, such as a conductive capping layer (e.g., providing electrical continuity between particle donor layer 326 and conductive layer 328), an adhesion layer, a diffusion barrier layer, an etch stop layer, an ion conductor layer, etc., may be disposed between particle donor layer 326 and conductive layer 328. An insulator / dielectric material 330 covers and surrounds the separated device 320, providing electrical isolation between the separated device 320 and the layer (not shown) covering the separated device.

[0091] Figure 4 A block diagram of an inter-device switching surface variation 400 according to an embodiment of the present disclosure is shown. A pair of separate devices 420 formed as part of an integrated circuit device is shown. In one or more embodiments, the separate devices 420 may be substantially similar to Figure 3 The present disclosure is not limited to the present embodiment, but the separation device 420 is provided. For example, the separation device 420 may be formed between adjacent rear-end metal wiring metal “x” 306 and metal “x+1” 428 of an integrated circuit device. In one embodiment, the metal wirings 306, 428 may be formed (or lined with) a dense metal material that is opaque to the visible, infrared, or ultraviolet electromagnetic spectrum. Examples include Ti, Ta, W, Cu, Al, Fe, suitable alloys or mixtures of the aforementioned metals, suitable nitrides or oxides of the aforementioned metals, or suitable combinations thereof. This arrangement helps to prevent the separation device 420 from being observed by unauthorized microscopy techniques, which could lead to incorrect readings of the bit state of the separation device 420 (e.g., see below). Figure 4B and Figure 4C ).

[0092] The separated device 420 includes switching layers 324 having manufactured surface roughnesses (including surface roughness device 1 425 and surface roughness device 2 427). Cutout portion 425A shows a close-up view of the manufactured surface roughness device 1 425 (see also...). Figure 4A The diagram illustrates individual surface roughness variations 405A at the boundary between conductive material 322 and switching layer 324, and an example range of RMS surface roughness 410. As described herein, in one or more embodiments, the RMS value of the surface roughness can be greater than 0.2 nm. In further embodiments, the maximum RMS value of the surface roughness does not exceed 10.0 nm. However, because surface roughness is formed by a random or substantially random process, the inherent variations in the surface roughness and associated thickness of the switching layer 324 between devices can lead to random variations in operating characteristics between the separate devices, including: programming voltages, intrinsic resistances, programming resistances (resistance in the programmed state), programming currents, erasing currents (current in the unprogrammed state, or leakage current), erasing voltages, currents, field strengths, field polarities, etc., or suitable combinations thereof. In some embodiments, one or more of these characteristics will be substantially mutually correlated between the separate devices 420 and substantially mutually correlated with spatial location on the die or wafer. Intentional variations during manufacturing can result in very small cross-correlation: in the range of about -0.2 to about 0.2, in the range of about -0.1 to about 0.1, in the range of about -0.02 to about 0.02, in the range of about -0.01 to about 0.01, and in some embodiments in the range of about -0.003 to about 0.003 (e.g., see below). Figure 9 ).

[0093] In one or more embodiments, the thickness of the switching layer 324 varies spatially with the RMS surface roughness (e.g., greater than 0.2 nm) of the lower and upper surfaces of the switching layer 324. In one embodiment, the process for depositing the switching layer 324 can be designed to be based entirely on a range of manufacturing parameters that is wider than the conventional range of manufacturing parameters used for depositing switching layers. In one or more embodiments, the nominal thickness of the switching layer 324 can be 10 angstroms. to to to The surface roughness can be within the range of, or any suitable value between, or any suitable range between. In various embodiments, greater variations in surface roughness can be achieved by adjusting the deposition temperature, deposition time, reagent chemical purity, reagent chemical flow rate, deposition power, etc., or suitable combinations thereof. In one or more embodiments, the spatial thickness variation of the switching layer 324 can be within the range of: 2% to 10%, 5% to 20%, 2% to 20%, or any suitable value between, or any suitable range between.

[0094] The thickness of the switching layer 324 is a parameter that can affect various operating characteristics of the discrete device 420. Examples of such operating characteristics may include: volatile / non-volatile, on / off current ratio, switching time, read time, memory endurance, program / erase cycle time, etc. Based on manufacturing tolerances, at least some of these characteristics of the resistive switching device can have very low cross-correlation between resistive switching devices in an array, or between switching devices on a die (within a device), between dies in a wafer, or between wafers (between devices). In some embodiments, the cross-correlation of intrinsic (unprogrammed) resistance, intrinsic (unprogrammed) current, intrinsic programming voltage, program resistance, erase voltage, etc., for two resistive switching devices on a die can be between -0.1 and 0.1 in some embodiments, or between -0.01 and -0.01 in further embodiments. As an example, the intrinsic resistance can be in the range of 100 kiloohms (kΩ) to 50 megaohms (MΩ), 100 kΩ to 100 MΩ, or any suitable value in between or in any suitable range in between.

[0095] Figure 4B and Figure 4C Example switch layer 324 for two resistive switching devices 320B and 320C is shown. However, switch layer 324 is merely representative, as the surface roughness of each device 320B, 320C is identical only for illustrative purposes; as discussed above, this is not the case for real devices. Instead, Figure 4B and Figure 4C The diagram shows filaments of conductive particles (hereinafter referred to as conductive filaments 402B and 402C) formed within the switching layer 324 of devices 320B and 320C. Since the conductivity through the switching layer 324 can be defined primarily by the electrical continuity (or at least based on the continuity of electron tunneling) between the conductive filament 402B and the conductive material 322, the resistive states of devices 320B and 320C can also be defined primarily by the electrical continuity of the conductive filaments. Conductive filament 402B represents an electrically continuous path through the particle donor layer 326 and the conductive layer 322 of the switching layer 324 of device 320B, resulting in a low-resistance (or programmed) resistive state for device 320B. Conversely, conductive filament 402C represents an electrically discontinuous path between the particle donor layer 326 and the conductive layer 322 of device 320C, resulting in a high-resistance (or erased or unprogrammed) resistive state for device 320C. Figure 4B and Figure 4CIn the examples shown, these continuity states are determined by only a pair of conductive particles 404B and 404C. For the conductive filament 402B, particle 404B is completely continuous between the conductive filament 402B and the conductive material 322, while for the conductive filament 402C, particle 404C is not completely continuous between the conductive filament 402C and the conductive material 322. Therefore, in these examples, the positions of these two particles 404B and 404C determine the resistance states of devices 320B and 320C. These figures illustrate the difficulty of side-channel readout of filament-based resistance switching devices. Because only a few atomic / molecular particles are needed to complete or disrupt the continuity, resulting in one state or another, illegal techniques (e.g., high-intensity microscopy) for determining the resistance state can be very difficult. When devices 320B and 320C are formed between layers of metal wiring (e.g., as described above), further difficulties arise. Figure 3 and Figure 4 As shown, this difficulty can be further exacerbated by the density of the metallic material typically used in back-end wiring structures. Therefore, the resistive switching device disclosed herein can provide identifier data with high intrinsic security against unauthorized side-channel access techniques that are vulnerable to other pseudo-random state devices (e.g., SRAM).

[0096] Figure 5 An example graph of the Hamming distance (HD) distribution 500 for a 100 megabit (Mb) resistive switching device according to one embodiment is shown. The graph plots the normalized Hamming distance on the x-axis versus the overall resistive switching device (re-normalized) on the y-axis. The Hamming distance represents the minimum deviation between uniquely identifiable bit sequences (e.g., two sequences where at least one bit differs between them). The blue graphs list the Hamming distances between different semiconductor dies generated by the resistive switching device technique disclosed herein. Figure 5 The Gaussian or near-Gaussian distribution centered at a 0.5 Hamming distance, shown, provides an excellent distribution with no significant overlap, indicating the unique sequence of each semiconductor die. The red line represents the Hamming device within which the identifier sequence is read multiple times on a single die. The ideal HD within a single die is 0.0, meaning the bit error rate (BER) is zero when the same data sequence is read each time. Existing structures used to generate identifier data, such as SRAM, have very high intrinsic BERs, resulting in HD values ​​significantly greater than 0.0. This reduces the safety margin for distinguishing between HD and HD, increases the likelihood of read errors overlapping with the identifier sequence of another semiconductor die, and compromises the uniqueness of the identifier. For resistive switching devices, an effective HD of 0.0 provides an excellent safety margin, minimizes the BER, and maximizes the uniqueness of the identifier sequence over multiple read cycles.

[0097] Figure 6An example view is shown of the spatial randomness 600 of identifier data generated from the disclosed resistive switching device according to a further embodiment of the present disclosure. Spatial randomness is defined by correlation function 620. Where N is a 256-bit number, x i It is the i-th position, x i+j It is the (i+j)th bit. As shown in the correlation 600 view, the correlation between adjacent bits is between -0.003 and 0.003, and largely between -0.002 and 0.002, which demonstrates the excellent uncorrelation of the disclosed resistive switching device.

[0098] Figure 7 An example view of the identifier data of a resistive switching device according to one or more embodiments of the present disclosure over a temperature range of 700 cycles is shown. This view plots the read operands on the x-axis and the bit error rate on the y-axis at temperatures of -40°C, 25°C, and 125°C. Even with reads of 10 at all temperatures... 8 After this number of times, the BER is essentially zero. In one embodiment, such as... Figure 7 As shown, a very high lifetime can be partially achieved by determining the identifier bit value from program-related events (e.g., median programming voltage, differential programming speed, etc.) that differentiate resistive switching device bits based on programming or non-programming. After initial differentiation, bits defined as programmable can be programmed in one go (e.g., using high-voltage programming pulses, long program loop times, multi-pulse program loops with high program peak values ​​and long pulse lengths, etc.) to present permanently programmed, non-erasable, one-time programmed, etc. One-time programming can significantly reduce bit loss in the programmed device, achieving extremely low bit error rates, such as... Figure 7 As shown.

[0099] Figure 8 An example view is shown comparing the randomness 800 of the disclosed resistive switching device according to a further embodiment to a benchmark cryptographic quality random number generator. The view plots the entropy of the binary number: 2 on the x-axis. -x Where x = 1.0 equals perfect entropy (the probability of any bit in a binary sequence being 0 or 1 is 50%). The y-axis plots the bit count. Light shaded bar 806 represents identifier data derived from the physically unclonable nature of a resistive switching device for 100 megabits of identifier data, dark shaded bar 802 represents the first reference random source, and medium shaded bar represents the second reference random source. Figure 8 As shown, the data generated by the resistive switching device has entropy comparable to that of two cryptographically high-quality random number generators.

[0100] Now for reference Figure 9This illustrates an example schematic diagram of a resistor switch device array according to one or more of the disclosed embodiments and an example differential group 900 of identifier bits 902, 902A, 902B (collectively, identifier bits 902). Figure 9 In the differential group 900, pairs of resistive switching devices are assigned to a single identifier bit (e.g., via such as...). Figure 1 (Controller 160). Also as shown in differential grouping 900, each pair of resistive switching devices grouped into individual identifier bits 902, 902A, 902B are adjacent resistive switching devices on a common word line (e.g., word line 0 910 to word line N 912, where N is an appropriate integer greater than 0). Thus, for example, the lower right identifier bit 902 includes resistive switching device 1 904 and adjacent resistive switching device 2 906 on word line N 912. Each resistive switching device 904, 906 can be connected to bit lines 936, 938 at one terminal and to source lines 926, 928 at a second terminal via respective transistors 908. Figure 9 In the schematic diagram, word line N 912 activates or deactivates transistor 908 connected to resistive switching devices 904 and 906, thereby connecting or disconnecting resistive switching devices 904 and 906 from source lines 926 and 928, respectively. In other words, when word line N 912 has a high voltage and activates transistor 908, resistive switching devices 904 and 906 are connected to source lines 926 and 928, respectively. Conversely, when word line N 912 has a low voltage and deactivates transistor 908, resistive switching devices 904 and 906 are disconnected from source lines 926 and 928, respectively.

[0101] The bit value of each identifier bit 902, 902A, 902B can be determined by the selected differential characteristic of the resistive switching device defined for each identifier bit 902, 902A, 902B. If the first resistive switching device in a pair of resistive switching devices 904, 906 (e.g., defined by controller 160) has a first threshold characteristic, then identifier bit 902 can have a first binary value (e.g., a "0" value). Conversely, if the second resistive switching device in a pair of resistive switching devices 904, 906 (e.g., defined by controller 160) has a first threshold characteristic, then identifier bit 902 can have a second binary value (e.g., a "1" value). Example differential characteristics may include: programming speed (e.g., which device is the first to be programmed in response to a programming voltage determines whether identifier bit 902 is "0" or "1"), programming voltage (e.g., device 1 904 with a programming voltage higher than device 2 906 determines "0", and vice versa), intrinsic current (e.g., device 1 904 with an intrinsic current higher than device 2 906 determines "0", and vice versa), intrinsic resistance (e.g., device 1 904 with an intrinsic resistance higher than device 2 906 determines "0", and vice versa), or suitable combinations of the foregoing. In one embodiment, once the differential programming-related event establishes the value of identifier bit 902, the first programmed device (or the device with a higher or lower programming voltage determined at controller 160) can be configured for one-time programmability, allowing the identifier bit to be reread multiple times with minimal error rate.

[0102] In at least one embodiment, the differential characteristics of the resistive switching devices defined for each identifier bit 902, 902A, 902B can be used to generate multi-bit binary data for the identifier bits. In one embodiment, more groups of resistive switching devices can be grouped into each identifier bit 902 to achieve multi-bit binary values. For example, four resistive switching devices can be grouped into identifier bits 902 to achieve two-bit identifier data (e.g., see below). Figure 11 and Figure 12However, in another embodiment, the controller (e.g., controller 160) may alternatively establish multiple states for the paired resistive switching devices 904, 906 to realize multi-bit binary information. For example, a threshold intrinsic current (or a range of intrinsic currents) may be established, and four (or more) differential states may be defined using the intrinsic current values ​​of the paired resistive switching devices 904, 906, which may be associated with two (or more) bits of binary data. As an example, the four differential states may be defined as including: a zero state, where both devices 904, 906 are less than the threshold intrinsic current (e.g., 500 nA); a first state, where device 904 is less than the threshold intrinsic current and device 906 is greater than the threshold intrinsic current; a second state, where device 906 is less than the threshold current and device 904 is greater than the threshold current; and a third state, where both devices 904, 906 are greater than the threshold current. Thus, measuring the intrinsic current of the paired devices 904, 906 can be used to generate a two-bit binary value for identifier bit 902. As another example, multiple threshold current values ​​can be defined relative to the intrinsic current values ​​of the paired devices 904, 906 to achieve a larger number of digits. For example, two intrinsic current thresholds (500nA, 550nA) can define three intrinsic current states for each pair of devices 904, 906 (a current state less than 500nA; a current state between 500nA and 550nA; and a current state greater than 550nA). The three intrinsic current states measured relative to the two resistive switching devices 904, 906 can produce 2 3 A number of differential states are defined, thereby enabling the definition of three-bit binary data such as identifier bit 902. In various embodiments, a large number of differential states can be achieved using a combination of a large number of resistive switching devices 904, 906 and multiple measurement thresholds, wherein 2 # Each differential state defines the number of binary bits that can be associated with a single identifier bit 902, 902A, or 902B.

[0103] Figure 10A schematic diagram of an example array of resistive switching devices according to alternative or additional embodiments of the present disclosure is shown, providing alternative definitions for differential grouping 1000 of identifier bits 902, 1002, 1010. Differential grouping 1000 can define multiple non-adjacent resistive switching devices on word lines as a single identifier group. For example, identifier bit 1002 includes a group of devices 1 1004 on word line 0910 and bit line 930, and device 2 1006 on word line 0910 and bit line 934 (which is not directly adjacent to bit line 930). Similarly, identifier group 1010 includes a group of devices 1 1014 on word line N912 and bit line 930, and device 2 1016 on word line N912 and bit line 935 (which is also not directly adjacent to bit line 930). Identifier bits 1002 and 1010, and other suitable combinations, can be derived from the following... Figure 1 The controller 160 is defined. In addition to the foregoing, in the embodiments described by differential grouping 1000, identifier bits 902 of devices having a common word line and adjacent bit lines can also be grouped. Therefore, in some disclosed embodiments, differential grouping 1000 can mix device groups on adjacent bit lines with device groups on non-adjacent bit lines.

[0104] Figure 11 A schematic diagram of an example array of resistive switching devices according to a further embodiment of the present disclosure is shown, providing an alternative definition of the differential group 1100 for identifier bits 1102, 1110. As shown, the differential group 1100 defines a plurality of resistive switching devices on common bit lines 930, 932... as identifier bits 1102, 1110, respectively. Although Figure 11 The example array accommodates one or more word lines between word line 0 910 and word line N 912, but in one embodiment, identifier bits 1102 and 1110 may group resistive switching devices on adjacent word lines. This disclosure is not limited thereto; the identifier bits may also include multiple groups of resistive switching devices on non-adjacent word lines. As described herein (e.g., see...), Figure 9 The differential operating characteristics of the respective resistive switching devices of each identifier bit 1102, 1110 can be used to generate identifier data for each identifier bit 1102, 1110. However, this disclosure is not limited thereto, and the definition of the differential operating characteristics explicitly disclosed using the identifier bit data, as well as the definition reasonably conveyed to those skilled in the art through the context provided herein, is considered to be within the scope of this disclosure.

[0105] Figure 12A schematic diagram of an example array of resistive switching devices according to yet another embodiment of the present disclosure is shown, providing another definition of differential grouping 1200 for identifier bits 1202, 1210, and 1220. Specifically, differential grouping 1200 allows resistive switching devices on different bit lines and different word lines to be grouped into identifier groups. For example, identifier bit 1202 includes resistive switching devices on bit lines 930, 932 and word lines 910, 912. Furthermore, identifier bits 1210 and 1220 group resistive switching devices on non-adjacent bit lines with other resistive switching devices on different word lines. It should be understood that, according to various embodiments of the present disclosure, any regular or irregular grouping of resistive switching devices into identifier bits can also be implemented, and the scope of the present disclosure is not limited to what is explicitly described. Furthermore, identifier bits 1202, 1210, and 1220 each include four resistive switching devices. Even for a single-threshold qualitative criterion (e.g., the first device programmed within the identifier bits in response to a programming voltage applied to all devices), this allows for two-bit binary data for each identifier bit 1202, 1210, 1220. For example, if device 11204 is the first to be programmed, the identifier bit equals 00; if device 2 1206 is the first to be programmed, it equals 01; if device 3 1208 is the first to be programmed, it equals 10; if device N 1209 is the first to be programmed, it equals 11, or similar definitions. In some embodiments, the number N of resistive switching devices for each identifier bit can be equal to 2. x , where x is the number of bits in a multi-bit binary number. In other embodiments, a differential quantitative thresholding metric can be used to increase the multi-bit capacity of each identifier bit with four resistive switching devices, similar to the above description. Figure 9 The description is as follows. Other variations and combinations known in the art or reasonably suggested by those skilled in the art from the context provided herein are considered to be within the scope of this disclosure.

[0106] The accompanying drawings included herein are descriptions of components, layers, and materials of a resistive switching device or a die or wafer comprising multiple resistive switching devices. It should be understood that such drawings may include the components, layers, and materials explicitly indicated therein, portions of the explicitly indicated components / layers / materials, or additional components / layers / materials not explicitly depicted but known in the art or reasonably conveyed to those skilled in the art through the context provided herein. Sublayers may also be implemented as adjacent other sublayers within the depicted layer. Furthermore, where appropriate, embodiments in specific drawings of this specification may be applied in part or in whole to other embodiments depicted in other drawings, and vice versa. As an exemplary example, Figure 3 The switch device stacked structure 300 can be used to form such as Figures 9 to 12 The array of resistor switches shown can be connected with... Figure 1The array of RS devices 105, or Figure 22 The memory array 2202, or Figure 23 The volatile memory 2310A or non-volatile memory 2310B, etc., are included together. Furthermore, it should be noted that one or more of the disclosed processes can be combined into a single process to provide aggregation functionality. For example, a deposition process may include an etching process (and vice versa) to facilitate the deposition and etching of components of an integrated circuit device through a single process. Components of the disclosed architecture may also interact with one or more other components not specifically described herein but known to those skilled in the art.

[0107] Given the exemplary view described above, refer to Figures 13 to 21A A flowchart will provide a better understanding of the processing methods that can be implemented based on the disclosed topic. Although for the sake of simplicity... Figures 13 to 21A The methods are shown and described as a series of blocks, but it should be understood and complied with that the claimed subject matter is not limited by the order of the blocks, as some blocks may appear in a different order and / or concurrently with other blocks depicted and described herein. Furthermore, not all shown blocks are required to implement the methods described herein, and in some embodiments, additional steps known in the art or reasonably conveyed to a person skilled in the art through the context provided herein are also considered to be within the scope of this disclosure. Additionally, where appropriate, some steps shown as part of a process may be implemented for another process; other steps of one or more processes may be added to or replaced within the scope of this disclosure in other processes disclosed herein. Furthermore, it should be further understood that the methods disclosed in this specification can be stored on an article of writing to facilitate the transfer and transfer of such methods to an electronic device. The term "article of writing" as used is intended to include a computer program accessible from any computer-readable device, a device incorporating a carrier, or a storage medium.

[0108] Figure 13 A flowchart of an example method 1300 for generating identifier data of an electronic device using resistive switching devices, according to various disclosed embodiments, is shown. At 1302, method 1300 may include selecting a subset of resistive switching devices on a die to generate bits for an identifier sequence. The selection may be in response to a memory control device (e.g., as described above). Figure 1 The controller 160, below Figure 22 The command interface 2216 and state machine 2220, as described below. Figure 23 Commands received at the system memory 2310 and processing unit 2304, or other suitable memory control, management, or operation device. In other embodiments, in at least some embodiments, the selection can be established when the manufacturer initializes the semiconductor device, or when the user initializes it, or during normal operation.

[0109] At 1304, method 1300 may include applying a low voltage, less than the programming voltage of the resistive switching device, to a subset of the resistive switching devices. In one embodiment, the low voltage may be in the range of about 0.1 volt to about 1 volt; or in some embodiments, in the range of about 0.3 volt to about 0.5 volt or about 0.6 volt. The programming voltage magnitude is selected to avoid program events of any subset of the resistive switching devices.

[0110] At 1306, method 1300 may include reading the raw current value of each resistive switching device in response to a low voltage. The raw current (also referred to herein as intrinsic current or initial current) may be a current associated with a previously unprogrammed (e.g., since manufacturing) resistive switching device. At 1308, method 1300 may include comparing the current value of each device to one or more thresholds for high and low currents. In one embodiment, a single current threshold may be used to distinguish measured raw current values ​​as being above or below a single current threshold. In other embodiments, multiple current thresholds may be utilized to distinguish measured current values ​​above a higher current threshold or below a lower current threshold. Other current thresholds known in the art or reasonably conveyed to those skilled in the art through the context provided herein, and their relationship to the raw current values ​​described herein, are considered to be within the scope of this disclosure.

[0111] At 1310, method 1300 may include digitizing the raw current value relative to high and low current thresholds. In one embodiment, digitizing the raw current value may include assigning a "0" bit value to a resistive switching device having a raw current value below (smaller) thresholds and assigning a "1" bit value to a resistive switching device having a raw current value above (larger) thresholds, or vice versa in other embodiments. At 1312, method 1300 may include forming a bit sequence from the digitized current value and making the digital bit sequence equivalent to an identifier sequence. In various embodiments, the identifier sequence may be output as part of an identification application in response to an ID request from a device (e.g., a semiconductor chip, an electronic device containing resistive switching devices, etc.), generated to authenticate the device as part of an authentication application, to generate or verify a key as part of an encryption application, or a suitable combination of the foregoing.

[0112] Now for reference Figure 14 and Figure 14AA flowchart of an example method 1400 for generating identifier data using a nanoscale resistive switching device, according to a further embodiment of the present disclosure, is shown. At 1402, method 1400 may include initiating an identifier acquisition process for a semiconductor chip. According to embodiments of the various disclosures, the identifier acquisition process may be configured to derive random or substantially random data from the physically non-clonable characteristics of the resistive switching device. In other applications using uncorrelated data sequences, random data may be used to generate random numbers for various applications, identify electronic devices, authenticate electronic devices, or generate / verify encryption keys in encryption applications.

[0113] At 1404, method 1400 may optionally include receiving a subset of resistive switching devices of a semiconductor chip. According to various embodiments, the selection may be received as a controller (e.g., Figure 1 The controller 160), memory controller (e.g., Figure 22 (state machine 2220 or command interface 2216) or other suitable processing or logic execution device (e.g., Figure 23 The input may be the system memory 2310 or the processing unit 2304, or a suitable combination of the foregoing. In other embodiments, the selection may be a parameter stored in memory (e.g., OTP device 130) during semiconductor chip initialization.

[0114] At 1406, method 1400 may include starting voltage and current control circuitry for a subset of resistive switching devices. At 1408, method 1400 may include applying a subprogrammed voltage to each resistive switching device in the subset of resistive switching devices, and at 1410, method 1400 may include measuring the original unprogrammed current of each resistive switching device in the subset.

[0115] At 1412, method 1400 may include comparing a measured current value to a set of threshold current values. In one embodiment, the measured current value may be compared to a single threshold to identify measured current values ​​below the threshold and measured current values ​​above the threshold. In other embodiments, the measured current value may be compared to a smaller threshold and a larger threshold to identify measured current values ​​below the smaller threshold and measured current values ​​above the larger threshold.

[0116] At 1414, it can be optionally determined whether the identifier bit sequence is a unit or a multi-bit sequence. In an alternative embodiment, method 1400 can be configured to implement only units or only multi-bit sequences, and determination 1414 can be replaced by performing exclusive unit or multi-bit procedures respectively. If the identifier bit sequence is determined to be a multi-bit sequence, method 1400 can proceed to... Figure 14A1424; otherwise, if the identifier bit sequence is determined to be a unit sequence, then method 1400 can proceed to 1416.

[0117] At 1416, method 1400 may include assigning the digit "0" to a resistive switching device below a small (or relatively small) threshold current value. At 1418, method 1400 may include assigning the digit "1" to a resistive switching device above a large (or relatively large) threshold current value. At 1420, method 1400 may include mapping the digital values ​​of the resistive switching device to an identifier bit sequence, and at 1422, method 1400 may include outputting the identifier bit sequence as the output of the identifier acquisition process.

[0118] Figure 14A Continuing with method 1400. At 1424, method 1400 may include assigning the digit "0" to a resistive switching device with a current below a minimum threshold. At 1426, method 1400 may include assigning the digit "1" to a resistive switching device with a current above a minimum threshold and below a second minimum threshold. At 1428, method 1400 may include assigning digital values ​​to resistive switching devices with currents between subsequent thresholds, up to the Xth digital value, where 2 N Define the number of X numeric values ​​for an N-bit binary number. At 1430, method 1400 may include mapping the numeric values ​​of the resistive switching device to a sequence of multiple numeric identifiers, and at 1432, method 1400 may include outputting the sequence of multiple numeric identifiers as the output of the identifier acquisition process.

[0119] Figure 15 A flowchart of an example method 1500 for generating identifier data using resistive switching devices according to one or more additional embodiments of the present disclosure is shown. At 1502, method 1500 may include selecting a subset of resistive switching devices in an array to generate bits for an identifier sequence. In one embodiment, the resistive switching devices may be contained on a semiconductor die, and the identifier sequence may be used on the semiconductor die.

[0120] At 1504, method 1500 may include applying a median programming loop to a subset of the resistive switching devices. The median programming loop may have the characteristic of being selected such that approximately half of the resistive switching devices are programmed and approximately half remain unprogrammed. In one or more embodiments, such characteristic may include programming voltage magnitude, program current magnitude, loop time, number, amplitude, or duration of loop pulses, or suitable combinations thereof.

[0121] At 1506, method 1500 may include stopping the median program loop upon completion of a stopping criterion. In one embodiment, the stopping criterion may be the completion of the median program loop. In other embodiments, the stopping criterion may be determining that half (or approximately half) of the resistive switching devices have been programmed.

[0122] At 1508, method 1500 may include performing a read operation on the resistive switching device and identifying the resistive switching device in a programmed state and a non-programmed state. At 1510, method 1500 may include assigning a first binary value to the resistive switching device in the programmed state and assigning a second binary value to the resistive switching device in the non-programmed state.

[0123] At 1512, method 1500 may include forming a bit sequence using binary values ​​and making the binary bit sequence equivalent to an identifier sequence. At 1514, method 1500 may optionally apply a permanent programming voltage to a resistive switching device in a programmed state to permanently program the resistive switching device in a programmed state.

[0124] Figure 16 and Figure 16A A flowchart of an example method 1600 for generating identifier sequence data according to a further embodiment of the present disclosure is shown. In one or more embodiments, according to at least some embodiments of the present disclosure, method 1600 can generate identifier sequence data by means of physically unclonable properties formed during the fabrication of a two-terminal resistive switching device on a bare die substrate using a nanoscale fabrication process.

[0125] At 1602, method 1600 may include initiating an identifier acquisition process for the semiconductor chip. At 1604, method 1600 may optionally include receiving a selection of a subset of resistive switching devices of the semiconductor chip. Method 1600 may also include organizing multiple subsets of resistive switching devices into identifier bits. In one or more embodiments, a single resistive switching device may be assigned to each identifier bit. In other embodiments, multiple resistive switching devices in each group may be assigned to each identifier bit. The multiple resistive switching devices may comprise X resistive switching devices, where X = 2. N N is the number of bits in the multi-bit binary number allocated to each identifier bit. As an example, where each identifier bit generated for the identifier sequence data is a two-bit binary number, the number of resistive switching devices allocated to each identifier bit could be X = 2. 2 Or 4. In other embodiments, X can be defined by combining a small number of resistive switching devices with multiple threshold metrics for defining identifier bit values ​​(or bit states) of multi-bit binary numbers (e.g., see above). Figure 9-12Where appropriate, the numbering and organization of the resistor switching devices for each of the above-described identifier bits can be used in other embodiments of this specification (e.g., Figure 13-15 And the method of 17-21A; Figure 1 , 2 (e.g., 9-12, 22, and 23, etc.), and vice versa (e.g., other numbering and organization described elsewhere herein may be used for method 1600). Other numbering and organization of logical states and threshold metrics of units or multiple bits of binary numbers known in the art or reasonably conveyed to those skilled in the art through the context provided herein are considered to be within the scope of this disclosure.

[0126] At 1606, method 1600 may include starting voltage and current control circuitry for a subset of resistive switching devices, and at 1608, applying a mid-range programming loop for each resistive switching device in the subset. In one embodiment, the mid-range programming loop may employ a programming voltage of approximately 2 volts; in other embodiments, the mid-range programming loop may employ a programming voltage in the range of approximately 1.8 volts to approximately 2.2 volts. Other voltages may be implemented in combination with appropriate current, pulse duration, number of pulses, relative amplitude of pulses, or timing. In one embodiment, the mid-range programming loop is selected such that after the mid-range programming loop completes, approximately half of the subset of resistive switching devices is programmed, and approximately half of the subset of resistive switching devices remains unprogrammed. In one embodiment, the mid-range programming loop may be selected such that after the mid-range programming loop, half + / - 5% is programmed; in other embodiments, half + / - 10% is programmed; in a further embodiment, half + / - 15% is programmed; in other embodiments, half + / - 20% is programmed. Where appropriate, these embodiments may be used in other aspects of this disclosure.

[0127] At 1610, method 1600 may include a median monitoring procedure loop relative to a stop criterion. In one embodiment, the stop criterion may be a procedure event that detects approximately half of the resistive switching devices (or, for example, half of the resistive switching devices at + / -5%, + / -10%, + / -15%, + / -20%). At 1612, the method may include terminating the median procedure loop upon determining the stop criterion.

[0128] At 1614, it can be optionally determined whether the identifier bit sequence is a unit or a multi-bit binary number. If it is a unit, method 1600 can proceed to reference numeral 1616; otherwise, method 1600 can proceed to... Figure 16AIn other embodiments, determination 1614 may not exist, method 1600 may be pre-configured only for one or more bits, and method 1600 then proceeds only to reference numeral 1616 or reference numeral 1626, respectively.

[0129] At 1616, method 1600 may include reading the programming state of each selected resistive switching device in the subset of resistive switching devices. At 1618, method 1600 may include assigning the digit "0" to a resistive switching device in the programming state, and at 1620, method 1600 may include assigning the digit "1" to a resistive switching device in the non-programming state. At 1622, method 1600 may include mapping the digital values ​​of the resistive switching devices to a sequence of identifier bits, and at 1624, method 1600 may optionally include outputting the identifier bit sequence as the output of the identifier acquisition process. In at least one embodiment, method 1600 may further include applying a permanent one-time programmable (OTP) program operation to each resistive switching device in the programming state to facilitate a very low bit error rate over time, multiple read cycles, and a considerable temperature range for subsequent reads of the identifier bit sequence.

[0130] refer to Figure 16A Method 1600 can continue at 1626. At 1626, method 1600 may include measuring the programming state of each selected resistive switching device in the subset of resistive switching devices. At 1628, method 1600 may include assigning the digit "0" to the resistive switching device measured in the unprogrammed state, and at 1630, method 1600 may include assigning the digit "1" to the resistive switching device measured in the first programming state (although in at least some embodiments, this relative digit assignment may be reversed). At 1632, method 1600 may include assigning digital values ​​to the resistive switching devices measured in the second and higher programming states, up to the Xth digital value (e.g., where 2...). N Define the number of X numeric values ​​used for an N-bit binary number, where N is an integer greater than 1.

[0131] At 1634, method 1600 may include mapping the digital value of the resistive switching device to a sequence of multiple digit identifiers (each digit in the identifier sequence comprising N bits of binary data). At 1636, method 1600 may optionally include outputting the sequence of multiple digit identifiers as the output of the identifier acquisition process.

[0132] Figure 17A flowchart of an example method 1700 for generating identifier data according to a further embodiment of the present disclosure is shown. At 1702, method 1700 may include selecting a subset of resistive switching devices on a die to generate bits for an identifier sequence for the die. At 1704, method 1700 may include applying a programming voltage to the subset of resistive switching devices at startup. In one embodiment, the resistive switching devices may be raw resistive switching devices that have never been programmed before. At 1706, method 1700 may include measuring the time from a start time to programming for each resistive switching device, optionally up to a predetermined stop time. At 1708, method 1700 may include comparing a programming speed value for each resistive switching device to one or more thresholds for high and low programming speeds. In one embodiment, a single programming speed threshold may be used, and the programming speed values ​​may be compared to the single programming speed threshold to determine their relationship to the single programming speed threshold (e.g., above or below). In other embodiments, multiple programming speed thresholds may be used, and the individual programming speed values ​​may be compared to determine programming speeds below a smaller threshold and programming speeds above a larger threshold.

[0133] At 1710, method 1700 may include assigning a first binary value to a resistive switching device with a speed below a threshold (or a smaller threshold speed). At 1712, method 1700 may include assigning a second binary value to a resistive switching device with a speed above a threshold (or a larger threshold speed). At 1714, method 1700 may include forming a bit sequence from the binary values ​​and making the bit sequence equivalent to an identifier sequence. At 1716, method 1700 may optionally include applying a one-time programmable program loop to the resistive switching device having the first binary value or the second binary value.

[0134] Figure 18 and Figure 18A A flowchart of an example method 1800 for generating an identifier bit sequence from a two-terminal resistive switching device, according to a further disclosed embodiment, is shown. At 1802, method 1800 may include initiating an identifier acquisition process for a semiconductor chip. At 1804, method 1800 may optionally include receiving a selection of a subset of resistive switching devices of the semiconductor chip. In one embodiment, the selection may be received as input from a control device contained on (or operatively connected to) the semiconductor chip, while in other embodiments, the selection may be a default selection stored on the semiconductor chip.

[0135] At 1806, method 1800 may include starting voltage and current control circuitry for a subset of resistive switching devices. At 1808, method 1800 may include looping the application program for each resistive switching device at a start time, and at 1810, method 1800 may include monitoring the electrical response of each resistive switching device in response to the program loop. At 1812, method 1800 may optionally include determining and storing a program time from the start time for each resistive switching device in the subset of resistive switching devices.

[0136] At 1814, it can be optionally determined whether the identifier bit sequence is a unit or a multi-bit binary number. If it is a unit, method 1800 can proceed to reference numeral 1816; otherwise, method 1800 can proceed to... Figure 18A At position 1826. In other embodiments, determination 1814 may not exist, method 1800 may be pre-configured only for units or bits, and method 1800 then proceeds only to reference numeral 1816 or reference numeral 1826, respectively.

[0137] At 1816, method 1800 may include assigning the digit "0" to a resistive switching device whose program time is below a threshold speed (or below a smaller threshold speed in some embodiments). At 1818, method 1800 may include assigning the digit "1" to a resistive switching device whose program time is above a threshold speed (or above a larger threshold speed in one or more embodiments). At 1820, method 1800 may include mapping the digital value of the resistive switching device to an identifier bit sequence. At 1822, method 1800 may optionally include outputting the identifier bit sequence as output of an identifier acquisition process. At 1824, method 1800 may optionally include applying a one-time programmable program loop to the means assigned to the digit "0" or the digit "1".

[0138] refer to Figure 18A At 1826, method 1800 may include comparing the measured program time with a minimum threshold in a set of program time thresholds. At 1828, method 1800 may include assigning a digit "0" to a resistive switching device that is measured to be programmed faster than the minimum threshold. At 1830, method 1800 may include comparing the measured program time with a second threshold in a set of program time thresholds, and at 1832, method 1800 may include assigning a digit "1" to a resistive switching device that measures the program time between the minimum threshold and the second threshold in a set of program time thresholds. At 1834, method 1800 may include assigning a digital value to a resistive switching device that measures the program time between subsequent thresholds in a set of program time thresholds, up to the Xth digital value, where 2 N Defined as the number of X numeric values ​​provided by an N-bit binary number.

[0139] At 1836, method 1800 may include mapping the digital value of the resistive switching device to a sequence of multiple digital identifiers. At 1838, method 1800 may include outputting the identifier sequence as the output of the identifier acquisition process.

[0140] Figure 19 A flowchart of an example method 1900 according to an alternative or additional embodiment of the present disclosure is shown. At 1902, method 1900 may include selecting a subset of resistive switching devices on the die to generate bits for an identifier sequence for the die. At 1904, method 1900 may include grouping subsets of multiple resistive switching devices into bits of the identifier sequence. In one embodiment, the multiple resistive switching devices grouped into an identifier bit may be devices on a word line and adjacent bit lines in an array, devices on a bit line and adjacent word lines in an array, devices on a word line and non-adjacent bit lines in an array, devices on a bit line and non-adjacent word lines in an array, or devices on non-adjacent word lines and non-adjacent bit lines in an array, or suitable combinations of the foregoing.

[0141] At 1906, method 1900 may include looping the application for each of the plurality of resistive switching devices in each group. At 1908, method 1900 may monitor program events for each of the plurality of resistive switching devices in each group for the program events of one of the resistive switching devices in each group. At 1910, method 1900 may include terminating the program loop for the plurality of resistive switching devices in response to detecting a program event for any of the resistive switching devices in the plurality of resistive switching devices. At 1912, method 1900 may include assigning digital values ​​to bits of an identifier sequence based on which of the associated plurality of resistive switching devices first exhibits a program event. For example, when grouping a pair of resistive switching devices into an identifier bit, if the first resistive switching device (e.g., a device connected to the first bit line in a pair of bit lines, a device connected to the first word line in a pair of word lines, a device connected to the first bit line and the first word line in a pair of bit lines and word lines, or other appropriate definition and arrangement) first exhibits a program event, the identifier bit can be assigned a first digital value (e.g., "0" or "1"), and if the second resistive switching device first exhibits a program event, the identifier bit can be assigned a second digital value (e.g., "1" or "0").

[0142] At 1914, method 1900 may include forming a bit sequence by digital values ​​and making the bit sequence equivalent to an identifier sequence. At 1916, method 1900 may optionally include applying a one-time programmable program loop to the first programmed resistive switching device in each group of a plurality of resistive switching devices.

[0143] Figure 20and Figure 20A A flowchart of an example method 2000 according to a further embodiment of the present disclosure is shown. At 2002, method 2000 may include initiating an identifier acquisition process for a semiconductor chip. At 2004, method 2000 may include optionally receiving a selection of a subset of resistive switching devices of the semiconductor chip, and at 2006, method 2000 may include grouping a plurality of resistive switching devices into individual identifier numbers of an identifier number sequence. In various embodiments, each identifier number may be a single digit, while in other embodiments, each identifier number may be a multi-digit number.

[0144] At 2008, method 2000 may include activating voltage and current control circuitry for the resistive switching device. At 2010, method 2000 may include looping through the application of multiple resistive switching devices for each identifier digit in the identifier number sequence. At 2012, method 2000 may include monitoring program events for resistive switching devices in each group of multiple resistive switching devices. At 2014, method 2000 may include detecting a program event for one of the multiple resistive switching devices grouped to an identifier digit. At 2016, method 2000 may include terminating the program loop for the multiple resistive switching devices grouped to that identifier digit in response to detecting the program event for that resistive switching device. At 2018, it is determined whether any other multiple resistive switching devices grouped to an identifier digit are still being programmed. If so, method 2000 may return to reference numeral 2014; otherwise, method 2000 may proceed to 2020 when the program loop for all multiple resistive switching devices has terminated.

[0145] At 2020, method 2000 may include assigning a first digital value to a first programmed identifier number of a first resistor switch device among a plurality of resistor switch devices, and at 2022, method 2000 may include assigning a second digital value to a first programmed identifier number of a second resistor switch device among a plurality of resistor switch devices.

[0146] Now for reference Figure 20A Method 2000 continues at 2024. At 2024, method 2000 may optionally include assigning an Xth digital value to the first programmed identifier digit of the Xth resistive switching device among a plurality of resistive switching devices. In various embodiments, the number of digital values ​​X = 2. NWhere N is the integer number of bits of the N-bit binary number associated with each identifier digit in the identifier digit sequence. At 2026, method 2000 may include mapping the numeric values ​​of the identifier digits to the identifier digit sequence. At 2028, method 2000 may optionally include outputting the identifier digit sequence as the output of the identifier acquisition process, and at 2030, method 2000 may optionally include applying a one-time programmable program loop to each first programmed resistive switching device grouped to each identifier digit.

[0147] Figure 21 and Figure 21A A flowchart of an example method 2100 according to a further embodiment of the present disclosure is shown. At 2102, method 2100 may include selecting a subset of resistive switching devices on a die to generate a sequence of identifiers for the die. At 2104, method 2100 may include measuring one or more device characteristics of the resistive switching devices that are affected by random physical characteristics of the resistive switching devices. At 2106, method 2100 may include generating characteristic thresholds for distinguishing resistive switching devices based on measurement differences.

[0148] At 2108, method 2100 may include assigning the digit "0" to a first group of resistive switching devices having a first relationship with a characteristic threshold. At 2110, method 2100 may include assigning "1" to a second group of resistive switching devices having a second relationship with a characteristic threshold. At 2112, method 2100 may include grouping resistive switching devices in a sequence of bits having values ​​defined by the assigned "0" and "1" values. At 2114, method 2100 may optionally include an output bit sequence as an identifier for the die. At 2116, method 2100 may include permanently programming (or erasing) one of the first group of resistive switching devices or the second group of resistive switching devices.

[0149] Figure 21A Continuing with method 2100, at 2218, method 2100 may include maintaining the second group of either the first group of resistive switching devices or the second group of resistive switching devices in an opposite state. At 2120, method 2100 may include receiving a request for an identifier sequence for the die. At 2122, method 2100 may include reading the states of the first group of resistive switching devices and the second group of resistive switching devices. At 2124, method 2100 may include regenerating the bit sequence by reading the states, and at 2126, method 2100 may include outputting the regenerated bit sequence in response to the request for the identifier sequence.

[0150] According to various embodiments, an electronic device is disclosed, comprising: a plurality of resistive switching devices disposed on a substrate of a semiconductor die, wherein each of the plurality of resistive switching devices includes a resistive switching material layer disposed between a first electrode and a second electrode, wherein one of the first electrode or the second electrode contains metal particles diffused in the material of the resistive switching material layer in response to an external stimulus applied between the first electrode and the second electrode; furthermore, wherein the plurality of resistive switching devices are associated with an operating characteristic having a correlation coefficient among the plurality of resistive switching devices in the range of -0.1 to 0.1; a first plurality of wires providing electrical connections to upper electrodes of the plurality of resistive switching devices; a second plurality of wires providing electrical connections to lower electrodes of the plurality of resistive switching devices; and a control circuit for partitioning a subset of the plurality of resistive switching devices to define a method for generating output based on the operating characteristic having the correlation coefficient. A first subset of resistive switching devices that generate data sequences; and a sensing circuit, at least partially disposed on a semiconductor substrate and electrically connected to a plurality of resistive switching devices via a first plurality of wires and a second plurality of wires, wherein the sensing circuit is configured to selectively apply a sensing signal to a first wire of the first plurality of wires and a second wire of the second plurality of wires to apply the sensing signal to a first resistive switching device in the first subset of the resistive switching devices, wherein the sensing circuit is configured to determine a first response signal from the first resistive switching device in response to the sensing signal, and wherein the sensing circuit is configured to selectively apply the sensing signal to a first wire of the first plurality of wires and a third wire of the second plurality of wires to apply the sensing signal to a second resistive switching device in the first subset of the resistive switching devices, wherein the sensing circuit is configured to determine a second response signal from the second resistive switching device in response to the sensing signal.

[0151] The electronic device may include control circuitry configured to receive an input command that identifies a subset of resistive switching devices, wherein in response to receiving the input command, a subset of multiple resistive switching devices is divided and a first subset of the resistive switching devices is defined.

[0152] In one embodiment, the control circuitry is further configured to divide the plurality of resistive switching devices into an additional subset (different from the aforementioned subset of the plurality of resistive switching devices, for one-time programmable (OTP) operation), thereby defining a second subset of OTP resistive switching devices. In a further embodiment, the control circuitry is further configured to define resistive switching devices that are not included in the first subset of resistive switching devices and are not included in the second subset of OTP resistive switching devices as rewritable nonvolatile resistive memory devices, thereby defining a third subset of rewritable nonvolatile resistive memory devices.

[0153] In another embodiment, the correlation coefficient between the first response signal and the second response signal is in the range of -0.1 to 0.1. In a further embodiment, the correlation coefficient between the first response signal and the second response signal is in a second range of -0.01 to 0.01. In other embodiments, the correlation coefficient between the first response signal and the second response signal is in a third range of -0.003 to 0.003.

[0154] In other embodiments, a first characteristic associated with the first resistive switching device is determined in response to a first response signal and a detection signal; and a second characteristic associated with the second resistive switching device is determined in response to a second response signal and a sensing signal. In one embodiment, the first and second characteristics are selected from the group consisting of intrinsic unprogrammed current, intrinsic programmed voltage, intrinsic programming speed, maximum program current, program resistance, erase voltage, minimum erase current, and at least one program and erase state current after erasure.

[0155] In one or more embodiments, the control circuitry further includes processing circuitry communicatively connected to the sensing circuitry and configured to compare a first response signal and a second response signal with one or more qualitative or quantitative references. In one embodiment, the processing circuitry is configured to assign a binary value to the first response signal based on a comparison of the first response signal with a reference among one or more qualitative or quantitative references. In another embodiment, the processing circuitry is also configured to assign a second binary value to the second response signal based on a comparison of the second response signal with a reference, wherein the processing circuitry is configured to generate a data sequence at least partially from the binary value and the second binary value.

[0156] In a further embodiment, the processing circuit is configured to assign a first logic value to the first response signal or the second response signal if the value of the first response signal or the second response signal is lower than the lower of one or more qualitative or quantitative references; and the processing circuit is configured to assign a second logic value to the first response signal or the second response signal if the value of the first response signal or the second response signal is higher than the higher of one or more qualitative or quantitative references. In a further embodiment, the processing circuit is configured to discard the first response signal or the second response signal if the value of the first response signal or the second response signal is higher than the lower reference and lower than the higher reference.

[0157] In one embodiment, the processing circuitry is configured to generate a data sequence at least partially from a first digital value or a second digital value. In other embodiments, the processing circuitry is configured to receive input values ​​and to determine an output value in response to the input values, a first logic value, and a second logic value. In other embodiments, the processing circuitry is configured to: receive a first input value and a second input value; determine a first output value in response to the first input value and the first logic value; and determine a second output value in response to the second input value and the second logic value. In other embodiments, the control circuitry is configured to store an order of a first subset of resistive switching devices and generate a data sequence using bit values ​​derived from the operating characteristics of the first subset of resistive switching devices, wherein the bit values ​​are sorted according to the first subset of resistive switching devices to generate the data sequence. In a further embodiment, the control circuitry is configured to define groups of two or more resistive switching devices from the first subset of resistive switching devices and assign each group of two or more resistive switching devices to a bit in the data sequence. In other embodiments, the control circuit assigns a first logic value to a bit of the data sequence in response to a first resistive switching device among two or more resistive switching devices in a group that satisfy a criterion for bit assignment, wherein the criterion is selected from the group consisting of a first presentation program event, a first presentation erase event, a minimum intrinsic current magnitude, a minimum intrinsic programming voltage, and a minimum erase voltage. In at least one embodiment, the control circuit assigns a second logic value to a bit of the data sequence in response to a second resistive switching device among two or more resistive switching devices in a group that satisfy a criterion for bit assignment.

[0158] A further embodiment discloses a method for operating a circuit, comprising: applying a first programming signal to a first resistor switch device in an unprogrammed state and a second resistor switch device in an unprogrammed state; determining, in response to applying the first programming signal, whether the first resistor switch device and the second resistor switch device remain in an unprogrammed state; and applying a second programming signal to the first resistor switch device and the second resistor switch device in response to determining that both the first resistor switch device and the second resistor switch device remain in an unprogrammed state; at least one of the following:

[0159] The circuit is characterized in a first programming state when the first resistive switch enters a programming state in response to a second programming signal and the second resistive switch remains in an unprogrammed state in response to the second programming signal; or the circuit is characterized in a second programming state when the second resistive switch enters a programming state in response to a second programming signal and the first resistive switch remains in an unprogrammed state in response to the second programming signal; receives an input stimulus; and at least one of the following: outputs a first output in response to an input stimulus, and the circuit is characterized in the first programming state; or outputs a second output in response to an input stimulus, and the circuit is characterized in the second programming state.

[0160] In one embodiment, the method further includes applying a third programming signal to the first resistive switching device in response to the first resistive switching device entering a programming state. In another embodiment, the third programming signal includes a one-time programming signal that causes the first resistive switching device to enter a one-time programmable programming state from a programming state. In yet another embodiment, the first programming signal is selected from the group consisting of a controlled current signal and a controlled voltage signal.

[0161] In a further embodiment, the method further includes: applying a first programming signal to a third resistor switch device in an unprogrammed state; determining, in response to the first programming signal, whether the third resistor switch device remains in an unprogrammed state; and applying a second programming signal to the third resistor switch device in the unprogrammed state in response to determining that the third resistor switch device remains in the unprogrammed state; wherein, the circuit being in a first programming state is characterized by the first resistor switch device and the third resistor switch device entering a programming state in response to the application of the second programming signal while the second resistor switch device remains in an unprogrammed state in response to the application of the second programming signal.

[0162] In a further embodiment, the method includes: applying a first programming signal to a fourth resistive switch device in an unprogrammed state; determining, in response to applying the first programming signal, whether the fourth resistive switch device remains in an unprogrammed state; and, in response to determining that the fourth resistive switch device remains in an unprogrammed state, applying a second programming signal to the fourth resistive switch device in the unprogrammed state; wherein, in response to the second and fourth resistive switch devices entering a programming state in response to the application of the second programming signal, while the first and third resistive switch devices remain in an unprogrammed state in response to the application of the second programming signal, the circuit is characterized as being in a second programming state. In a further embodiment, compared to the first programming signal, the second programming signal has increased parameters, wherein the parameters are selected from a group consisting of current or voltage magnitude, signal duration, pulse count, and duty cycle.

[0163] In other embodiments, determining whether the first resistor switch and the second resistor switch remain in an unprogrammed state further includes: applying a read signal to the first resistor switch; determining whether the first resistor switch is in an unprogrammed state in response to the read signal; applying a read signal to the second resistor switch; and determining whether the second resistor switch is in an unprogrammed state in response to the read signal.

[0164] In some embodiments, the data word includes a plurality of resistive switching devices, including a first resistive switching device and a second resistive switching device; and the first resistive switching device is disposed at a predetermined position within the data word. In a further embodiment, the predetermined position is selected from the group consisting of the most significant bit (MSB) and the least significant bit (LSB).

[0165] A method of operating a circuit including an array of resistive switching devices is disclosed, comprising: selecting a subset of resistive switching devices to generate bits for an identifier sequence; defining a group of two or more resistive switching devices in the subset of resistive switching devices and assigning the group to a bit of the identifier sequence; performing a program loop on the two or more resistive switching devices in the group; monitoring the program loop on the two or more resistive switching devices in the group; terminating the program loop in response to detecting a program even for one of the two or more resistive switching devices; and at least one of the following: assigning a first logic value to a bit of the identifier sequence in response to a program event exhibited by a first resistive switching device among the two or more resistive switching devices; or assigning a second logic value to a bit of the identifier sequence in response to a program event exhibited by a second resistive switching device among the two or more resistive switching devices.

[0166] In one embodiment, the method further includes receiving a command input identifying a subset of resistive switching devices and selecting the subset of resistive switching devices in response to the command input. In other embodiments, the method further includes defining two or more resistive switching devices in each of a plurality of groups within the subset of resistive switching devices and assigning each group to a respective bit of an identifier sequence. In an additional embodiment, the method includes looping through the application for each of the two or more resistive switching devices in the plurality of groups and monitoring each group for program events associated with any resistive switching device in each group. In another embodiment, the method further includes terminating the program loop for one of the two or more resistive switching devices in the plurality of groups in response to detecting a second program event for any one of the two or more resistive switching devices. In an additional embodiment, the method further includes determining whether the second program event was exhibited by a first resistive switching device or a second resistive switching device in the plurality of two or more resistive switching devices.

[0167] In one or more other embodiments, the method further includes one of the following: assigning a first logic value to a second identifier bit of an identifier sequence in response to a first resistive switching device exhibiting a second program event among the two or more resistive switching devices; and assigning a second logic value to a second identifier bit of an identifier sequence in response to a second resistive switching device exhibiting a second program event among the two or more resistive switching devices.

[0168] Other embodiments of the method further include: detecting each program event in each of the multiple groups of two or more resistive switching devices; assigning a first logic value or a second logic value to each identifier bit of the identifier sequence; and compiling the identifier sequence from each corresponding logic value assigned to each identifier bit.

[0169] In one embodiment, the method may include applying a one-time programmable program signal to the first resistive switching device in response to detecting a program event of the first resistive switching device. In yet another embodiment, the method may include applying a one-time programmable program signal to the second resistive switching device in response to detecting a program event of the second resistive switching device.

[0170] A method of operating a circuit is disclosed according to a further embodiment, comprising: selecting a subset of unprogrammed resistive switching devices on a semiconductor die to generate bit values ​​of a data sequence; applying a subprogramming voltage to the subset of unprogrammed resistive switching devices; reading the raw current of each resistive switching device in the subset of unprogrammed resistive switching devices; comparing the raw current of a resistive switching device with one or more thresholds of high and low raw current; and defining a logic value for a bit of the data sequence based on the comparison of the raw current with one or more thresholds of high and low raw current.

[0171] A further embodiment of the method includes comparing the raw current value of each resistive switching device with one or more thresholds for high and low raw currents, and defining a logic value for each bit of the data sequence by comparing the respective raw current value with one or more thresholds. In another embodiment, comparing the raw current with one or more thresholds further includes comparing the raw current with a threshold current value and determining whether the raw current is less than or greater than the threshold current value. In other embodiments, the method further includes defining a first logic level for a bit of the data sequence in response to the raw current being less than the threshold current value; or defining a second logic level for a bit of the data sequence in response to the raw current being greater than the threshold current value. In one embodiment, the method further includes setting the threshold current value to a current magnitude of approximately 500 nA. In alternative or additional embodiments, the method further includes setting the threshold current value to a current magnitude selected from a range between 400 nA and 600 nA.

[0172] In another embodiment, comparing the original current with one or more thresholds further includes: comparing the original current with a smaller threshold current and a larger threshold current, and determining whether the original current is lower than the smaller threshold current or higher than the larger threshold current. In one embodiment, the method further includes: defining a first logic level for a bit of the data sequence in response to the original current being lower than the smaller threshold current; or defining a second logic level for a bit of the data sequence in response to the original current being higher than the larger threshold current. In a further embodiment, the method further includes removing the bit from the data sequence in response to the original current being higher than the smaller threshold current and lower than the larger threshold current. In other embodiments, the method further includes receiving an input defining a subset of unprogrammed resistive switching devices, and selecting a subset in response to the input.

[0173] According to alternative or additional embodiments, a method of operating a semiconductor device including resistive switching devices is disclosed, comprising: initiating an identifier acquisition sequence for a semiconductor chip; identifying a subset of resistive switching devices on the semiconductor chip for the identifier acquisition sequence; applying a subprogrammed voltage to each resistive switching device in the subset of resistive switching devices; measuring the raw unprogrammed current of each resistive switching device in the subset; comparing the measured current value with one or more thresholds of the unprogrammed current; defining a digital value of the measured current value based on the respective comparison results with the one or more thresholds of the unprogrammed current; and aggregating the defined digital values ​​into a data sequence.

[0174] In one embodiment, the method further includes comparing the measured current value with a single unprogrammed current threshold. In other embodiments, the method further includes assigning a digit "0" to a resistive switching device with a current below the single unprogrammed current threshold and assigning a digit "1" to a resistive switching device with a current above the single unprogrammed current threshold. In other embodiments, the method further includes comparing the measured current value with a smaller unprogrammed current threshold and a larger unprogrammed current threshold. In an additional embodiment, the method further includes assigning a digit "0" to a resistive switching device with a measured current below the smaller unprogrammed current threshold and assigning a digit "1" to a resistive switching device with a measured current above the larger unprogrammed current threshold.

[0175] In one or more additional embodiments, the method may include an output data sequence as a unique identifier for a semiconductor chip. Further embodiments provide that the method further includes generating or verifying an encryption key associated with a semiconductor device using the data sequence. Additional embodiments of the method further include: comparing a measured current value to a set of discrete current value thresholds; assigning a digit "0" to a resistive switching device whose measured current value is below the minimum current threshold among the discrete current value thresholds; assigning a digit "1" to a resistive switching device whose measured current value is between the minimum current threshold and a second minimum current threshold among the discrete current value thresholds; assigning a digital value to a resistive switching device whose current is between subsequent pairs of discrete current value thresholds, up to the Xth digital value of an N-bit binary number, where the number of X digital values ​​is increased by 2^N. N The definition is given, and N is greater than 1. In one embodiment, the method further includes aggregating N bits of binary data for each bit of the data sequence. In other embodiments, the method further includes obtaining a sequence output data sequence in response to an identifier.

[0176] A method of operating a circuit is disclosed, comprising: selecting a subset of unprogrammed resistive switching devices on a semiconductor die to generate bit values ​​of a data sequence; applying a median programming voltage to the subset of unprogrammed resistive switching devices; monitoring the subset of unprogrammed resistive switching devices against a stop criterion; stopping the median programming voltage in response to detecting a threshold number of unprogrammed resistive switching devices triggering the stop criterion; performing a read operation and identifying resistive switching devices in a programmed state and a non-programmed state within the subset of unprogrammed resistive switching devices; and defining logical values ​​of bits of the data sequence based on the result of the read operation for each resistive switching device. In one embodiment, the method further comprises receiving an input command to identify the subset of unprogrammed resistive switching devices and selecting the subset in response to the input command. In another embodiment, the method may include selecting a median programming voltage such that the voltage magnitude is configured to program approximately half of the unprogrammed resistive switching devices in response to the median programming voltage. In another embodiment, approximately half of the unprogrammed resistor switching devices are selected from the group consisting of half of the + / -5% unprogrammed resistor switching devices, half of the + / -10% unprogrammed resistor switching devices, half of the + / -15% unprogrammed resistor switching devices, and half of the + / -20% unprogrammed resistor switching devices.

[0177] In a further embodiment, the number of thresholds for unprogrammed resistive switching devices is approximately half that of unprogrammed resistive switching devices. In other embodiments, the stopping criterion is an initial program event, wherein one of the subset of unprogrammed resistive switching devices is the first to be programmed. In yet another embodiment, defining logic values ​​for the bits of the data sequence further includes, in response to a read operation, assigning a logic level "0" to the bit of the data sequence associated with the resistive switching device in the unprogrammed state and assigning a logic level "1" to the bit of the data sequence associated with the resistive switching device in the programmed state.

[0178] In one embodiment, the method further includes aggregating defined logic values ​​into a data sequence according to the order of unprogrammed resistive switching devices in an array on a semiconductor die. In other embodiments, the method further includes applying a one-time programmable signal to resistive switching devices identified as being in a programmed state in response to a read operation. In other embodiments, the median programming voltage is selected from a range of 1.8 volts to 2.2 volts.

[0179] According to one or more additional embodiments, a method of operating a semiconductor device including resistive switching devices is disclosed, comprising: initiating an identifier acquisition sequence of a semiconductor chip; identifying a subset of unprogrammed resistive switching devices on the semiconductor chip for the identifier acquisition process; applying a median program loop to each unprogrammed resistive switching device in the subset of unprogrammed resistive switching devices; monitoring the median program loop relative to a stop criterion; terminating the median program loop after determining the stop criterion; in response to terminating the median program loop, reading the subset of unprogrammed resistive switching devices and identifying resistive switching devices in a programmed state and resistive switching devices remaining in a non-programmed state; and defining bits of a bit sequence in response to identifying resistive switching devices in a programmed state and resistive switching devices in a non-programmed state.

[0180] In one or more embodiments, the method may include applying a median program loop, further comprising: applying a programming signal to a subset of unprogrammed resistive switching devices; determining a second subset of resistive switching devices from the programmed subset and a third subset of resistive switching devices from the unprogrammed subset in response to the programming signal; and determining whether the second subset of resistive switching devices is equal to half of the unprogrammed resistive switching devices within a threshold range. In a further embodiment, the method further comprises increasing the programming signal in response to determining that the second subset of resistive switching devices is less than half of the unprogrammed resistive switching devices within the threshold range, until the second subset of resistive switching devices is equal to half of the unprogrammed resistive switching devices within the threshold range. In one embodiment, the threshold range is selected from the group consisting of 5%, 10%, 15%, and 20% of half of the unprogrammed resistive switching devices. In other embodiments, defining the bits of the bit sequence further comprises assigning a logic level "0" to bits associated with resistive switching devices in the unprogrammed state in response to the median program loop, and assigning a logic level "1" to bits associated with resistive switching devices in the programmed state in response to the median program loop.

[0181] In one embodiment, defining the bits of the bit sequence further includes measuring the programming state of each unprogrammed resistive switch device, assigning a digit "0" to the bit associated with the measured resistive switch device in an unprogrammed state, and assigning a digit "1" to the bit associated with the measured resistive switch device in a first programmed state. In this embodiment, the method further includes assigning digital values ​​to the bits of the bit sequence associated with the measured resistive switch devices in second and higher programmed states, up to the Xth digital value, where 2 NDefine the number of X numeric values ​​of an N-bit binary number. In yet another embodiment, the method may further include aggregating a bit sequence by means of an N-bit binary number associated with the bits of the bit sequence, in an order defined by the positions of unprogrammed resistive switching devices in an array on a semiconductor chip. In at least one embodiment, the method further includes applying a one-time programmable signal to a resistive switching device identified as being in a programmed state.

[0182] Example operating environment

[0183] Figure 22 A block diagram illustrating an example operation of a memory array 2202 and a control environment 2200 for a memory cell array according to aspects of the present disclosure is shown. In some embodiments, the control environment 2200 and the memory array 2202 may be formed within a single semiconductor die; however, the present disclosure is not limited thereto, and in other embodiments, some components of the control environment 2200 may be formed on separate semiconductor dies. In at least one aspect of the present disclosure, the memory array 2202 may include a memory selected from a variety of memory cell technologies. In at least one embodiment, the memory array 2202 may include a dual-ended memory technology configured in a compact two-dimensional or three-dimensional architecture. Suitable dual-ended memory technologies may include resistive-switch memory, conductive bridge memory, phase-change memory, organic memory, magnetoresistive memory, etc., or suitable combinations of the foregoing. In a further embodiment, the dual-ended memory technology may be a dual-ended resistive-switch technology.

[0184] Column controller 2206 and sense amplifier 2208 may be configured to be adjacent to memory array 2202. Furthermore, column controller 2206 may be configured to activate (or identify to activate) a subset of bit lines of memory array 2202. Column controller 2206 may utilize control signals provided by reference and control signal generator 2218 to activate and operate corresponding bit lines in the subset of bit lines, applying appropriate program, erase, or read voltages to these bit lines. Inactive bit lines may be maintained at a suppression voltage (also applied via reference and control signal generator 2218) to mitigate or avoid bit interference effects on these inactive bit lines.

[0185] Furthermore, the operating and control environment 2200 may include a row controller 2204. The row controller 2204 may be configured to be adjacent to and electrically connected to the word lines of the memory array 2202. Utilizing control signals from a reference and control signal generator 2218, the row controller 2204 may select a specific row of memory cells with an appropriate selection voltage. Furthermore, the row controller 2204 can facilitate programming, erasing, or reading operations by applying an appropriate voltage at the selected word line.

[0186] The sensing amplifier 2208 can read data from or write data to the active memory cell of the memory array 2202 selected by column control 2206 and row control 2204. Data read from the memory array 2202 can be provided to the input / output buffer 2212. Similarly, data to be written to the memory array 2202 can be received from the input / output buffer 2212 and written to the active memory cell of the memory array 2202.

[0187] Clock source 2210 can provide corresponding clock pulses to facilitate the timing of read, write, and programming operations of row controller 2204 and column controller 2206. Clock source 2210 can respond to external or internal commands received by operating and control environment 2200, further facilitating word line or bit line selection. Input / output buffer 2212 can include command and address inputs, as well as bidirectional data inputs and outputs. Instructions are provided via command and address inputs, and data to be written to memory array 2202 and data read from memory array 2202 are transferred on bidirectional data inputs and outputs, thereby facilitating connection to external host devices (not shown, but described below), such as computers or other processing devices. Figure 23 Computer 2302).

[0188] The input / output buffer 2212 can be configured to receive write data, receive erase commands, receive status or maintenance commands, output read data, output status information, receive address data and command data, and address data of corresponding commands. Address data can be transferred to the row controller 2204 and column controller 2206 via the address register 2214. Furthermore, input data is transferred to the memory array 2202 via the signal input line between the sense amplifier 2208 and the input / output buffer 2212, and output data is received from the memory array 2202 via the signal output line from the sense amplifier 2208 to the input / output buffer 2212. Input data can be received from the host device, and output data can be transferred to the host device via the I / O bus.

[0189] Commands received from the host device can be provided to command interface 2216. Command interface 2216 can be configured to receive external control signals from the host device and determine whether the data input to input / output buffer 2212 is write data, a command, or an address. Input commands can be transmitted to state machine 2220.

[0190] State machine 2220 can be configured to manage the programming and reprogramming of memory array 2202 (and other memory groups in multiple memory arrays). Instructions provided to state machine 2220 are implemented according to control logic configuration, enabling state machine 2220 to manage read, write, erase, data input, data output, and other functions associated with memory array 2202. In some aspects, state machine 2220 can send and receive acknowledgments and denials regarding the successful reception or execution of various commands. In further embodiments, state machine 2220 can decode and implement state-related commands, decode and implement configuration commands, etc.

[0191] To perform functions such as read, write, erase, input, and output, state machine 2220 can control clock source 2210 or reference and control signal generator 2218. Control of clock source 2210 can generate output pulses configured to facilitate specific functions of row controller 2204 and column controller 2206. For example, output pulses can be transmitted to selected bit lines via column controller 2206, or, for example, output pulses can be transmitted to selected word lines via row controller 2204.

[0192] Combination Figure 23 The systems, apparatuses, and / or processes described herein can be implemented in hardware such as a single integrated circuit (IC) chip, multiple ICs, application-specific integrated circuits (ASICs), etc. Furthermore, the order in which some or all process blocks appear in each process should not be considered restrictive. Rather, it should be understood that some processing blocks can be executed in various orders, and not all of these orders are explicitly stated herein.

[0193] refer to Figure 23 The appropriate environment 2300 for implementing the various aspects of the claimed subject matter includes a computer 2302. The computer 2302 includes a processing unit 2304, system memory 2310, a codec 2314, and a system bus 2308. The system bus 2308 integrates system components, including (but not limited to) system memory 2310, into the processing unit 2304. The processing unit 2304 can be any of a variety of available processors. Dual microprocessors and other multiprocessor architectures can also be used as the processing unit 2304.

[0194] The system bus 2308 can be any of several types of bus architectures, including memory buses or memory controllers, peripheral buses or external buses and / or local buses using any of the various available bus architectures, including but not limited to Industry Standard Architecture (ISA), Micro Channel Architecture (MSA), Extended ISA (EISA), Intelligent Drive Electronics (IDE), VESA Local Bus (VLB), Peripheral Component Interconnect (PCI), Card Bus, Universal Serial Bus (USB), Advanced Graphics Port (AGP), PCMCIA Bus, FireWire (IEEE 1394), and Small Computer System Interface (SCSI).

[0195] System memory 2310 includes volatile memory 2310A and non-volatile memory 2310B. The Basic Input / Output System (BIOS) is stored in the non-volatile memory 2310B. The BIOS contains basic routines for transferring information between components within the computer 2302 (e.g., during startup). Furthermore, according to the invention, codec 2314 may include at least one of an encoder or a decoder, wherein the encoder or decoder may be composed of hardware, software, or a combination of hardware and software. Although codec 2314 is shown as a separate component, it may be included in the non-volatile memory 2310B. By way of example and not limitation, non-volatile memory 2310B may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, dual-ended memory, etc. Volatile memory 2310A includes random access memory (RAM) and, in some embodiments, may include cache memory. As an example and not a limitation, RAM comes in many forms such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDR SDRAM), and enhanced SDRAM (ESDRAM).

[0196] Computer 2302 may further include removable / non-removable, volatile / non-volatile computer storage media. For example, Figure 23Disk storage device 2306 is shown. Disk storage device 2306 includes, but is not limited to, devices such as disk drives, solid-state drives (SSDs), floppy disk drives, tape drives, Jaz drives, Zip drives, LS-100 drives, flash memory cards, or memory sticks. Furthermore, disk storage device 2306 may include storage media, alone or in combination with other storage media, including, but not limited to, optical disc drives such as optical disc ROM devices (CD-ROM), CD recordable drives (CD-R drives), CD rewritable drives (CD-RW drives), or digital universal optical disc ROM drives (DVD-ROM). To facilitate connection of disk storage device 2306 to system bus 2308, a removable or non-removable interface, such as storage interface 2312, is typically used. It should be understood that storage device 2306 may store user-related information. This information may be stored in or provided to a server or an application running on a user device. In one embodiment, the type of information stored in disk storage device 2306 or transferred to a server or application may be notified to the user (e.g., via output device 2332). Users may be given the opportunity to opt in or out of collecting information from a server or application and / or share such information with the server or application (e.g., via input from input device 2342).

[0197] It should be understood that Figure 23 Software is described that acts as an intermediary between the user and the basic computer resources described in the appropriate operating environment 2300. This software includes an operating system 2306A. The operating system 2306A, which may be stored on disk storage 2306, is used to control and allocate the resources of the computer system 2302. Application program 2306C utilizes the operating system 2306A to manage resources through program modules 2306D and program data 2306D, such as start / stop transaction tables, which are stored in system memory 2310 or disk storage 2306. It should be understood that the claimed subject matter can be implemented with various operating systems or combinations of operating systems.

[0198] Users input commands or information to computer 2302 via input device 2342. Input device 2342 includes, but is not limited to, pointing devices such as mice, trackballs, styluses, touchpads, keyboards, microphones, joysticks, gamepads, satellite dishes, scanners, TV tuner cards, digital cameras, digital camcorders, webcams, etc. These and other input devices are connected to processing unit 2304 via system bus 2308 and input port 2340. For example, input port 2340 includes serial ports, parallel ports, game ports, and Universal Serial Bus (USB). Output device 2332 uses some of the same type of ports as input device 2342. Therefore, for example, a USB port can be used to provide input to computer 2302 and output information from computer 2302 to output device 2332. Output adapter 2330 is provided to illustrate the existence of other output devices 2332 that require special adapters, such as monitors, speakers, and printers. By way of example and not limitation, output adapter 2330 includes a video and sound card that provides a connection between output device 2332 and system bus 2308. It should be noted that other devices and / or systems of devices provide both input and output capabilities, such as remote computer 2338.

[0199] Computer 2302 can operate in a networked environment using a logical connection to one or more remote computers (e.g., remote computer 2324). Remote computer 2324 can be a personal computer, server, router, network PC, workstation, microprocessor-based device, peer-to-peer device, smartphone, tablet, or other network node, and typically includes many of the elements described relative to computer 2302. For simplicity, only remote computer 2324 is shown as a memory storage device 2326. Remote computer 2324 is logically connected to computer 2302 via network 2322 and then via communication interface 2320. Network 2322 includes wired or wireless communication networks, such as local area networks (LANs) and wide area networks (WANs), as well as cellular networks. LAN technologies include Fiber Distributed Data Interface (FDDI), Copper Distributed Data Interface (CDDI), Ethernet, Token Ring, etc. WAN technologies include, but are not limited to, point-to-point links, circuit-switched networks (such as Integrated Services Digital Network (ISDN) and its variants), packet-switched networks, and Digital Subscriber Line (DSL).

[0200] Communication interface 2320 refers to the hardware / software used to connect network 2322 to bus 2308. Although for clarity, communication interface 2320 is shown as being inside computer 2302, it may also be located outside computer 2302. For illustrative purposes only, the hardware / software required to connect to network 2322 includes internal and external technologies such as modems (including conventional telephone-grade modems, cable modems, and DSL modems), ISDN adapters, wired and wireless Ethernet cards, hubs, and routers.

[0201] The aspects shown in this disclosure can also be implemented in a distributed computing environment, where certain tasks are performed by remote processing devices linked via a communication network. In a distributed computing environment, program modules or stored information, instructions, etc., can reside in local or remote memory storage devices.

[0202] Furthermore, it should be understood that the various components described herein may include circuits, which may include components and circuit elements of suitable value to implement embodiments of this disclosure. Furthermore, it should be understood that many different components may be implemented on one or more IC chips. For example, in one embodiment, a set of components may be implemented in a single IC chip. In other embodiments, one or more corresponding components are fabricated or implemented on separate IC chips.

[0203] Regarding the various functions performed by the aforementioned components, architectures, circuits, processes, etc., unless otherwise stated, the terminology used to describe such components (including references to "method") is intended to correspond to any component that performs the specific function of the described component (e.g., functionally equivalent), even if it is not structurally equivalent to the disclosed structure (which performs the functions in the exemplary aspects of the embodiments shown herein). In this regard, it will also be appreciated that the embodiments include systems having computer-executable instructions for performing actions and / or events of various processes, as well as computer-readable media.

[0204] Furthermore, while a particular feature may be disclosed only for one of several implementations, such feature may be combined with one or more other features of other implementations that are anticipated and advantageous for any given or particular application. Additionally, where the terms “comprising” and “including” and variations thereof are used in the detailed description or claims, these terms are intended to be inclusive, similar to the term “comprising.”

[0205] As used herein, the term “or” is intended to mean inclusive “or” rather than exclusive “or.” That is, unless otherwise stated or explicitly indicated by context, “X uses A or B” is intended to mean any reasonable inclusive arrangement. That is, “X uses A or B” holds true in any of the foregoing cases if X uses A; X uses B; or X uses both A and B. Furthermore, unless otherwise stated or explicitly indicated by context, the article “a” as used herein and in the appended claims should generally be interpreted as “one or more”.

[0206] Upon reading this disclosure, those skilled in the art can conceive of further embodiments. For example, in various embodiments, erase operations can be initiated simultaneously on multiple ReRAM devices (e.g., 16, 32, etc.).

[0207] In other embodiments, combinations or sub-combinations of the embodiments disclosed above may be advantageously performed. For ease of understanding, the architectural diagrams and flowcharts have been grouped. However, it should be understood that combinations of blocks, additions of new blocks, rearrangements of blocks, etc., are considered alternative embodiments of this disclosure.

[0208] It should also be understood that the examples and embodiments described herein are for illustrative purposes only, and various modifications or changes made thereto will be communicated to those skilled in the art and will be included within the spirit and scope of this application and the scope of the appended claims.

Claims

1. An electronic device comprising: A plurality of resistive switching devices are disposed on a substrate of a semiconductor die, wherein each of the plurality of resistive switching devices includes a resistive switching material layer disposed between a first electrode and a second electrode, wherein one of the first electrode or the second electrode contains metal particles that diffuse in the material of the resistive switching material layer in response to an external stimulus applied between the first electrode and the second electrode, and wherein the plurality of resistive switching devices are associated with an operating characteristic having a correlation coefficient in the range of -0.1 to 0.1 among the resistive switching devices; A first plurality of wires, the first plurality of wires providing an electrical connection to the top electrode of the plurality of resistive switching devices; A second plurality of wires, the second plurality of wires providing electrical connection to the bottom electrode of the plurality of resistive switching devices; Control circuitry, the control circuitry being configured to partition a subset of the plurality of resistive switching devices, thereby defining a first subset of the resistive switching devices for generating a data sequence based on the operating characteristics having the correlation coefficient; and A sensing circuit, at least partially disposed on a semiconductor substrate and electrically connected to a plurality of resistive switching devices via a first plurality of wires and a second plurality of wires, wherein the sensing circuit is configured to selectively apply a sensing signal to a first wire of the first plurality of wires and a second wire of the second plurality of wires to apply the sensing signal to a first resistive switching device in a first subset of the resistive switching devices, wherein the sensing circuit is configured to determine a first response signal from the first resistive switching device in response to the sensing signal, and wherein the sensing circuit is configured to selectively apply the sensing signal to a first wire of the first plurality of wires and a third wire of the second plurality of wires to apply the sensing signal to a second resistive switching device in the first subset of the resistive switching devices, wherein the sensing circuit is configured to determine a second response signal from the second resistive switching device in response to the sensing signal.

2. The electronic device according to claim 1, wherein, The control circuit is configured to receive an input command to determine the subset of the resistive switching devices, wherein, in response to receiving the input command, the subset of the plurality of resistive switching devices is divided and the first subset of the resistive switching devices is defined.

3. The electronic device according to claim 1, wherein, The control circuit is further configured to divide the plurality of resistive switching devices into an additional subset, thereby defining a second subset of one-time programmable resistive switching devices, wherein the additional subset is different from the subset of the plurality of resistive switching devices and is used for one-time programmable operation.

4. The electronic device according to claim 3, wherein, The control circuit is further configured to define a third subset of the rewritable non-volatile resistor storage devices as resistor switching devices that are not included in the first subset of the resistor switching devices and are not included in the second subset of the one-time programmable resistor switching devices.

5. The electronic device according to claim 1, wherein, The correlation coefficient between the first response signal and the second response signal is in the range of -0.1 to 0.

1.

6. The electronic device according to claim 5, wherein, The correlation coefficient between the first response signal and the second response signal is in the second range of -0.01 to 0.

01.

7. The electronic device according to claim 6, wherein, The correlation coefficient between the first response signal and the second response signal is in the third range of -0.003 to 0.

003.

8. The electronic device according to claim 1, wherein, In response to the first response signal and the sensing signal, a first feature associated with the first resistive switching device is determined; and In response to the second response signal and the sensing signal, a second feature associated with the second resistive switching device is determined.

9. The electronic device according to claim 8, wherein, The first feature and the second feature are selected from the group consisting of intrinsic unprogrammed current, intrinsic programming voltage, intrinsic programming speed, maximum programming current, programming resistance, erase voltage, minimum erase current, and at least one erase state current after programming and erasing.

10. The electronic device according to claim 1, wherein, The control circuit further includes a processing circuit communicatively connected to the sensing circuit and configured to compare the first response signal and the second response signal with one or more qualitative or quantitative references.

11. The electronic device according to claim 10, wherein, The processing circuit is configured to assign a binary value to the first response signal based on a comparison of the first response signal with a reference among the one or more qualitative or quantitative references.

12. The electronic device according to claim 10, wherein, The processing circuit is further configured to assign a second binary value to the second response signal based on a comparison between the second response signal and the reference, wherein the processing circuit is configured to generate the data sequence at least in part from the binary value and the second binary value.

13. The electronic device according to claim 10, wherein, The processing circuit is configured to assign a first logic value to the first response signal or the second response signal if the value of the first response signal or the second response signal is lower than the lower of the one or more qualitative or quantitative benchmarks. The processing circuit is configured to assign a second logic value to the first response signal or the second response signal if the value of the first response signal or the second response signal is higher than the higher of the one or more qualitative or quantitative references.

14. The electronic device according to claim 13, wherein, The processing circuit is configured to discard the first response signal or the second response signal if the value of the first response signal or the second response signal is higher than the lower reference and lower than the higher reference.

15. The electronic device according to claim 14, wherein, The processing circuit is configured to generate the data sequence at least in part from a first digital value or a second digital value.

16. The electronic device according to claim 13, wherein, The processing circuit is configured to receive an input value and to determine an output value in response to the input value, the first logic value, and the second logic value.

17. The electronic device according to claim 13, wherein, The processing circuit is configured as follows: Receive the first input value and the second input value; A first output value is determined in response to the first input value and the first logic value; and The second output value is determined in response to the second input value and the second logic value.

18. The electronic device according to claim 1, wherein, The control circuit is configured to store the order of the first subset of the resistive switching device and generate the data sequence by bit values ​​derived from the operating characteristics of the first subset of the resistive switching device, wherein the bit values ​​are sorted according to the first subset of the resistive switching device to generate the data sequence.

19. The electronic device according to claim 1, wherein, The control circuit is configured to define multiple groups of two or more resistor switching devices from a first subset of the resistor switching devices, and to assign each group of two or more resistor switching devices to a specific bit of the data sequence.

20. The electronic device according to claim 19, wherein, The control circuit, in response to a first resistive switch device among two or more resistive switch devices in the group to be assigned a bit conforming to a criterion, assigns a first logic value to the bit of the data sequence, wherein the criterion is selected from the group consisting of a first manifest programming event, a first manifest erase event, a minimum intrinsic current magnitude, a minimum intrinsic programming voltage, and a minimum erase voltage. The control circuit assigns a second logic value to the bit of the data sequence in response to the second resistor switch in one of the two or more resistor switch devices in the group assigned to the bit conforming to the criterion.

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