Bottom package and manufacturing method thereof, and stacked package structure and manufacturing method thereof

Abstract

The application discloses a bottom package, a manufacturing method of the bottom package, a stacked package structure and a manufacturing method of the stacked package structure. The manufacturing method of the bottom package comprises the following steps: processing a through hole on an organic resin core plate, and performing electroplating to form an interconnection metal column in the through hole; processing a through slot on the organic resin core plate after the electroplating, and fixing the organic resin core plate after the processing of the through slot on a hard temporary carrier; placing a preset chip in the through slot above the hard temporary carrier, and making a pad side of the preset chip away from the hard temporary carrier; plastic packaging the preset chip in the through slot from the pad side of the preset chip, and grinding the pad side of the organic resin core plate after the plastic packaging to expose the pad of the preset chip; manufacturing a first connecting line on the pad side of the organic resin core plate after the grinding; and removing the hard temporary carrier, and manufacturing a second connecting line on a non-pad side of the preset chip. By using the application, the three-dimensional interconnection structure has high density, low manufacturing cost and more delicate surface line of the chip.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor packaging, and in particular to a bottom package, a manufacturing method thereof, a stacked package structure and a manufacturing method thereof. BACKGROUND

[0002] In modern chip packaging technology, one widely used chip packaging technology is the stacked package (Package on Package, PoP), the main idea of which is to stack a memory chip on top of a logic chip (or flip-chip). Of course, it can further be mounted on the top of the logic chip.

[0003] The biggest technical challenge of chip stacked packaging is the interconnection problem between the bottom package and the top package. Currently, the interconnection between the bottom package and the top package mainly adopts three methods:

[0004] The first method is based on traditional packaging technology, that is, after the chip is molded on the packaging substrate as a bottom package, a hole is drilled in the molding layer of the bottom package, and the interconnection is realized by filling conductive paste in the hole, and then the top package is flip-chip mounted on the top of the bottom package. The biggest disadvantage of this scheme is that the laser drilling or tin ball size is large, so the density of the three-dimensional interconnection structure is low.

[0005] The second method is based on advanced packaging technology, which first makes a seed layer on a temporary carrier, then pastes a dry film to electroplate copper pillars, and etches the seed layer, thus obtaining a three-dimensional interconnection structure, further mounting the chip, and finally molding the chip to grind the copper pillars, thus obtaining a three-dimensional interconnection structure. The advantage of this scheme is that the density of the three-dimensional interconnection structure is high, but the manufacturing cost is also high. During chip molding, the molding material has a large flow distance, which has an adverse effect on the mounting accuracy of the chip. In addition, due to the low modulus of the molding material, the scheme will have difficulty in transferring, that is, after the temporary carrier is removed, there is a risk of sample fragmentation.

[0006] The third type of method is also based on advanced packaging technology, first, a through hole is processed on an organic resin core board for a printed circuit board, then electroplating is performed to realize interconnection on both sides of the organic resin core board, then a through slot is processed at a designated position, then adhesive tape is sequentially pasted, and a chip is attached to the adhesive tape in the through slot, and finally the chip is molded, so that a three-dimensional interconnection structure is obtained. The biggest advantage of this scheme is low cost, and there is a through slot limit, the flow distance of the molding material is short, which can reduce the influence on the position accuracy of the chip. Another advantage is that the organic resin core board is reinforced with glass cloth, so the modulus is larger, the processing process is difficult to transfer, and the product has strong warpage resistance. But the disadvantage is also obvious, that is, the thermal expansion coefficient of the adhesive tape is larger than that of the organic resin core board and the molding material, and this mismatch of the thermal expansion coefficient leads to a large deviation of the position of the chip during the molding process. And because of uneven heating, it is also difficult to completely avoid irregular deviation of the chip by pre-compensation through the difference in thermal expansion coefficient. Because the flatness of the organic resin core board is poorer than that of the special temporary carrier such as glass, the fineness of the surface circuit is also affected.

[0007] In summary, the existing packaging technology has the problems of low density of three-dimensional interconnection structure, high manufacturing cost, and low fineness of chip surface circuit. SUMMARY

[0008] Therefore, a bottom package and a manufacturing method thereof, and a stacked package structure and a manufacturing method thereof are provided to solve the problems of low density of three-dimensional interconnection structure, high manufacturing cost, and low fineness of chip surface circuit in the prior art.

[0009] The manufacturing method of the bottom package provided by the embodiment of the present application comprises the following steps.

[0010] A through hole is processed on an organic resin core board, and electroplating is performed to form an interconnection metal column in the through hole;

[0011] A through slot is processed on the organic resin core board after electroplating, and the organic resin core board after the through slot is processed is fixed on a hard temporary carrier;

[0012] A preset chip is placed in the through slot above the hard temporary carrier, and a pad side of the preset chip is away from the hard temporary carrier;

[0013] The preset chip in the through slot is molded from the pad side of the preset chip, and the pad side of the molded organic resin core board is ground to expose the pad of the preset chip;

[0014] A first connection circuit is formed on the pad side of the ground organic resin core board;

[0015] Releasing the hard temporary carrier, forming a second connecting line on the non-pad side of the preset chip, and forming the bottom package.

[0016] Optionally, the fixing the organic resin core board after processing the through slot on the hard temporary carrier comprises:

[0017] Optionally, the fixing the organic resin core board after processing the through slot on the hard temporary carrier comprises:

[0018] Optionally, the fixing the organic resin core board after processing the through slot on the hard temporary carrier comprises:

[0019] Optionally, the fixing the organic resin core board after processing the through slot on the hard temporary carrier comprises:

[0020] Optionally, the placing the preset chip in the through slot above the hard temporary carrier, with the pad side of the preset chip away from the hard temporary carrier comprises:

[0021] Optionally, the placing the preset chip in the through slot above the hard temporary carrier, with the pad side of the preset chip away from the hard temporary carrier comprises:

[0022] Optionally, the placing the preset chip in the through slot above the hard temporary carrier, with the pad side of the preset chip away from the hard temporary carrier comprises:

[0023] Optionally, the hard temporary carrier has a release layer on the side close to the organic resin core board, and the adhesive and the chip attaching film are attached to the release layer.

[0024] Optionally, the method further comprises: after releasing the hard temporary carrier, removing part of the chip attaching film, so that the surface of the remaining part of the chip attaching film is lower than or flush with the surface of the organic resin core board on the non-pad side of the preset chip.

[0025] Optionally, the forming the first connecting line on the pad side of the organic resin core board after grinding comprises:

[0026] Optionally, the forming the first connecting line on the pad side of the organic resin core board after grinding comprises:

[0027] Optionally, the forming the second connecting line on the non-pad side of the preset chip comprises:

[0028] Optionally, the forming the second connecting line on the non-pad side of the preset chip comprises:

[0029] Optionally, the forming the second connecting line on the non-pad side of the preset chip comprises:

[0030] Optionally, the method further comprises the step of forming a surface treatment layer on the first connecting line and the second connecting line.

[0031] The method for manufacturing the bottom package provided by the application adopts the organic resin core plate to assist the chip plastic sealing, which can manufacture the interconnection metal column with low cost and high yield, improve the mechanical strength of the chip plastic sealing layer, is especially suitable for large-size advanced package, can reduce the amount of plastic sealing material and the material cost of plastic sealing. In addition, the method for manufacturing the bottom package provided by the application can improve the warpage resistance of the package, and is beneficial to realize the larger-size package and improve the integration of the package product. The hard temporary carrier is adopted to assist the plastic sealing chip, specifically, the hard temporary carrier with small thermal expansion coefficient and isotropy is selected, which can significantly improve the predictability of the chip position deviation during the chip plastic sealing and the position precision after the chip plastic sealing, and is beneficial to improve the alignment precision of the conductive line on the chip pad side and the chip. The hard temporary carrier is adopted to assist the line manufacturing, specifically, the high-flatness hard temporary carrier is selected, and the grinding technology is combined, which can obtain the high-flatness surface on the chip pad side, is beneficial to manufacture the high-precision conductive line on the chip pad side and improve the chip packaging density.

[0032] The method for manufacturing the stacked package structure provided by the embodiment of the application comprises the following steps:

[0033] The bottom package is obtained according to the method for manufacturing the bottom package.

[0034] One side of the bottom package is welded to the printed circuit board, and the top package is attached to the other side of the bottom package.

[0035] Compared with the conventional stacked package technology, the method for manufacturing the stacked package structure provided by the application has the advantages of fine line, small chip drift and good predictability. The organic resin core plate is adopted to manufacture the three-dimensional interconnection structure, which has the advantages of low manufacturing cost, short plastic sealing material flow distance, low processing and transportation difficulty and good warpage resistance, thereby avoiding the shortcomings of the conventional stacked package scheme.

[0036] The bottom package provided by the embodiment of the application comprises the following parts:

[0037] The organic resin core plate of the organic resin material has a through hole, and the through hole is electroplated with an interconnection metal column;

[0038] The organic resin core plate is provided with a through slot, and a preset chip is plastic sealed in the through slot; the pads of the plastic sealed preset chip are exposed from the through slot;

[0039] The pad side of the organic resin core plate is formed with a first connecting line; and the non-pad side of the organic resin core plate is formed with a second connecting line.

[0040] The bottom package provided by the application embeds a chip in an organic resin core plate, and a three-dimensional interconnection structure is made of the organic resin core plate, so that the three-dimensional interconnection structure has high density, high efficiency and low cost, and in addition, the organic resin of the core plate structure has the characteristic of short flow distance, which is beneficial to improving the mounting precision of the chip. The bottom package has fine lines, avoids the problem of large chip drift, and has higher packaging structure density.

[0041] The embodiment of the application provides a stacked packaging structure, and the stacked packaging structure comprises:

[0042] The bottom package, the printed circuit board and the top package, the top package comprises a top package chip and a passive element.

[0043] The bottom package is mounted on the printed circuit board through the second connecting line or the first connecting line, and the top package chip and the passive element in the top package are mounted on the first connecting line or the second connecting line of the bottom package.

[0044] Compared with the conventional stacked packaging structure, the stacked packaging structure provided by the application has the advantages of fine lines, small chip drift and good predictability. The three-dimensional interconnection structure made of the organic resin core plate has the advantages of low manufacturing cost, short plastic flow distance, low processing and transportation difficulty and good warpage resistance, thereby avoiding the shortcomings of the conventional stacked packaging scheme. BRIEF DESCRIPTION OF DRAWINGS

[0045] In order to more clearly illustrate the technical solutions of the embodiments of the application, the following will briefly introduce the drawings needed to be used in the description of the embodiments of the application. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.

[0046] Figure 1 It is a flow chart of the manufacturing method of the bottom package provided by the embodiment of the application;

[0047] Figure 2 It is a flow chart of the manufacturing method of the stacked packaging structure provided by the embodiment of the application;

[0048] Figure 3-1 It is a schematic diagram of processing a through hole on a core plate provided by the embodiment of the application;

[0049] Figure 3-2is a schematic diagram of through-hole electroplating on a core board provided by an embodiment of the present application;

[0050] Figure 3-3 is a schematic diagram of machining a through slot on a core board provided by an embodiment of the present application;

[0051] Figure 3-4 is a schematic diagram of pasting adhesive on a core board provided by an embodiment of the present application;

[0052] Figure 3-5 is a schematic diagram of removing adhesive in a through slot on a core board provided by an embodiment of the present application;

[0053] Figure 3-6 is a schematic diagram of pasting a hard temporary carrier on a core board through adhesive provided by an embodiment of the present application;

[0054] Figure 3-7 is a schematic diagram of pasting a preset chip in a through slot on a hard temporary carrier provided by an embodiment of the present application;

[0055] Figure 3-8 is a schematic diagram of plastic packaging of a preset chip in a through slot provided by an embodiment of the present application;

[0056] Figure 3-9 is a schematic diagram of grinding a plastic packaging layer of a preset chip provided by an embodiment of the present application;

[0057] Figure 3-10 is a schematic diagram of forming a first connecting circuit on a surface of a core board provided by an embodiment of the present application;

[0058] Figure 3-11 is a schematic diagram of removing a hard temporary carrier and grinding a side of a core board where the hard temporary carrier is removed provided by an embodiment of the present application;

[0059] Figure 3-12 is a schematic diagram of manufacturing a connecting pad on a non-pad side of a core board provided by an embodiment of the present application;

[0060] Figure 3-13 is a schematic diagram of manufacturing a second connecting circuit on a non-pad side of a core board provided by an embodiment of the present application;

[0061] Figure 3-14 is a schematic diagram of ball planting of a first connecting circuit provided by an embodiment of the present application;

[0062] Figure 3-15 is a schematic diagram of soldering a bottom package to a printed circuit board provided by an embodiment of the present application;

[0063] Figure 3-16 is a schematic diagram of pasting a top package to a bottom package provided by an embodiment of the present application;

[0064] Figure 4-1 is a schematic diagram of a second connection line ball placement provided by another embodiment of the present application;

[0065] Figure 4-2 is a schematic diagram of a bottom package soldered to a printed circuit board provided by another embodiment of the present application;

[0066] Figure 4-3 is a schematic diagram of a bottom package attached to a top package provided by another embodiment of the present application;

[0067] Figure 5 is a schematic diagram of a stacked package structure provided by an embodiment of the present application;

[0068] Figure 6 is a schematic diagram of a stacked package structure provided by another embodiment of the present application;

[0069] wherein 1 is an organic resin core plate, 2 is a through hole, 3 is an interconnection metal column, 4 is a through slot, 5 is adhesive glue, 6 is a hard temporary carrier, 7 is a chip, 8 is plastic sealing material, 9 is a connecting plate, 10 is a first connection line, 11 is a second connection line, 12 is a BGA solder ball, 13 is a printed circuit board, 14 is a passive element, 15 is a top package chip, 16 is a chip attaching film, 17 is a top package, 18 is a bottom package, and 19 is a printed circuit board. DETAILED DESCRIPTION

[0070] In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular sequences of steps, techniques, etc., in order to provide a thorough understanding of the embodiments of the present application. However, it will be apparent to those skilled in the art that the present application can be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known methods, devices, and apparatuses are omitted so as not to obscure the description of the present application with unnecessary detail.

[0071] It is to be understood that the terminology "includes", "has", "holds", "contains" and / or "comprising", when used in the present specification and in the accompanying claims, is taken to specify the presence of stated features, integers, steps, operations, elements, and / or components but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0072] It is also to be understood that the terminology "and / or" when used in the present specification and in the accompanying claims includes all possible combinations of one or more of the associated listed items and that the term "at least one of A and B" is intended to mean "at least one but not more than one of A and B".

[0073] As used in the description of the application and the appended claims, the term “if’ can be interpreted to mean “when” or “upon” or “in response to determining” or “in response to detecting” depending on the context. Similarly, the phrase “if it is determined” or “if [a described condition or event] is detected” can be interpreted to mean “upon determining” or “in response to determining” or “upon detecting [the described condition or event]” or “in response to detecting [the described condition or event]”, depending on the context.

[0074] In addition, in the description of the application and the appended claims, the terms “first”, “second”, “third”, etc. are used only to distinguish descriptions, and cannot be understood as indicating or implying relative importance.

[0075] In the description of the application, the reference to “one embodiment” or “some embodiments” and the like means that the particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the application. Therefore, the statements “in one embodiment”, “in some embodiments”, “in other some embodiments”, “in further some embodiments” and the like appearing in various places in the specification are not necessarily all referring to the same embodiment, but mean “one or more but not all embodiments”, unless otherwise specifically stated. The terms “include”, “contain”, “have” and their variants mean “include but not limited to”, unless otherwise specifically stated.

[0076] It should be understood that the size of the serial number of each step in the following embodiments does not mean the order of execution, and the execution order of each process should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the application.

[0077] In order to illustrate the technical solutions of the application, the following specific embodiments are described.

[0078] Referring to Figure 1 is a flowchart of a method for manufacturing a bottom package provided by an embodiment of the application, and the method comprises:

[0079] S101, machining a through hole on an organic resin core plate, and electroplating to form an interconnection metal column in the through hole.

[0080] Referring to Figure 3-1 and Figure 3-2, select one organic resin core board 1, as preferred, the organic resin core board 1 can be the organic resin core board 1 with copper foil on the surface, and the through hole 2 is processed at the preset position of the organic resin core board 1 where the interconnection metal column 3 needs to be made. The method of processing the through hole 2 on the organic resin core board 1 can be to drill the through hole 2 on the organic resin core board 1 by mechanical drilling, or to process the through hole 2 on the organic resin core board 1 by laser. The electroplating is to electroplate the upper and lower surfaces of the organic resin core board 1 and the through hole 2, and the electroplating material can be copper. The electroplating method is to use the existing technology of sputtering, evaporation or chemical copper plating, adsorption of conductive materials and other methods to cover the through hole wall with a conductive seed layer, and then to fill the through hole 2 of the organic resin core board 1 with metal, i.e. copper, by electroplating to form the interconnection metal column 3, also known as three-dimensional interconnection structure.

[0081] S102, processing a through slot on the organic resin core board after electroplating, and fixing the organic resin core board after processing the through slot on the hard temporary carrier.

[0082] Referring to Figure 3-3 , the through slot 4 is processed on the organic resin core board 1 at the position where the preset chip needs to be embedded, and the size of the through slot 4 is larger than the size of the preset chip. Alternatively, the through slot 4 can accommodate one preset chip or two or more preset chips. The method of processing the through slot 4 on the organic resin core board 1 can be to process the organic resin core board 1 by laser to expose the through slot 4 of the organic resin core board 1, or to expose the through slot 4 of the organic resin core board 1 by mechanical processing.

[0083] In an example, fixing the organic resin core board 1 after processing the through slot 4 on the hard temporary carrier 6 includes:

[0084] As shown in Figure 3-4 , the adhesive is pasted on one side of the organic resin core board 1 after processing the through slot 4;

[0085] As shown in Figure 3-5 , the adhesive in the through slot is cut off;

[0086] As shown in Figure 3-6 , the side of the organic resin core board 1 with the adhesive is attached to the hard temporary carrier 6.

[0087] In an example, the adhesive can be double-sided adhesive, one side for attaching to one side of the organic resin core board 1, and the other side for attaching to the hard temporary carrier 6. The function of the adhesive is to better fix the organic resin core board to the hard temporary carrier 6. When cutting the adhesive in the above-mentioned through slot, the technology known to those skilled in the art can be used, such as laser processing.

[0088] The rigid temporary carrier 6 can be one of a glass carrier, a stainless steel carrier or a silicon wafer carrier. When a silicon wafer is used as the rigid temporary carrier 6, the rigid temporary carrier 6 must be circular, while when a glass or stainless steel is used as the rigid temporary carrier 6, the rigid temporary carrier 6 can be circular or square.

[0089] S103, placing the preset chip in the through slot above the rigid temporary carrier, with the pad side of the preset chip away from the rigid temporary carrier.

[0090] Referring to Figure 3-7 , the number of the preset chips 7 accommodated in the through slot above the rigid temporary carrier 6 is not limited and can be one, two or more.

[0091] In an example, placing the preset chip 7 in the through slot above the rigid temporary carrier 6, with the pad side of the preset chip 7 away from the rigid temporary carrier specifically includes:

[0092] attaching the non-pad side of the preset chip 7 with the chip attaching film 16;

[0093] attaching the preset chip in the through slot 4 above the rigid temporary carrier 6 through the chip attaching film 16.

[0094] The chip attaching film 16 is used on the non-pad side of the preset chip 7 to replace the original adhesive tape, and the preset chip 7 is attached to the rigid temporary carrier 6 with good coefficient of thermal expansion matching and uniformity, avoiding the problem of large drift of the preset chip 7 caused by large difference in the coefficient of thermal expansion of the adhesive tape in the prior art solution, and the fixing effect of the chip attaching film using resin curing and fixing is better than that of the adhesive tape whose viscosity is greatly affected by temperature.

[0095] In an example, the rigid temporary carrier 6 is provided with a release layer on the side close to the organic resin core plate 1, and the adhesive and the chip attaching film are attached to the release layer.

[0096] The release layer can be a light-sensitive debonding release layer or a heat-sensitive debonding release layer, and is preferably a light-sensitive debonding release layer.

[0097] The release layer is provided to facilitate the peeling of the organic resin core plate 1 and the chip attaching film 16 from the rigid temporary carrier, and the release layer can ensure that the adhesive and the cured chip attaching film 16 are peeled from the rigid temporary carrier without causing the rigid temporary carrier to break, the adhesive to remain and the chip attaching film to break due to the huge stress during peeling.

[0098] S104, plastic packaging the preset chip from the preset chip in the through slot on the pad side of the preset chip, and grinding the pad side of the organic resin core plate after plastic packaging to expose the pad of the preset chip.

[0099] It is particularly pointed out that the pad side in the present application refers to the preset chip pad side, and the non-pad side in the present application refers to the preset chip non-pad side.

[0100] Referring to Figure 3-8 The preset chip 7 in the pad side of the preset chip 7 in the plastic encapsulation through slot 4 is filled with plastic encapsulation material 8 in the gap between the through slot wall of the organic resin core plate 1 and the preset chip 7, and covers the upper surface of the organic resin core plate 1. When two or more preset chips 7 are placed in one through slot 4, the plastic encapsulation material 8 also fills the gap between the preset chips 7.

[0101] The plastic encapsulation material 8 is also called epoxy plastic encapsulation material, which is an encapsulation material for electronic components. It is made of epoxy resin, phenolic resin as base resin, silicon powder as filler, and various additives. It is a prior art.

[0102] The plastic encapsulation material 8 can be in the form of particles, liquid or film, and the plastic encapsulation method can be compression molding or vacuum film lamination. When vacuum film lamination is used, only thin film type epoxy plastic encapsulation material can be used.

[0103] Referring to Figure 3-9 The pad side of the plastic-encapsulated organic resin core plate 1 is ground to expose the pads of the preset chip 7. The grinding can be performed by mechanical grinding, which grinds off the plastic encapsulation material 8 and the metal layer on the upper surface of the pad side of the preset chip 7, so that the metal layer on the pad side surface of the organic resin core plate 1 is completely ground off and the pads on the surface of the preset chip 7 are exposed. Because the surface of the hard temporary carrier has high flatness, the surface of the organic resin core plate 1 after grinding can have high flatness, which is beneficial to the manufacture of fine lines.

[0104] S105, forming a first connection line on the pad side of the ground organic resin core plate.

[0105] Referring to Figure 3-10 In an example, forming a first connection line 10 on the pad side of the ground organic resin core plate 1 specifically includes:

[0106] The lamination method is used to make a plurality of cycles of conductive lines on the pad side of the preset chip 7, each cycle being made by the semi-additive method to obtain a preset number of first connection lines 10.

[0107] The preset chip 7 is adhered to the surface of the organic resin core plate 1 through the chip adhering film 16, and the hard temporary carrier 6 is adhered to the surface of the organic resin core plate 1 through the adhesive layer 5. The hard temporary carrier 6 is removed, and the first connecting circuit 10 is formed on the non-pad side of the preset chip 7.

[0108] The process of forming the first connecting circuit 10 is prior art and will not be described here.

[0109] S106, the hard temporary carrier is removed, and the second connecting circuit is formed on the non-pad side of the preset chip to form a bottom package.

[0110] Referring to Figure 3-11 The way of removing the hard temporary carrier can be determined according to the type of the release layer, which is prior art and will not be described here. The adhesive layer, i.e., the adhesive glue, on the non-pad side of the organic resin core plate 1 is removed, and the plasma is used to etch and remove part of the protruding chip adhering film 16, so that the surface of the chip adhering film 16 is flush with or slightly recessed from the surface metal layer on the non-pad side of the organic resin core plate 1 after the hard temporary carrier 6 is removed. Then, part of the chip adhering film 16 is removed, so that the surface of the remaining chip adhering film 16 is lower than or flush with the surface of the organic resin core plate 1 on the non-pad side of the preset chip 7.

[0111] Optionally, forming the second connecting circuit 11 on the non-pad side of the preset chip 7 specifically includes:

[0112] Referring to Figure 3-12 The connecting pad 9 is formed on the position of the interconnection metal column 3 on the surface of the non-pad side of the organic resin core plate 1 through the subtractive method; the diameter of the connecting pad 9 is greater than the diameter of the interconnection metal column 3.

[0113] In an example, the connecting pads can also be made by subtractive method at the positions of the interconnection metal pillars on the non-pad side surface of the organic resin core board after the interconnection metal pillars 3 are obtained by electroplating in step S101. The advantage of this scheme is that the connecting pads can be used as the reference points for the chip mounting, and the amount of grinding of the metal layer on the pad side of the organic resin core board in step S104 is reduced. In addition, in this example, the step of removing part of the protruding chip attaching film by plasma in step S106 can be omitted, but the disadvantage is that the connecting pads on the non-pad side surface of the organic resin core board in this example will be embedded in the adhesive, and the adhesive will be directly bonded to the metal-free part of the surface of the organic resin core board. Therefore, when the organic resin core board is attached to the hard temporary carrier, the local pressure of the protruding connecting pads is higher, and the porous structure left after etching of the metal layer on the surface of the organic resin core board increases the risk of adhesive residue when the adhesive is removed after the hard temporary carrier is debonded. The adhesive residue increases the risk of delamination of the package and reduces the reliability of the package.

[0114] In an example, no connecting pads are made at the positions of the interconnection metal pillars 3 on the non-pad side surface of the organic resin core board 1, which is used to make finer lines to obtain a higher density package structure.

[0115] Referring to Figure 3-13 The second connecting lines 11 are made by additive method on the non-pad side surface of the organic resin core board 1 in several cycles to obtain the target number of layers.

[0116] The target number of layers of conductive line layers are made by additive method in several cycles on the non-pad side of the preset chip 7, which includes conductive lines and insulating medium. The conductive lines are preferably made by semi-additive method, or can be made by subtractive method. The photoresist material is selected according to the fineness of the conductive lines, and the photoresist material is preferably dry film. The insulating medium is selected according to the fineness of the conductive lines, and the insulating medium layer is preferably ABF, or can be glass fiber cloth reinforced epoxy resin.

[0117] The process of making the second connecting lines 11 is a prior art, which is not described here.

[0118] Optionally, it also includes the step of making a surface treatment layer on the surface of the first connecting lines and the second connecting lines.

[0119] In the method for manufacturing the bottom package provided by the application, the organic resin core plate is used to assist the plastic packaging of the chip, so that the interconnection metal column can be manufactured at low cost and high yield, the mechanical strength of the plastic packaging layer of the chip can be improved, and the method is especially suitable for large-size advanced packaging, and the amount of plastic packaging material can be reduced and the material cost of the plastic packaging can be reduced. In addition, the use of the organic resin core plate to assist the plastic packaging of the chip can improve the warpage resistance of the package, and is conducive to realizing a larger-size package and improving the integration of the packaged product. The hard temporary carrier is used to assist the plastic packaging of the chip, in particular, the hard temporary carrier with small thermal expansion and isotropy is selected, so that the predictability of the position deviation of the chip during the plastic packaging of the chip and the position accuracy after the plastic packaging of the chip can be significantly improved, and the alignment accuracy of the conductive circuit on the chip pad side and the chip can be improved. The hard temporary carrier is used to assist the manufacturing of the circuit, in particular, the hard temporary carrier with high flatness is selected, and the grinding technology is combined, so that the surface with high flatness can be obtained on the chip pad side, and the conductive circuit with high precision can be manufactured on the chip pad side, and the packaging density of the chip can be improved.

[0120] Referring to Figure 2 , a flow of a method for manufacturing a stacked package structure provided by an embodiment of the application is shown, and the method comprises the following steps:

[0121] S201, obtaining a bottom package manufactured according to the method for manufacturing the bottom package described above;

[0122] Referring to Figure 3-1 to Figure 3-13 , the bottom package is manufactured according to the method for manufacturing the bottom package described above, and details are not described herein.

[0123] S202, mounting a top package on the upper side of the bottom package, and welding the lower side of the bottom package to a printed circuit board.

[0124] In an example, referring to Figure 3-14 , the ball is planted on the first connection circuit surface on the preset chip pad side of the bottom package to form a BGA (Ball Gird Array, Ball Grid Array Package) tin ball 12, referring to Figure 3-15 , the bottom package is welded to the printed circuit board 13, and the encapsulation bottom is filled by dispensing. Referring to Figure 3-16 , the top package chip 15 and the passive element 14 are mounted on the conductive circuit surface on the chip non-pad side of the bottom package, and if the top package chip is flip-chip soldering, the encapsulation bottom of the top package is also filled by dispensing.

[0125] The filling agent used for dispensing is non-conductive glue or capillary bottom filling glue.

[0126] In an example, the top package is flip-chip soldered on the pad side of the buried chip, referring to Figure 4-1That is, the second connecting line 11 on the non-pad side of the preset chip 7 of the bottom package is surface-mounted with a ball, forming a BGA tin ball 12, see Figure 4-2 The bottom package is welded to the printed circuit board 13, and glue is applied to achieve bottom filling of the package. See Figure 4-3 The top package chip 15 and passive element 14 are surface-mounted on the conductive line of the chip 7 pad side of the bottom package, which has the advantage of shortening the interconnection distance between the embedded chip 7 and the top package, which is beneficial to reduce signal transmission loss, but the disadvantage is that the chip fan-out line density, that is, the number of interconnection solder balls with the printed circuit board, is limited by the density of the interconnection metal column, so it can only be suitable for chips with fewer inputs and outputs.

[0127] The manufacturing method of the stacked package structure provided by the present application has the advantages of fine lines, small chip drift, and good predictability compared with conventional stacked package technology. The three-dimensional interconnection structure made of an organic resin core plate has the advantages of low manufacturing cost, short plastic flow glue distance, low processing and transportation difficulty, and good warpage resistance, avoiding the disadvantages of conventional stacked package solutions.

[0128] See Figure 3-13 is a schematic diagram of a bottom package provided by an embodiment of the present application, the bottom package comprising:

[0129] The organic resin core plate 1 is made of an organic resin material, and the organic resin core plate 1 has a through hole in which an interconnection metal column 3 is electroplated;

[0130] A through slot is opened on the organic resin core plate 1, and a preset chip 7 is plastic encapsulated in the through slot; the pads of the plastic encapsulated preset chip 7 are exposed therefrom;

[0131] A first connecting line 10 is formed on the pad side of the organic resin core plate 1; and a second connecting line 11 is formed on the non-pad side of the organic resin core plate 1.

[0132] In an example, a chip attachment film 16 is further arranged between the non-pad side of the preset chip 7 and the organic resin core plate 1.

[0133] The bottom package provided by the present application embeds a chip in an organic resin core plate, and a three-dimensional interconnection structure is made of an organic resin core plate, so that the three-dimensional interconnection structure has low density, high efficiency, and low cost. In addition, the organic resin of the core plate structure has the characteristic of short flow distance, which is beneficial to improve the mounting accuracy of the chip. The present application uses a hard temporary carrier, and the pad side of the chip is polished to have high surface flatness, so that finer lines can be made.

[0134] See Figure 5 is a schematic diagram of a stacked package structure provided by an embodiment of the present application, the stacked package structure comprising:

[0135] The bottom package 18, the printed circuit board 19 and the top package 17, the top package 17 comprising: a top package chip and a passive element;

[0136] The bottom package 18 is mounted on the printed circuit board 19 through the first connecting lines, and the top package chip and the passive element in the top package 17 are mounted on the second connecting lines of the bottom package 18.

[0137] Referring to Figure 6 , it is a schematic diagram of a stack package structure provided by an embodiment of the present application, the stack package structure comprising:

[0138] The bottom package 18, the printed circuit board 19 and the top package 17, the top package 17 comprising: a top package chip and a passive element;

[0139] The bottom package 18 is mounted on the printed circuit board 19 through the first connecting lines, and the top package chip and the passive element in the top package 17 are mounted on the second connecting lines of the bottom package 18.

[0140] The stack package structure provided by the present application has the advantages of fine lines, small chip drift and good predictability compared with conventional stack package structures. The three-dimensional interconnection structure made of organic resin core plate has the advantages of low manufacturing cost, short plastic flow glue distance, low processing and transportation difficulty and good anti-warping capability, avoiding the shortcomings of conventional stack package solutions.

[0141] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. A method of fabricating a bottom package, comprising: The method comprises the following steps: processing a through hole on an organic resin core board, and electroplating to form an interconnection metal column in the through hole; processing a through slot on the organic resin core board after electroplating, and fixing the organic resin core board after processing the through slot on a hard temporary carrier; placing a preset chip in the through slot above the hard temporary carrier, and making the pad side of the preset chip away from the hard temporary carrier; molding the preset chip in the through slot from the pad side of the preset chip, and grinding the pad side of the molded organic resin core board to expose the pad of the preset chip; forming a first connection circuit on the pad side of the ground organic resin core board; removing the hard temporary carrier, forming a second connection circuit on the non-pad side of the preset chip, and forming the bottom package; the fixing of the organic resin core board after processing the through slot on the hard temporary carrier comprises: pasting adhesive on one side of the organic resin core board after processing the through slot; cutting off the adhesive at the through slot; attaching the organic resin core board with the adhesive on the hard temporary carrier; the placing of the preset chip in the through slot above the hard temporary carrier, and making the pad side of the preset chip away from the hard temporary carrier comprises: attaching the non-pad side of the preset chip to a chip attachment film; attaching the preset chip in the through slot above the hard temporary carrier through the chip attachment film.

2. The method for manufacturing the bottom package as described in claim 1, characterized in that, The hard temporary carrier has a release layer on the side close to the organic resin core board, and the adhesive and the chip attachment film are attached to the release layer.

3. The method of claim 1, wherein the step of forming the bottom encapsulant is performed by a method selected from the group consisting of a spin coating method, a dispensing method, a printing method, and a flow coating method. Further comprising: after removing the hard temporary carrier, removing part of the chip attachment film, and making the surface of the remaining part of the chip attachment film lower than or flush with the surface of the organic resin core board at the non-pad side of the preset chip.

4. The method for manufacturing the bottom package as described in claim 1, characterized in that, The forming of the first connection circuit on the pad side of the ground organic resin core board comprises: adopting a build-up method to make a conductive circuit on the pad side of the preset chip for several times, and adopting a semi-additive method to make each time to obtain a first connection circuit with a preset number of layers.

5. The method for manufacturing the bottom package as described in claim 1, characterized in that, The forming of the second connection circuit on the non-pad side of the preset chip comprises: making a connection pad on the surface of the non-pad side of the organic resin core board at the position of the interconnection metal column by a subtractive method; the diameter of the connection pad is greater than the diameter of the interconnection metal column; adopting a build-up method to make a second connection circuit with a target number of layers on the surface of the non-pad side of the organic resin core board for several times.

6. The method for manufacturing the bottom package as described in claim 1, characterized in that, Further comprising the step of making a surface treatment layer on the surface of the first connection circuit and the second connection circuit.

7. A method for fabricating a stacked package structure, the method comprising: The method comprises the following steps: obtaining a bottom package made by the method for making a bottom package according to any one of claims 1-6; welding one side of the bottom package to a printed circuit board, and attaching a top package to the other side of the bottom package.

8. A bottom package, characterized by, The bottom package is prepared by the method for making a bottom package according to any one of claims 1-6, comprising: an organic resin core board made of an organic resin material, the organic resin core board having a through hole, and an interconnection metal column electroplated in the through hole; The organic resin core plate is provided with a through slot, and a preset chip is plastic-sealed in the through slot; and the pads of the plastic-sealed preset chip are exposed; The pad side of the organic resin core plate is formed with a first connecting line, and the non-pad side of the organic resin core plate is formed with a second connecting line.

9. A stacked package structure, comprising: Comprise: The bottom package, the printed circuit board and the top package of claim 8, wherein the top package comprises a top package chip and a passive element; The bottom package is mounted on the printed circuit board through the second connecting line or the first connecting line, and the top package chip and the passive element in the top package are mounted on the first connecting line or the second connecting line of the bottom package.

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