NOR-type memory device, method of manufacturing the same, and electronic device including the memory device

Abstract

A NOR-type memory device, a manufacturing method thereof, and an electronic device including the same are disclosed. According to an embodiment, the NOR-type memory device can include a memory cell layer disposed on a substrate, including first source / drain layers, first channel layers, second source / drain layers, second channel layers, and third source / drain layers stacked on each other in a vertical direction; a gate stack vertically extending with respect to the substrate to pass through the memory cell layer, including a gate conductor layer and a storage function layer disposed between the gate conductor layer and the memory cell layer; and at least one of a source line contact and a body contact. The source line contact vertically extends with respect to the substrate to pass through the memory cell layer and is electrically connected to the first source / drain layers and the third source / drain layers in the memory cell layer, respectively. The body contact vertically extends with respect to the substrate to pass through the memory cell layer and is electrically connected to the first channel layers and the second channel layers in the memory cell layer, respectively.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of semiconductor, and in particular, to a NOR-type memory device and a manufacturing method thereof, and an electronic device including the same. BACKGROUND

[0002] In a horizontal-type device such as a metal-oxide-semiconductor field-effect transistor (MOSFET), a source, a gate, and a drain are arranged in a direction substantially parallel to a surface of a substrate. Due to this arrangement, the horizontal-type device is not easily further scaled down. In contrast, in a vertical-type device, the source, the gate, and the drain are arranged in a direction substantially perpendicular to the surface of the substrate. Thus, the vertical-type device is more easily scaled down than the horizontal-type device.

[0003] For the vertical-type device, integration density can be increased by stacking the devices on top of each other. However, this can cause performance to deteriorate. Because, in order to facilitate stacking of multiple devices, a polysilicon is often used as a channel material, causing resistance to become larger than that of a single-crystal silicon channel material. In addition, it is desirable to further increase integration density and improve performance. SUMMARY

[0004] In view of the above, it is at least in part an object of the present disclosure to provide a NOR-type memory device and a manufacturing method thereof that improve integration density, performance, reliability, and manufacturing process, and an electronic device including the same.

[0005] According to an aspect of the present disclosure, there is provided a NOR-type memory device, including: at least one memory cell layer disposed on a substrate, the at least one memory cell layer including a first source / drain layer, a first channel layer, a second source / drain layer, a second channel layer, and a third source / drain layer stacked on top of each other in a vertical direction; at least one gate stack extending vertically with respect to the substrate to pass through the at least one memory cell layer, the at least one gate stack including a gate conductor layer and a memory function layer disposed between the gate conductor layer and the at least one memory cell layer, wherein a memory cell is defined at an intersection of the at least one gate stack and the at least one memory cell layer; and at least one of a source line contact and a body contact. The source line contact extends vertically with respect to the substrate to pass through the at least one memory cell layer. The first source / drain layer and the third source / drain layer in the at least one memory cell layer are respectively electrically connected to the source line contact at a location where the source line contact is located. The body contact extends vertically with respect to the substrate to pass through the at least one memory cell layer. The first channel layer and the second channel layer in the at least one memory cell layer are respectively electrically connected to the body contact at a location where the body contact is located.

[0006] According to another aspect of this disclosure, a method for manufacturing a NOR-type memory device is provided, comprising: forming at least one memory cell layer on a substrate including a contact region and a device region, the at least one memory cell layer including a first source / drain layer, a first channel layer, a second source / drain layer, a second channel layer and a third source / drain layer stacked on top of each other in a vertical direction; forming at least one gate via extending vertically relative to the substrate through the at least one memory cell layer in the device region; forming respective gate stacks in the at least one gate via, the gate stacks including a gate conductor layer and a memory function layer disposed between the gate conductor layer and the at least one memory cell layer; forming a first contact via extending vertically relative to the substrate through the at least one memory cell layer in the contact region; selectively etching at least a portion of the sidewalls of the second source / drain layer exposed in the first contact via to recess laterally to form a lateral channel; introducing an etchant through the first contact via to etch at least the second source / drain layer, wherein the etchant also acts on the second source / drain layer through the lateral channel, thereby causing the second source / drain layer to be relatively recessed in the first contact via; and forming a first contact portion electrically isolated from the second source / drain layer in the first contact via.

[0007] According to another aspect of this disclosure, an electronic device is provided, including the aforementioned NOR-type memory device.

[0008] According to embodiments of this disclosure, stacks of single-crystal materials can be used as building blocks to construct three-dimensional (3D) NOR memory devices. Therefore, when multiple memory cell layers are stacked on top of each other, the increase in resistance can be suppressed. No additional isolation layers are required between memory cell layers, particularly between adjacent bit lines (BLs) in the vertical direction, which optimizes the process and facilitates increased integration. The number of contacts can be reduced and thus area saved through common source line contacts and / or body contacts. Attached Figure Description

[0009] The above and other objects, features and advantages of this disclosure will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0010] Figures 1 to 21 A schematic diagram of some stages in the process of manufacturing a NOR-type memory device according to an embodiment of the present disclosure is shown;

[0011] Figure 22 An equivalent circuit diagram of a NOR-type memory device according to an embodiment of the present disclosure is shown schematically.

[0012] in, Figure 2(a) , 6(a) Figures 11(a), 20(a), and 21 are top views. Figure 2(a) shows the positions of lines AA′, BB′, CC′, and DD′.

[0013] Figure 1 , 2(b) Figures 3 to 5, 6(b), 7(a), 8(a), 9, 10, 11(b), and 20(b) are cross-sectional views along line AA′.

[0014] Figure 6(c) , 7(b) 8(b) is a cross-sectional view along line BB′.

[0015] Figure 11(c) , 12 This is a cross-sectional view along the CC′ / DD′ line.

[0016] Figure 13(a) , 14(a) Figures 15(a), 17(a), 18, and 19(a) are cross-sectional views along line CC′.

[0017] Figure 13(b) , 14(b) Figures 15(b), 16, 17(b), and 19(b) are cross-sectional views along line DD′.

[0018] Throughout the accompanying drawings, the same or similar reference numerals denote the same or similar parts. Detailed Implementation

[0019] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0020] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0021] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0022] A memory device according to embodiments of the present disclosure is based on a vertical type device. The vertical type device can include an active region disposed in a vertical direction (a direction substantially perpendicular to a surface of a substrate) on the substrate, including source / drain regions provided at both upper and lower ends and a channel region located between the source / drain regions. A conductive path can be formed between the source / drain regions through the channel region. In the active region, the source / drain regions and the channel region can be defined, for example, by a doping concentration.

[0023] According to embodiments of the present disclosure, the active region can be defined by a stack of a lower source / drain layer, a channel layer, and an upper source / drain layer on the substrate. The source / drain regions can be formed in the lower source / drain layer and the upper source / drain layer, respectively, and the channel region can be formed in the channel layer. A gate stack can extend through the stack, so that the active region can surround an outer periphery of the gate stack. Here, the gate stack can include at least one of a storage function layer such as a charge trapping material or a ferroelectric material, so as to implement a storage function. In this way, the gate stack cooperates with the active region opposite thereto to define a storage cell (or a cell constituting device used to constitute the storage cell). Here, the storage cell can be a flash cell.

[0024] According to embodiments of the present disclosure, a single storage cell can be defined based on two cell constituting devices connected in parallel, in adaptation to an arrangement of a bit line (BL) and a source line (SL). To this end, a stack of a first source / drain layer, a first channel layer, a second source / drain layer, a second channel layer, and a third source / drain layer can be provided. Then, a gate stack extending through the stack can define a first cell constituting device opposite the first source / drain layer, the first channel layer, and the second source / drain layer, and a second cell constituting device opposite the second source / drain layer, the second channel layer, and the third source / drain layer. The two cell constituting devices can be electrically connected to the same BL (in parallel) through the common second source / drain layer, and can be electrically connected to the same word line (WL) (through the gate stack). Then, the first cell constituting device and the second cell constituting device (defining a single storage cell) can be addressed by the same BL and the same WL.

[0025] In a NOR ("NOR") type memory device, the storage cell can be electrically connected between the BL and the SL. In a case where the second source / drain layer in the stack is electrically connected to the BL, the first source / drain layer and the third source / drain layer can be electrically connected to the SL.

[0026] A plurality of gate stacks can be provided to extend through the stack, so that a plurality of storage cells are defined at intersections of the plurality of gate stacks with the stack. The storage cells are arranged in an array (e.g., a two-dimensional array generally arranged in rows and columns) corresponding to the plurality of gate stacks in a plane in which the stack is located.

[0027] Due to the characteristic of the vertical type device that is easy to stack, the memory device according to embodiments of the present disclosure can be a three-dimensional (3D) array. Specifically, a plurality of such stacks can be provided in a vertical direction. The gate stack can extend vertically, thereby passing through the plurality of stacks. In this way, for a single gate stack, a plurality of memory cells stacked in the vertical direction are defined by the intersection with the plurality of stacks stacked in the vertical direction.

[0028] The stacks can be formed by epitaxial growth on a substrate, and can be of single-crystalline semiconductor material. When grown, each layer in the stack can be doped in-situ, and there can be a doping concentration interface between differently doped layers. In this way, the doping profile in the vertical direction can be better controlled. The stack of lower source / drain layers, channel layers, and upper source / drain layers can constitute a bulk material, and thus the channel region is formed in the bulk material. In this case, the process is relatively simple.

[0029] In a conventional process, an isolation layer is needed between (at least some of) the stacks to electrically isolate BLs adjacent to each other. A relatively complex process is needed to form the (semiconductor, particularly single-crystalline semiconductor) stacks and the isolation layer to be stacked on each other. According to embodiments of the present disclosure, each stack can be in direct contact with each other. For example, the uppermost source / drain layer (i.e., the third source / drain layer) of a lower stack can be the same layer as the lowermost source / drain layer (i.e., the first source / drain layer) of an upper stack, and / or the lowermost source / drain layer (i.e., the first source / drain layer) of an upper stack can be the same layer as the uppermost source / drain layer (i.e., the third source / drain layer) of a lower stack. A plurality of (semiconductor, particularly single-crystalline semiconductor) stacks can be formed relatively easily to be stacked on each other. Moreover, although there is an isolation layer between adjacent BLs, there can still be mutual interference. In contrast, according to embodiments of the present disclosure, each BL is separated from other BLs by at least one SL and the cell formed by the SL is electrically connected, and thus mutual interference between different BLs can be effectively suppressed, and reliability can be improved.

[0030] In addition, although compared to a conventional process in which a memory cell is based on a single cell and thus has a relatively small size (e.g., a relatively small height), a memory cell according to embodiments of the present disclosure is based on more (i.e., two) cells and thus has a relatively large size (e.g., a relatively large height), but since the isolation layer can be omitted, and since the manufacturing process, particularly the optimization of the process of forming the stacks as described above, can also improve the integration density.

[0031] According to embodiments of the present disclosure, to reduce the number of contacts, storage units at different heights in the vertical direction can share common contacts, e.g., common SL contacts and / or common body contacts. The common contacts can extend vertically to pass through the storage unit layers and electrically connect with (e.g., by contacting each other) the corresponding layers in the storage unit layers. For example, the common SL contacts can electrically connect with the first source / drain layers and the third source / drain layers in the storage unit layers, and the common body contacts can electrically connect with the first channel layers and the second channel layers in the storage unit layers. According to embodiments, the SL contacts and the body contacts can be integral, i.e., the common contacts can electrically connect to the first source / drain layers and the third source / drain layers as well as the first channel layers and the second channel layers in the storage unit layers at the same time.

[0032] According to embodiments of the present disclosure, to reduce the number of interconnections, a respective select transistor can be provided on each gate stack. As described below, the select transistor can be self-aligned to the respective gate stack.

[0033] Such a vertical memory device can be fabricated, for example, as follows. Specifically, a plurality of storage unit layers can be provided on a substrate, each storage unit layer comprising, for example, a stack of a first source / drain layer, a first channel layer, a second source / drain layer, a second channel layer, and a third source / drain layer. These layers can be provided, for example, by epitaxial growth. During epitaxial growth, the thickness of each layer, in particular the channel layers, can be controlled. In addition, in-situ doping can be performed during epitaxial growth to achieve the desired doping polarity and doping concentration. Here, each layer in the stack can comprise the same material. In this case, a so-called "layer" can be defined by the doping concentration interface between them.

[0034] In the device region, a gate hole can be formed which extends vertically with respect to the substrate to pass through the stack in each storage unit layer. In the gate hole, a gate stack can be formed, and a select transistor can be fabricated on the gate stack.

[0035] In the contact region, a first contact hole can be formed which extends vertically relative to the substrate to pass through the stack in each of the memory cell layers. By selective etching, at least a portion of the sidewall of the second source / drain layer exposed in the first contact hole can be laterally recessed to form a lateral channel. Such a lateral channel exposes the second source / drain layer more, so that it can be etched more by an etchant introduced via the first contact hole, so that it is recessed relative to the first source / drain layer and the third source / drain layer. If the etching recipe employed also etches the first channel layer and the second channel layer and to a significant extent, the first channel layer and the second channel layer can also be recessed relative to the first source / drain layer and the third source / drain layer. Thus, in the first contact hole, the first source / drain layer and the third source / drain layer can be achieved which protrude relative to the second source / drain layer (and optionally, the first channel layer and the second channel layer). Therefore, in the first contact hole, a first contact, such as a SL contact, can be formed which is electrically connected to the first source / drain layer and the third source / drain layer and electrically isolated from the second source / drain layer (and optionally, the first channel layer and the second channel layer).

[0036] In addition, in the contact region, a second contact hole can be formed which extends vertically relative to the substrate to pass through the stack in each of the memory cell layers. By selective etching, at least a portion of the sidewall of the first source / drain layer, the second source / drain layer and the third source / drain layer exposed in the second contact hole can be laterally recessed to form a lateral channel. Again, such a lateral channel exposes the first source / drain layer, the second source / drain layer and the third source / drain layer more, so that it can be etched more by an etchant introduced via the second contact hole, so that it is recessed relative to the first channel layer and the second channel layer. Thus, in the second contact hole, the first channel layer and the second channel layer can be achieved which protrude relative to the first source / drain layer, the second source / drain layer and the third source / drain layer. Therefore, in the second contact hole, a second contact, such as a body contact, can be formed which is electrically connected to the first channel layer and the second channel layer and electrically isolated from the first source / drain layer, the second source / drain layer and the third source / drain layer.

[0037] To achieve such selective etching, the source / drain layers can comprise a stack structure, such as a stack of an upper sublayer, an intermediate sublayer and an upper sublayer. The intermediate sublayer can have etching selectivity relative to the upper sublayer and the lower sublayer, so that it can be selectively etched to achieve the lateral channel described above. In addition, the upper sublayer and the lower sublayer can have substantially the same material as the adjacent channel layers.

[0038] The present disclosure can take form in various aspects of which some examples are described below. In the following description, reference is made to the selection of various materials. The selection of materials is considered in addition to their functionality (e.g., semiconductor materials for forming active regions, dielectric materials for forming electrical isolation, conductive materials for forming electrodes, interconnect structures, etc.) to etch selectivity. In the following description, the required etch selectivity can or can not be indicated. It will be apparent to those skilled in the art that when etching of a material layer is mentioned below, the etching can be selective and the material layer can have etch selectivity with respect to other layers exposed to the same etch recipe if no other layers are mentioned to be etched or are not shown in the figure.

[0039] Figures 1 to 21 Figures 1A-1C show schematic diagrams of some stages in a flow of fabricating a NOR-type memory device according to embodiments of the present disclosure.

[0040] As shown in Fig. 1A, a substrate 101 is provided. The substrate 101 can be various forms of substrates including but not limited to bulk semiconductor material substrates such as bulk Si substrates, semiconductor-on-insulator (SOI) substrates, compound semiconductor substrates such as SiGe substrates, etc. In the following description, bulk Si substrates such as Si wafers are described by way of example for convenience of illustration. Figure 1

[0041] On the substrate 101, a memory device such as a NOR-type flash memory can be formed as described below. The memory cells in the memory device can include n-type cell-constituting devices or p-type cell-constituting devices. Here, n-type cell-constituting devices are described by way of example, for which p-type wells can be formed in the substrate 101. Accordingly, the following description, particularly the description regarding the doping type, is directed to the formation of n-type cell-constituting devices. However, the present disclosure is not limited thereto.

[0042] On the substrate 101, source / drain layers 1031, 1071, 1032, 1072, 1033 and channel layers 1051, 1052, 1053, 1054 can be formed alternately by, for example, epitaxial growth, such that each channel layer 1051, 1052, 1053, 1054 can have a source / drain layer adjacent thereto on each of the upper and lower sides. Thus, each channel layer 1051, 1052, 1053, 1054 can define a device layer together with the adjacent source / drain layers on the upper and lower sides, respectively. In each device layer, an array of cell-constituting devices can be formed, the active regions of which can be defined by the corresponding device layer. The device layers adjacent to each other can have a common source / drain layer (and thus be electrically connected to each other).

[0043] In the following description, the required etch selectivity can or can not be indicated. It will be apparent to those skilled in the art that when etching of a material layer is mentioned below, the etching can be selective and the material layer can have etch selectivity with respect to other layers exposed to the same etch recipe if no other layers are mentioned to be etched or are not shown in the figure. Figure 1 ​The example shows four device layers corresponding to the four channel layers 1051, 1052, 1053, and 1054, but this disclosure is not limited thereto. For example, there may be more (or fewer) channel layers, and therefore more (or fewer) device layers.

[0044] exist Figure 1 The diagram also shows memory cell layers M1 and M2. As further described below, in embodiments of this disclosure, a pair of vertically adjacent (parallel connected) cells constitute a memory cell, and this pair of cell-constituting devices is formed in a pair of adjacent device layers. Thus, each memory cell layer M1 and M2 can correspond to a corresponding pair of device layers, and an array of memory cells can be formed in each memory cell layer (corresponding to the array of cell-constituting devices in the corresponding pair of device layers).

[0045] Here, different labels 103 are used for the source / drain layers on the upper and lower sides of the same channel layer. n (exist Figure 1 In the example, n = 1, 2, 3; n can be larger in cases with more device layers) and 107 m (exist Figure 1 In the example, m = 1, 2; in the case of more device layers, m can be larger), partly because they can subsequently be connected differently (e.g., connected to SL and BL respectively; in the following, with 103 n The marked source / drain layers can be connected to SL, while at 107 m The marked source / drain layers can be connected to the BL, but this does not mean that they necessarily have different properties (e.g., geometric properties such as thickness, material properties such as composition, doping properties such as doping elements and concentration, etc.; of course, they can also be different in at least one aspect).

[0046] In addition, each source / drain layer 103 n and 107 m It can have a layered structure. For example, such as Figure 1 As shown, each source / drain layer 103 n and 107 m It can have sublayers labeled a, b, and c, respectively. Since the topmost source / drain layer 1033 no longer has a channel layer above it, it can only have a sublayer 1033a, as described below, for defining the source / drain regions for the cell-based device constructed from the channel layer 1054, and a sublayer 103, as described below, for aiding in the formation of SL electrical connections. 3b, and can not have the sub-layers labeled with subscript c (of course, such sub-layers can be provided as well, as with the other source / drain layers). Similarly, the lowermost source / drain layer 1031 can not have the sub-layers labeled with subscript a, since there is no channel layer below it. However, the sub-layers 103 1a are still provided here, as described below, to provide space for providing electrical isolation between the SL contacts, body contacts, and the substrate. Note that the source / drain layers 103 n and 107 m are provided in this stack structure to provide the required etch selectivity, as described below, but the present disclosure is not limited thereto.

[0047] One or more (or even all) of the source / drain layers and channel layers formed on the substrate 101, particularly the channel layers, can be single-crystalline semiconductor layers. The layers can have a crystal interface or a doping concentration interface between them due to separate growth or doping.

[0048] The source / drain layers 1031, 1071, 1032, 1072, 1033 can define source / drain regions of the unit-constituting devices. The source / drain layers 1031, 1071, 1032, 1072, 1033 (particularly, their respective sub-layers) can form the source / drain regions by doping (e.g., in-situ doping while growing). For n-type unit-constituting devices, n-type doping can be performed with As or P, for example, and the doping concentration can be about 5E18-1E21 cm -3 .

[0049] In the source / drain layers 103 n (n = 1, 2, 3,...), the lowermost sub-layer 103 1a may have a relatively large thickness (T bt ) of about 20 nm-150 nm, for example, to provide sufficient space for providing electrical isolation between the SL contacts, body contacts, and the substrate (see, e.g., FIGS. 1A and 1B). Figure 19(a) and 19(b) The sub-layers 103 1c , 103 2a , 103 2c , 103 3a adjacent to the respective channel layers 1051, 1052, 1053, 1054 can each define a source / drain region of the corresponding device, and can have a thickness (denoted by T s1 ) of about 20 nm-150 nm, for example (the thicknesses of the respective sub-layers 103 1c , 1032a, 103 2c , 103 3a may be set individually, and can be substantially equal to or different from each other); the intermediate sub-layers 103 1b , 1032b 、103 3b (uppermost sub-layer 103 3b functionally equivalent to the other intermediate sub-layers 103 1b 、103 2b For the sake of convenience, hereinafter, also the sub-layer 103 s representing the thickness thereof, for example, about 10-50 nm (the thickness of the respective sub-layers 103 1b 、103 2b 、103 3b may be respectively set, and can be substantially equal to or different from each other) can be considered as an electrical connection to the SL. Note that, here, each sub-layer of each source / drain layer 103n is respectively considered as a source / drain region or an electrical connection to the SL, only for the sake of better understanding the structure of the memory device according to embodiments of the present disclosure. According to embodiments, each sub-layer of each source / drain layer 103 n may define together a source / drain region.

[0050] In the source / drain layers 107 m (= 1, 2,...), the sub-layers 107 1a 、107 1c 、107 2a 、107 2c may each define a source / drain region of the respective device, the thickness thereof (represented by T bl , for example, about 20-150 nm (the thickness of the respective sub-layers 107 1a 、107 1c 、107 2a 、107 2c may be respectively set, and can be substantially equal to or different from each other) ; the intermediate sub-layers 107 1b 、107 2b may be considered as an electrical connection to the BL, the thickness thereof (represented by T b , for example, about 10-50 nm (the thickness of the respective sub-layers 107 1b 、107 2b may be respectively set, and can be substantially equal to or different from each other). Also, here, each sub-layer of each source / drain layer 107 m is respectively considered as a source / drain region or an electrical connection to the BL, only for the sake of better understanding the structure of the memory device according to embodiments of the present disclosure. According to embodiments, each sub-layer of each source / drain layer 107 m may define together a source / drain region.

[0051] For each channel layer, in the source / drain layer 107 adjacent to that channel layer m and 103 n In the middle, the sublayer 107 adjacent to the channel layer ma (or 107) mc The thickness T) bl and the sublayer 103 adjacent to the channel layer nc (or 103na) thickness T sl They can be roughly equal, and the sublayer is 107. mb Thickness T b It can be not equal to, and preferably greater than, sublayer 103 nb Thickness T s For example, for channel layer 1051, the adjacent sublayer 107 1a The thickness of the adjacent sublayer 103 1c The thicknesses can be approximately equal, and the corresponding sublayers 107 1b The thickness can be greater than the corresponding sublayer 103 1b The thickness, and so on. This is because, according to embodiments of this disclosure, the current flowing through BL is greater than the current flowing through SL. When a pair of unit components connected in parallel to the same BL are respectively connected to the corresponding SL, the BL current can be approximately twice the SL current.

[0052] The channel layers 1051, 1052, 1053, and 1054 can define the channel region of the unit cell constituting the device, and their thickness (in T) 1g The gate length of the device can be defined by the cell structure, for example, from approximately 40nm to 300nm. The thicknesses of each channel layer 1051, 1052, 1053, and 1054 can be set individually, and can be approximately equal or unequal to each other. The channel layers 1051, 1052, 1053, and 1054 may be undoped, or they may be lightly doped by in-situ doping during growth to improve the short-channel effect (SCE) and adjust the device threshold voltage (V). t For example, for devices constructed from n-type units, p-type doping can be performed using B, with a doping concentration of approximately 1E17-2E19 cm⁻¹. -3 In addition, to optimize device performance, the doping concentration in the channel layer can be non-uniformly distributed in the vertical direction, for example, higher near the drain region (connected to BL) to improve SCE, and lower near the source region (connected to SL) to reduce channel resistance.

[0053] These semiconductor layers can include various suitable semiconductor materials, such as elemental semiconductor materials like Si or Ge, compound semiconductor materials like SiGe, etc. In the example where substrate 1001 is a silicon wafer, the source / drain layers and channel layers can include silicon-based materials. Furthermore, considering the selective etching required in the following processes, the intermediate sublayers in each source / drain layer can have etching selectivity relative to the sublayers above and below them. For example, each channel layer can include Si, the sublayers in each source / drain layer indicated by subscripts a and c can include Si, and the sublayer indicated by subscript b can include SiGe (the atomic percentage of Ge is, for example, about 15%-30%). However, this disclosure is not limited thereto.

[0054] A hard mask layer can be disposed on these semiconductor layers formed on substrate 101 to facilitate patterning. In this example, to facilitate the subsequent formation of a selection transistor, the hard mask layer may include a stacked configuration, such as a first sublayer 1151, a second sublayer 1152, and a third sublayer 1153. The first sublayer 1151 and the third sublayer 1153 may be solid-phase dopant sources to facilitate subsequent doping of the selection transistor. Considering the etch selectivity in subsequent processes, the first sublayer 1151 and the third sublayer 1153 may include oxides (e.g., silicon oxide) containing dopants such as P to serve as solid-phase dopant sources; the second sublayer 1152 may include nitrides (e.g., silicon nitride). The thickness of each sublayer is, for example, about 50 nm to 200 nm.

[0055] In the device layer formed as described above, cell-structured devices can be fabricated to form memory cells.

[0056] For example, such as Figure 2(a) and 2(b) As shown, photoresist 117 can be formed on a hard mask layer and patterned by photolithography to have a series of openings (in the device region on the substrate), which can define the locations of gate holes in which gate stacks will be formed. The openings can be of various suitable shapes, such as circular, rectangular, square, polygonal, etc., and have suitable sizes, such as a diameter or side length of about 20 nm to 500 nm. Here, these openings can be arranged in an array, such as a two-dimensional array along the horizontal and vertical directions in the plane of the paper in FIG. 2(a). This array can then define an array of cells constituting a device (and therefore, memory cells). According to embodiments of this disclosure, the openings can have different layouts, sizes, shapes, etc.

[0057] In this example, as shown in FIG. 2(a), the substrate can include a device region to form the unit cell device (and thus, the memory cell) (and optionally, the select transistor) and a contact region adjacent to the device region. In this example, the contact region can include a contact region 1 for the SL and a contact region 2 for the BL. For example, the contact region 1 and the contact region 2 can be disposed on opposite sides of the device region, respectively. However, the present disclosure is not limited thereto. Their layout can be changed according to the circuit design.

[0058] As shown in FIG. 2(b), the photoresist 117 thus patterned can be used as an etch mask to etch the layers on the substrate 101 by anisotropic etching, such as reactive ion etching (RIE), to form a series of gate holes T. The RIE can be performed in a substantially vertical direction (e.g., a direction perpendicular to the surface of the substrate) and can be performed into the substrate 101. Thus, a series of vertical gate holes T are left on the substrate 101. After that, the photoresist 117 can be removed. Figure 3

[0059] In the gate holes T, a gate stack can be formed. Here, the storage function can be implemented by the gate stack. For example, the gate stack can include a storage structure, such as a charge trapping layer or a ferroelectric material, etc.

[0060] As shown in FIG. 2(c), the storage function layer 125 and the gate conductor layer 127 can be formed in sequence, for example, by deposition. The storage function layer 125 can be formed in a substantially conformal manner, and the gate conductor layer 127 can fill the voids left in the gate holes T after the formation of the storage function layer 125. The gate conductor layer 127 and the storage function layer 125 thus formed can be subjected to a planarization process, such as chemical mechanical polishing (CMP) (e.g., which can be stopped on the hard mask layer), so that the gate conductor layer 127 and the storage function layer 125 can be left in the gate holes T to form the gate stack. Figure 4

[0061] The storage function layer 125 can be based on dielectric charge trapping, ferroelectric material effect, or bandgap engineered charge storage (SONOS), etc. For example, the storage function layer 125 can include a dielectric tunneling layer (e.g., an oxide with a thickness of about 1 nm-5 nm, which can be formed by oxidation or atomic layer deposition (ALD)) - a band offset layer (e.g., a nitride with a thickness of about 2 nm-10 nm, which can be formed by chemical vapor deposition (CVD) or ALD) - an isolation layer (e.g., an oxide with a thickness of about 2 nm-6 nm, which can be formed by oxidation, CVD, or ALD). Such a three-layer structure can result in a band structure that traps electrons or holes. Alternatively, the storage function layer 125 can include a ferroelectric material layer, such as HfZr02 with a thickness of about 2 nm-20 nm.

[0062] The gate conductor layer 127 can include, for example, a (doped, e.g., p-type doped in the case of an n-type unit cell device) polysilicon or a metal gate material.​​

[0063] As shown in Figure 4 , the gate stack (125 / 127) with the storage function layer is surrounded by the active region. The gate stack cooperates with the active region (stack of the source / drain layer, the channel layer and the source / drain layer) to define a cell constituting device, as shown in the dotted circle in Figure 4 . The channel region formed in the channel layer can connect the source / drain regions formed in the opposite source / drain layers, and the channel region can be controlled by the gate stack. Figure 4 A pair of cell constituting devices adjacent to each other in the vertical direction is shown in two dotted circles in

[0064] The gate stack extends in a columnar shape in the vertical direction, and overlaps with multiple device layers, so as to define multiple cell constituting devices (and thus, multiple storage cells) stacked on each other in the vertical direction. The storage cells associated with a single gate stack column can form a storage cell string. Corresponding to the layout of the gate hole T (for example, a two-dimensional array) described above, multiple such storage cell strings are arranged on the substrate, so as to form a three-dimensional (3D) array of storage cells.

[0065] In addition, above each storage cell string, a selection transistor can be formed, respectively.

[0066] For example, as shown in Figure 5 , the gate stack (125 / 127) can be etched back / recessed by a certain height through selective etching such as RIE. The top surface height of the etched back / recessed gate stack can be such that the first sub-layer 1151 (at least part of the thickness) of the hard mask layer is exposed on the sidewall of the gate hole T, while the uppermost source / drain layer 1033 is not exposed on the sidewall of the gate hole T and is still shielded by the gate stack. For example, the top surface height of the etched back / recessed gate stack can be between the top surface and the bottom surface of the first sub-layer 1151 of the hard mask layer. In the space released in the gate hole T due to the etching back / recessing of the gate stack, the active layer 109 can be formed by deposition in a substantially conformal manner. Thus, the active layer 109 can be cup-shaped, including a bottom extending on the top surface of the gate stack and a side extending on the sidewall of the gate hole T (the part outside the gate hole T will be removed due to subsequent processes).

[0067] The active layer 109 can include a semiconductor material such as (poly)Si to define an active region of the select transistor, with a thickness of, for example, about 5-20 nm. Dopants can be driven from the first sub-layer 1151 and the third sub-layer 1153 as solid-phase dopant sources into the active layer 109 by annealing, for example, a spike anneal or rapid thermal process (RTP) at a temperature of about 700-1050 °C for about 0.5-2 seconds, to form source / drain regions S / D of the select transistor at regions of the active layer 109 corresponding to the first sub-layer 1151 and the third sub-layer 1153. Here, the conditions of the annealing process can be controlled such that the dopants diffused from the solid-phase dopant sources do not substantially affect a middle portion of the active layer 109 in the vertical direction (corresponding to the region of the second sub-layer 1152).

[0068] In addition, to reduce contact resistance, the bottom portion of the active layer 109 can be doped (of the same type as the source / drain regions S / D, with a doping concentration of, for example, about 1E19-1E21 cm -3 ) by, for example, ion implantation in the vertical direction. According to embodiments of the present disclosure, this ion implantation process can be performed prior to the annealing process described above, such that the dopants implanted thereby can be activated by the annealing process described above without having to perform an anneal separately for the ion implantation process.

[0069] Thus, an active region of the select transistor is defined above each string of memory cells. The active region of the select transistor can include source / drain regions formed at both upper and lower ends of the active layer 109 (in the vertical direction) and a channel region (in the middle portion in the vertical direction) between the source / drain regions. The source / drain region of the lower end of the select transistor (via the highly doped region of the bottom portion of the active layer 109) is electrically connected to the gate conductor layer 127 of the memory cell.

[0070] In the voids after forming the active layer 109 in the gate holes T, a fill portion 111 can be formed by depositing a dielectric material such as oxide and then performing a planarization process such as CMP (the portions of the active layer 109 outside the gate holes T can be removed in this planarization process).

[0071] The gate stack of the select transistor can be fabricated by a self-alignment process. For example, the second sub-layer 1152 in the hard mask can be replaced by the gate stack of the select transistor, which can be self-aligned to the channel region of the select transistor as formed.

[0072] Currently, the hard mask layer extends continuously around each gate hole. The second sub-layer 1152 needs to be exposed for replacement. In addition, the hard mask layer can be patterned into a series of lines extending substantially in parallel, in view of the formation of the select line as described below.

[0073] For example, as Figure 6(a) , 6(b)As shown in FIGS. 6(c), a photoresist 131 can be formed on the hard mask layer and patterned by photolithography into a series of linear patterns extending in a first direction (e.g., horizontally in the plane of the paper in FIG. 6(a)) and spaced apart from each other in a second direction (e.g., vertically in the plane of the paper in FIG. 6(a)) intersecting (e.g., perpendicular to) the first direction (to cover a row of gate holes in the first direction, respectively). The photoresist 131 can be used as an etch mask to sequentially etch the third sub-layer 1153 and the second sub-layer 1152 of the hard mask layer by selective etching, e.g., RIE. Here, the etching can stop at the first sub-layer 1151 to protect the underlying device layers when forming the gate stack of the select transistor later. In this way, as shown in FIG. 6(a), the third sub-layer 1153 and the second sub-layer 1152 in the hard mask layer are formed into strips extending in the first direction around the outer periphery of the corresponding row of gate holes (in which the active layer 109 is formed), and the sidewall of the second sub-layer 1152 is exposed. Thereafter, the photoresist 131 can be removed.

[0074] As shown in FIGS. 6(c), a photoresist 131 can be formed on the hard mask layer and patterned by photolithography into a series of linear patterns extending in a first direction (e.g., horizontally in the plane of the paper in FIG. 6(a)) and spaced apart from each other in a second direction (e.g., vertically in the plane of the paper in FIG. 6(a)) intersecting (e.g., perpendicular to) the first direction (to cover a row of gate holes in the first direction, respectively). The photoresist 131 can be used as an etch mask to sequentially etch the third sub-layer 1153 and the second sub-layer 1152 of the hard mask layer by selective etching, e.g., RIE. Here, the etching can stop at the first sub-layer 1151 to protect the underlying device layers when forming the gate stack of the select transistor later. In this way, as shown in FIG. 6(a), the third sub-layer 1153 and the second sub-layer 1152 in the hard mask layer are formed into strips extending in the first direction around the outer periphery of the corresponding row of gate holes (in which the active layer 109 is formed), and the sidewall of the second sub-layer 1152 is exposed. Thereafter, the photoresist 131 can be removed. Figure 7(a) 7(b) As shown in FIGS. 6(c), a photoresist 131 can be formed on the hard mask layer and patterned by photolithography into a series of linear patterns extending in a first direction (e.g., horizontally in the plane of the paper in FIG. 6(a)) and spaced apart from each other in a second direction (e.g., vertically in the plane of the paper in FIG. 6(a)) intersecting (e.g., perpendicular to) the first direction (to cover a row of gate holes in the first direction, respectively). The photoresist 131 can be used as an etch mask to sequentially etch the third sub-layer 1153 and the second sub-layer 1152 of the hard mask layer by selective etching, e.g., RIE. Here, the etching can stop at the first sub-layer 1151 to protect the underlying device layers when forming the gate stack of the select transistor later. In this way, as shown in FIG. 6(a), the third sub-layer 1153 and the second sub-layer 1152 in the hard mask layer are formed into strips extending in the first direction around the outer periphery of the corresponding row of gate holes (in which the active layer 109 is formed), and the sidewall of the second sub-layer 1152 is exposed. Thereafter, the photoresist 131 can be removed.

[0075] At this point, the fabrication of the memory cells (strings) and the select transistors is substantially complete. Then, various electrical contacts can be fabricated to achieve the desired electrical connections.

[0076] To achieve electrical connections to the various device layers, a staircase structure can be formed in the contact region (more specifically, the contact region 2 for the BL) on the substrate. There are various ways to form such a staircase structure in the art. According to embodiments of the present disclosure, the staircase structure can be formed, for example, as follows.

[0077] As shown in FIGS. 6(c), a photoresist 131 can be formed on the hard mask layer and patterned by photolithography into a series of linear patterns extending in a first direction (e.g., horizontally in the plane of the paper in FIG. 6(a)) and spaced apart from each other in a second direction (e.g., vertically in the plane of the paper in FIG. 6(a)) intersecting (e.g., perpendicular to) the first direction (to cover a row of gate holes in the first direction, respectively). The photoresist 131 can be used as an etch mask to sequentially etch the third sub-layer 1153 and the second sub-layer 1152 of the hard mask layer by selective etching, e.g., RIE. Here, the etching can stop at the first sub-layer 1151 to protect the underlying device layers when forming the gate stack of the select transistor later. In this way, as shown in FIG. 6(a), the third sub-layer 1153 and the second sub-layer 1152 in the hard mask layer are formed into strips extending in the first direction around the outer periphery of the corresponding row of gate holes (in which the active layer 109 is formed), and the sidewall of the second sub-layer 1152 is exposed. Thereafter, the photoresist 131 can be removed. Figure 7(a) 7(b) ​​As shown, the top of the active layer 109 of the currently selected transistor is exposed at the surface of the hard mask layer. To protect the active layer 109 during the subsequent fabrication of the stepped structure, another hard mask layer can be formed on top of the hard mask layer. In this example, this other mask layer may include oxide, just like the first sublayer 1151, the third sublayer 1153, and the filler 111, and therefore... Figure 8(a) and 8(b) The first sublayer 1151, the third sublayer 1153, and the filler 111 are shown as a single unit, marked 113. On the hard mask layer 113, photoresist 123 can be formed and patterned by photolithography to mask the device region and the contact region 1 for SL, exposing the contact region 2 for BL. The photoresist 123 can be used as an etching mask to selectively etch the hard mask layer 113, such as by RIE, to expose the device layer (here, the uppermost source / drain layer 1033). Afterwards, the photoresist 123 can be removed.

[0078] like Figure 9 As shown, the hard mask layer 113, which can be formed in this way, serves as an etching mask. The source / drain layer 1033 and the channel layer 1054 can be etched selectively, such as by RIE, to expose the source / drain layer 1072 to be electrically connected to the BL. The etching depth can be controlled so that the etching stops above the source / drain layer 1072, for example, sublayer 107. 2c Thus, in contact region 2, between source / drain layer 1033 and source / drain layer 1072 (more specifically, sublayer 107... 2c A step is formed between the surfaces.

[0079] Sidewall 133 can be formed at the aforementioned steps (and on the sidewalls of hard mask layer 113) using a spacer forming process. For example, sidewall 133 can be formed by depositing a dielectric, such as an oxide, in a generally conformal manner, followed by anisotropic etching, such as a vertical RIE, of the deposited dielectric to remove the lateral extensions of the deposited dielectric, leaving only its vertical extensions. Here, considering that hard mask layer 113 also includes oxide, the etching depth of the RIE can be controlled to be substantially equal to or slightly greater than the deposition thickness of the dielectric to avoid exposing the active layer 109. The width of sidewall 133 (in the horizontal direction in the figure) can be substantially equal to the deposition thickness of the dielectric. The width of sidewall 133 defines the size of the landing pad subsequently extending to the contact area of ​​source / drain layer 1072.

[0080] like Figure 10As shown, using the sidewall 133 thus formed as an etching mask, selective etching, such as RIE, can be used to sequentially etch the remaining portion of the source / drain layer 1072, the channel layer 1053, the source / drain layer 1032, and the channel layer 1052 to expose the source / drain layer 1071 to be electrically connected to the BL. The etching depth can be controlled so that the etching stops at the top of the source / drain layer 1071, for example, at the sublayer 107. 1c This creates another step in contact zone 2.

[0081] You can combine the above methods. Figure 9 and 10 The described process involves forming sidewalls and using the sidewalls as etching masks to create multiple steps in contact area 2, such as... Figure 10 As shown. These steps form a stepped structure that allows for electrical connection to each source / drain layer 107 that requires electrical connection to the BL. m Its ends protrude relative to the layer above it to define the landing pads for the contact portion of that layer. Figure 10 In the diagram, 135 represents the portion of the sidewalls formed in each step that remains after processing. Since these sidewalls 135 and the hard mask layer are both oxides, they are shown as a single unit here (the undulations of the sidewalls 135 are not shown in the following illustrations for ease of illustration only). Here, the stepped structure also exposes a portion of the substrate 101 for subsequent fabrication of contacts to the substrate.

[0082] Additionally, in contact area 1, a common SL contact portion and / or a common body contact portion can be fabricated. This common SL contact portion and common body contact portion, compared to those for each source / drain layer 103... n By forming SL contacts separately and body contacts separately for each channel layer, area can be saved. The following description uses both SL contacts and body contacts as examples to provide a more comprehensive understanding of the invention. However, this disclosure is not limited thereto. For example, a common SL contact can be formed instead of a common body contact, and the body contact can be formed separately for each channel layer, for example, in contact area 1 by forming more steps (to expose each channel layer). Alternatively, a common body contact can be formed instead of a common SL contact, and the SL contact can be formed, for example, in contact area 1 by forming more steps (to expose each source / drain layer 103). n ) to target each source / drain layer 103 n They can be formed separately. It is even possible to avoid forming (common or separate) body contact areas.

[0083] Therefore, such as Figure 11(a) , 11(b)As shown in FIG. 11(c), photoresist 129 can be formed and patterned by photolithography to have openings for body contacts (e.g., the upper openings in FIG. 11(a)) and openings for SL contacts (e.g., the lower openings in FIG. 11(a)) over contact region 1. Note that the number of common body contacts (and thus, the corresponding openings in photoresist 129) and common SL contacts (and thus, the corresponding openings in photoresist 129) can not be limited to one, but can be multiple. In this example, the openings can be approximately aligned with the locations between select lines to suppress the mutual influence between adjacent wires.

[0084] As shown in FIG. 11(d), photoresist 129 can be used as an etch mask to etch the layers on substrate 101 by anisotropic etching, such as RIE, to form contact holes H. RIE can be performed in a substantially vertical direction and can be performed into substrate 101, leaving vertical contact holes H in substrate 101. After that, photoresist 129 can be removed. Figure 12

[0085] In the contact holes H thus formed, contacts can be formed by filling with a conductive material, such as metal. However, at this point, the sidewalls of each source / drain layer and channel layer are exposed in the contact holes H. In the contact holes for SL contacts, the contacts should be in contact with source / drain layer 107 m but should not be in contact with source / drain layer 103 n (and optionally, channel layers 1051, 1052, 1053, 1054). Similarly, in the contact holes for body contacts, the contacts should be in contact with each channel layer 1051, 1052, 1053, 1054 but should not be in contact with source / drain layer 103 n (and optionally, source / drain layer 107 m ). According to embodiments, at least part of source / drain layer 107 m and at least part of the channel layers can be electrically connected to the same contact.

[0086] According to embodiments of the present disclosure, by the thickness design of the layers and the etch selectivity, an etching scheme is provided such that in the contact holes for SL contacts, source / drain layer 103 n is relatively protruding while source / drain layer 107 m (and optionally, channel layers 1051, 1052, 1053, 1054) is relatively recessed; and in the contact holes for body contacts, channel layers 1051, 1052, 1053, 1054 are relatively protruding while source / drain layer 107 m (and optionally, source / drain layer 103 n ) is relatively recessed.

[0087] ​The contact holes for the SL contacts and the contact holes for the bulk contacts can be configured differently, so that they can be handled separately, e.g. one can be masked while the other is handled. Their handling order can be changed.

[0088] For example, as shown in Figure 13(a) and 13(b) , a photoresist 151 can be formed to mask the contact holes for the bulk contacts, while exposing the contact holes for the SL contacts. Via the contact holes for the SL contacts, the middle sublayer 107 m (in this example, SiGe) of each source / drain layer 107 mb may be recessed in the lateral direction relative to the other sublayers and the channel layer in each source / drain layer, which is Si in this example, by a certain depth (in this example, since the middle sublayer 103 n (in this example, SiGe) of each source / drain layer 103 nb also comprises SiGe, it can also be etched to be recessed in the lateral direction). Due to this recessing, a lateral passage for the etchant is formed, so that each source / drain layer 107 m may be exposed to the etchant more and thus be etched more, and therefore be recessed relatively. This is because the source / drain layer 107 m should be electrically connected to the corresponding BL (through the contact formed on the step structure in the contact region 1) respectively, and should not be electrically connected to the (common) contact formed in the contact hole.

[0089] Here, the recessing depth Dc of each sublayer 107 mb may be greater than: (1) the sum of the thickness of the sublayer 107 ma adjacent to this sublayer and the thickness of the channel layer adjacent to the sublayer 107 ma , (2) the sum of the thickness of the sublayer 107 mc adjacent to this sublayer and the thickness of the channel layer adjacent to the sublayer 107 mc (these two sums are generally represented as (T bl + T lg ) in general).

[0090] After that, the photoresist 151 can be removed.

[0091] In this contact hole for the SL contact, it is desired that the source / drain layer 103n is protruded relative to the source / drain layer 107 m so as to achieve electrical connection between the source / drain layer 103 n and the SL contact formed in this contact hole. However, since the middle sublayer 103 nb of the source / drain layer 103 n is also recessed as described above, this recessing will result in a lateral passage for the etchant to enter so that the source / drain layer 103n It is subsequently etched further and therefore becomes difficult to extend relatively. For this purpose, it can be done in source / drain layer 103. n A filler plug is made at the end to shield the source / drain layer 103. n This lateral channel at the end avoids source / drain layer 103 n It has been etched too much and is now recessed.

[0092] For example, such as Figure 14(a) and 14(b) As shown, the plugging material layer 153 can be formed by deposition in a generally conformal manner. The deposition thickness of the plugging material layer 153 can be controlled to be greater than that of the thinner sublayer 103. nb Half the thickness T s / 2 (thus completely filling the thinner sublayer 103) nb (The indentation at the end), and smaller than the thicker sublayer 107 mb Half the thickness T b / 2 (thus maintaining a thicker sublayer 107) mb (The recess at the end is not completely filled). ALD (Alternating Deposition) can be used to better control the deposition thickness. Considering etching selectivity, the plug material layer 153 may include, for example, a nitride.

[0093] like Figure 15(a) and 15(b) As shown, photoresist 155 can be formed to mask the contact holes for the body contact portion, exposing the contact holes for the SL contact portion. For the exposed contact holes for the SL contact portion, a certain thickness of the plug material layer 153 can be removed by selective etching. For example, the removal thickness can be substantially equal to or slightly greater than the deposition thickness of the plug material layer 153. Thus, the plug material layer 153 can be removed from the thicker sublayer 107. mb Removed from the indentation at the end, leaving it in the thinner sublayer 103. nb A filler plug 157 is formed in the recess at the end. ALE (Alternating Layer) can be used to better control the removal thickness. In the contact hole for body contact, the plug material layer 153 is retained by photoresist 155. The photoresist 155 can then be removed.

[0094] Although T will be here s Set to less than T b This is advantageous (because, as mentioned above, the BL current is greater than the SL current), but the fabrication of the filler plug 157 does not necessarily require T. s Less than T b They simply need to be unequal to each other. For example, if T s Greater than T b Then, the above process can be used in sublayer 107 mb The indentation at the end (not in sublayer 103)nb An auxiliary plug is formed in the recess at the end. At this point, it can be deposited and etched back into sublayer 103. nb A filler plug is formed in the recess at the end. The material of this additional filler plug can be etch-selective relative to the material of the auxiliary plug. Thus, sublayer 107 can be removed by selective etching. mb The auxiliary plug at the end leaves sublayer 103. nb End filler plug.

[0095] Then, as Figure 16 As shown, in the contact holes used for the SL contact portion, substantially non-selective etching can be performed. This is due to sublayer 107. mb Relatively concave, therefore with sublayer 107 mb The adjacent sublayers are more exposed to the etchant (which can act on both Si and SiGe), and therefore are etched to a greater extent. On the other hand, the ends of sublayer 103n are shielded by the filler plug 157, and are therefore essentially unetched, while the adjacent sublayers are less exposed to the etchant and thus etched to a smaller extent. Thus, a structure like... Figure 16 The shapes shown are as follows: source / drain layers 103n protrude relative to each other, while source / drain layers 107m and channel layers 1051, 1052, 1053, and 1054 are relatively recessed.

[0096] Here, as mentioned above, the recess depth Dc can be greater than (T) b1 +T lg (Therefore, etching via the lateral channel formed by the etchant through this recess can be more significant or even dominant), and the etching depth can be greater than (T). bl +T lg (This means that adjacent source / drain sublayers and channel layers can be etched upwards and downwards from this lateral channel to make them relatively recessed.) In this case, channel layers 1051, 1052, 1053, and 1054 are also etched more extensively and relatively recessed, thus making source / drain layer 103... n Fully extended. However, the recess of the channel layer is not necessary, because as mentioned above, the channel layer can be connected to the source / drain layer 103. n Electrical connections are made to the same contact points. In this case, the recess depth Dc can be greater than T. bl The etching depth can be greater than T. bl Thus, source / drain layer 107 m It can be etched more deeply to create recesses, while the channel layers 1051, 1052, 1053, and 1054 may be relatively smaller than the source / drain layer 103. n There is no indentation or the indentation is not obvious.

[0097] In addition, in the contact hole for the body contact, the original shape can be maintained due to the presence of the plug material layer 153.

[0098] In fact, if the formation of the body contact is not taken into account, the source / drain layer 103 n and the source / drain layer 107 m may not necessarily be provided in a stacked structure. For example, the source / drain layer 107 m may be etch-selective with respect to the source / drain layer 103 n and the channel layer as a whole, so that the source / drain layer 107 m may be etched selectively to be recessed, while the source / drain layer 103 n and the channel layer can be substantially unaffected. With this recessing of the source / drain layer 107 m , the source / drain layer 107 m (and, in the case of a larger etch amount, the channel layer adjacent thereto) can be etched more to be recessed relatively, so that the source / drain layer 103 n is relatively protruded. In this case, it is not necessary to form the fill plug as described above. Alternatively, for example, the source / drain layer 103 n and the source / drain layer 107 m may be etch-selective with respect to the channel layer and have different thicknesses from each other. They can be etched selectively to be recessed at the end portions, and in the recesses at the end portions of the source / drain layer 103 n , the fill plug can be formed as described above.

[0099] Alternatively, for example, the intermediate sublayer 103 n of the source / drain layer 103 nb and the intermediate sublayer 107 m of the source / drain layer 107 mb may be etch-selective with respect to each other, so that the intermediate sublayer 107 m of the source / drain layer 107 mb can be etched selectively without forming the fill plug as described above.

[0100] In short, the source / drain layers can be provided differently, for example, by thickness, material, stacking, etc., as long as the (at least part of) the sidewall of the source / drain layer 107 m can be opened to form a lateral passage of the etchant, so that it can be etched more to be recessed.

[0101] In addition, in the case where a plurality of memory cell layers are formed, the contact hole H is deep, and in the case where the etchant is introduced from the opening of the contact hole, there can be a concentration distribution in the vertical direction, for example, the concentration at a higher position is higher than that at a lower position. For this reason, at least one of T bl and T lg , for example, Tbl (T lg (It can remain basically unchanged to ensure consistency between devices), and can have different values ​​at different heights, for example, larger at higher positions, thus (T) bl +T lg At lower locations, the etching depth can be smaller to ensure that the etching depth is greater than (T) across the entire height of the contact hole. bl +T lg ).

[0102] like Figure 17(a) and 17(b) As shown, in the contact holes configured for the SL contact portion, a dielectric material such as SiC can be filled (considering the etching selectivity relative to, for example, hard mask layers and fill plugs) to form a fill portion 159. Since the contact holes for the SL contact portion have a variation in size in the vertical direction, a repeated deposition-etching method can be used to ensure good filling. Of course, dielectric material will also fill the contact holes for the body contact portion to form a fill portion.

[0103] Next, a similar process can be performed on the contact holes for the body contacts. For this purpose, photoresist 161 can be formed to mask the contact holes (where filler 159 is formed) for the SL contacts, exposing the contact holes for the body contacts. The filler and plug material layer 153 in the contact holes for the body contacts can be removed by selective etching, thereby exposing the sidewalls of each source / drain layer and channel layer in the contact holes. The intermediate sublayer 103 in each source / drain layer can be selectively etched through these contact holes. nb 107 mb (In this example, SiGe) is recessed to a certain depth laterally relative to the other sublayers and channel layers (in this example, Si) in each source / drain layer. Here, the recess depth can be greater than that of the intermediate sublayer 103. nb Upper and lower sub-layers 103 na 103 nc Thickness (T) sl ) and the intermediate sublayer 107 mb Upper and lower sub-layers 107 ma 107 mc Thickness (T) bl After that, photoresist 161 can be removed.

[0104] like Figure 18 As shown, in the contact holes used for body contacts, substantially non-selective etching can be performed. This is due to sublayer 103. nb and 107 mb Relatively concave (and as mentioned above, the concave depth can be greater than T) bl T slTherefore, the etching that occurs through the lateral channels formed by the etchant via the recess can be more significant or even dominant, thus affecting the sublayer 103. nb 107 mb Adjacent sublayers are more exposed to the etchant and therefore undergo a greater amount of etching. On the other hand, each channel layer 1051, 1052, 1053, and 1054 is covered by the corresponding source / drain layers on its upper and lower sides, thus being less exposed to the etchant and therefore undergoing a smaller amount of etching. Therefore, it is possible to form... Figure 18 The shape shown: channel layers 1051, 1052, 1053, and 1054 extend relative to each other, while source / drain layer 103... n and 107 m Relatively recessed. The etching depth can be greater than T. bl T sl (This means that adjacent source / drain sublayers can be etched upwards and downwards from this lateral channel to make them relatively recessed), so that the channel layers 1051, 1052, 1053, and 1054 can be fully extended.

[0105] As mentioned above, when the contact hole H is relatively deep, considering the concentration distribution of the etchant in the vertical direction, T bl and T sl At least one of them can have different values ​​at different heights, for example, larger at higher positions, to ensure that the etching depth is greater than T throughout the height of the contact hole. bl T sl .

[0106] Similarly, a dielectric material such as SiC can be formed in the contact hole used for the body contact portion.

[0107] like Figure 19(a) and 19(b) As shown, the fill portions 159 and 163 in the contact holes can be etched back by selectively etching, such as the RIE in the vertical direction. During the etch-back, a certain thickness of fill portion is left at the bottom of the contact hole to prevent the contact portion subsequently formed in the contact hole from directly contacting the substrate. Afterwards, the remaining fill portion and the fill plug (in the contact hole for the SL contact portion) can be isotropically etched through the space released in the contact hole due to the etch-back, so that: in the contact hole for the SL contact portion, the protruding source / drain layer 103... n It can be exposed from the filling part 159, while the relatively recessed source / drain layer 107 m The channel layers 1051, 1052, 1053, and 1054 remain covered by the filler portion 159; in the contact holes for the body contact portion, the relatively protruding channel layers 1051, 1052, 1053, and 1054 can be exposed from the filler portion 163, while the relatively recessed source / drain layer 103 n and 107m It is still covered by the filler portion 163. In addition, isotropic etching will not cause the filler portion left at the bottom of the contact hole to be completely etched and expose the substrate 101.

[0108] In the spaces released by the etching process described above, conductive materials such as metals can be filled to form body contact portions 165a in the contact holes for body contacts, which contact the opposing channel layers 1051, 1052, 1053, and 1054, respectively, and source / drain layers 103 are formed in the contact holes for SL contacts, which contact the opposing channel layers 1051, 1052, 1053, and 1054. n The SL contact portion 165b is in contact. The contact area between the protruding portion and the corresponding contact portion is shown by a dashed circle in the figure.

[0109] In this embodiment, after etching the filling portions 159 and 163, contact portions 165a and 165b are formed, thereby forming the source / drain layer 103. n The channel layers 1051, 1052, 1053, and 1054 can each maintain a relatively protruding shape within the contact holes. However, this disclosure is not limited thereto. For example, the relatively protruding source / drain layers 103 can be etched back while the filler portions 159 and 163 shield the other (sub)layers. n The channel layers 1051, 1052, 1053, and 1054 are arranged such that they do not protrude or are even recessed. In this case, the subsequently formed contact portions 165a and 165b can protrude relative to each other to contact the corresponding source / drain layer 103n and channel layers 1051, 1052, 1053, and 1054.

[0110] After that, other contact parts can be made.

[0111] For example, such as Figure 20(a) and 20(b) As shown, the interlayer dielectric layer 137 can be formed by depositing oxides and planarizing them, such as by CMP. Here, since all are oxides, the previous sidewalls 135 are shown as integral with the interlayer dielectric layer 137. Contacts 139, 141, 143, 145a, and 145b can be formed in the interlayer dielectric layer 137. Specifically, contact 139 can be formed in the device region, electrically connected to the select transistor, and electrically connected to the gate conductor layer 127 that constitutes the device cell via the select transistor; contact 141 can be formed in the contact region 2, electrically connected to each source / drain layer 107. mThe contact 143 can be formed in the device region, electrically connected to the gate conductor layer 121 of the select transistor (or, the corresponding select line). The contact 145a can be formed in the contact region 1, electrically connected to the body contact 165a. The contact 145b can be formed in the contact region 1, electrically connected to the contact 165b. These contacts can be formed by etching a hole in the interlayer dielectric layer 137, and filling the hole with a conductive material such as metal.

[0112] Here, the contact 139 can be electrically connected to the WL. Via the WL, a gate control signal can be applied to the gate conductor layer 127 of the cell-constituting device via the contact 139 (and in turn, via the select transistor). Via the contact 143, a gate control signal can be applied to the gate conductor layer 121 of the select transistor, and thus control the application of the signal from the WL to the gate conductor layer 127 of the cell-constituting device.

[0113] The contact 141 can be electrically connected to the BL. The contact 145a can be electrically connected to the (common) body contact BD. The contact 145b can be electrically connected to the (common) source line SL. In addition, a contact to the substrate 101 (to the well region therein) can also be provided.

[0114] In this example, one of the source / drain regions (103 n ) of each cell-constituting device can be electrically connected to the BL, while the other source / drain region (107 m ) can be electrically connected to the SL. In this way, a NOR-type configuration can be obtained. Two cell-constituting devices vertically adjacent to each other can be connected (in parallel) to the same BL, and thus define one memory cell.

[0115] Figure 21 The layout of the word lines WL1, WL2, WL3, the bit lines BL1, BL2, the (common) source line SL, the (common) body contact BD, and the select lines SG1, SG2, SG3, SG4 is schematically shown.

[0116] The word lines WL1, WL2, WL3 can extend along the second direction to be electrically connected to a column of the contacts 139 (and thus, a corresponding column of select transistors, and in turn, a corresponding column of the gate conductor layers 127 in the gate holes) in the second direction. The bit lines BL1, BL2 can extend along the second direction to be electrically connected to the source / drain layers 1072, 1071, respectively. The source line SL can be electrically connected to the source / drain layers 1033, 1032, 1031. The body contact BD can be electrically connected to the channel layers 1051, 1052, 1053, 105. The select lines SG1, SG2, SG3, SG4 can extend along the first direction, surrounding the select transistors and as the gate electrodes of the select transistors.

[0117] Figure 22An equivalent circuit diagram of a NOR-type memory device according to an embodiment of the present disclosure is schematically shown.

[0118] In the example of Fig. 13, three word lines WL1, WL2, WL3 and two bit lines BL1, BL2 are schematically shown. However, the specific number of bit lines and word lines is not limited thereto. At the intersections of the bit lines and the word lines, storage cells MC are provided. Figure 22 Three source lines SL1, SL2, SL3 are also shown in Fig. 13. Each source line can be connected to each other and can be connected to a common source line SL. As described above, a pair of cell constituting devices connected to the same bit line and adjacent in the vertical direction form a storage cell MC, which is connected to the corresponding source line on each of the upper and lower sides. The bit lines WL1, WL2, WL3 are electrically connected to the gates of the cell constituting devices in the storage cells via the corresponding selection transistors, the gates of which are electrically connected to the selection line SG1. In addition, Figure 22 In Fig. 13, (optional) body connections to the storage cells are also schematically shown in dashed lines, which can have a common body contact BD. The BD and the SL can be electrically connected to each other.

[0119] Here, only for the sake of illustration, a two-dimensional array of storage cells MC is shown. A plurality of such two-dimensional arrays can be provided in a direction intersecting the two-dimensional array (e.g., the direction perpendicular to the plane of the paper in the figure), thereby obtaining a three-dimensional array.

[0120] In the above embodiments, the common SL contact and the common body contact are described in connection with the embodiment of the storage cell based on a pair of cell constituting devices. However, the present disclosure is not limited thereto. The common SL contact and the common body contact according to the embodiments of the present disclosure and the method of manufacturing the same can also be applied to other configurations, such as a NOR-type memory device based on a single cell constituting device.

[0121] The memory device according to the embodiments of the present disclosure can be applied to various electronic devices. For example, the memory device can store various programs, applications, and data required for the operation of the electronic device. The electronic device can also include a processor cooperating with the memory device. For example, the processor can operate the electronic device by running the programs stored in the memory device. Such electronic devices are, for example, a smart phone, a personal computer (PC), a tablet, an artificial intelligence device, a wearable device, or a mobile power supply, etc.

[0122] In the above description, the technical details of the patterning, etching, etc. of each layer are not described in detail. However, it should be understood by those skilled in the art that the layers, regions, etc. of the desired shape can be formed by various technical means. In addition, those skilled in the art can also design methods that are not exactly the same as the methods described above in order to form the same structure. In addition, although each embodiment is described separately above, this does not mean that the measures in each embodiment cannot be used advantageously in combination.

[0123] The embodiments of the present disclosure are described above. However, these embodiments are only for illustrative purposes, and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A NOR-type memory device, comprising: at least one memory cell layer disposed on a substrate, the at least one memory cell layer comprising a first source / drain layer, a first channel layer, a second source / drain layer, a second channel layer, and a third source / drain layer stacked on each other in a vertical direction; at least one gate stack extending vertically with respect to the substrate to pass through the at least one memory cell layer, the at least one gate stack comprising a gate conductor layer and a memory functional layer disposed between the gate conductor layer and the at least one memory cell layer, wherein a memory cell is defined at an intersection of the at least one gate stack and the at least one memory cell layer; and at least one of a source line contact and a body contact, wherein the source line contact extends vertically with respect to the substrate to pass through the at least one memory cell layer, wherein at a location where the source line contact is located, the first source / drain layer and the third source / drain layer in the at least one memory cell layer respectively protrude with respect to the first channel layer, the second channel layer, and the second source / drain layer to contact and electrically connect with the source line contact, wherein the body contact extends vertically with respect to the substrate to pass through the at least one memory cell layer, wherein at a location where the body contact is located, the first channel layer and the second channel layer in the at least one memory cell layer respectively protrude with respect to the first source / drain layer, the second source / drain layer, and the third source / drain layer to contact and electrically connect with the body contact. 2.The NOR-type memory device according to claim 1, wherein at the location where the source line contact is located, the first channel layer, the second channel layer, and the second source / drain layer in the at least one memory cell layer are electrically isolated from the source line contact, at the location where the body contact is located, the first source / drain layer, the second source / drain layer, and the third source / drain layer in the at least one memory cell layer are electrically isolated from the body contact. 3.The NOR-type memory device according to claim 1, the second source / drain layer comprising a stack of a fourth sub-layer, a fifth sub-layer, and a sixth sub-layer, the fifth sub-layer having an etching selectivity with respect to the fourth sub-layer and the sixth sub-layer. wherein 4.The NOR-type memory device according to claim 3, the first source / drain layer comprising a stack of a first sub-layer, a second sub-layer, and a third sub-layer, the third source / drain layer comprising a stack of a seventh sub-layer, an eighth sub-layer, and a ninth sub-layer, the second sub-layer, the fifth sub-layer, and the eighth sub-layer having an etching selectivity with respect to the first sub-layer, the third sub-layer, the fourth sub-layer, the sixth sub-layer, the seventh sub-layer, and the ninth sub-layer, wherein wherein a thickness of the second sub-layer and the eighth sub-layer is not equal to a thickness of the fifth sub-layer. the thickness of the second sub-layer and the eighth sub-layer is less than the thickness of the fifth sub-layer.

5. The NOR-type memory device of claim 4, wherein, a thickness of the fourth sub-layer at a higher level is greater than a thickness of the fourth sub-layer at a lower level, and a thickness of the sixth sub-layer at the higher level is greater than a thickness of the sixth sub-layer at the lower level.

6. The NOR-type memory device of claim 3, wherein, ​ 7. The NOR-type memory device according to claim 3 or 6, wherein, The thickness of the first channel layer at the higher level is greater than the thickness of the first channel layer at the lower level, and the thickness of the second channel layer at the higher level is greater than the thickness of the second channel layer at the lower level.

8. The NOR-type memory device of claim 4, wherein, The thickness of the first sub-layer at the higher level is greater than the thickness of the first sub-layer at the lower level, the thickness of the third sub-layer at the higher level is greater than the thickness of the third sub-layer at the lower level, the thickness of the seventh sub-layer at the higher level is greater than the thickness of the seventh sub-layer at the lower level, and the thickness of the ninth sub-layer at the higher level is greater than the thickness of the ninth sub-layer at the lower level.

9. The NOR-type memory device of claim 4, wherein, The sidewall of the first source / drain layer and the third source / drain layer adjacent to the source line contact portion is dentiform and engages the source line contact portion.

10. The NOR-type memory device of claim 1, wherein, The first source / drain layer and the third source / drain layer respectively surround the source line contact portion.

11. The NOR-type memory device of claim 1, wherein, The first channel layer and the second channel layer respectively surround the body contact portion.

12. The NOR-type memory device of claim 1, wherein, The source line contact portion is electrically isolated from the substrate at the bottom by a dielectric, and the body contact portion is electrically isolated from the substrate at the bottom by a dielectric.

13. The NOR-type memory device of claim 1, wherein, The at least one storage unit layer includes a plurality of storage unit layers, and the first source / drain layer, the first channel layer, the second source / drain layer, the second channel layer and the third source / drain layer in each storage unit layer are in direct contact with each other, and adjacent storage unit layers are in direct contact with each other.

14. The NOR-type memory device of claim 1, wherein, At least one of the first source / drain layer, the first channel layer, the second source / drain layer, the second channel layer and the third source / drain layer laterally surrounds one or more of the at least one gate stack.

15. The NOR-type memory device of claim 1, further comprising: At least one selection transistor disposed on the at least one gate stack, the at least one selection transistor being self-aligned to the at least one gate stack.

16. The NOR memory of claim 4, wherein, The at least one storage unit layer includes a plurality of storage unit layers, and the uppermost storage unit layer includes a stack of the seventh sub-layer and the eighth sub-layer, and does not include the ninth sub-layer.

17. A method of manufacturing a NOR-type memory device, comprising: disposing at least one storage unit layer on a substrate including a contact region and a device region, the at least one storage unit layer including a first source / drain layer, a first channel layer, a second source / drain layer, a second channel layer and a third source / drain layer stacked in a vertical direction with respect to each other; forming at least one gate hole extending vertically with respect to the substrate in the device region to pass through the at least one storage unit layer; forming a corresponding gate stack in the at least one gate hole, respectively, the gate stack including a gate conductor layer and a storage function layer disposed between the gate conductor layer and the at least one storage unit layer; forming a first contact hole extending vertically with respect to the substrate in the contact region to pass through the at least one storage unit layer; laterally retracting at least a portion of the sidewall of the second source / drain layer exposed in the first contact hole by selective etching to form a lateral channel; introducing an etchant via the first contact hole to etch at least the second source / drain layer, wherein the etchant also acts on the second source / drain layer through the lateral channel, so that the second source / drain layer is relatively recessed in the first contact hole; and forming a first contact portion in the first contact hole that is electrically isolated from the second source / drain layer, wherein, after the selective etching, the first source / drain layer and the third source / drain layer respectively protrude relative to the second source / drain layer in the first contact hole, wherein the first contact portion is electrically connected to the first source / drain layer and the third source / drain layer.

18. The method of claim 17, wherein, In the operation of introducing an etchant via the first contact hole to etch at least the second source / drain layer, the first channel layer and the second channel layer are also etched, so that the first source / drain layer and the third source / drain layer respectively protrude relative to the second source / drain layer and the first channel layer and the second channel layer in the first contact hole.

19. The method of claim 17 or 18, wherein, The second source / drain layer comprises a stack of a fourth sub-layer, a fifth sub-layer and a sixth sub-layer, wherein the fifth sub-layer has etching selectivity relative to the fourth sub-layer and the sixth sub-layer, wherein the selective etching comprises selectively etching the fifth sub-layer.

20. The method of claim 19, wherein, An etching depth of the selective etching of the fifth sub-layer is greater than a sum of a thickness of the fourth sub-layer and a thickness of the first channel layer, and greater than a sum of a thickness of the sixth sub-layer and a thickness of the second channel layer.

21. The method of claim 19, wherein, In the operation of introducing an etchant via the first contact hole to etch at least the second source / drain layer, the etching depth is greater than a sum of a thickness of the fourth sub-layer and a thickness of the first channel layer, and greater than a sum of a thickness of the sixth sub-layer and a thickness of the second channel layer.

22. The method of claim 21, wherein, A thickness of the fourth sub-layer at a higher level is greater than a thickness of the fourth sub-layer at a lower level, and a thickness of the sixth sub-layer at the higher level is greater than a thickness of the sixth sub-layer at the lower level.

23. The method of claim 22, wherein, A thickness of the first channel layer at a higher level is greater than a thickness of the first channel layer at a lower level, and a thickness of the second channel layer at the higher level is greater than a thickness of the second channel layer at the lower level.

24. The method of claim 17, wherein, Forming the first contact portion in the first contact hole comprises: filling a dielectric material in the first contact hole; selectively etching the dielectric material so that the dielectric material left in the first contact hole shields the second source / drain layer, and a certain thickness of the dielectric material is left at a bottom of the first contact hole; filling a conductive material in the first contact hole left with the dielectric material to form the first contact portion.

25. A method of manufacturing a NOR-type memory device, comprising: providing at least one memory cell layer on a substrate comprising a contact region and a device region, the at least one memory cell layer comprising a first source / drain layer, a first channel layer, a second source / drain layer, a second channel layer and a third source / drain layer stacked in a vertical direction relative to each other; forming at least one gate hole in the device region extending vertically relative to the substrate to pass through the at least one memory cell layer; forming a respective gate stack in the at least one gate hole, the gate stack comprising a gate conductor layer and a storage functional layer disposed between the gate conductor layer and the at least one storage unit layer; forming a first contact hole in the contact region extending vertically with respect to the substrate to pass through the at least one storage unit layer; lateral recessing at least part of the exposed sidewall of the second source / drain layer in the first contact hole by selective etching to form a lateral channel; introducing an etchant through the first contact hole to etch at least the second source / drain layer, wherein the etchant also acts on the second source / drain layer through the lateral channel, thereby recessing the second source / drain layer in the first contact hole relative to the first source / drain layer and the third source / drain layer; and forming a first contact portion in the first contact hole electrically isolated from the second source / drain layer, wherein, in the selective etching, at least part of the exposed sidewall of the first source / drain layer and the third source / drain layer in the first contact hole is also laterally recessed to form a further lateral channel; wherein, in the operation of introducing an etchant through the first contact hole to etch at least the second source / drain layer, the first source / drain layer and the third source / drain layer are also etched, wherein the etchant also acts on the first source / drain layer and the third source / drain layer through the further lateral channel, thereby extending the first channel layer and the second channel layer in the first contact hole relative to the first source / drain layer, the second source / drain layer and the third source / drain layer respectively, wherein the first contact portion is electrically connected to the first channel layer and the second channel layer.

26. The method of claim 25, wherein, The first source / drain layer comprises a stack of a first sub-layer, a second sub-layer and a third sub-layer, the second source / drain layer comprises a stack of a fourth sub-layer, a fifth sub-layer and a sixth sub-layer, and the third source / drain layer comprises a stack of a seventh sub-layer, an eighth sub-layer and a ninth sub-layer, wherein the second sub-layer, the fifth sub-layer and the eighth sub-layer have etching selectivity with respect to the first sub-layer, the third sub-layer, the fourth sub-layer, the sixth sub-layer, the seventh sub-layer and the ninth sub-layer, wherein the selective etching comprises selectively etching the second sub-layer, the fifth sub-layer and the eighth sub-layer.

27. The method of claim 26, wherein, The etching depth of the selective etching of the second sub-layer, the fifth sub-layer and the eighth sub-layer is greater than the thickness of each of the first sub-layer, the third sub-layer, the fourth sub-layer, the sixth sub-layer, the seventh sub-layer and the ninth sub-layer.

28. The method of claim 26, wherein, In the operation of introducing an etchant through the first contact hole to etch the first source / drain layer, the second source / drain layer and the third source / drain layer, the etching depth is greater than the thickness of each of the first sub-layer, the third sub-layer, the fourth sub-layer, the sixth sub-layer, the seventh sub-layer and the ninth sub-layer.

29. The method of claim 28, wherein, The thickness of the first sub-layer at the higher level is greater than the thickness of the first sub-layer at the lower level, the thickness of the third sub-layer at the higher level is greater than the thickness of the third sub-layer at the lower level, the thickness of the seventh sub-layer at the higher level is greater than the thickness of the seventh sub-layer at the lower level, and the thickness of the ninth sub-layer at the higher level is greater than the thickness of the ninth sub-layer at the lower level.

30. A method of manufacturing a NOR-type memory device, comprising: providing at least one memory cell layer on a substrate including a contact region and a device region, the at least one memory cell layer including a first source / drain layer, a first channel layer, a second source / drain layer, a second channel layer, and a third source / drain layer stacked on one another in a vertical direction; forming at least one gate hole extending vertically relative to the substrate to pass through the at least one memory cell layer in the device region; forming respective gate stacks in the at least one gate hole, the gate stacks including a gate conductor layer and a memory functional layer disposed between the gate conductor layer and the at least one memory cell layer; forming a first contact hole extending vertically relative to the substrate to pass through the at least one memory cell layer in the contact region; laterally recessing at least a portion of a sidewall of the second source / drain layer exposed in the first contact hole by selective etching to form a lateral channel; introducing an etchant via the first contact hole to etch at least the second source / drain layer, wherein the etchant also acts on the second source / drain layer through the lateral channel, thereby recessing the second source / drain layer in the first contact hole relative to the first source / drain layer and the third source / drain layer; and forming a first contact portion in the first contact hole that is electrically isolated from the second source / drain layer, wherein the first source / drain layer and the third source / drain layer respectively protrude relative to the second source / drain layer and the first channel layer and the second channel layer in the first contact hole after the selective etching, wherein the first contact portion is electrically connected to the first source / drain layer and the third source / drain layer, the method further comprising: forming a second contact hole extending vertically relative to the substrate to pass through the at least one memory cell layer in the contact region; laterally recessing at least a portion of a sidewall of the first source / drain layer, the second source / drain layer, and the third source / drain layer exposed in the second contact hole by selective etching to form further lateral channels; introducing an etchant via the second contact hole to etch the first source / drain layer, the second source / drain layer, and the third source / drain layer, wherein the etchant also acts on the first source / drain layer, the second source / drain layer, and the third source / drain layer through the further lateral channels, thereby protruding the first channel layer and the second channel layer relative to the first source / drain layer, the second source / drain layer, and the third source / drain layer in the second contact hole, respectively; and forming a second contact portion in the second contact hole that is electrically connected to the first channel layer and the second channel layer.

31. The method of claim 30, wherein, In the operation of introducing an etchant via the first contact hole to etch at least the second source / drain layer, the first channel layer and the second channel layer are also etched, so that the first source / drain layer and the third source / drain layer respectively protrude relative to the second source / drain layer and the first channel layer and the second channel layer in the first contact hole.

32. The method of claim 31, wherein, The second source / drain layer comprises a stack of a fourth sub-layer, a fifth sub-layer and a sixth sub-layer, wherein the fifth sub-layer has etching selectivity relative to the fourth sub-layer and the sixth sub-layer, wherein the selective etching comprises selectively etching the fifth sub-layer.

33. The method of claim 32, wherein, The etching depth of the selective etching of the fifth sub-layer is greater than the sum of the thickness of the fourth sub-layer and the thickness of the first channel layer, and greater than the sum of the thickness of the sixth sub-layer and the thickness of the second channel layer.

34. The method of claim 32, wherein, In the operation of introducing an etchant via the first contact hole to etch at least the second source / drain layer, the etching depth is greater than the sum of the thickness of the fourth sub-layer and the thickness of the first channel layer, and greater than the sum of the thickness of the sixth sub-layer and the thickness of the second channel layer.

35. The method of claim 34, wherein, The thickness of the fourth sub-layer at a higher level is greater than the thickness of the fourth sub-layer at a lower level, and the thickness of the sixth sub-layer at a higher level is greater than the thickness of the sixth sub-layer at a lower level.

36. The method of claim 34, wherein, The thickness of the first channel layer at a higher level is greater than the thickness of the first channel layer at a lower level, and the thickness of the second channel layer at a higher level is greater than the thickness of the second channel layer at a lower level.

37. The method of claim 32, wherein, The first source / drain layer comprises a stack of a first sub-layer, a second sub-layer and a third sub-layer, and the third source / drain layer comprises a stack of a seventh sub-layer, an eighth sub-layer and a ninth sub-layer, the thickness of the second sub-layer and the eighth sub-layer are not equal to the thickness of the fifth sub-layer, wherein the second sub-layer, the fifth sub-layer and the eighth sub-layer are simultaneously selectively etched via the first contact hole and the second contact hole, wherein the method further comprises: forming a filling plug in the recesses of the second sub-layer and the eighth sub-layer respectively caused by the selective etching in the first contact hole.

38. The method of claim 37, wherein, The thickness of the second sub-layer and the eighth sub-layer is less than the thickness of the fifth sub-layer, wherein forming the filling plug comprises: depositing a plug material layer having a thickness greater than half of the thickness of the second sub-layer and the eighth sub-layer respectively and less than half of the thickness of the fifth sub-layer; selectively etching the plug material layer to a thickness such that the plug material layer remains in the recesses of the second sub-layer and the eighth sub-layer respectively caused by the selective etching to form the filling plug, and is removed from the recess of the fifth sub-layer caused by the selective etching.

39. An electronic device comprising the NOR memory device of any one of claims 1 to 16.

40. The electronic device of claim 39, wherein, The electronic device comprises a smartphone, a personal computer, a tablet computer, an artificial intelligence device, a wearable device or a mobile power supply. The electronic device comprises a smartphone, a personal computer, a tablet computer, an artificial intelligence device, a wearable device or a mobile power supply.

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