A junction barrier schottky diode and its manufacturing method and application

Abstract

The application provides a junction barrier Schottky diode, a manufacturing method and application thereof. The junction barrier Schottky diode comprises a substrate, opposite sides of a surface of the substrate are respectively provided with a cell region and a P+ field limiting ring region, a position of the surface of the substrate between the cell region and the P+ field limiting ring region is further provided with a P+ main junction region, and the cell region, the P+ main junction region and the P+ field limiting ring region are mutually spaced; the cell region comprises a plurality of mutually spaced P+ regions, a metal barrier region is formed between the P+ region close to the P+ main junction region and the P+ main junction region and between any two adjacent P+ regions, a ratio of a width of a single P+ region in a preset direction to a width of a single metal barrier region in the preset direction is 0.45-0.5, and the preset direction is a direction from the cell region to the P+ field limiting ring region. The application fully considers the width ratio between the single P+ region and the single metal barrier region, thereby improving the shielding effect of the metal barrier region, so that the junction barrier Schottky diode can have an ultra-low reverse leakage current.

Description

[Technical Field]

[0001] This application relates to the field of power electronic device technology, and in particular to a junction barrier Schottky diode, its fabrication method, and its application. [Background Technology]

[0002] In related technologies, JBS (Junction Barrier Schottky) diodes typically consist of a substrate, a buffer layer, an epitaxial layer, a field-limiting ring region, a main junction region, a unit cell region, a metal barrier region, and an anode metal. The unit cell region comprises multiple spaced-apart P+ regions, and the area between any two adjacent P+ regions is part of the metal barrier region. The unit cell region and the termination structure (i.e., the field-limiting ring region) of a JBS diode need to be matched during design. Furthermore, due to limitations in manufacturing processes, JBS diodes exhibit significant shortcomings in forward characteristics, reverse leakage current, avalanche withstand capability, surge current, and power dissipation, which greatly limits their application range.

[0003] Therefore, it is necessary to improve the structure of the JBS diode described above. [Summary of the Invention]

[0004] This application provides a junction barrier Schottky diode, its fabrication method, and its application, aiming to solve the problem of high reverse leakage current in JBS diodes in related technologies.

[0005] To solve the above-mentioned technical problems, the first aspect of the present application provides a junction barrier Schottky diode, including a substrate, wherein a primitive cell region and a P+ field-limiting ring region are respectively disposed on opposite sides of the surface of the substrate, and a P+ main junction region is further disposed on the surface of the substrate at a position between the primitive cell region and the P+ field-limiting ring region, wherein the primitive cell region, the P+ main junction region and the P+ field-limiting ring region are spaced apart from each other;

[0006] The unit cell region includes multiple P+ regions spaced apart from each other. A metal barrier region is formed between the P+ regions near the P+ main junction region and between any two adjacent P+ regions. The ratio of the width of a single P+ region in a predetermined direction to the width of a single metal barrier region in the predetermined direction is 0.45 to 0.5. The predetermined direction is the direction from the unit cell region to the P+ field-limiting ring region.

[0007] A second aspect of this application provides a method for fabricating a junction barrier Schottky diode, comprising:

[0008] Obtain the substrate;

[0009] Using photoresist as a masking layer, inactive primitive cell regions, P+ field-confining ring regions, and P+ main junction regions are implanted on the surface of the substrate. The primitive cell regions and the P+ field-confining ring regions are located on opposite sides of the substrate surface, and the P+ main junction region is located between the primitive cell regions and the P+ field-confining ring regions on the substrate surface. The primitive cell regions, the P+ main junction regions, and the P+ field-confining ring regions are spaced apart from each other. Each primitive cell region includes multiple spaced P+ regions. A metal barrier region is formed between each P+ region near the P+ main junction region and between any two adjacent P+ regions. The ratio of the width of a single P+ region in a predetermined direction to the width of a single metal barrier region in the predetermined direction is 0.45 to 0.5. The predetermined direction is the direction from the primitive cell region to the P+ field-confining ring region.

[0010] The protocell region, the P+ field-confined ring region, and the P+ main junction region are ion activated by a high-temperature ion activation process under carbon film protection.

[0011] The third aspect of this application provides an application of the junction barrier Schottky diode described in the first aspect of this application in power electronic devices.

[0012] As can be seen from the above description, compared with related technologies, the beneficial effects of this application are as follows:

[0013] A junction barrier Schottky diode is constructed using a substrate, a unit cell region, a P+ field-limiting ring region, and a P+ main junction region. The unit cell region is configured to include multiple mutually spaced P+ regions, so that a metal barrier region is formed between the P+ regions near the P+ main junction region and between any two adjacent P+ regions. At the same time, the ratio of the width of a single P+ region in a preset direction (from the unit cell region to the P+ field-limiting ring region) to the width of a single metal barrier region in the preset direction is set to 0.45 to 0.5. Understandably, traditional JBS diodes do not take into account the width ratio between a single P+ region and a single metal barrier region, and the widths of the P+ region and the metal barrier region also need to be adapted to the width of the termination structure (i.e., field limiting ring). This results in a large leakage current in the metal barrier region and poor forward characteristics of the diode. However, this application fully considers the width ratio between a single P+ region and a single metal barrier region, that is, sets the width ratio between a single P+ region and a single metal barrier region to 0.45 to 0.5, thereby improving the shielding effect of the metal barrier region and enabling the junction barrier Schottky diode to have ultra-low reverse leakage current. [Attached Image Description]

[0014] To more clearly illustrate the related technologies or the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the related technologies or the embodiments of this application will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application, and not all embodiments. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 This is a schematic diagram of the structure of a traditional JBS diode;

[0016] Figure 2 This is a schematic diagram of the junction barrier Schottky diode provided in an embodiment of this application;

[0017] Figure 3 This is a schematic flowchart illustrating the fabrication method of the junction barrier Schottky diode provided in an embodiment of this application.

Detailed Implementation Methods

[0018] To make the objectives, technical solutions, and advantages of this application more apparent and understandable, the application will be clearly and completely described below in conjunction with the embodiments and corresponding drawings. Throughout, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions. It should be understood that the various embodiments of this application described below are merely illustrative and not intended to limit the application. That is, all other embodiments obtained by those skilled in the art based on the various embodiments of this application without creative effort are within the scope of protection of this application. Furthermore, the technical features involved in the various embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0019] JBS (Junction Barrier Schottky) diodes are widely used in various power electronic devices, such as solar inverters, new energy vehicle chargers, switching power supplies, energy storage devices, and high-frequency power converters. In solar inverters, JBS diodes significantly improve switching speed and energy consumption. In new energy vehicle chargers, JBS diodes not only ensure the safety margin of nominal and peak voltages but also further improve the charger's space utilization and reduce its weight. In high-frequency power converters, JBS diodes offer excellent characteristics such as fast switching, zero recovery, and temperature independence. In recent years, with the continuous improvement and development of power electronics technology, higher requirements have been placed on the performance of JBS diodes, such as the increasingly stringent requirements for leakage current in energy storage devices.

[0020] For related technologies, please refer to Figure 1 , Figure 1 This is a schematic diagram of a traditional JBS diode. A traditional JBS diode typically includes a substrate 1′, a buffer layer 2′, an epitaxial layer 3′, a field-limiting ring region 4′, a main junction region 5′, a unit cell region 6′, a metal barrier region 7′, and an anode metal 8′. The unit cell region 6′ comprises multiple spaced-apart P+ regions 9′, and the area between any two adjacent P+ regions 9′ is part of the metal barrier region 7′. Traditional JBS diodes have low reverse voltage and high leakage current, thus limiting their application range. Therefore, to expand their application range, improving the breakdown voltage and reducing the leakage current of JBS diodes has become a research direction for optimization and improvement. For example, embedding the P+ region 9′ within the unit cell region 6′ aims to improve the breakdown voltage of the JBS diode. Furthermore, the electric field is concentrated at the terminal edge of the JBS diode, which reduces its breakdown voltage and increases its leakage current. This leads to deterioration of the JBS diode's functional characteristics or even breakdown, resulting in frequent JBS diode failures. Therefore, protection techniques are needed at the terminal of the JBS diode to reduce the surface electric field intensity at the terminal edge and improve its breakdown voltage. The protection techniques used at the JBS diode terminal are highly correlated with the materials, the thickness and ion doping concentration of the epitaxial layer 3′, and the diode's structure itself. The forward and reverse characteristics of the JBS diode are one of the main factors affecting power loss. The forward voltage drop is a major factor in the diode's operation, primarily contributing to conduction losses. This creates a contradiction between the reverse breakdown voltage and the forward voltage drop of the JBS diode. From a physical structure perspective, the structure, dimensions, and ratio of the P+ region 9′ and the metal barrier region 7′ in a traditional JBS diode are the main influencing factors of its static and dynamic parameters. From a manufacturing process perspective, the junction depth of the PN junction, the metal material of the metal barrier region 7′, and the annealing process also significantly affect the characteristics of a JBS diode. As described above, the unit cell region 6′ and the termination structure (i.e., the field-limiting loop region 4′) of a traditional JBS diode need to be matched during design. Furthermore, due to limitations in manufacturing processes, JBS diodes suffer from significant deficiencies in forward characteristics, reverse leakage current, avalanche withstand capability, surge current, and power dissipation, which greatly limits their application range. Therefore, this application provides a junction barrier Schottky diode that can be applied to various power electronic devices, such as solar inverters, new energy vehicle chargers, switching power supplies, energy storage devices, and high-frequency power converters.

[0021] Please see Figure 2 , Figure 2This is a schematic diagram of the junction barrier Schottky diode provided in an embodiment of this application. The junction barrier Schottky diode provided in this embodiment includes a substrate 10. A primitive cell region 20 and a P+ field-limiting ring region 30 are respectively disposed on opposite sides of the surface of the substrate 10. A P+ main junction region 40 is also disposed on the surface of the substrate 10 between the primitive cell region 20 and the P+ field-limiting ring region 30, and the primitive cell region 20, the P+ main junction region 40 and the P+ field-limiting ring region 30 are spaced apart from each other. Specifically, the unit cell region 20 includes multiple mutually spaced P+ regions 21. A metal barrier region 22 is formed between the P+ regions 21 near the P+ main junction region 40 and between any two adjacent P+ regions 21. The ratio of the width of a single P+ region 21 in a predetermined direction to the width of a single metal barrier region 22 in a predetermined direction is 0.45 to 0.5. The predetermined direction is from the unit cell region 20 to the P+ field-limiting ring region 30. The P+ main junction region 40 can be considered as an extension region of the P+ regions 21 in the unit cell region 20. The metal barrier region 22 is also the ohmic contact region between the unit cell region 20 (i.e., the P+ regions 21) and the P+ main junction region 40. In this paper, the metal thickness of the metal barrier region 22 can be... The junction depths of the P+ field confinement ring region 30, the P+ main junction region 40, and the primitive cell region 20 can all be 1 to 1.5 μm. Of course, the thickness and junction depth here are only preferred options, and this application embodiment does not limit them to the only one.

[0022] In this embodiment, a junction barrier Schottky diode is constructed using a substrate 10, a primitive cell region 20, a P+ field-limiting ring region 30, and a P+ main junction region 40. The primitive cell region 20 includes a plurality of mutually spaced P+ regions 21, so that a metal barrier region 22 is formed between the P+ regions 21 near the P+ main junction region 40 and between any two adjacent P+ regions 21. At the same time, the ratio of the width of a single P+ region 21 in a preset direction (from the primitive cell region 20 to the P+ field-limiting ring region 30) to the width of a single metal barrier region 22 in the preset direction is set to 0.45 to 0.5. Understandably, traditional JBS diodes do not take into account the width ratio between a single P+ region 9′ and a single metal barrier region 7′, and the widths of the P+ region 9′ and the metal barrier region 7′ also need to be adapted to the width of the termination structure (i.e., the field limiting ring in the field limiting ring region 4′). This results in a large leakage current in the metal barrier region 7′ and poor forward characteristics of the diode. However, the embodiments of this application fully consider the width ratio between a single P+ region 21 and a single metal barrier region 22, that is, setting the width ratio between a single P+ region 21 and a single metal barrier region 22 to 0.45 to 0.5, thereby improving the shielding effect of the metal barrier region 22, enabling the junction barrier Schottky diode to have an ultra-low reverse leakage current.

[0023] As one implementation method, please refer to Figure 2The P+ field limiting ring region 30 may include multiple P+ field limiting rings 31 spaced apart from each other. The width of the P+ field limiting ring region 30 remains constant in a preset direction. The distance between the P+ main junction region 40 and the P+ field limiting ring 31 adjacent to the P+ main junction region 40, as well as the distance between the multiple P+ field limiting rings 31, increases gradually along the preset direction. For example, the P+ field limiting ring region 30 includes 5 P+ field limiting rings 31, which are represented by A, B, C, D, and E respectively. A to E are arranged sequentially along the preset direction. AB represents the distance between A and B, BC represents the distance between B and C, CD represents the distance between C and D, DE represents the distance between D and E, and AA represents the distance between the P+ main junction region 40 and A. Therefore, DE > CD > BC > AB > AA.

[0024] In one specific implementation, the width of the P+ field limiting ring region 30 remains constant at 3.8 μm in a preset direction. The distance between the P+ main junction region 40 and the P+ field limiting ring 31 adjacent to the P+ main junction region 40, as well as the distance between multiple P+ field limiting rings 31, increases within the preset direction from 1.2 to 3.2 μm. Here, continuing with the example given earlier, AE (the distance between A and E) is 3.8 μm, while AA can be 1.2 μm, AB can be 1.8 μm, BC can be 2.2 μm, CD can be 2.6 μm, and DE can be 3.2 μm.

[0025] It should be understood that this embodiment is only a preferred implementation of the embodiments of this application, and it is not the only limitation on the P+ field limiting region 30; those skilled in the art can make flexible settings based on the embodiments of this application and according to the actual application scenario.

[0026] As one implementation method, please refer to Figure 2 The substrate 10 can adopt a dual-base region structure, that is, the substrate 10 can include an N+ substrate layer 11, an N-type buffer layer 12 and an N-epipolar layer 13; wherein, the N-type buffer layer 12 is covered on the surface of the N+ substrate layer 11, the N-epipolar layer 13 is covered on the surface of the N-type buffer layer 12, and the materials of the N+ substrate layer 11, the N-type buffer layer 12 and the N-epipolar layer 13 are all silicon carbide.

[0027] In one specific implementation, the thickness of the N-type buffer layer 12 can be 0.5–1 μm, and the ion doping concentration can be 0.9E18–1.1E18. Meanwhile, the thickness of the N-epitaxial layer 13 can be 6–7 μm, and the ion doping concentration can be 1E16–2E16. Therefore, both the thickness and ion doping concentration of the N-epitaxial layer 13 are greater than those of the N-type buffer layer 12.

[0028] It should be understood that this embodiment is only a preferred implementation of the embodiments of this application and is not the only limitation on the substrate 10; those skilled in the art can make flexible settings based on the embodiments of this application and according to the actual application scenario.

[0029] In some embodiments, the junction barrier Schottky diode provided in this application may include, in addition to the substrate 10 (composed of an N+ substrate layer 11, an N-type buffer layer 12, and an N-epipolar layer 13), the unit cell region 20 (composed of multiple P+ regions 21), the P+ field-limiting ring region 30, the P+ main junction region 40, and the metal barrier region 22, other common structures provided in junction barrier Schottky diodes in the art, such as the anode metal 50 covering the surface of the substrate 10 (i.e., the surface of the N-epipolar layer 13) and located above the unit cell region 20 and the P+ main junction region 40. Of course, it may also include the cathode metal, which will not be listed one by one in this embodiment. In addition, it should be noted that since the metal barrier region 22 is also the ohmic contact region of the unit cell region 20 (i.e., the P+ region 21 therein) and the P+ main junction region 40, an additional metal layer 60 for ohmic contact and barrier contact will be formed between the anode metal 50 and the N-epitaxial layer 13 (specifically, the unit cell region 20 and the P+ main junction region 40).

[0030] Please see Figure 3 , Figure 3 This is a schematic flowchart illustrating a method for fabricating a junction barrier Schottky diode according to an embodiment of this application. This application also provides a method for fabricating a junction barrier Schottky diode, which includes steps 301 to 303.

[0031] Step 301: Obtain the substrate.

[0032] In the embodiments of this application, when fabricating a junction barrier Schottky diode, some preliminary preparations are required, namely, obtaining a substrate 10; wherein, the substrate 10 may be composed of an N+ substrate layer 11, an N-type buffer layer 12 and an N-epipolar layer 13 as shown above.

[0033] Step 302: Using photoresist as a masking layer, inactive primitive cell regions, P+ field confinement ring regions, and P+ main junction regions are implanted on the surface of the substrate.

[0034] In this embodiment of the application, after the substrate 10 is prepared, it is also necessary to use photoresist as a masking layer to implant and form an inactive primitive cell region 20, a P+ field confinement ring region 30 and a P+ main junction region 40 on the surface of the substrate 10; wherein, the primitive cell region 20 and the P+ field confinement ring region 30 are located on opposite sides of the surface of the substrate 10, and the P+ main junction region 40 is located between the primitive cell region 20 and the P+ field confinement ring region 30 on the surface of the substrate 10, and the primitive cell region 20, the P+ main junction region 40 and the P+ field confinement ring region 30 are spaced apart from each other. Specifically, the unit cell region 20 includes a plurality of mutually spaced P+ regions 21. A metal barrier region 22 is formed between the P+ regions 21 near the P+ main junction region 40 and between any two adjacent P+ regions 21. The ratio of the width of a single P+ region 21 in a predetermined direction to the width of a single metal barrier region 22 in a predetermined direction is 0.45 to 0.5. The predetermined direction is the direction from the unit cell region 20 to the P+ field-limiting ring region 30.

[0035] Step 303: Ion activation of the unit cell region, P+ field-confined ring region and P+ main junction region is carried out by high-temperature ion activation process under carbon film protection.

[0036] In this embodiment of the application, after the unactivated primitive cell region 20, P+ field confinement ring region 30 and P+ main junction region 40 are formed by implantation on the surface of the substrate 10, the primitive cell region 20, P+ field confinement ring region 30 and P+ main junction region 40 need to be ion activated by a high-temperature ion activation process under carbon film protection.

[0037] To clearly understand the fabrication method of the junction barrier Schottky diode provided in the embodiments of this application, a specific example will be used below to aid understanding of the fabrication method of the junction barrier Schottky diode:

[0038] 1. Initial cleaning and oxidation of silicon carbide wafers, followed by field oxygen growth, with a thickness of [missing information].

[0039] 2. Perform coating, photolithography, and development processes to form the field oxide etchable areas of P+ field confinement ring region 30, P+ main junction region 40, and unit cell region 20;

[0040] 3. Perform field oxygen wet etching process to form the ion implantation regions of P+ field confinement zone 30, P+ main junction zone 40 and unit cell zone 20;

[0041] 4. Remove adhesive and etch, then clean the silicon carbide wafer;

[0042] 5. High-temperature aluminum ion implantation in the P+ field-limiting ring region 30, the P+ main junction region 40, and the unit cell region 20, with an implantation dose of 5E13~8E14 / cm². 2 The injection temperature is 500℃, forming an inactive P+ field-limited ring region 30, a P+ main junction region 40, and a primitive cell region 20.

[0043] 6. Remove all oxide layers and clean the silicon wafer;

[0044] 7. Coat a carbon film (used as a protective layer) with photoresist to form a thickness of 2μm;

[0045] 8. Carbon film annealing: temperature 800-820℃, duration 20-30 min, gas is nitrogen;

[0046] 9. High-temperature ion activation: temperature 1750–1850℃, duration 30 min, gas is argon;

[0047] 10. Carbon film removal: temperature 800℃, duration 115–130 min, gas is oxygen;

[0048] 11. Inorganic and organic cleaning of silicon carbide wafers;

[0049] 12. Perform field oxygen growth, with a thickness of [missing information].

[0050] 13. Fabrication of the ohmic contact metal on the back side (i.e., the side of the N+ substrate 11 away from the N-type buffer layer 12), the thickness of the titanium is... The thickness of the nickel is

[0051] 14. RTP annealing, temperature 1050~100℃, duration 200~220s, gas is nitrogen;

[0052] 15. Coating and pre-baking the surface of silicon carbide wafers;

[0053] 16. Exposure and baking of metal electrode photomasks;

[0054] 17. Exposure and development of silicon carbide wafers;

[0055] 18. Sputtered metal, titanium thickness is

[0056] 19. Electron beam evaporated aluminum electrode, with a thickness of 4–5 μm;

[0057] 20. The separation of titanium and aluminum metals;

[0058] 21. Metal alloy, temperature 450℃, duration 60min;

[0059] 22. Coating with polyimide and photolithography of polyimide to form the electrode PAD area;

[0060] 23. Polyimide is cured at high temperature: 350-400℃ for 60-80 minutes.

[0061] 24. Metal vapor deposition on the back, the metal from bottom to top is titanium (thickness is...) Ni (thickness is) ), silver (thickness is ).

[0062] It is understandable that in the above steps 1 to 24, steps 1 to 5 are used to form the unactivated unit cell region 20, P+ field-limiting ring region 30 and P+ main junction region 40, steps 6 to 10 are used to perform high-temperature ion activation on the unactivated unit cell region 20, P+ field-limiting ring region 30 and P+ main junction region 40, and steps 11 to 24 are used to form other common structures of junction barrier Schottky diodes, such as anode metal 50, etc.

[0063] In summary, this application provides a junction barrier Schottky diode (JBS) with a device structure comprising a uniformly ion-doped N-type buffer layer 12, a unit cell region 20 (including multiple spaced P+ regions 21), a P+ main junction region 40 (serving as an extension region of the P+ region 21 in the unit cell region 20), a P+ field-limiting ring region 30 (including multiple spaced P+ field-limiting rings 31), a metal barrier region 22 (serving as the ohmic contact region of the P+ main junction region and the P+ region 21), a metal surface electrode (i.e., anode metal 50), and a metal layer 60 for ohmic and barrier contacts. The ratio between the P+ region 21 and the metal barrier region 22 in the unit cell region 20 is optimized, enabling the high-voltage silicon carbide JBS diode to meet the withstand voltage requirements during reverse operation, while also possessing excellent forward characteristics and ultra-low reverse leakage current. This lays a solid foundation for the product's application in the energy storage field and expands the application range of JBS diodes. In addition to considering the selection of the metal used in the metal barrier region and the process conditions, the high-temperature ion implantation process is also an important aspect that needs to be considered in the fabrication method. For example, the process implantation conditions of the P+ region 21 may lead to poor reverse characteristics of the JBS diode, which will limit the application of the JBS diode in the field of low power consumption, that is, it will weaken the JBS diode's ability to suppress reverse current. However, the embodiments of this application utilize the characteristics of high-temperature implantation of silicon carbide, and use an unshielded ion implantation process and an ultra-high temperature annealing process to fabricate a JBS diode with excellent characteristics. At the same time, the process steps are simplified and the process cycle is shortened, making the manufacturing cost of the JBS diode lower, thereby meeting the needs of mass production.

[0064] This embodiment of the application uses photoresist as a masking layer to achieve localized, zero-degree-angle unmasked ion implantation on the uniformly ion-doped N-epilithial layer 13, and simultaneously performs high-temperature ion activation under the protection of an annealed carbon film. The result is the formation of a P-type heavily doped unit cell region 20, a P+ field-limiting ring region 30, and a P+ main junction region 40. In the traditional JBS diode fabrication method, the unit cell region 6′ and the termination structure (i.e., the field-limiting ring region 4′) generally employ an oxide layer barrier and a non-zero implantation angle. Regarding the physical structure of the traditional JBS diode, the width ratio between the unit cell region 6′ and the metal barrier region 7′ does not consider an optimal combination, and the widths of the P+ region 9′ and the metal barrier region 7′ in the unit cell region 6′ need to be compatible with the field-limiting ring in the field-limiting ring region 4′. As a result, the leakage current in the metal barrier region 7′ in the unit cell region 6′ is relatively large, and the forward characteristics of the diode are not optimal. However, in this embodiment, the influence of the width ratio between the P+ region 21 and the metal barrier region 22 in the unit cell region 20 on the JBS diode is fully considered. At the same time, since the minority carrier effect does not need to be considered, the step of synchronously implanting the unit cell region 20 and the P+ field-limiting ring region 30 is implemented to simplify the process steps.

[0065] To reduce the forward voltage drop and conduction loss of the JBS diode, this embodiment selects an N-epitaxial layer 13 with a specific ion doping concentration and thickness. This embodiment utilizes a unique fabrication process for the metal barrier region 22 to reduce the contact resistance of the JBS diode, thereby further reducing its on-state power consumption. Although silicon carbide JBS diodes have almost no reverse recovery time compared to other silicon devices, the ion implantation process of the P+ region 21 in this embodiment effectively suppresses current transients. Furthermore, a steeper ion doping gradient results in fewer carriers implanted in the P+ region 21, meaning lower turn-off losses. Moreover, the ion implantation process of the P+ region 21 also facilitates the formation of ohmic contact characteristics, thus reducing the forward voltage drop and turn-on losses. In this embodiment, the formation of the metal barrier region 22 does not require a separate photomask; it is the same photomask as the aluminum electrode. The process involves two ion implantations and one annealing step to form the metal barrier region 22 and the electrode, shortening the process cycle and saving fabrication costs. Furthermore, this application embodiment also utilizes the negative charge properties of polyimide to suppress the fixed charge and mobile charge of the oxide layer at the terminal (i.e., at the P+ field limiting ring region 30), thereby stabilizing the voltage withstand properties of the JBS diode and improving the reliability level of the JBS diode.

[0066] Compared with traditional JBS diodes, the embodiments of this application have at least the following advantages: By setting the width ratio between the P+ region 21 and the metal barrier region 22 in the unit cell region 20 to 0.45-0.5, the shielding effect of the metal barrier region 22 is improved, resulting in ultra-low reverse leakage current for the JBS diode; the implementation of unshielded, zero-degree angle high-temperature ion implantation and ultra-high temperature annealing simplifies the process steps while achieving excellent characteristics of high withstand voltage and low forward voltage drop; utilizing the passivation properties of polyimide, it is directly covered on the chip surface, ensuring the original excellent characteristics of the product and Beyond reliability, this application reduces the number of photolithography steps, simplifies process steps, lowers manufacturing costs, and shortens the manufacturing cycle. The embodiments of this application feature a unique method for forming a good ohmic contact between the metal barrier region 22 and the P+ region 21, as well as a method for forming the surface electrode of the JBS diode. This reduces photolithography steps and the use of photomasks, as well as the metal alloying process, saving manufacturing costs and shortening the manufacturing cycle. Furthermore, the JBS diode has a lower forward voltage drop and a higher surge current, thereby reducing the conduction loss of the JBS diode and improving its reliability.

[0067] It should be noted that the various embodiments in this application are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For product-related embodiments, since they are similar to method-related embodiments, the descriptions are relatively simple, and relevant parts can be referred to the descriptions of the method-related embodiments.

[0068] It should also be noted that, in this application, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0069] The above description of the disclosed embodiments enables those skilled in the art to implement or use the content of this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined in this application may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A junction barrier Schottky diode, comprising a substrate, characterized in that, The substrate has a primitive cell region and a P+ field confinement ring region on opposite sides of its surface. A P+ main junction region is also provided on the surface of the substrate between the primitive cell region and the P+ field confinement ring region. The primitive cell region, the P+ main junction region and the P+ field confinement ring region are spaced apart from each other. The primitive cell region includes multiple mutually spaced P+ regions. A metal barrier region is formed between the P+ regions near the P+ main junction region and between any two adjacent P+ regions. The ratio of the width of a single P+ region in a predetermined direction to the width of a single metal barrier region in the predetermined direction is 0.45 to 0.

5. The predetermined direction is the direction from the primitive cell region to the P+ field-limiting ring region. The metal barrier region is also the ohmic contact region between the primitive cell region and the P+ main junction region.

2. The junction barrier Schottky diode as described in claim 1, characterized in that, The P+ field limiting ring region includes multiple P+ field limiting rings spaced apart from each other. The width of the P+ field limiting ring region remains constant in the preset direction. The distance between the P+ main junction region and the P+ field limiting rings near the P+ main junction region, as well as the distance between the multiple P+ field limiting rings, increases along the preset direction.

3. The junction barrier Schottky diode as described in claim 2, characterized in that, The width of the P+ field limiting ring region remains constant at 3.8 μm in the preset direction, and the distance between the P+ main junction region and the P+ field limiting ring near the P+ main junction region, as well as the distance between multiple P+ field limiting rings, increases within the range of 1.2 to 3.2 μm along the preset direction.

4. The junction barrier Schottky diode as described in claim 1, characterized in that, The substrate includes an N+ substrate layer, an N-type buffer layer, and an N-epipolar layer; wherein the N-type buffer layer covers the surface of the N+ substrate layer, and the N-epipolar layer covers the surface of the N-type buffer layer.

5. The junction barrier Schottky diode as described in claim 4, characterized in that, The thickness of the N-type buffer layer is 0.5–1 μm, and the ion doping concentration is 0.9E18–1.1E18.

6. The junction barrier Schottky diode as described in claim 4, characterized in that, The thickness of the N-epitaxial layer is 6–7 μm, and the ion doping concentration is 1E16–2E16.

7. The junction barrier Schottky diode as described in claim 1, characterized in that, The knot depths of the P+ field-limited ring region, the P+ main knot region, and the protocell region are all 1–1.5 μm.

8. The junction barrier Schottky diode as described in claim 1, characterized in that, The metal thickness of the metal barrier region is 9. A method for fabricating a junction barrier Schottky diode as described in claim 1, characterized in that, include: Obtain the substrate; Using photoresist as a masking layer, inactive primitive cell regions, P+ field-confining ring regions, and P+ main junction regions are implanted on the surface of the substrate. The primitive cell regions and the P+ field-confining ring regions are located on opposite sides of the substrate surface, and the P+ main junction region is located between the primitive cell regions and the P+ field-confining ring regions on the substrate surface. The primitive cell regions, the P+ main junction regions, and the P+ field-confining ring regions are spaced apart from each other. Each primitive cell region includes multiple spaced P+ regions. A metal barrier region is formed between each P+ region near the P+ main junction region and between any two adjacent P+ regions. The ratio of the width of a single P+ region in a predetermined direction to the width of a single metal barrier region in the predetermined direction is 0.45 to 0.

5. The predetermined direction is the direction from the primitive cell region to the P+ field-confining ring region. The protocell region, the P+ field-confined ring region, and the P+ main junction region are ion activated by a high-temperature ion activation process under carbon film protection.

10. An application of a junction barrier Schottky diode as described in any one of claims 1-8 in power electronic devices.

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