Semiconductor device

Abstract

A semiconductor device includes: a substrate including a cell region and a peripheral region outside the cell region; a first conductivity type semiconductor layer located on an upper surface of the substrate; a second conductivity type doped well region located within the first conductivity type semiconductor layer; a gate electrode located on the first conductivity type semiconductor layer; a gate insulating layer located between the first conductivity type semiconductor layer and the gate electrode; a source electrode located on the second conductivity type doped well region; and a drain electrode located below the substrate. The source electrode includes a first source electrode on the gate electrode, a second source electrode on the first source electrode, and an interlayer source electrode. The interlayer source electrode includes insulating structures spaced apart in a first direction parallel to the upper surface and conductive lines between the insulating structures, and is disposed between the first source electrode and the second source electrode.

Description

Cross-reference of related applications

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2024-0197476, filed on December 26, 2024, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to semiconductor devices. Background Technology

[0003] In modern society, semiconductor devices are closely related to daily life. Specifically, the importance of power semiconductor devices is increasing in various fields such as transportation (e.g., electric vehicles, railways, trams), renewable energy systems (e.g., solar power, wind power), and mobile devices. Power semiconductor devices can be semiconductor devices used to handle high voltages or high currents and perform functions such as power conversion and control in high-power systems or high-output electronic devices. In some cases, power semiconductor devices can have the ability and durability to handle high power, and they can handle large amounts of current and withstand high voltages. For example, power semiconductor devices can handle voltages from hundreds to thousands of volts and currents from tens to thousands of amperes. Power semiconductor devices can improve the efficiency of electrical energy by minimizing power losses. Furthermore, power semiconductor devices can be stably driven even in environments such as high temperatures.

[0004] These power semiconductor devices can be categorized based on their materials, and examples may include SiC power semiconductor devices and GaN power semiconductor devices. In some examples, SiC or GaN can be used instead of existing silicon wafers (Si wafers) to fabricate power semiconductor devices, compensating for the drawbacks of silicon, which may exhibit instability at high temperatures. SiC power semiconductor devices are heat-resistant, have low power loss, and are suitable for electric vehicles, renewable energy systems, etc. GaN power semiconductor devices may come with higher costs, but they offer speed efficiency and are suitable for high-speed charging of mobile devices. Summary of the Invention

[0005] Generally speaking, in some aspects, this disclosure provides a semiconductor device that can reduce the saturation drain current (Id). sat To prevent short circuits without changing the conduction state, the drain-source resistance (Rds) is used. on Without altering the structure in the active source contact area, such as changing the channel length, and without adding additional resistors outside the circuit (e.g., package or module), it can reduce current concentration at the active source contact and improve voltage overshoot or non-uniformity of the source current to improve current spread by the location of the cell area.

[0006] Typically, in some aspects, this disclosure provides a semiconductor device comprising: a substrate including a cell region and a peripheral region located outside the cell region; a first conductivity type semiconductor layer located on an upper surface of the substrate; a second conductivity type doped well region located within the first conductivity type semiconductor layer; a gate electrode located on the first conductivity type semiconductor layer; a gate insulating layer located between the first conductivity type semiconductor layer and the gate electrode; a source electrode located on the second conductivity type doped well region; and a drain electrode located below a lower surface of the substrate, wherein the source electrode includes a first source electrode located on the gate electrode, a second source electrode located on the first source electrode, and an interlayer source electrode, the interlayer source electrode including an insulating structure spaced apart in a first direction parallel to the upper surface of the substrate and a conductive line located between the insulating structures, and the interlayer source electrode being disposed between the first source electrode and the second source electrode.

[0007] Generally, in some aspects, this disclosure provides a semiconductor device comprising: a substrate including a cell region and a peripheral region located outside the cell region; a first conductivity type semiconductor layer on an upper surface of the substrate; a second conductivity type doped well region within the first conductivity type semiconductor layer; a gate electrode on the first conductivity type semiconductor layer; a gate insulating layer between the first conductivity type semiconductor layer and the gate electrode; a source electrode on the second conductivity type doped well region; and a drain electrode below a lower surface of the substrate, wherein the source electrode includes a first source electrode on the gate electrode, a second source electrode on the first source electrode, and an interlayer source electrode, the interlayer source electrode including insulating structures spaced apart in a first direction parallel to the upper surface of the substrate and conductive lines between the insulating structures, and disposed between the first source electrode and the second source electrode, the source electrode including multiple layers of second source electrodes and multiple layers of interlayer source electrodes, and the second source electrodes and interlayer source electrodes being alternately stacked in a third direction.

[0008] Typically, in some aspects, this disclosure provides a semiconductor device comprising: a substrate including a cell region and a peripheral region located outside the cell region; a first conductivity type semiconductor layer on an upper surface of the substrate; a second conductivity type doped well region within the first conductivity type semiconductor layer; a gate electrode on the first conductivity type semiconductor layer; a gate insulating layer between the first conductivity type semiconductor layer and the gate electrode; a source electrode on the second conductivity type doped well region; and a drain electrode below a lower surface of the substrate, wherein the source electrode includes a first source electrode on the gate electrode, a first source electrode disposed on the first source electrode and including a first source electrode parallel to the upper surface of the substrate. The first interlayer source electrode comprises an insulating structure spaced apart in a first direction and conductive lines disposed between the insulating structures, and a first second source electrode on the first interlayer source electrode; a second interlayer source electrode disposed on the first second source electrode and comprising an insulating structure spaced apart in a first direction and conductive lines disposed between the insulating structures, and a second second source electrode on the second interlayer source electrode, wherein the center point of the insulating structure of the first interlayer source electrode along the first direction and parallel to the upper surface of the substrate and different from the first direction does not overlap with the center point of the insulating structure of the second interlayer source electrode along the first direction and the second direction in a third direction, and the third direction is perpendicular to the upper surface of the substrate.

[0009] The semiconductor device according to the embodiment can reduce the saturation drain current (Id) sat Without changing the drain / source on-resistance (Rds) on And without changing the structure in the active source contact area (such as changing the channel length), and without adding additional resistance outside the circuit (e.g., package or module) to prevent short circuits.

[0010] In addition, current spread can be improved by reducing the current concentration at active source contacts and improving the voltage overshoot or non-uniformity of source current at cell locations. Attached Figure Description

[0011] Figure 1 This is a plan view showing a semiconductor device.

[0012] Figure 2 It is along Figure 1 A cross-sectional view taken from line A-A'.

[0013] Figure 3 It is a circuit diagram of a semiconductor device.

[0014] Figure 4 It is a cross-sectional view showing a semiconductor device, and it corresponds to... Figure 2 The illustration.

[0015] Figure 5 This is a plan view showing a semiconductor device.

[0016] Figure 6 This is a plan view showing a semiconductor device.

[0017] Figure 7 This is a plan view showing a semiconductor device.

[0018] Figure 8 It is along Figure 7 A cross-sectional view taken from line A-A'.

[0019] Figure 9 It is along Figure 7 The cross-sectional view taken by line B-B'.

[0020] Figure 10 This is a plan view showing a semiconductor device.

[0021] Figure 11 It is along Figure 10 A cross-sectional view taken from line A-A'.

[0022] Figure 12 This is a plan view showing a semiconductor device.

[0023] Figure 13 It is along Figure 12 A cross-sectional view taken from line A-A'.

[0024] Figure 14 This is a plan view showing the first interlayer source electrode of the semiconductor device.

[0025] Figure 15 It is shown Figure 14 A plan view of the second interlayer source electrode of the semiconductor device.

[0026] Figure 16 It is shown Figure 14 A plan view of the third interlayer source electrode of the semiconductor device.

[0027] Figure 17 It is along Figure 16 A cross-sectional view taken from line A-A'.

[0028] Figure 18 This is a plan view showing the first interlayer source electrode of the semiconductor device.

[0029] Figure 19 It is shown Figure 18 A plan view of the second interlayer source electrode of the semiconductor device.

[0030] Figure 20 It is along Figure 19 A cross-sectional view taken from line A-A'.

[0031] Figure 21 It is along Figure 19The cross-sectional view taken by line B-B'.

[0032] Figure 22 This is a plan view showing the first interlayer source electrode of the semiconductor device.

[0033] Figure 23 It is shown Figure 22 A plan view of the second interlayer source electrode of the semiconductor device.

[0034] Figure 24 It is along Figure 23 A cross-sectional view taken from line A-A'.

[0035] Figure 25 It is along Figure 23 The cross-sectional view taken by line B-B'.

[0036] Figure 26 This is a plan view showing the first interlayer source electrode of the semiconductor device.

[0037] Figure 27 It is shown Figure 26 A plan view of the second interlayer source electrode of the semiconductor device.

[0038] Figure 28 It is along Figure 27 A cross-sectional view taken from line A-A'.

[0039] Figure 29 It is along Figure 27 The cross-sectional view taken by line B-B'.

[0040] Figure 30 This is a plan view showing the first interlayer source electrode of the semiconductor device.

[0041] Figure 31 yes Figure 30 A plan view of the second interlayer source electrode of the semiconductor device.

[0042] Figure 32 It is along Figure 31 A cross-sectional view taken from line A-A'.

[0043] Figure 33 It is along Figure 31 The cross-sectional view taken by line B-B'. Detailed Implementation

[0044] In the following description, various embodiments of this disclosure will be described in detail with reference to the accompanying drawings, enabling those skilled in the art to readily implement this disclosure. This disclosure can be implemented in many different forms and is not limited to the embodiments set forth herein.

[0045] The accompanying drawings and description should be considered illustrative rather than restrictive. Throughout the description, the same reference numerals denote the same elements.

[0046] For better understanding and ease of description, the dimensions and thicknesses of each component shown in the accompanying drawings are indicated randomly, and this disclosure is not necessarily limited to those shown. In the drawings, the thicknesses of layers, regions, etc., are exaggerated for clarity. Furthermore, in the drawings, the thicknesses of some layers and regions are exaggerated for better understanding and ease of description.

[0047] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it may be directly on the other element, or there may be intermediate elements present. Conversely, when an element is referred to as being "directly on" another element, there are no intermediate elements present. The terms "on" or "above" refer to being positioned on or below a portion of an object, and do not necessarily refer to being positioned on the upper side of the object portion based on the direction of gravity.

[0048] Furthermore, unless explicitly stated otherwise, the words “comprising” and variations such as “including” or “containing” will be understood to imply inclusion of the stated element but not exclusion of any other element.

[0049] Furthermore, in this specification, the expression "in a plane" means the target portion as viewed from above, and the expression "in a cross section" means the cross section formed by vertically cutting off the target portion as viewed from the side.

[0050] Furthermore, throughout the specification, two directions parallel to and perpendicular to the upper surface of the substrate are defined as a first direction D1 and a second direction D2, respectively, and the direction perpendicular to the upper surface of the substrate is described as a third direction D3. For example, the first direction D1 and the second direction D2 may be the length direction and the width direction, respectively, and the third direction D3 may be the thickness direction.

[0051] Figure 1 This is a plan view illustrating a semiconductor device according to some embodiments. Figure 2 It is along Figure 1 A cross-sectional view taken from line A-A'. Figure 3 It is a circuit diagram of a semiconductor device according to some implementation methods.

[0052] To ensure clarity and simplify the explanation, Figure 1The main features shown are: the first conductive line 1752D1 and the second conductive line 1752D2 of the interlayer source electrode 175, the insulating structure 1751, the gate pad 155 and the gate wiring 156, and the substrate 110, the first conductivity type semiconductor layer 131, the second conductivity type doped well region 133, the gate electrode 150, the gate insulating layer 151, the first source electrode 171 and the second source electrode 172 of the source electrode 170, and the drain electrode 180.

[0053] Reference Figures 1 to 3 The semiconductor device includes a substrate 110, a first conductivity type semiconductor layer 131 on the upper surface of the substrate 110, a second conductivity type doped well region 133 within the first conductivity type semiconductor layer 131, a gate electrode 150 on the first conductivity type semiconductor layer 131 and the second conductivity type doped well region 133, a gate insulating layer 151 between the first conductivity type semiconductor layer 131 and the gate electrode 150, a source electrode 170 on the second conductivity type doped well region 133, and a drain electrode 180 under the lower surface of the substrate 110.

[0054] The substrate 110 may include a cell region (CELL) and a peripheral region (PERI) surrounding the cell region (CELL).

[0055] The first source electrode 171 of the source electrode 170, described later, may be disposed on the cell region CELL. The first source electrode 171 may cover the cell region CELL. In other words, the cell region CELL may completely overlap with the first source electrode 171 in the third direction D3.

[0056] A gate pad 155 may be disposed on one side of the first source electrode 171 in a first direction D1 or a second direction D2. For example, the gate pad 155 may be disposed in the peripheral region PERI. Furthermore, a gate wiring 156 extending from the gate pad 155 may be disposed in the peripheral region PERI. The gate wiring 156 may extend to cover the peripheral region PERI. In other words, the gate wiring 156 may surround the cell region CELL.

[0057] As described below, the first source electrode 171 may extend downward along the third direction D3 to form an active source contact with the second conductivity type doped well region 133. The gate pad 155 and the gate wiring 156 are in electrical contact with the gate electrode 150.

[0058] Substrate 110 may be a semiconductor substrate including SiC. For example, substrate 110 may be made of 4H SiC substrate. In some cases, substrate 110 may be made of 3C SiC substrate, 6H SiC substrate, etc. Substrate 110 may be doped with a first conductivity type impurity. For example, the first conductivity type impurity may be an n-type impurity. In other words, substrate 110 may be doped with an n-type impurity. Substrate 110 may be doped with an n-type impurity at a high concentration. The resistivity of substrate 110 may be greater than or equal to about 0.005 Ω·cm and less than or equal to about 0.035 Ω·cm. The thickness of substrate 110 may be greater than or equal to about 100 μm and less than or equal to about 700 μm. The material, doping type, doping concentration, resistivity, thickness, etc. of substrate 110 are not limited thereto and may be varied in various ways. Substrate 110 may have a first surface and a second surface facing each other. The first surface of substrate 110 may be the upper surface of substrate 110, and the second surface of substrate 110 may be the lower surface of substrate 110.

[0059] A first conductivity type semiconductor layer 131 may be disposed on a first surface (i.e., the upper surface) of the substrate 110. The lower surface of the first conductivity type semiconductor layer 131 may contact the upper surface of the substrate 110. However, it is not limited thereto, and another layer may be disposed between the substrate 110 and the first conductivity type semiconductor layer 131. The first conductivity type semiconductor layer 131 may be an epitaxial layer formed from the substrate 110 using an epitaxial growth method. The first conductivity type semiconductor layer 131 may include SiC. For example, the first conductivity type semiconductor layer 131 may include 4H SiC. The first conductivity type semiconductor layer 131 may be doped to n-type. The first conductivity type semiconductor layer 131 may be doped to n-type at a low concentration. The doping concentration of the first conductivity type semiconductor layer 131 may be lower than the doping concentration of the substrate 110. The doping concentration of the first conductivity type semiconductor layer 131 may be greater than or equal to about 1 × 10⁻⁶. 15 cm -3 And less than or equal to approximately 1 × 10 17 cm -3 The thickness of the first conductivity type semiconductor layer 131 may be greater than or equal to about 1 μm and less than or equal to about 13 μm. The material, doping type, doping concentration, etc. of the first conductivity type semiconductor layer 131 are not limited thereto and can be changed in various ways.

[0060] A second conductivity type doped well region 133 may be disposed within a first conductivity type semiconductor layer 131. The second conductivity type doped well region 133 may be disposed on the first conductivity type semiconductor layer 131. The second conductivity type doped well region 133 may contact the lower surface of a second conductivity type doped layer 135, which will be described later. The second conductivity type doped well region 133 may surround the lower and side surfaces of a first conductivity type doped layer 137, which will be described later.

[0061] At least a portion of the upper surface of the second conductivity type doped well region 133 may overlap with at least a portion of the gate electrode 150 and at least a portion of the gate insulating layer 151 on the third direction D3.

[0062] The second conductivity type doped well region 133 may extend from the upper surface of the first conductivity type semiconductor layer 131 toward the lower surface of the first conductivity type semiconductor layer 131. That is, the second conductivity type doped well region 133 may extend from the upper surface of the first conductivity type semiconductor layer 131 in a third direction D3. The second conductivity type doped well region 133 may be formed in at least a portion of the first conductivity type semiconductor layer 131 by ion implantation.

[0063] The second conductivity type doped well region 133 may include SiC. For example, the second conductivity type doped well region 133 may include 4HSiC. The second conductivity type doped well region 133 may be doped with p-type. The second conductivity type doped well region 133 may be doped with p-type at a low concentration. The doping concentration of the second conductivity type doped well region 133 may be greater than or equal to about 1 × 10⁻⁶. 17 cm -3 And less than or equal to approximately 1 × 10 19 cm -3 The material, doping type, doping concentration, etc. of the second conductivity type doped well region 133 are not limited to this, and can be changed in various ways.

[0064] The semiconductor device may further include a second conductivity type doped layer 135 and a first conductivity type doped layer 137 on a first conductivity type semiconductor layer 131.

[0065] A second conductivity type doped layer 135 may be disposed within a second conductivity type doped well region 133. The second conductivity type doped layer 135 may be disposed on a first conductivity type semiconductor layer 131 and may have an upper surface that is in direct contact with the lower surface of the silicide layer 190 connected to the source electrode 170 described later.

[0066] At least a portion of the upper surface of the second conductivity type doped layer 135 may contact the lower surface of the silicide layer 190, which will be described later, but is not limited thereto. For example, at least a portion of the upper surface of the second conductivity type doped layer 135 may contact the lower surface of the source electrode 170. In this case, the second conductivity type doped layer 135 may have a width wider than the width of the source electrode 170.

[0067] The second conductivity type doped layer 135 may extend from the upper surface of the first conductivity type semiconductor layer 131 along a third direction D3. In this case, the thickness of the second conductivity type doped layer 135 along the third direction D3 may be less than the thickness of the second conductivity type doped well region 133 along the third direction D3. Furthermore, the second conductivity type doped layer 135 may have a narrower width than the second conductivity type doped well region 133. That is, the second conductivity type doped layer 135 may be buried within the second conductivity type doped well region 133. The second conductivity type doped layer 135 may be formed in at least a portion of the second conductivity type doped well region 133 by ion implantation.

[0068] The second conductivity type doped layer 135 may include SiC. For example, the second conductivity type doped layer 135 may include 4HSiC. The second conductivity type doped layer 135 may be p-type doped. The second conductivity type doped layer 135 may form an ohmic contact with the source electrode 170. For this purpose, the second conductivity type doped layer 135 may be highly doped to be p-type. In some embodiments, the doping concentration of the second conductivity type doped layer 135 may be higher than the doping concentration of the second conductivity type doped well region 133. The doping concentration of the second conductivity type doped layer 135 may be greater than or equal to about 1 × 10⁻⁶. 18 cm -3 And less than or equal to approximately 5 × 10 20 cm -3 The material, doping type, and doping concentration of the second conductivity type doped layer 135 are not limited to this, and can be changed in various ways.

[0069] A first conductivity type doped layer 137 may be disposed within a second conductivity type doped well region 133. The first conductivity type doped layer 137 may be disposed on a first conductivity type semiconductor layer 131 and may surround both sides of the second conductivity type doped layer 135. The upper surface of the first conductivity type doped layer 137 may overlap with at least a portion of the gate electrode 150 and at least a portion of the gate insulating layer 151 in the third direction D3, as will be described below. Furthermore, the upper surface of the first conductivity type doped layer 137 may overlap with at least a portion of the source electrode 170, described later, in the third direction D3, but is not limited thereto. The upper surface of the first conductivity type doped layer 137 may directly contact the gate insulating layer 151, described later.

[0070] A first conductivity type doped layer 137 may extend from the upper surface of the first conductivity type semiconductor layer 131 along a third direction D3. The first conductivity type doped layer 137 may be buried within a second conductivity type doped well region 133. In this case, the thickness of the first conductivity type doped layer 137 along the third direction D3 may be less than the thickness of the second conductivity type doped well region 133 along the third direction D3.

[0071] The first conductivity type doped layer 137 may be a doped region formed within the first conductivity type semiconductor layer 131 using an ion implantation process. The first conductivity type doped layer 137 may include SiC. For example, the first conductivity type doped layer 137 may include 4H SiC. The first conductivity type doped layer 137 may be doped with n-type impurities. The first conductivity type doped layer 137 may be doped to n-type at a high concentration. The doping concentration of the first conductivity type doped layer 137 may be greater than or equal to approximately 1 × 10⁻⁶. 18 cm -3 And less than or equal to approximately 5 × 10 20 cm -3 The material, doping type, doping concentration, etc. of the first conductivity type doped layer 137 are not limited to this, and can be changed in various ways.

[0072] A gate electrode 150 may be disposed on a first conductivity type semiconductor layer 131. The gate electrode 150 may be spaced apart from the first conductivity type semiconductor layer 131. For example, the gate electrode 150 may be spaced apart from the first conductivity type semiconductor layer 131 in a vertical direction (e.g., in the third direction D3) by a gate insulating layer 151. In some embodiments, the semiconductor device may have a planar gate structure. That is, in the semiconductor device, the gate electrode 150 has a plate shape having an upper surface and a lower surface, and the lower surface of the gate electrode 150 may be disposed at a level higher than the uppermost surface of the first conductivity type semiconductor layer 131. However, this is not limited to the above description, and according to some embodiments, the semiconductor device may have a trench-shaped gate structure. For example, in the semiconductor device, a trench of a predetermined depth is formed in the first conductivity type semiconductor layer 131, and the gate electrode 150 may be disposed within the trench, spaced apart from the first conductivity type semiconductor layer 131 in the third direction D3. Furthermore, the gate electrode 150 may be configured to be spaced apart from the first conductivity type semiconductor layer 131 in the first direction D1 and / or the second direction D2. The gate electrode 150 may overlap with the second conductivity type doped well region 133 and the first conductivity type doped layer 137 in the third direction D3.

[0073] The gate electrode 150 may include a conductive material. For example, the gate electrode 150 may include polycrystalline silicon doped with impurities. As another example, the gate electrode 150 may include a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, a conductive metal oxynitride, or a combination thereof. The gate electrode 150 may be made of a single layer or multiple layers.

[0074] A gate insulating layer 151 may be disposed between the first conductivity type semiconductor layer 131 and the gate electrode 150. That is, the gate insulating layer 151 may be disposed below the gate electrode 150 on a third-direction D3 and may cover the lower surface of the gate electrode 150. The gate electrode 150 may be insulated from the first conductivity type semiconductor layer 131 by the gate insulating layer 151. The thickness of the gate insulating layer 151 may be substantially constant.

[0075] The gate insulating layer 151 may overlap with the second conductivity type doped well region 133 and the first conductivity type doped layer 137 on the third direction D3. The lower surface of the gate insulating layer 151 may be in direct contact with the second conductivity type doped well region 133 and the first conductivity type doped layer 137, but is not limited thereto.

[0076] The gate insulating layer 151 may include an insulating material. For example, the gate insulating layer 151 may include SiO2. However, it is not limited to this, and the material of the gate insulating layer 151 may be varied in various ways. As another example, the gate insulating layer 151 may include SiN, SiON, SiC, SiCN, or a combination thereof. The gate insulating layer 151 may be formed as a single layer or multiple layers.

[0077] A first interlayer insulating layer 140 may be disposed on a first conductivity type semiconductor layer 131. For example, the first interlayer insulating layer 140 may be disposed on a gate electrode 150. In other words, the first interlayer insulating layer 140 may cover the upper surface and side surface of the gate electrode 150. The first interlayer insulating layer 140 may cover the side surface of the gate insulating layer 151. The first interlayer insulating layer 140 may also be disposed on a first conductivity type doped layer 137. The first interlayer insulating layer 140 may have a lower surface that contacts at least a portion of the upper surface of the first conductivity type doped layer 137. The gate electrode 150 may be insulated from the source electrode 170 through the first interlayer insulating layer 140.

[0078] The first interlayer insulating layer 140 may include an insulating material. For example, the first interlayer insulating layer 140 may include the same insulating material as the gate insulating layer 151. For example, the first interlayer insulating layer 140 may include SiO2. However, it is not limited to this, and the first interlayer insulating layer 140 may include various types of insulating materials to insulate the gate electrode 150 from the source electrode 170. For example, the first interlayer insulating layer 140 may include SiOP, SiN, SiON, or combinations thereof. The first interlayer insulating layer 140 may be formed as a single layer or multiple layers. When the first interlayer insulating layer 140 is made of the same material as the gate insulating layer 151, the boundary between the first interlayer insulating layer 140 and the gate insulating layer 151 may not be clearly distinguishable at the contact portion.

[0079] A source electrode 170 may be disposed on a second conductivity type doped well region 133. A second conductivity type doped layer 135 and a first conductivity type doped layer 137 may be disposed between the source electrode 170 and the second conductivity type doped well region 133. The source electrode 170 may be electrically connected to the second conductivity type doped well region 133 through the second conductivity type doped layer 135. Current or voltage may be supplied to the cell region CELL through the source electrode 170.

[0080] The source electrode 170 may include a first source electrode 171 and a second source electrode 172.

[0081] The first source electrode 171 may be disposed on the second conductivity type doped well region 133. The first source electrode 171 may be disposed on both sides of the gate electrode 150. However, it is not limited to this, and the first source electrode 171 may be disposed only on one side of the gate electrode 150. The first source electrode 171 may be disposed on the gate electrode 150.

[0082] The first interlayer insulating layer 140 may be disposed between the first source electrode 171 and the gate electrode 150. The first source electrode 171 may be separated from the gate electrode 150 through the first interlayer insulating layer 140. The first source electrode 171 may contact the side surface and the top surface of the first interlayer insulating layer 140.

[0083] For example, the first source electrode 171 may have a first portion 171P1 on the gate electrode 150 and a second portion 171P2 between the gate electrode 150.

[0084] The first portion 171P1 of the first source electrode 171 may be disposed on the cell region CELL. The first portion 171P1 of the first source electrode 171 may cover the cell region CELL.

[0085] The first portion 171P1 of the first source electrode 171 may be a plane (hereinafter referred to as the "plane") extending in a first direction D1 and a second direction D2 perpendicular to the third direction D3, for example, on a plane extending along the first direction D1 and the second direction D2. Figure 1 The area of ​​the cell region CELL in the first source electrode 171 can be substantially the same as the area of ​​the first portion 171P1 of the first source electrode 171. In other words, the first portion 171P1 of the first source electrode 171 can completely overlap with the cell region CELL in the third direction D3. In some embodiments, the first portion 171P1 of the first source electrode 171 extends in a plane along the first direction D1 and the second direction D2 (e.g., Figure 1 The first source electrode 171 may have a larger area than the cell region CELL. In other words, the first portion 171P1 of the first source electrode 171 may only partially overlap with the cell region CELL in the third direction D3, but the cell region CELL may completely overlap with the first portion 171P1 of the first source electrode 171 in the third direction D3.

[0086] The second portion 171P2 of the first source electrode 171 may be disposed on either side of the gate electrode 150 in the first direction D1 or the second direction D2. The second portion 171P2 of the first source electrode 171 may be surrounded by the gate electrode 150, with the first interlayer insulating layer 140 inserted therebetween. However, it is not limited thereto, and the second portion 171P2 of the first source electrode 171 may be disposed on only one side of the gate electrode 150.

[0087] The second portion 171P2 of the first source electrode 171 may be a portion extending downward from the first portion 171P1 of the first source electrode 171 toward the second conductivity type doped well region 133 in the third direction D3. The second portion 171P2 of the first source electrode 171 may extend downward along the third direction D3 and form an active source contact with the second conductivity type doped well region 133. The second portion 171P2 of the first source electrode 171 may overlap with the second conductivity type doped layer 135 and the first conductivity type doped layer 137 in the third direction D3. However, it is not limited to this, and the second portion 171P2 of the first source electrode 171 may not overlap with the first conductivity type doped layer 137 in the third direction D3. In this case, the upper surface of the first conductivity type doped layer 137 may be covered by the gate insulating layer 151.

[0088] For example, the first source electrode 171 may include a conductive material. For example, the first source electrode 171 may include a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, or a conductive metal oxide nitride. For example, the first source electrode 171 may include titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), titanium titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (T... aCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel-platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), or combinations thereof, but not limited to these. The first source electrode 171 may be formed of a single layer or multiple layers.

[0089] The second source electrode 172 can be disposed on the first source electrode 171.

[0090] The second source electrode 172 is electrically connected to the first source electrode 171, and the externally supplied source voltage can be applied to the first source electrode 171 through the second source electrode 172.

[0091] The second source electrode 172 can be disposed on the cell region CELL. The second source electrode 172 can cover the cell region CELL.

[0092] For example, in a plane extending along the first direction D1 and the second direction D2 (e.g., Figure 1 On the cell region, the second source electrode 172 may have substantially the same area as the cell region. In other words, the second source electrode 172 may completely overlap with the cell region on the third direction D3. In some embodiments, on a plane extending along the first direction D1 and the second direction D2 (e.g., Figure 1 On the cell region D3, the second source electrode 172 may have an area larger than that of the cell region CELL. In other words, the second source electrode 172 may only partially overlap with the cell region CELL in the third direction D3, but the cell region CELL may completely overlap with the second source electrode 172 in the third direction D3. Alternatively, in a plane extending along the first direction D1 and the second direction D2 (e.g., Figure 1 On the cell region CELL, the second source electrode 172 may have a smaller area than the cell region CELL. In other words, the second source electrode 172 may completely overlap with the cell region CELL in the third direction D3, but the cell region CELL may only partially overlap with the second source electrode 172 in the third direction D3.

[0093] Furthermore, in the plane extending along the first direction D1 and the second direction D2 (e.g., Figure 1 On the first source electrode 171, the second source electrode 172 may have substantially the same area as the first portion 171P1 of the first source electrode 171. In other words, the second source electrode 172 may completely overlap with the first portion 171P1 of the first source electrode 171 in the third direction D3. In some embodiments, on the plane extending along the first direction D1 and the second direction D2 (e.g., Figure 1 On the first source electrode 171, the second source electrode 172 may have a larger area than the first portion 171P1 of the first source electrode 171. In other words, the second source electrode 172 may only partially overlap the first portion 171P1 of the first source electrode 171 in the third direction D3, but the first portion 171P1 of the first source electrode 171 may completely overlap the second source electrode 172 in the third direction D3. Alternatively, in a plane extending along the first direction D1 and the second direction D2 (e.g., Figure 1On the first source electrode 171, the second source electrode 172 may have a smaller area than the first portion 171P1 of the first source electrode 171. In other words, the second source electrode 172 may completely overlap with the first portion 171P1 of the first source electrode 171 in the third direction D3, but the first portion 171P1 of the first source electrode 171 may only partially overlap with the second source electrode 172 in the third direction D3.

[0094] For example, the second source electrode 172 may include a conductive material. For example, the second source electrode 172 may include a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, or a conductive metal oxide nitride. For example, the second source electrode 172 may include titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), titanium titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (T... aCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel-platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), or combinations thereof, but not limited to these. The second source electrode 172 may be formed of a single layer or multiple layers.

[0095] For example, the thickness of the second source electrode 172 can be greater than or equal to about 10 nm, for example, greater than or equal to about 20 nm, greater than or equal to about 30 nm, greater than or equal to about 40 nm, greater than or equal to about 50 nm, greater than or equal to about 60 nm, greater than or equal to about 70 nm, greater than or equal to about 80 nm, greater than or equal to about 90 nm, greater than or equal to about 100 nm, greater than or equal to about 200 nm, greater than or equal to about 300 nm, greater than or equal to about 400 nm, greater than or equal to about 500 nm, greater than or equal to about 600 nm, greater than or equal to about 700 nm, greater than or equal to about 800 nm, greater than or equal to about 900 nm, greater than or equal to about 1 μm, greater than or equal to about 2 μm, greater than or equal to about 3 μm, greater than or equal to about 4 μm, greater than or equal to about 5 μm, greater than or equal to about 6 μm, greater than or equal to about 7 μm, greater than or equal to about 8 μm, greater than or equal to about 9 ...9 μm, greater than or equal to about 1 μm, greater than or equal to about 9 μm, greater than or equal to about 1 μm, greater than or equal to about 1 μm, greater than or equal to about 1 μm The thickness of the second source electrode 172 can be less than or equal to about 10 μm, for example, less than or equal to about 9 μm, less than or equal to about 8 μm, less than or equal to about 7 μm, less than or equal to about 6 μm, less than or equal to about 5 μm, less than or equal to about 4 μm, less than or equal to about 3 μm, less than or equal to about 2 μm, less than or equal to about 1 μm, less than or equal to about 900 nm, less than or equal to about 800 nm, less than or equal to about 700 nm, less than or equal to about 600 nm, less than or equal to about 500 nm, less than or equal to about 400 nm, less than or equal to about 300 nm, less than or equal to about 200 nm, less than or equal to about 100 nm, less than or equal to about 90 nm, less than or equal to about 80 nm, less than or equal to about 70 nm, less than or equal to about 60 nm, less than or equal to about 50 nm, less than or equal to about 40 nm, less than or equal to about 30 nm, or less than or equal to about 20 nm. nm, and the thickness of the second source electrode 172 can be from about 10 nm to about 10 μm. Here, in the cross-section cut along the first direction D1 and the third direction D3 perpendicular to the second direction D2 (e.g., Figure 2 In the process, the thickness of the second source electrode 172 can be the shortest distance along the third direction D3 from the lower surface to the upper surface of the second source electrode 172.

[0096] The source electrode 170 may also include an interlayer source electrode 175 between the first source electrode 171 and the second source electrode 172. For example, the first source electrode 171, the interlayer source electrode 175, and the second source electrode 172 may be sequentially stacked on a third-direction D3.

[0097] The first source electrode 171 can be electrically connected to the second source electrode 172 via the interlayer source electrode 175. In other words, the first source electrode 171 and the second source electrode 172 are not in direct contact with each other and can be spaced apart from each other on the third direction D3, with the interlayer source electrode 175 located between the first source electrode 171 and the second source electrode 172.

[0098] Interlayer source electrode 175 can be disposed on cell region CELL. Interlayer source electrode 175 can cover cell region CELL.

[0099] For example, in a plane extending along the first direction D1 and the second direction D2 (e.g., Figure 1 On the cell region 175, the interlayer source electrode 175 may have substantially the same area as the cell region 171, the first portion 171P1 of the first source electrode 171, or the second source electrode 172. In other words, the interlayer source electrode 175 may completely overlap with the cell region 171, the first portion 171P1 of the first source electrode 171, or the second source electrode 172 in the third direction D3. In some embodiments, in a plane extending along the first direction D1 and the second direction D2 (e.g., Figure 1 On the cell region 175, the interlayer source electrode 175 may have an area larger than that of the cell region 171, the first portion 171P1 of the first source electrode 171, or the second source electrode 172. In other words, the interlayer source electrode 175 may only partially overlap with the cell region 171, the first portion 171P1 of the first source electrode 171, or the second source electrode 172 in the third direction D3, but the cell region 171, the first portion 171P1 of the first source electrode 171, or the second source electrode 172 may completely overlap with the interlayer source electrode 175 in the third direction D3. Alternatively, in a plane extending along the first direction D1 and the second direction D2 (e.g., Figure 1 On the cell region 175, the area of ​​the interlayer source electrode 175 may be smaller than the area of ​​the cell region 171, the first portion 171P1 of the first source electrode 171, or the second source electrode 172. In other words, the interlayer source electrode 175 may completely overlap with the cell region 171, the first portion 171P1 of the first source electrode 171, or the second source electrode 172 in the third direction D3, but the cell region 171, the first portion 171P1 of the first source electrode 171, or the second source electrode 172 may only partially overlap with the interlayer source electrode 175 in the third direction D3.

[0100] For example, the thickness of the interlayer source electrode 175 can be greater than or equal to about 10 nm, for example, greater than or equal to about 20 nm, greater than or equal to about 30 nm, greater than or equal to about 40 nm, greater than or equal to about 50 nm, greater than or equal to about 60 nm, greater than or equal to about 70 nm, greater than or equal to about 80 nm, greater than or equal to about 90 nm, greater than or equal to about 100 nm, greater than or equal to about 200 nm, greater than or equal to about 300 nm, greater than or equal to about 400 nm, greater than or equal to about 500 nm, greater than or equal to about 600 nm, greater than or equal to about 700 nm, greater than or equal to about 800 nm, greater than or equal to about 900 nm, greater than or equal to about 1 μm, greater than or equal to about 2 μm, greater than or equal to about 3 μm, greater than or equal to about 4 μm, greater than or equal to about 5 μm, greater than or equal to about 6 μm, greater than or equal to about 7 μm, greater than or equal to about 8 μm, or greater than or equal to about 9 μm. μm, and the thickness of the interlayer source electrode 175 can be less than or equal to about 10 μm, for example, less than or equal to about 9 μm, less than or equal to about 8 μm, less than or equal to about 7 μm, less than or equal to about 6 μm, less than or equal to about 5 μm, less than or equal to about 4 μm, less than or equal to about 3 μm, less than or equal to about 2 μm, less than or equal to about 1 μm, less than or equal to about 900 nm, less than or equal to about 800 nm, less than or equal to about 700 nm, less than or equal to about 600 nm, less than or equal to about 500 nm, less than or equal to about 400 nm, less than or equal to about 300 nm, less than or equal to about 200 nm, less than or equal to about 100 nm, less than or equal to about 90 nm, less than or equal to about 80 nm, less than or equal to about 70 nm, less than or equal to about 60 nm, less than or equal to about 50 nm, less than or equal to about 40 nm, less than or equal to about 30 nm, or less than or equal to about 200 nm. nm, and the thickness of the interlayer source electrode 175 can be from about 10 nm to about 10 μm. Here, in a cross-section cut along a first direction D1 perpendicular to the second direction D2 and a third direction D3 (e.g., Figure 2 In the process, the thickness of the interlayer source electrode 175 can be the shortest distance along the third direction D3 from the lower surface to the upper surface of the second source electrode 172.

[0101] The interlayer source electrode 175 may include an insulating structure 1751 and a conductive line 1752.

[0102] An insulating structure 1751 may be disposed on the first source electrode 171. The insulating structure 1751 may contact the upper surface of the first source electrode 171. In addition, the insulating structure 1751 may contact the side surface of the conductive wire 1752.

[0103] The insulating structures 1751 may be spaced apart from each other in the first direction D1. Alternatively, the insulating structures 1751 may be spaced apart from each other in the second direction D2. Alternatively, the insulating structures 1751 may be spaced apart from each other in the first direction D1 and the second direction D2. For example, the insulating structures 1751 may be arranged in a matrix on a plane along the first direction D1 and the second direction D2 (e.g., Figure 1 ).

[0104] Insulating structure 1751 may be on a plane (e.g., Figure 1 The cell regions are densely arranged from one end to the other in the first direction D1 and the second direction D2 at set intervals. In other words, in the plane of the interlayer source electrode 175 (e.g., Figure 1 On the same surface, the same number of insulating structures 1751 can be disposed at any location within the same area. For example, the length of the insulating structure 1751 along the first direction D1 or the second direction D2 can be greater than or substantially equal to the separation distance of the insulating structure 1751 along the first direction D1 or the second direction D2.

[0105] For example, insulating structures 1751 may be disposed at locations where they overlap with gate electrodes 150 along a third direction D3, and all gate electrodes 150 may be configured such that they overlap with at least one insulating structure 1751 along the third direction D3. Alternatively, insulating structures 1751 may be disposed at locations where they overlap with second portions 171P2 of the first source electrodes 171 along the third direction D3, and all second portions 171P2 of the first source electrodes 171 may be configured such that they overlap with at least one insulating structure 1751 along the third direction D3.

[0106] An insulating structure 1751 may be disposed on a third direction D3 between the first source electrode 171 and the second source electrode 172. For example, the insulating structure 1751 of the first source electrode 171, the interlayer source electrode 175, and the second source electrode 172 may be stacked sequentially on a third direction D3. The first source electrode 171 and the second source electrode 172 are not in direct contact with each other and may be spaced apart from each other on a third direction D3 by the insulating structure 1751 of the interlayer source electrode 175, and may be electrically connected by the conductive lines 1752 of the interlayer source electrode 175 as described below.

[0107] Insulating structure 1751 is on a plane (e.g., Figure 1 The insulating structure 1751 can have various shapes, such as circles, ellipses, or polygons. For example, a polygon can be a rectangle, square, rhombus, or hexagon. Alternatively, the insulating structure 1751 can be planar (e.g., Figure 1 The line has a line extending along a first direction D1 and spaced along a second direction D2, or a line extending along a second direction D2 and spaced along a first direction D1.

[0108] The insulating structure 1751 may include an insulating material. For example, the insulating structure 1751 may include SiO2. However, it is not limited to this, and the insulating structure 1751 may include various types of insulating materials for insulating the first source electrode 171 and the second source electrode 172. For example, the insulating structure 1751 may include SiOP, SiN, SiON, or combinations thereof. The insulating structure 1751 may be made of a single layer or multiple layers.

[0109] Conductive wires 1752 are disposed between insulating structures 1751.

[0110] Conductive wire 1752 may be disposed on the first source electrode 171. Conductive wire 1752 may cover the upper surface of the first source electrode 171. In addition, conductive wire 1752 may cover the side surface of the insulating structure 1751.

[0111] The conductive wire 1752 may have a first conductive wire 1752D1 and a second conductive wire 1752D2. The first conductive wire 1752D1 may extend in a first direction D1 and be spaced apart in a second direction D2, with an insulating structure 1751 inserted therebetween. The second conductive wire 1752D2 may extend in the second direction D2 and be spaced apart in the first direction D1, with an insulating structure 1751 inserted therebetween.

[0112] The first conductive line 1752D1 and the second conductive line 1752D2 may intersect each other. For better understanding and ease of description, the conductive line 1752 has been described as having the first conductive line 1752D1 and the second conductive line 1752D2; however, the conductive line 1752 is not limited to having a straight shape, and the first conductive line 1752D1 and the second conductive line 1752D2 may comprise the same material and be formed simultaneously in the same process. In this case, the boundary is not clearly distinguished, and the first conductive line 1752D1 and the second conductive line 1752D2 may essentially have one configuration, wherein only the direction of extension differs. Therefore, the first conductive line 1752D1 and the second conductive line 1752D2 may be connected to each other at their intersection points to surround the insulating structure 1751 between the first conductive line 1752D1 and the second conductive line 1752D2. In other words, the conductive wire 1752 is electrically connected to the first source electrode 171 and the second source electrode 172 disposed on the upper and lower sides of the insulating structure 1751, and can be an interlayer conductive layer disposed between the insulating structures 1751 along the first direction D1 or the second direction D2.

[0113] The first conductive line 1752D1 can be on a plane (e.g., Figure 1 The cells are arranged densely at set intervals from one end to the other in the second direction D2. In other words, on a plane (e.g., Figure 1The same number of first conductive lines 1752D1 can be disposed at any location on the interlayer source electrode 175 within the same region. Furthermore, the second conductive lines 1752D2 can be disposed on a plane (e.g., Figure 1 The cells are densely arranged at set intervals from one end to the other in the first direction D1. In other words, on a plane (e.g., Figure 1 The same number of second conductive lines 1752D2 can be disposed at any location on the interlayer source electrode 175 within the same region. For example, the length of the first conductive line 1752D1 along the second direction D2 can be greater than or substantially equal to the separation distance of the first conductive line 1752D1 along the second direction D2. Furthermore, the length of the second conductive line 1752D2 along the first direction D1 can be greater than or substantially equal to the separation distance of the insulating structure 1751 along the first direction D1.

[0114] Here, in a cross-section cut along a second direction D2 and a third direction D3 perpendicular to the first direction D1, the length of the first conductive wire 1752D1 along the second direction D2 can be the shortest distance along the second direction D2 from the side surface of the first conductive wire 1752D1 on one side along the second direction D2 to the side surface on the other side. In other words, the length of the first conductive wire 1752D1 along the second direction D2 can be the shortest separation distance along the second direction D2 between the insulating structures 1751 on both sides of the first conductive wire 1752D1 on the second direction D2. Furthermore, in a cross-section cut along a first direction D1 and a third direction D3 perpendicular to the second direction D2, the length of the second conductive wire 1752D2 along the first direction D1 can be the shortest distance along the first direction D1 from the side surface of the second conductive wire 1752D2 on one side along the first direction D1 to the side surface on the other side. In other words, the length of the second conductive line 1752D2 along the first direction D1 can be the shortest separation distance along the first direction D1 between the insulating structures 1751 located on both sides of the second conductive line 1752D2 along the first direction D1.

[0115] For example, the first conductive lines 1752D1 may be disposed at locations where they overlap with the gate electrode 150 in the third direction D3, and all gate electrodes 150 may be configured such that they overlap with at least one of the first conductive lines 1752D1 in the third direction D3. Alternatively, the first conductive lines 1752D1 may be disposed at locations where they overlap with the second portion 171P2 of the first source electrode 171 in the third direction D3, and all the second portions 171P2 of the first source electrode 171 may be configured such that they overlap with at least one of the first conductive lines 1752D1 in the third direction D3.

[0116] Furthermore, the second conductive lines 1752D2 may be disposed at locations where they overlap with the gate electrode 150 along the third direction D3, and all gate electrodes 150 may be configured to overlap with at least one of the second conductive lines 1752D2 along the third direction D3. Alternatively, the second conductive lines 1752D2 may be disposed at locations where they overlap with the second portion 171P2 of the first source electrode 171 along the third direction D3, and all the second portions 171P2 of the first source electrodes 171 may be configured such that they overlap with at least one of the second conductive lines 1752D2 along the third direction D3.

[0117] Conductive lines 1752 may be disposed on the third direction D3 between the first source electrode 171 and the second source electrode 172. For example, the first source electrode 171, the conductive lines 1752 of the interlayer source electrode 175, and the second source electrode 172 may be stacked sequentially on the third direction D3. The first source electrode 171 and the second source electrode 172 may not be in direct contact with each other, and may be spaced apart from each other on the third direction D3 by the insulating structure 1751 of the interlayer source electrode 175, and the first source electrode 171 and the second source electrode 172 may be electrically connected by the conductive lines 1752 of the interlayer source electrode 175.

[0118] For example, conductive line 1752 may include a conductive material. For example, conductive line 1752 may include the same conductive material as the first source electrode 171 and the second source electrode 172. In this case, the boundary between conductive line 1752 and the first source electrode 171 and the second source electrode 172 may not be clearly distinguishable.

[0119] For example, conductive wire 1752 may include metal, metal alloy, conductive metal nitride, metal silicide, doped semiconductor material, conductive metal oxide, or conductive metal oxide nitride. For example, conductive wire 1752 may include titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), titanium titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), and tantalum carbonitride (Ta... The conductive wire 1752 may be formed from a single layer or multiple layers. It may also contain, but is not limited to, tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel-platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), or combinations thereof.

[0120] For example, the center line of the first conductive line 1752D1 along the second direction D2 may overlap with the second portion 171P2 of the first source electrode 171 along the third direction D3. Alternatively, the center line of the second conductive line 1752D2 along the first direction D1 may overlap with the second portion 171P2 of the first source electrode 171 along the third direction D3.

[0121] In this case, the center line of the first conductive line 1752D1 along the second direction D2 may not overlap with the center line of the gate electrode 150 along the first direction D1 or the second direction D2 in the third direction D3. Alternatively, the center line of the second conductive line 1752D2 along the first direction D1 may not overlap with the center line of the gate electrode 150 along the first direction D1 or the second direction D2 in the third direction D3.

[0122] Furthermore, since the insulating structure 1751 is disposed between the first conductive lines 1752D1 or the second conductive lines 1752D2, the center point of the insulating structure 1751 along the first direction D1 and the second direction D2 may not overlap with the second portion 171P2 of the first source electrode 171 along the third direction D3. The center point of the insulating structure 1751 along the first direction D1 and the second direction D2 may overlap with the center line of the gate electrode 150 along the first direction D1 or the second direction D2 in the third direction D3.

[0123] Here, the centerline of the first conductive line 1752D1 along the second direction D2 can be a dashed line segment, which passes through the center point of the first conductive line 1752D1 in the second direction D2 and extends along the first conductive line 1752D1 in the first direction D1. The center point of the first conductive line 1752D1 in the second direction D2 can be the point that divides the shortest distance between the two facing sides of the first conductive line 1752D1 in the second direction D2. Similarly, the centerline of the second conductive line 1752D2 along the first direction D1 can be a dashed line segment, which passes through the center point of the second conductive line 1752D2 in the first direction D1 and extends along the second conductive line 1752D2 in the second direction D2. The center point of the second conductive line 1752D2 in the first direction D1 can be the point that divides the shortest distance between the two facing side surfaces of the second conductive line 1752D2 in the first direction D1. The center point of the insulating structure 1751 along the first direction D1 and the second direction D2 can be the point where the diameter of the insulating structure 1751 along the first direction D1 and the diameter along the second direction D2 meet.

[0124] When the gate electrode 150 extends in the first direction D1, in other words, when the length of the gate electrode 150 along the first direction D1 is greater than its length along the second direction D2, the centerline of the gate electrode 150 along either the first direction D1 or the second direction D2 can be a dashed line segment that passes through the center point of the gate electrode 150 along the second direction D2 and extends along the gate electrode 150 in the first direction D1. The center point of the gate electrode 150 in the second direction D2 can be the point that divides the shortest distance between the two side surfaces of the gate electrode 150 facing each other in the second direction D2. Alternatively, when the gate electrode 150 extends in the second direction D2, in other words, when the length of the gate electrode 150 along the second direction D2 is greater than its length along the first direction D1, the centerline of the gate electrode 150 along either the first direction D1 or the second direction D2 can be a dashed line segment that passes through the center point of the gate electrode 150 along the first direction D1 and extends along the gate electrode 150 in the second direction D2. The center point of the gate electrode 150 in the first direction D1 can be the point that divides the shortest distance between the two side surfaces of the gate electrode 150 facing each other in the first direction D1. Alternatively, when the length of the gate electrode 150 along the first direction D1 is substantially the same as the length of the gate electrode 150 along the second direction D2, the center point of the gate electrode 150 along the first direction D1 or the second direction D2 can be the point where the diameter of the gate electrode 150 along the first direction D1 meets the diameter along the second direction D2.

[0125] In SiC power semiconductor devices, there is a method to control the current to prevent short circuits. However, in this case, the resistance of the channel, etc., increases, thus increasing the drain-source resistance (Rds) in the on-state. on This increases the channel length, thus reducing Rds. on However, changing the channel length requires increasing the current, which leads to a saturation drain current (Id). sat Therefore, it is necessary to reduce the loss of Id. sat At the same time, keep Rds on At the same time, it prevents short circuits.

[0126] A semiconductor device according to some embodiments includes a source electrode 170 between a first source electrode 171 and a second source electrode 172, and an interlayer source electrode 175 including an insulating structure 1751 and a conductive line 1752. In other words, the source electrode 170 includes the interlayer source electrode 175, which increases resistance and increases the length of the current flow path between the first source electrode 171 and the second source electrode 172.

[0127] Therefore, as Figure 3As shown in the circuit diagram, the gate pad 155 on the gate (G) side is in direct contact with the metal, but the current entering the source (S) side is supplied through the interlayer source electrode 175, which has high resistance. Thus, by increasing the local resistance in the current path on the source (S) side, a large current flows due to the ballast resistor principle, and the potential difference between the gate (G) and source (S) is reduced due to the voltage drop. When the potential difference between the gate G and the source S decreases, the channel closes, thereby limiting the current and preventing a short circuit.

[0128] Therefore, without changing Rds on Furthermore, without altering the structure in the active source contact region (such as changing the channel length), by reducing Id sat It can prevent short circuits without adding additional resistance to the circuit (e.g., the package or module).

[0129] Furthermore, since the source electrode 170 includes an interlayer source electrode 175 that increases resistance and lengthens the current flow path between the first source electrode 171 and the second source electrode 172, the areas of the first source electrode 171 and the second source electrode 172 are relatively large compared to the area of ​​the interlayer source electrode 175. Therefore, the current concentration in the active source contact area can be reduced, and the voltage overshoot or non-uniformity of the source current at the cell location can be improved, thereby improving current diffusion.

[0130] The semiconductor device may also include a silicide layer 190 disposed between the source electrode 170 and the second conductivity type doped layer 135 and between the source electrode 170 and the first conductivity type doped layer 137.

[0131] The silicide layer 190 may be conformally disposed along the interfaces between the source electrode 170 and the second conductivity type doped layer 135, and between the source electrode 170 and the first conductivity type doped layer 137. The lower surface of the silicide layer 190 may directly contact the second conductivity type doped layer 135 and the first conductivity type doped layer 137. The upper surface of the silicide layer 190 may directly contact the source electrode 170. The silicide layer 190 may comprise a metal silicide material. For example, the silicide layer 190 may comprise tungsten silicide (WSi), titanium silicide (TiSi), cobalt silicide (CoSi), nickel silicide (NiSi), or combinations thereof.

[0132] In the manufacturing process of a semiconductor device, a silicide process can be performed on the upper surfaces of the second conductivity type doped layer 135 and the first conductivity type doped layer 137 to form a silicide layer 190. However, it is not limited to this, and after the source electrode 170 is formed, an annealing process can be subsequently performed to reduce the contact resistance between the second conductivity type doped layer 135 and the source electrode 170, and between the first conductivity type doped layer 137 and the source electrode 170. Therefore, the silicide layer 190 can be formed along the interfaces between the source electrode 170 and the second conductivity type doped layer 135, and between the source electrode 170 and the first conductivity type doped layer 137.

[0133] Drain electrode 180 may be disposed below the second surface (i.e., lower surface) of substrate 110. The upper surface of drain electrode 180 may contact the lower surface of substrate 110. Drain electrode 180 may have an ohmic contact with substrate 110. Compared to other regions, the region within substrate 110 in contact with drain electrode 180 may be doped at a relatively high concentration. However, this is not the only possibility, and another layer may be additionally disposed between drain electrode 180 and substrate 110. For example, a silicide layer may be disposed between drain electrode 180 and substrate 110. The silicide layer may comprise a metal silicide material. Drain electrode 180 and substrate 110 may be smoothly electrically connected via the metal silicide layer.

[0134] The drain electrode 180 may include a conductive material. For example, the drain electrode 180 may include a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, or a conductive metal oxynitride. The drain electrode 180 may be made of the same material as the source electrode 170, or it may be made of a different material.

[0135] For example, the drain electrode 180 can be made of titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), titanium carbide (TiC), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), tantalum (Ta), tantalum carbide (TaC), tantalum nitride (TaN), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), tantalum aluminum nitride (TaAlN), tungsten (W), tungsten nitride (… The drain electrode 180 may be formed from a single layer or multiple layers. The drain electrode 180 may be formed from a single layer or multiple layers. Other materials include, but are not limited to, nickel (Ni), nickel-vanadium (Ni-V), nickel-platinum (Ni-Pt), vanadium (V), zinc (Zn), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), ruthenium (Ru), platinum (Pt), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), or combinations thereof.

[0136] For example, the thickness of the drain electrode 180 may be greater than or equal to about 100 nm, such as 1 μm, greater than or equal to about 2 μm, greater than or equal to about 3 μm, greater than or equal to about 4 μm, greater than or equal to about 5 μm, greater than or equal to about 6 μm, greater than or equal to about 7 μm, greater than or equal to about 8 μm, or greater than or equal to about 9 μm, and the thickness of the drain electrode 180 may be less than or equal to about 10 μm, such as less than or equal to about 9 μm, less than or equal to about 8 μm, less than or equal to about 7 μm, less than or equal to about 6 μm, less than or equal to about 5 μm, less than or equal to about 4 μm, less than or equal to about 3 μm, less than or equal to about 2 μm, or less than or equal to about 1 μm, and the thickness of the drain electrode 180 may be from about 100 nm to about 10 μm or from about 100 nm to about 100 μm.

[0137] In the following text, reference will be made to Figure 4 Describes a semiconductor device according to some implementation methods.

[0138] Figure 4 This is a cross-sectional view showing a semiconductor device according to some embodiments, and is corresponding to... Figure 2 The illustration.

[0139] Figure 4 The implementation methods shown are similar to Figure 2 The embodiments shown are substantially the same, and therefore their description will be omitted, with the differences being explained primarily. Furthermore, the same reference numerals are used for the same elements as in the previous embodiments.

[0140] Reference Figure 4 The center line of the first conductive line 1752D1 along the second direction D2 may not overlap with the second portion 171P2 of the first source electrode 171 along the third direction D3. Alternatively, the center line of the second conductive line 1752D2 along the first direction D1 may not overlap with the second portion 171P2 of the first source electrode 171 along the third direction D3.

[0141] In this case, the center line of the first conductive line 1752D1 along the second direction D2 may overlap with the center line of the gate electrode 150 along the first direction D1 or the second direction D2 in the third direction D3. Alternatively, the center line of the second conductive line 1752D2 along the first direction D1 may overlap with the center line of the gate electrode 150 along the first direction D1 or the second direction D2 in the third direction D3.

[0142] Furthermore, since the insulating structure 1751 is disposed between the first conductive lines 1752D1 or the second conductive lines 1752D2, the center point of the insulating structure 1751 along the first direction D1 and the second direction D2 can overlap with the second portion 171P2 of the first source electrode 171 along the third direction D3. The center point of the insulating structure 1751 along the first direction D1 and the second direction D2 can not overlap with the center line of the gate electrode 150 along the first direction D1 or the second direction D2 along the third direction D3.

[0143] Therefore, the length of the current path between the first source electrode 171 and the second source electrode 172 is further increased, thereby reducing the drain / source on-resistance (Rds) without changing the drain / source on-resistance. on Reduce the saturation drain current (Id) under the condition of sat This prevents short circuits.

[0144] Figure 5 This is a plan view illustrating a semiconductor device according to some embodiments. Figure 6 This is a plan view illustrating a semiconductor device according to some embodiments.

[0145] Figure 5 and Figure 6 The implementation methods shown are the same as Figure 1 The embodiments shown are substantially the same, and therefore their description will be omitted, with the main differences explained. Furthermore, the same reference numerals are used for the same elements as in the previous embodiments.

[0146] exist Figure 1 The diagram shows that the insulating structure 1751 has a circular shape on a plane extending along a first direction D1 and a second direction D2 perpendicular to the third direction D3.

[0147] exist Figure 5 The diagram shows that the insulating structure 1751 has a square shape on a plane extending along a first direction D1 and a second direction D2 perpendicular to the third direction D3.

[0148] exist Figure 6 The diagram shows that the insulating structure 1751 has a hexagonal shape on a plane extending along a first direction D1 and a second direction D2 perpendicular to the third direction D3.

[0149] Figure 7 This is a plan view illustrating a semiconductor device according to some embodiments. Figure 8 It is along Figure 7 A cross-sectional view taken from line A-A'. Figure 9 It is along Figure 7 The cross-sectional view taken by line B-B'.

[0150] Figures 7 to 9 The implementation methods shown are the same as Figure 1 and Figure 2 The embodiments shown are substantially the same, and therefore their description will be omitted, with the main differences being described. Furthermore, the same reference numerals are used for the same elements as in the previous embodiments.

[0151] To ensure clarity and simplify the explanation, Figure 7 The main features shown are: the first conductive line 1752D1 and the second conductive line 1752D2 of the conductive line 1752 of the interlayer source electrode 175; the first insulating structure 1751P1, the second insulating structure 1751P2 and the third insulating structure 1751P3 of the insulating structure 1751; the gate pad 155 and the gate wiring 156; and the substrate 110, the first conductivity type semiconductor layer 131, the second conductivity type doped well region 133, the gate electrode 150, the gate insulating layer 151, the first source electrode 171 and the second source electrode 172 of the source electrode 170, and the drain electrode 180.

[0152] Reference Figures 7 to 9 The insulating structure 1751 of the interlayer source electrode 175 may include a first insulating structure 1751P1 and a second insulating structure 1751P2. In addition, the insulating structure 1751 of the interlayer source electrode 175 may also include a third insulating structure 1751P3.

[0153] For example, in Figure 7 In the plane (hereinafter referred to as the "plane") extending along a first direction D1 and a second direction D2 perpendicular to the third direction D3, the first insulating structure 1751P1 may be configured to be closer to the peripheral region PERI in the first direction D1 and the second direction D2 than the second insulating structure 1751P2. Furthermore, the third insulating structure 1751P3 may be configured to be farther away from the peripheral region PERI in the first direction D1 and the second direction D2 than the first insulating structure 1751P1 and the second insulating structure 1751P2.

[0154] In other words, the first insulating structure 1751P1 can be disposed on the outer edge of the cell region CELL. The first insulating structure 1751P1 can be configured to be adjacent to the gate pad 155 or gate wiring 156 of the peripheral region PERI. The second insulating structure 1751P2 can be disposed in the central portion of the cell region CELL. The second insulating structure 1751P2 can be surrounded by the first insulating structure 1751P1. The first insulating structure 1751P1 can be disposed between the second insulating structure 1751P2 and the gate pad 155 or gate wiring 156. Furthermore, the third insulating structure 1751P3 can be disposed in the central portion of the cell region CELL. The third insulating structure 1751P3 can be surrounded by the first insulating structure 1751P1 and the second insulating structure 1751P2. The first insulating structure 1751P1 and the second insulating structure 1751P2 can be disposed between the third insulating structure 1751P3 and the gate pad 155 or gate wiring 156.

[0155] For example, on a plane (e.g., Figure 7 The first insulating structure 1751P1, the second insulating structure 1751P2, and the third insulating structure 1751P3 may be sequentially arranged from the peripheral region PERI in the first direction D1 and the second direction D2, or sequentially arranged from the outer edge of the cell region CELL to the center portion in the first direction D1 and the second direction D2. In some embodiments, the insulating structure 1751 of the interlayer source electrode 175 may further include a fourth insulating structure, a fifth insulating structure, a sixth insulating structure, a seventh insulating structure, an eighth insulating structure, a ninth insulating structure, or a tenth insulating structure, and the fourth insulating structure, the fifth insulating structure, the sixth insulating structure, the seventh insulating structure, the eighth insulating structure, the ninth insulating structure, or the tenth insulating structure may be sequentially arranged away from the peripheral region PERI.

[0156] For example, on a plane extending along the first direction D1 and the second direction D2 (e.g., Figure 7 The area of ​​the first insulating structure 1751P1 can be smaller than the area of ​​the second insulating structure 1751P2. Furthermore, the area of ​​the second insulating structure 1751P2 on the plane extending along the first direction D1 and the second direction D2 can be smaller than the area of ​​the third insulating structure 1751P3 on the plane extending along the first direction D1 and the second direction D2. In other words, when the insulating structure 1751 moves away from the peripheral region PERI along the first direction D1 and the second direction D2, or when the insulating structure 1751 moves from the outer edge of the cell region CELL to the center portion of the cell region CELL in the first direction D1 and the second direction D2, the area of ​​the insulating structure 1751 on the plane extending along the first direction D1 and the second direction D2 can increase.

[0157] Therefore, the resistance may decrease near the gate pad 155 or gate wiring 156 where the electric field is concentrated, thereby further improving the non-uniformity of the source current at the CELL location.

[0158] In some embodiments, when the insulating structure 1751 of the interlayer source electrode 175 further includes a fourth insulating structure, a fifth insulating structure, a sixth insulating structure, a seventh insulating structure, an eighth insulating structure, a ninth insulating structure, or a tenth insulating structure, the area of ​​the third insulating structure 1751P3 on the plane extending along the first direction D1 and the second direction D2 may be smaller than the area of ​​the fourth insulating structure on the plane extending along the first direction D1 and the second direction D2, the area of ​​the fourth insulating structure on the plane extending along the first direction D1 and the second direction D2 may be smaller than the area of ​​the fifth insulating structure on the plane extending along the first direction D1 and the second direction D2, and the area of ​​the fifth insulating structure on the plane extending along the first direction D1 and the second direction D2 may be smaller than the area of ​​the sixth insulating structure on the plane extending along the first direction D1 and the second direction D2. The area of ​​the sixth insulating structure on the plane extending along the first direction D1 and the second direction D2 can be smaller than the area of ​​the seventh insulating structure on the plane extending along the first direction D1 and the second direction D2, the area of ​​the seventh insulating structure on the plane extending along the first direction D1 and the second direction D2 can be smaller than the area of ​​the eighth insulating structure on the plane extending along the first direction D1 and the second direction D2, the area of ​​the eighth insulating structure on the plane extending along the first direction D1 and the second direction D2 can be smaller than the area of ​​the ninth insulating structure on the plane extending along the first direction D1 and the second direction D2, and the area of ​​the ninth insulating structure on the plane extending along the first direction D1 and the second direction D2 can be smaller than the area of ​​the tenth insulating structure on the plane extending along the first direction D1 and the second direction D2.

[0159] Figure 10 This is a plan view illustrating a semiconductor device according to some embodiments. Figure 11 It is along Figure 10 A cross-sectional view taken from line A-A'.

[0160] Figure 10 and Figure 11 The implementation methods shown are the same as Figure 1 and 2 The embodiments shown are substantially the same, and therefore their description will be omitted; the differences will be described primarily. Furthermore, the same reference numerals are used for the same elements as in the previous embodiments.

[0161] To ensure clarity and simplify the explanation, Figure 10The main features shown are the first conductive overlapping line and the first conductive non-overlapping line of the first conductive line 1752D1 of the conductive line 1752 of the interlayer source electrode 175, the second conductive overlapping line 1752D2P1 and the second conductive non-overlapping line 1752D2P2 of the second conductive line 1752D2, the insulating structure 1751, the gate pad 155 and the gate wiring 156, and the substrate 110, the first conductivity type semiconductor layer 131, the second conductivity type doped well region 133, the gate electrode 150, the gate insulating layer 151, the first source electrode 171 and the second source electrode 172 of the source electrode 170 and the drain electrode 180.

[0162] Reference Figure 10 and Figure 11 The first conductive line 1752D1 may include a first conductive overlapping line and a first conductive non-overlapping line.

[0163] The center line of the first conductive overlap line along the second direction D2 may overlap with the second portion 171P2 of the first source electrode 171 along the third direction D3. In this case, the center line of the first conductive overlap line along the second direction D2 may not overlap with the center line of the gate electrode 150 along the first direction D1 or the second direction D2 in the third direction D3.

[0164] The centerline of the first conductive non-overlapping line along the second direction D2 may not overlap with the second portion 171P2 of the first source electrode 171 along the third direction D3. In this case, the centerline of the first conductive non-overlapping line along the second direction D2 may overlap with the centerline of the gate electrode 150 along the first direction D1 or the second direction D2 in the third direction D3.

[0165] At this point, the length of the first conductive overlapping line along the second direction D2 can be less than the length of the first conductive non-overlapping line along the second direction D2. In other words, the closer the conductive line 1752 is to the active source contact region, the larger its width can be. Therefore, the resistance can be increased towards the active source contact region where the electric field is concentrated, thereby further improving the non-uniformity of the source current through the cell location.

[0166] The second conductive line 1752D2 may include a second conductive overlapping line 1752D2P1 and a second conductive non-overlapping line 1752D2P2.

[0167] The second conductive overlap line 1752D2P1 may overlap with the second portion 171P2 of the first source electrode 171 in the third direction D3 along the center line of the first direction D1. In this case, the second conductive overlap line 1752D2P1 may not overlap with the center line of the gate electrode 150 in the third direction D3 along the center line of the first direction D1 or the second direction D2.

[0168] The centerline of the second conductive non-overlapping line 1752D2P2 along the first direction D1 may not overlap with the second portion 171P2 of the first source electrode 171 along the third direction D3. In this case, the centerline of the second conductive non-overlapping line 1752D2P2 along the first direction D1 may overlap with the centerline of the gate electrode 150 along the first direction D1 or the second direction D2 in the third direction D3.

[0169] At this point, the length of the second conductive overlapping line 1752D2P1 along the first direction D1 can be less than the length of the second conductive non-overlapping line 1752D2P2 along the first direction D1. In other words, the closer the conductive line 1752 is to the active source contact region, the greater its width. Therefore, the resistance can be increased towards the active source contact region where the electric field is concentrated, thereby further improving the non-uniformity of the source current through the cell location.

[0170] At the same time, Figure 10 and Figure 11 In the illustration, the length of the insulating structure 1751 along either the first direction D1 or the second direction D2 is shown to be the same, but this disclosure is not limited thereto, and the lengths of the insulating structure 1751 along either the first direction D1 or the second direction D2 may be different from each other. For example, the length of the insulating structure 1751 along the first direction D1 that overlaps with the second conductivity type doped layer 135 on the third direction D3 may be greater than the length of the insulating structure 1751 along the first direction D1 that does not overlap with the second conductivity type doped layer 135 on the third direction D3 and, for example, overlaps with the gate electrode 150 on the third direction D3. Alternatively, the length of the insulating structure 1751 along the second direction D2 that overlaps with the second conductivity type doped layer 135 on the third direction D3 may be greater than the length of the insulating structure 1751 along the second direction D2 that does not overlap with the second conductivity type doped layer 135 on the third direction D3 and, for example, overlaps with the gate electrode 150 on the third direction D3.

[0171] In addition, Figure 10 In the diagram, the insulating structure 1751 is shown arranged in pairs of three adjacent insulating structures 1751 in the first direction D1, and these pairs are spaced apart in the first direction D1. However, this disclosure is not limited to this, and the insulating structure 1751 may also be arranged in pairs of three adjacent insulating structures 1751 in the second direction D2, and these pairs are spaced apart in the second direction D2. Furthermore, the insulating structures 1751 may be arranged in pairs of two, four, five, six, seven, eight, nine, or ten.

[0172] Figure 12 This is a plan view illustrating a semiconductor device according to some embodiments. Figure 13 It is along Figure 12 A cross-sectional view taken from line A-A'.

[0173] Figure 12 and Figure 13 The implementation methods shown are the same as Figure 1 and Figure 2 The embodiments shown are substantially the same, and therefore their description will be omitted, with the main differences being described. Furthermore, the same reference numerals are used for the same elements as in the previous embodiments.

[0174] To make the explanation clear and simplified, Figure 12 The main features shown are the third first conductive line 1752D1_3 and the third second conductive line 1752_3 of the third interlayer source electrode 175_3, the third insulating structure 1751_3 of the third interlayer source electrode 175_3, the gate pad 155 and the gate wiring 156. The substrate 110, the first conductivity type semiconductor layer 131, the second conductivity type doped well region 133, the gate electrode 150, the gate insulating layer 151, the first source electrode 171 of the source electrode 170, the first interlayer source electrode 175_1, the first second source electrode 172_1, the second interlayer source electrode 175_2, the second second source electrode 172_2 and the third second source electrode 172_3 and the drain electrode 180.

[0175] Reference Figure 12 and Figure 13 The source electrode 170 may include multilayer second source electrodes 172_1, 172_2, and 172_3 and multilayer interlayer source electrodes 175_1, 175_2, and 175_3. The multilayer second source electrodes 172_1, 172_2, and 172_3 and the multilayer interlayer source electrodes 175_1, 175_2, and 175_3 may be alternately stacked on the third-direction D3.

[0176] As an example, Figure 13 The source electrode 170 is shown to include three layers of second source electrodes 172_1, 172_2, and 172_3, and three layers of interlayer source electrodes 175_1, 175_2, and 175_3. In other words, the source electrode 170 may include a first interlayer source electrode 175_1 on a first source electrode 171, a first second source electrode 172_1 on the first interlayer source electrode 175_1, a second interlayer source electrode 175_2 on the first second source electrode 172_1, a second second source electrode 172_2 on the second interlayer source electrode 175_2, a third interlayer source electrode 175_3 on the second second source electrode 172_2, and a third second source electrode 172_3 on the third interlayer source electrode 175_3.

[0177] Thus, when the source electrode 170 includes multiple layers of second source electrodes 172_1, 172_2, and 172_3 and multiple layers of interlayer source electrodes 175_1, 175_2, and 175_3, the length of the current path can be further increased to reduce the saturation leakage current (Id).sat Without changing the drain / source on-resistance (Rds) on This prevents short circuits.

[0178] In some embodiments, source electrode 170 may include two or more layers of second source electrode 172, for example, three or more layers, four or more layers, five or more layers, six or more layers, seven or more layers, eight or more layers, nine or more layers, ten or more layers, twenty or more layers, thirty or more layers, forty or more layers, fifty or more layers, sixty or more layers, seventy or more layers, eighty or more layers, or ninety or more layers, and source electrode 1 70 may include 100 layers or fewer, for example, 90 layers or fewer, 80 layers or fewer, 70 layers or fewer, 60 layers or fewer, 50 layers or fewer, 40 layers or fewer, 30 layers or fewer, 20 layers or fewer, 10 layers or fewer, 9 layers or fewer, 8 layers or fewer, 7 layers or fewer, 6 layers or fewer, 5 layers or fewer, 4 layers or fewer, 3 layers or fewer, or 2 layers or fewer, and the source electrode 170 may include 2 to 100 layers. However, if the number of layers in the second source electrode 172 is too large, cracks or stresses may occur in the interlayer source electrodes 175_1, 175_2, and 175_3 during scribing.

[0179] Furthermore, the source electrode 170 may include two or more interlayer source electrodes 175_1, 175_2, and 175_3. For example, the source electrode 170 may include three or more layers, four or more layers, five or more layers, six or more layers, seven or more layers, eight or more layers, nine or more layers, ten or more layers, twenty or more layers, thirty or more layers, forty or more layers, fifty or more layers, sixty or more layers, seventy or more layers, eighty or more layers, or ninety or more layers. The source electrode 170 may comprise 100 or fewer layers, for example, 90 or fewer layers, 80 or fewer layers, 70 or fewer layers, 60 or fewer layers, 50 or fewer layers, 40 or fewer layers, 30 or fewer layers, 20 or fewer layers, 10 or fewer layers, 9 or fewer layers, 8 or fewer layers, 7 or fewer layers, 6 or fewer layers, 5 or fewer layers, 4 or fewer layers, 3 or fewer layers, or 2 or fewer layers, and the source electrode 170 may comprise 2 to 100 layers. However, if the number of layers in the interlayer source electrodes 175_1, 175_2, and 175_3 is too large, cracks or stresses may occur in the interlayer source electrodes 175_1, 175_2, and 175_3 during scribing.

[0180] The multilayer interlayer source electrodes 175_1, 175_2, and 175_3 each include insulating structures 1751_1, 1751_2, and 1751_3 and conductive lines (e.g., 1752_3). The conductive lines (e.g., 1752_3) may have a first conductive line (e.g., 1752D1_3) and second conductive lines 1752D2_1, 1752D2_2, and 1752D2_3.

[0181] For example, the first interlayer source electrode 175_1 may include a first insulating structure 1751_1, a first conductive line (not shown), and a first second conductive line 1752D2_1. The second interlayer source electrode 175_2 may include a second insulating structure 1751_2, a second first conductive line (not shown), and a second second conductive line 1752D2_2. The third interlayer source electrode 175_3 may include a third insulating structure 1751_3, a third first conductive line 1752D1_3, and a third second conductive line 1752D2_3.

[0182] Figure 14 This is a plan view showing the first interlayer source electrode of a semiconductor device according to some embodiments. Figure 15 It is shown Figure 14 A plan view of the second interlayer source electrode of the semiconductor device. Figure 16 It is shown Figure 14 A plan view of the third interlayer source electrode of the semiconductor device. Figure 17 It is along Figure 16 A cross-sectional view taken from line A-A'.

[0183] Figures 14 to 17 The embodiments shown have the same Figure 1 and Figure 2 or Figure 12 and Figure 13 The embodiments shown have substantially the same components, and therefore their description will be omitted; instead, the differences will be described primarily. Furthermore, the same reference numerals are used for the same elements as in the previous embodiments.

[0184] For clarity and to simplify the presentation, Figure 14 The main features shown are the first first conductive line 1752D1_1 and the first second conductive line 1752D2_1 of the first conductive line 1752_1 of the first interlayer source electrode 175_1, the first insulating structure 1751_1 of the first interlayer source electrode 175_1, the gate pad 155, and the gate wiring 156. Figure 15The main illustrations include the second first conductive line 1752D1_2 and the second second conductive line 1752D2_2 of the second interlayer source electrode 175_2, the second insulating structure 1751_2 of the second interlayer source electrode 175_2, the first insulating structure 1751_1 of the first interlayer source electrode 175_1, the gate pad 155, and the gate wiring 156. Figure 16 The main features shown are the third first conductive line 1752D1_3 and the third second conductive line 1752D2_3 of the third interlayer source electrode 175_3, the third insulating structure 1751_3 of the third interlayer source electrode 175_3, the second insulating structure 175l_2 of the second interlayer source electrode 175_2, the gate pad 155 and the gate wiring 156, and... Figures 14 to 16 The substrate 110, the first conductive semiconductor layer 131, the second conductivity type doped well region 133, the gate electrode 150, the gate insulating layer 151, the first source electrode 171 of the source electrode 170, the first interlayer source electrode 175_1, the first second source electrode 172_1, the second interlayer source electrode 175_2, the second second source electrode 172_2 and the third second source electrode 172_3, and the drain electrode 180 are not shown.

[0185] Reference Figures 14 to 17 The source electrode 170 may include multiple layers of second source electrodes 172_1, 172_2, and 172_3, and multiple layers of interlayer source electrodes 175_1, 175_2, and 175_3. The multiple layers of second source electrodes 172_1, 172_2, and 172_3, and the multiple layers of interlayer source electrodes 175_1, 175_2, and 175_3 may be alternately stacked on a third-direction D3.

[0186] For example, the length of the first conductive line 1752D1_1 of the first interlayer source electrode 175_1 along the second direction D2 can be greater than the length of the first conductive line 1752D1_2 of the second interlayer source electrode 175_2 along the second direction D2. The length of the first conductive line 1752D1_2 of the second interlayer source electrode 175_2 along the second direction D2 can be greater than the length of the first conductive line 1752D1_3 of the third interlayer source electrode 175_3 along the second direction D2. In other words, the length of the first conductive line of an interlayer source electrode of a layer along the second direction D2 can be greater than the length of the first conductive line of other interlayer source electrodes located above that interlayer source electrode in the third direction D3 along the second direction D2, and can be less than the length of the first conductive line of other interlayer source electrodes located below that interlayer source electrode in the third direction D3 along the second direction D2. That is, the higher the interlayer source electrode 175 is positioned in the third direction D3, the shorter the length of the first conductive line 1752D1 along the second direction D2.

[0187] Furthermore, the length of the second conductive line 1752D2_1 of the first interlayer source electrode 175_1 along the first direction D1 can be greater than the length of the second conductive line 1752D2_2 of the second interlayer source electrode 175_2 along the first direction D1. The length of the second conductive line 1752D2_2 of the second interlayer source electrode 175_2 along the first direction D1 can be greater than the length of the second conductive line 1752D2_3 of the third interlayer source electrode 175_3 along the first direction D1. In other words, the length of the second conductive line of an interlayer source electrode of a layer along the first direction D1 can be greater than the length of the second conductive line of other interlayer source electrodes located above that interlayer source electrode in the third direction D3 along the first direction D1, and can be less than the length of the second conductive line of other interlayer source electrodes located below that interlayer source electrode in the third direction D3 along the first direction D1. That is, the higher the interlayer source electrode 175 is positioned in the third direction D3, the shorter the length of the second conductive line 1752D2 along the first direction D1.

[0188] Furthermore, the separation distance of the insulating structure 1751_1 of the first interlayer source electrode 175_1 along the first direction D1 or the second direction D2 can be greater than the separation distance of the insulating structure 1751_2 of the second interlayer source electrode 175_2 along the first direction D1 or the second direction D2. The separation distance of the insulating structure 1751_2 of the second interlayer source electrode 175_2 along the first direction D1 or the second direction D2 can be greater than the separation distance of the insulating structure 1751_3 of the third interlayer source electrode 175_3 along the first direction D1 or the second direction D2. In other words, the separation distance of the insulating structure of an interlayer source electrode of one layer along the first direction D1 or the second direction D2 can be greater than the separation distance of the insulating structure of other interlayer source electrodes located above that interlayer source electrode in the third direction D3 along the first direction D1 or the second direction D2, and can be less than the separation distance of the insulating structure of other interlayer source electrodes located below that interlayer source electrode in the third direction D3 along the first direction D1 or the second direction D2. In other words, the higher the interlayer source electrode 175 is set on the third direction D3, the smaller the separation distance between the insulating structures 1751 on the first direction D1 or the second direction D2.

[0189] Furthermore, the length of the insulating structure 1751_1 of the first interlayer source electrode 175_1 along the first direction D1 or the second direction D2 may be less than the length of the insulating structure 1751_2 of the second interlayer source electrode 175_2 along the first direction D1 or the second direction D2. The length of the insulating structure 1751_2 of the second interlayer source electrode 175_2 along the first direction D1 or the second direction D2 may be greater than the length of the insulating structure 1751_3 of the third interlayer source electrode 175_3 along the first direction D1 or the second direction D2. In other words, the length of the insulating structure of an interlayer source electrode of one layer along the first direction D1 or the second direction D2 may be less than the length of the insulating structure of other interlayer source electrodes located above the interlayer source electrode in the third direction D3 along the first direction D1 or the second direction D2, and may be greater than the length of the insulating structure of other interlayer source electrodes located below the interlayer source electrode in the third direction D3 along the first direction D1 or the second direction D2. In other words, the higher the interlayer source electrode 175 is set on the third direction D3, the longer the insulation structure 1751 can be on the first direction D1 or the second direction D2.

[0190] In this way, when the interlayer source electrode 175 is set higher on the third direction D3, the length of the first conductive line 1752D1 along the second direction D2 becomes smaller, or the length of the second conductive line 1752D2 along the first direction D1 becomes smaller, thereby adjusting the required resistance.

[0191] Figure 18 This is a plan view showing the first interlayer source electrode of a semiconductor device according to some embodiments. Figure 19 It is shown Figure 18 A plan view of the second interlayer source electrode of the semiconductor device. Figure 20 It is along Figure 19 A cross-sectional view taken from line A-A'. Figure 21 It is along Figure 19 The cross-sectional view taken by line B-B'.

[0192] Figures 18 to 20 The embodiments shown have the same Figure 1 and Figure 2 or Figure 12 and Figure 13 The embodiments shown have substantially the same components, and therefore their description will be omitted, with the differences being described primarily. Furthermore, the same reference numerals are used for the same elements as in the previous embodiments.

[0193] To clearly understand and simplify the diagram, Figure 18The main features shown are the first first conductive line 1752D1_1 and the first second conductive line 1752D2_1 of the first conductive line 1752_1 of the first interlayer source electrode 175_1, the first insulating structure 1751_1 of the first interlayer source electrode 175_1, the gate pad 155, and the gate wiring 156. Figure 19 The main features shown are the second first conductive line 1752D1_2 and the second second conductive line 1752D2_2 of the second conductive line 1752_2 of the second interlayer source electrode 175_2, the second insulating structure 1751_2 of the second interlayer source electrode 175_2, the first insulating structure 1751_1 of the first interlayer source electrode 175_1, the gate pad 155 and the gate wiring 156, and in addition... Figure 18 and Figure 19 The substrate 110, the first conductivity type semiconductor layer 131, the second conductivity type doped well region 133, the gate electrode 150, the gate insulating layer 151, the first source electrode 171, the first second source electrode 172_1, the second second source electrode 172_2, and the drain electrode 180 are not shown in the figure.

[0194] Reference Figures 18 to 20 The diagram shows that the source electrode 170 includes two layers of second source electrodes 172_1 and 172_2, and two layers of interlayer source electrodes 175_1 and 175_2. In other words, the source electrode 170 may include a first interlayer source electrode 175_1 on the first source electrode 171, a first second source electrode 172_1 on the first interlayer source electrode 175_1, a second interlayer source electrode 175_2 on the first second source electrode 172_1, and a second second source electrode 172_2 on the second interlayer source electrode 175_2.

[0195] The first interlayer source electrode 175_1 may include a first insulating structure 1751_1, a first first conductive line 1752D1_1, and a first second conductive line 1752D2_1. The second interlayer source electrode 175_2 may include a second insulating structure 1751_2, a second first conductive line 1752D1_2, and a second second conductive line 1752D2_2.

[0196] For example, the center point of the first insulating structure 1751_1 of the first interlayer source electrode 175_1 along the first direction D1 and the second direction D2 may not overlap with the center point of the second insulating structure 1751_2 of the second interlayer source electrode 175_2 along the first direction D1 and the second direction D2 in the third direction D3. In this case, the length of the current path can be further increased to reduce the saturation drain current (Id). sat ), without changing the drain / source on-resistance (Rds) on This prevents short circuits.

[0197] The center point of the first insulating structure 1751_1 of the first interlayer source electrode 175_1 along the first direction D1 and the second direction D2 can overlap with the center line of the second first conductive line 1752D1_2 of the second interlayer source electrode 175_2 along the second direction D2 in the third direction D3. The center point of the first insulating structure 1751_1 of the first interlayer source electrode 175_1 along the first direction D1 and the second direction D2 can overlap with the center line of the second second conductive line 1752D2_2 of the second interlayer source electrode 175_2 along the first direction D1 in the third direction D3.

[0198] Furthermore, the center point of the second insulating structure 1751_2 of the second interlayer source electrode 175_2 along the first direction D1 and the second direction D2 can overlap with the center line of the first first conductive line 1752D1_1 of the first interlayer source electrode 175_1 along the second direction D2 in the third direction D3. The center point of the second insulating structure 1751_2 of the second interlayer source electrode 175_2 along the first direction D1 and the second direction D2 can overlap with the center line of the first second conductive line 1752D2_1 of the first interlayer source electrode 175_1 along the first direction D1 in the third direction D3.

[0199] The center line of the first first conductive line 1752D1_1 of the first interlayer source electrode 175_1 along the second direction D2 may not overlap with the center line of the second first conductive line 1752D1_2 of the second interlayer source electrode 175_2 along the second direction D2 on the third direction D3.

[0200] The center line of the first second conductive line 1752D2_1 of the first interlayer source electrode 175_1 along the first direction D1 may not overlap with the center line of the second conductive line 1752D2_2 of the second interlayer source electrode 175_2 along the first direction D1 on the third direction D3.

[0201] For example, in a plane extending along a first direction D1 and a second direction D2 perpendicular to the third direction D3 (e.g., Figure 18 and Figure 19 The shapes of the first insulating structure 1751_1 of the first interlayer source electrode 175_1 and the second insulating structure 1751_2 of the second interlayer source electrode 175_2 may be different or substantially the same. Figure 18 and Figure 19 In the first interlayer source electrode 175_1, the first insulating structure 1751_1 has a square planar shape, and the second insulating structure 1751_2 of the second interlayer source electrode 175_2 has a circular planar shape. In some embodiments, the shapes of the first insulating structure 1751_1 of the first interlayer source electrode 175_1 and the second insulating structure 1751_2 of the second interlayer source electrode 175_2 can independently have various shapes, such as circular, elliptical, polygonal, or linear.

[0202] Furthermore, in a plane extending perpendicularly to a third party in a first direction D1 and a second direction D2 (e.g.) Figure 18 and Figure 19 The area of ​​the first insulating structure 1751_1 of the first interlayer source electrode 175_1 may be greater than, less than or substantially equal to the area of ​​the second insulating structure 1751_2 of the second interlayer source electrode 175_2.

[0203] Figure 22 This is a plan view showing the first interlayer source electrode of a semiconductor device according to some embodiments. Figure 23 It is shown Figure 22 A plan view of the second interlayer source electrode of the semiconductor device. Figure 24 It is along Figure 23 A cross-sectional view taken from line A-A'. Figure 25 It is along Figure 23 The cross-sectional view taken by line B-B'.

[0204] Figures 22 to 25 The implementation methods shown are the same as Figures 18 to 21 The embodiments shown are substantially the same, and therefore their description will be omitted, with the main differences being described. Furthermore, the same reference numerals are used for the same elements as in the previous embodiments.

[0205] To ensure clarity and simplify the explanation, Figure 22 The main features shown are the first first conductive line 1752D1_1 and the first second conductive line 1752D2_1 of the first conductive line 1752_1 of the first interlayer source electrode 175_1, the first insulating structure 1751_1 of the first interlayer source electrode 175_1, the gate pad 155 and the gate wiring 156. Figure 23 The main features shown are the second first conductive line 1752D1_2 and the second second conductive line 1752D2_2 of the second conductive line 1752_2 of the second interlayer source electrode 175_2, the second insulating structure 1751_2 of the second interlayer source electrode 175_2, the first insulating structure 1751_1 of the first interlayer source electrode 175_1, the gate pad 155 and the gate wiring 156. The substrate 110, the first conductivity type semiconductor layer 131, the second conductivity type doped well region 133, the gate electrode 150, the gate insulating layer 151, the first source electrode 171, the first second source electrode 172_1 and the second second source electrode 172_2 are omitted.

[0206] Reference Figures 22 to 25The center point of the first insulating structure 1751_1 of the first interlayer source electrode 175_1 along the first direction D1 and the second direction D2 may not overlap with the center point of the second insulating structure 1751_2 of the second interlayer source electrode 175_2 along the first direction D1 and the second direction D2 in the third direction D3. In this case, the length of the current path can be further increased to reduce the saturation drain current (Id). sat ), without changing the drain / source on-resistance (Rds) on This prevents short circuits.

[0207] For example, the center point of the first insulating structure 1751_1 of the first interlayer source electrode 175_1 along the first direction D1 and the second direction D2 may overlap with the center line of the second first conductive line 1752D1_2 of the second interlayer source electrode 175_2 along the second direction D2 in the third direction D3. However, the center point of the first insulating structure 1751_1 of the first interlayer source electrode 175_1 along the first direction D1 and the second direction D2 may not overlap with the center line of the second second conductive line 1752D2_2 of the second interlayer source electrode 175_2 along the first direction D1 in the third direction D3.

[0208] Furthermore, the center point of the second insulating structure 1751_2 of the second interlayer source electrode 175_2 along the first direction D1 and the second direction D2 may overlap with the center line of the first first conductive line 1752D1_1 of the first interlayer source electrode 175_1 along the second direction D2 in the third direction D3. However, the center point of the second insulating structure 1751_2 of the second interlayer source electrode 175_2 along the first direction D1 and the second direction D2 may not overlap with the center line of the first second conductive line 1752D2_1 of the first interlayer source electrode 175_1 along the first direction D1 in the third direction D3.

[0209] The centerline of the first first conductive line 1752D1_1 of the first interlayer source electrode 175_1 along the second direction D2 may not overlap with the centerline of the second first conductive line 1752D1_2 of the second interlayer source electrode 175_2 along the second direction D2 in the third direction D3. However, the centerline of the first second conductive line 1752D2_1 of the first interlayer source electrode 175_1 along the first direction D1 may overlap with the centerline of the second conductive line 1752D2_2 of the second interlayer source electrode 175_2 along the first direction D1 in the third direction D3.

[0210] Figure 26 This is a plan view showing the first interlayer source electrode of a semiconductor device according to some embodiments. Figure 27 It is shown Figure 26 A plan view of the second interlayer source electrode of the semiconductor device. Figure 28 It is along Figure 27A cross-sectional view taken from line A-A'. Figure 29 It is along Figure 27 The cross-sectional view taken by line B-B'.

[0211] Figures 26 to 29 The implementation methods shown are the same as Figures 18 to 21 The embodiments shown are substantially the same, and therefore their description will be omitted, with the main differences being described. Furthermore, the same reference numerals are used for the same elements as in the previous embodiments.

[0212] To make the explanation clear and simplified, Figure 26 The main features shown are the first first conductive line 1752D1_1 and the first second conductive line 1752D2_1 of the first conductive line 1752_1 of the first interlayer source electrode 175_1, the first insulating structure 1751_1 of the first interlayer source electrode 175_1, the gate pad 155 and the gate wiring 156. Figure 27 The main features shown are the second first conductive line 1752D1_2 and the second second conductive line 1752D2_2 of the second conductive line 1752_2 of the second interlayer source electrode 175_2, the second insulating structure 1751_2 of the second interlayer source electrode 175_2, the first insulating structure 1751_1 of the first interlayer source electrode 175_1, the gate pad 155, and the gate wiring 156. Figure 26 and Figure 27 The substrate 110, the first conductivity semiconductor layer 131, the second conductivity doped well region 133, the gate electrode 150, the gate insulating layer 151, the first source electrode 171, the first second source electrode 172_1, the second second source electrode 172_2, and the drain electrode 180 are not shown in the figure.

[0213] Reference Figures 26 to 29 The center point of the first insulating structure 1751_1 of the first interlayer source electrode 175_1 along the first direction D1 and the second direction D2 may not overlap with the center point of the second insulating structure 1751_2 of the second interlayer source electrode 175_2 along the first direction D1 and the second direction D2 in the third direction D3. In this case, the length of the current path can be further increased to reduce the saturation drain current (Id). sat ), without changing the drain / source on-resistance (Rds) on This prevents short circuits.

[0214] For example, the center point of the first insulating structure 1751_1 of the first interlayer source electrode 175_1 along the first direction D1 and the second direction D2 may not overlap with the center line of the second first conductive line 1752D1_2 of the second interlayer source electrode 175_2 along the second direction D2 in the third direction D3. However, the center point of the first insulating structure 1751_1 of the first interlayer source electrode 175_1 along the first direction D1 and the second direction D2 may overlap with the center line of the second second conductive line 1752D2_2 of the second interlayer source electrode 175_2 along the first direction D1 in the third direction D3.

[0215] Furthermore, the center point of the second insulating structure 1751_2 of the second interlayer source electrode 175_2 along the first direction D1 and the second direction D2 may not overlap with the center line of the first first conductive line 1752D1_1 of the first interlayer source electrode 175_1 along the second direction D2 in the third direction D3. However, the center point of the second insulating structure 1751_2 of the second interlayer source electrode 175_2 along the first direction D1 and the second direction D2 may overlap with the center line of the first second conductive line 1752D2_1 of the first interlayer source electrode 175_1 along the first direction D1 in the third direction D3.

[0216] The centerline of the first conductive line 1752D1_1 of the first interlayer source electrode 175_1 along the second direction D2 may overlap with the centerline of the first conductive line 1752D1_2 of the second interlayer source electrode 175_2 along the second direction D2 in the third direction D3. However, the centerline of the first second conductive line 1752D2_1 of the first interlayer source electrode 175_1 along the first direction D1 may not overlap with the centerline of the second conductive line 1752D2_2 of the second interlayer source electrode 175_2 along the first direction D1 in the third direction D3.

[0217] Figure 30 This is a plan view showing the first interlayer source electrode according to some implementations of a semiconductor device. Figure 31 yes Figure 30 A plan view of the second interlayer source electrode of the semiconductor device. Figure 32 It is along Figure 31 A cross-sectional view taken from line A-A'. Figure 33 It is along Figure 31 The cross-sectional view taken by line B-B'.

[0218] Figures 30 to 33 Implementation methods and Figures 18 to 21 The implementation methods are substantially the same, and therefore their descriptions will be omitted, with the main differences being described. Furthermore, the same reference numerals are used for the same elements as in the previous embodiments.

[0219] To make the explanation clear and simplified, Figure 30The main features shown are the first first conductive line 1752D1_1 and the first second conductive line 1752D2_1 of the first conductive line 1752_1 of the first interlayer source electrode 175_1, the first insulating structure 1751_1 of the first interlayer source electrode 175_1, the gate pad 155 and the gate wiring 156, and... Figure 31 The main features shown are the second first conductive line 1752D1_2 and the second second conductive line 1752D2_2 of the second conductive line 1752_2 of the second interlayer source electrode 175_2, the second insulating structure 1751_2 of the second interlayer source electrode 175_2, the first insulating structure 1751_1 of the first interlayer source electrode 175_1, the gate pad 155 and the gate wiring 156, and... Figure 30 and Figure 31 The substrate 110, the first conductivity semiconductor layer 131, the second conductivity doped well region 133, the gate electrode 150, the gate insulating layer 151, the first source electrode 171, the first second source electrode 172_1, the second second source electrode 172_2, and the drain electrode 180 are not shown in the figure.

[0220] Reference Figures 30 to 33 The source electrode 170 includes two layers of second source electrodes 172_1 and 172_2, and two layers of interlayer source electrodes 175_1 and 175_2. In other words, the source electrode 170 may include a first interlayer source electrode 175_1 on the first source electrode 171, a first second source electrode 172_1 on the first interlayer source electrode 175_1, a second interlayer source electrode 175_2 on the first second source electrode 172_1, and a second second source electrode 172_2 on the second interlayer source electrode 175_2.

[0221] The first interlayer source electrode 175_1 may include a first insulating structure 1751_1 and a first second conductive line 1752D2_1. The second interlayer source electrode 175_2 may include a second insulating structure 1751_2, a second first conductive line 1752D1_2 and a second second conductive line 1752D2_2.

[0222] For example, in a plane extending along a first direction D1 and a second direction D2 perpendicular to the third direction D3 (e.g., Figure 30 and Figure 31In the diagram, the first insulating structure 1751_1 of the first interlayer source electrode 175_1 is shown as having a linear shape extending along the second direction D2 and spaced apart along the first direction D1. In other words, the first insulating structure 1751_1 of the first interlayer source electrode 175_1 may have different lengths along the second direction D2 and along the first direction D1. In some embodiments, the first insulating structure 1751_1 of the first interlayer source electrode 175_1 may have a linear shape extending in the first direction D1 and spaced apart in the second direction D2. Therefore, the first interlayer source electrode 175_1 may have a first second conductive line 1752D2_1 extending in the second direction D2 and spaced apart from each other in the first direction D1, but may not have a first first conductive line 1752D1_1 extending in the first direction D1 and spaced apart from each other in the second direction D2.

[0223] Furthermore, in a plane extending along a first direction D1 and a second direction D2 perpendicular to the third direction D3 (e.g., Figure 30 and Figure 31 In the diagram, the second insulating structure 1751_2 of the second interlayer source electrode 175_2 is shown as having a circular shape in a plane. In other words, the second insulating structure 1751_2 of the second interlayer source electrode 175_2 may have a length along a second direction D2 and a length along a first direction D1, both lengths being substantially the same. In some embodiments, the shape of the second insulating structure 1751_2 of the second interlayer source electrode 175_2 may each have various shapes independently, such as circular, elliptical, polygonal, or linear.

[0224] In some embodiments, the second insulating structure 1751_2 of the second interlayer source electrode 175_2 may have a planar linear shape, and the first insulating structure 1751_1 of the first interlayer source electrode 175_1 may have a planar circular shape. In other words, the first insulating structure 1751_1 of the first interlayer source electrode 175_1 may have substantially the same length in the second direction D2 and substantially the same length in the first direction D1, and the second insulating structure 1751_2 of the second interlayer source electrode 175_2 may have different lengths in the second direction D2 and the same length in the first direction D1.

[0225] For example, the center point of the first insulating structure 1751_1 of the first interlayer source electrode 175_1 along the first direction D1 and the center point of the second insulating structure 1751_2 of the second interlayer source electrode 175_2 along the first direction D1 and the second direction D2 may overlap or not overlap in the third direction D3. Figures 30 to 33In the first layer source electrode 175_1, the center line of the first insulating structure 1751_1 along the first direction D1 and the center point of the second insulating structure 1751_2 of the second layer source electrode 175_2 along the first direction D1 and the second direction D2 may not overlap on the third direction D3.

[0226] In this way, when the center line of the first insulating structure 1751_1 of the first interlayer source electrode 175_1 along the first direction D1 and the center point of the second insulating structure 1751_2 of the second interlayer source electrode 175_2 along the first direction D1 and the second direction D2 do not overlap on the third direction D3, the length of the current path will be further increased, thereby reducing the saturation drain current Id. sat Without changing the drain / source on-resistance Rds on This helps prevent short circuits.

[0227] In some embodiments, when the center line of the first insulating structure 1751_1 of the first interlayer source electrode 175_1 along the first direction D1 overlaps with the center point of the second insulating structure 1751_2 of the second interlayer source electrode 175_2 along the first direction D1 and the second direction D2 in the third direction D3, since the first insulating structure 1751_1 of the first interlayer source electrode 175_1 extends along the second direction D2, any one of the first insulating structures 1751_1 can overlap with the center point of the second insulating structure 1751_2 along the first direction D1 and the second direction D2 in the third direction D3.

[0228] The centerline of the first insulating structure 1751_1 of the first interlayer source electrode 175_1 along the first direction D1 and the centerline of the second first conductive line 1752D1_2 of the second interlayer source electrode 175_2 along the second direction D2 can overlap in the third direction D3. The centerline of the first insulating structure 1751_1 of the first interlayer source electrode 175_1 along the first direction D1 and the centerline of the second second conductive line 1752D2_2 of the second interlayer source electrode 175_2 along the first direction D1 can overlap in the third direction D3.

[0229] Furthermore, the center point of the second insulating structure 1751_2 of the second interlayer source electrode 175_2 along the first direction D1 and the second direction D2 can overlap with the center line of the first second conductive line 1752D2_1 of the first interlayer source electrode 175_1 along the first direction D1 on the third direction D3.

[0230] The centerline of the first second conductive line 1752D2_1 of the first interlayer source electrode 175_1 along the first direction D1 can overlap with the centerline of the second second conductive line 1752D2_2 of the second interlayer source electrode 175_2 along the first direction D1 in the third direction D3. The centerline of the first second conductive line 1752D2_1 of the first interlayer source electrode 175_1 along the first direction D1 can overlap with the centerline of the second first conductive line 1752D1_2 of the second interlayer source electrode 175_2 along the second direction D2 in the third direction D3.

[0231] While this specification contains numerous specific implementation details, these should not be construed as limiting the scope of any invention or the scope of claims, but rather as descriptions of features specific to particular embodiments of the invention. Specific features described in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as functioning in a particular combination, one or more features from the combination may be removed from the combination in some cases, and combinations may be for sub-combinations or variations thereof.

[0232] Although this disclosure has been described in conjunction with embodiments now considered to be practical, it should be understood that this disclosure is not limited to the disclosed embodiments, but rather, this disclosure is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A semiconductor device, comprising: The substrate includes a cell region and a peripheral region located outside the cell region; A first conductivity type semiconductor layer is present on the upper surface of the substrate; A second conductivity type doped well region is located within the first conductivity type semiconductor layer; Gate electrode, which is located on the semiconductor layer of the first conductivity type; A gate insulating layer is located between the first conductivity type semiconductor layer and the gate electrode; The source electrode is located on the doped well region of the second conductivity type. as well as The drain electrode is located below the lower surface of the substrate. The source electrode includes: The first source electrode is located on the gate electrode. The second source electrode, which is on the first source electrode, and An interlayer source electrode includes: (i) a plurality of insulating structures spaced apart from each other in a first direction parallel to the upper surface of the substrate and (ii) a plurality of conductive lines, wherein each of the plurality of conductive lines is located between adjacent insulating structures in the plurality of insulating structures, and wherein the interlayer source electrode is disposed between a first source electrode and a second source electrode.

2. The semiconductor device of claim 1, wherein, The plurality of insulating structures are spaced apart from each other in a second direction parallel to the upper surface of the substrate and different from the first direction. The plurality of conductive lines include: A plurality of first conductive lines extend in a first direction and are spaced apart from each other in a second direction, wherein each of the plurality of insulating structures is inserted between adjacent first conductive lines. A plurality of second conductive lines extend in a second direction and are spaced apart from each other in the first direction, wherein each of the plurality of insulating structures is inserted between adjacent second conductive lines. The plurality of first conductive lines intersect with the plurality of second conductive lines.

3. The semiconductor device as claimed in claim 2, wherein, The plurality of first conductive lines and the plurality of second conductive lines are interconnected and surround the plurality of insulating structures, and The plurality of first conductive lines and the plurality of second conductive lines extend upward on a third side perpendicular to the upper surface of the substrate, thereby connecting the first source electrode to the second source electrode.

4. The semiconductor device of claim 3, wherein, The first source electrode includes: The first part, which is on the gate electrode; and The second part extends downward from the first part along the third part, is disposed between the gate electrodes, and is connected to the second conductivity type doped well region.

5. The semiconductor device of claim 4, wherein, (i) the center line of each of the plurality of first conductive lines along the second direction overlaps with the second portion of the first source electrode in the third direction upwards, or (ii) the center line of each of the plurality of second conductive lines along the first direction overlaps with the second portion of the first source electrode in the third direction upwards, and Wherein, the center point of each of the plurality of insulating structures along the first direction and the second direction does not overlap with the second portion of the first source electrode in the third direction.

6. The semiconductor device of claim 4, wherein, (i) the centerline of each of the plurality of first conductive lines along the second direction does not overlap with the second portion of the first source electrode in the third direction, or (ii) the centerline of each of the plurality of second conductive lines along the first direction does not overlap with the second portion of the first source electrode in the third direction, and Wherein, the center point of each of the plurality of insulating structures along the first direction and the second direction overlaps with the second portion of the first source electrode in the third direction.

7. The semiconductor device of claim 4, wherein, The insulating structure of the plurality of insulating structures has one of the following shapes in a plane: (i) a circular shape, (ii) an elliptical shape, (iii) a polygonal shape, (iv) a linear shape extending in the first direction, or (v) a linear shape extending in the second direction.

8. The semiconductor device of claim 3, wherein, The semiconductor device includes a gate pad or gate wiring in the peripheral region of the substrate. The interlayer source electrode includes a first insulating structure and a second insulating structure. Wherein, the first insulating structure is closer to the peripheral region than the second insulating structure in both the first and second directions, and Wherein, the area of ​​the first insulating structure on the plane extending along the first direction and the second direction is smaller than the area of ​​the second insulating structure on the plane extending along the first direction and the second direction.

9. The semiconductor device of claim 3, wherein, The plurality of first conductive lines include: Multiple first conductive overlap lines, wherein the center line of the multiple first conductive overlap lines along the second direction overlaps with the second portion of the first source electrode in the third direction, and Multiple first conductive non-overlapping lines, wherein the center lines of the multiple first conductive non-overlapping lines along the second direction do not overlap with the second portion of the first source electrode in the third direction. Wherein, the length of each of the plurality of first conductive overlapping lines along the second direction is less than the length of each of the plurality of first conductive non-overlapping lines along the second direction, or The plurality of second conductive lines include: Multiple second conductive overlap lines, wherein the center line of the multiple second conductive overlap lines along the first direction overlaps with the second portion of the first source electrode in the third direction, and Multiple second conductive non-overlapping lines, wherein the center lines of the multiple second conductive non-overlapping lines along the first direction do not overlap with the second portion of the first source electrode in the third direction. Wherein, the length of each of the plurality of second conductive overlapping lines along the first direction is less than the length of each of the plurality of second conductive non-overlapping lines along the first direction.

10. A semiconductor device, comprising: The substrate includes a cell region and a peripheral region located outside the cell region; A first conductivity type semiconductor layer, on the upper surface of the substrate, A second conductivity type doped well region is located within the first conductivity type semiconductor layer; Gate electrode, which is located on the semiconductor layer of the first conductivity type; A gate insulating layer is located between the first conductivity type semiconductor layer and the gate electrode; The source electrode is located on the doped well region of the second conductivity type. as well as The drain electrode is located below the lower surface of the substrate. The source electrode includes: The first source electrode is located on the gate electrode. Multiple second source electrodes, which are located above the first source electrode, and A plurality of interlayer source electrodes, each of the plurality of interlayer source electrodes comprising: (i) a plurality of insulating structures spaced apart from each other in a first direction parallel to the upper surface of the substrate, and (ii) a plurality of conductive lines located between adjacent insulating structures among the plurality of insulating structures, and the plurality of interlayer source electrodes being disposed between the first source electrode and adjacent second source electrodes among the plurality of second source electrodes. and The plurality of second source electrodes and the plurality of interlayer source electrodes are stacked alternately in the third direction.

11. The semiconductor device of claim 10, wherein, The source electrode includes: The plurality of second source electrodes described in layers 2 to 100, and Multiple interlayer source electrodes, ranging from 2 to 100 layers.

12. The semiconductor device of claim 10, wherein, The plurality of insulating structures are spaced apart in the first direction and the second direction, the second direction being parallel to the upper surface of the substrate and different from the first direction. The plurality of conductive lines include: A plurality of first conductive lines extend in a first direction and are spaced apart from each other in a second direction, wherein each of the plurality of insulating structures is inserted between adjacent first conductive lines. A plurality of second conductive lines extend in a second direction and are spaced apart from each other in the first direction, wherein each of the plurality of insulating structures is inserted between adjacent second conductive lines. The plurality of first conductive lines intersect with the plurality of second conductive lines.

13. The semiconductor device of claim 12, wherein, The length (i) of each first conductive line of the first interlayer source electrode in the plurality of interlayer source electrodes along the first direction is greater than the length (ii) of each first conductive line of the second interlayer source electrode located above the first interlayer source electrode in the third direction along the first direction, and less than the length (ii) of each first conductive line of the third interlayer source electrode located below the first interlayer source electrode in the third direction along the first direction, or The length (i) of each second conductive line of the first interlayer source electrode along the second direction is greater than the length of each second conductive line of the second interlayer source electrode along the second direction, and (ii) is less than the length of each second conductive line of the third interlayer source electrode along the second direction. The separation distance (i) of adjacent insulating structures in the plurality of insulating structures of at least one of the plurality of interlayer source electrodes along the first direction or the second direction is greater than the separation distance (ii) of adjacent insulating structures in the plurality of insulating structures of other interlayer source electrodes located above the at least one interlayer source electrode in the third direction along the first direction or the second direction.

14. The semiconductor device of claim 12, wherein, The source electrode includes: The first source electrode is located on the gate electrode; A first interlayer source electrode is located on the first source electrode and includes (i) a plurality of insulating structures spaced apart from each other in a first direction parallel to the upper surface of the substrate and (ii) a plurality of conductive lines between the plurality of insulating structures. The first second source electrode is located on the first interlayer source electrode; The second interlayer source electrode is located on the first second source electrode and includes (i) a plurality of insulating structures spaced apart from each other in the first direction and (ii) a plurality of conductive lines between the plurality of insulating structures. The second source electrode is located on the second interlayer source electrode; A third interlayer source electrode, located on the second source electrode, and comprising (i) a plurality of insulating structures spaced apart from each other in the first direction and (ii) a plurality of conductive lines between the plurality of insulating structures; and The third second source electrode is located on the third interlayer source electrode. Wherein, the length of each of the plurality of first conductive lines of the first interlayer source electrode along the first direction is greater than the length of each of the plurality of first conductive lines of the second interlayer source electrode along the first direction, and Wherein, (i) the length of each of the plurality of first conductive lines of the second interlayer source electrode along the first direction is greater than the length of each of the plurality of first conductive lines of the third interlayer source electrode along the first direction, or (ii) the length of each of the plurality of second conductive lines of the first interlayer source electrode along the second direction is greater than the length of each of the plurality of second conductive lines of the second interlayer source electrode along the second direction. Wherein, the length of each of the plurality of second conductive lines of the second interlayer source electrode along the second direction is greater than the length of each of the plurality of second conductive lines of the third interlayer source electrode along the second direction. Wherein, the separation distance between adjacent insulating structures in the plurality of insulating structures of the first interlayer source electrode along the first direction or the second direction is greater than the separation distance between adjacent insulating structures in the plurality of insulating structures of the second interlayer source electrode along the first direction or the second direction, and Wherein, the separation distance between adjacent insulating structures in the plurality of insulating structures of the second interlayer source electrode along the first direction or the second direction is greater than the separation distance between adjacent insulating structures in the plurality of insulating structures of the third interlayer source electrode along the first direction or the second direction.

15. A semiconductor device, comprising: The substrate includes a cell region and a peripheral region located outside the cell region; A first conductivity type semiconductor layer is present on the upper surface of the substrate; A second conductivity type doped well region is located within the first conductivity type semiconductor layer; Gate electrode, which is located on the semiconductor layer of the first conductivity type; A gate insulating layer is located between the first conductivity type semiconductor layer and the gate electrode; The source electrode is located on the doped well region of the second conductivity type. as well as The drain electrode is located below the lower surface of the substrate. The source electrode includes: The first source electrode is located on the gate electrode. A first interlayer source electrode, which is on the first source electrode and includes (i) a plurality of insulating structures spaced apart from each other in a first direction parallel to the upper surface of the substrate and (ii) a plurality of conductive lines disposed between the plurality of insulating structures. The first and second source electrodes are located on the first interlayer source electrode. A second interlayer source electrode, which is located on the first second source electrode, and includes (i) a plurality of insulating structures spaced apart from each other in the first direction and (ii) a plurality of conductive lines between the plurality of insulating structures. The second source electrode is located on the second interlayer source electrode. and Wherein, each of the center points of the plurality of insulating structures of the first interlayer source electrode along the first direction and parallel to the upper surface of the substrate and different from the first direction, does not overlap with each of the center points of the plurality of insulating structures of the second interlayer source electrode along the first direction and the second direction in a third direction, wherein the third direction is perpendicular to the upper surface of the substrate.

16. The semiconductor device of claim 15, wherein, The plurality of insulating structures of the first interlayer source electrode are spaced apart from each other in the first direction and the second direction. The plurality of insulating structures of the second interlayer source electrode are spaced apart from each other in the first direction and the second direction. The plurality of conductive lines include: A plurality of first conductive lines extend in a first direction and are spaced apart from each other in a second direction, wherein each of the plurality of insulating structures is inserted between adjacent first conductive lines. A plurality of second conductive lines extend in a second direction and are spaced apart from each other in the first direction, wherein each of the plurality of insulating structures is inserted between adjacent second conductive lines. The plurality of first conductive lines intersect with the plurality of second conductive lines.

17. The semiconductor device of claim 16, wherein, The center point of each of the plurality of insulating structures of the first interlayer source electrode along the first direction and the second direction overlaps with the center line of each of the plurality of first conductive lines of the second interlayer source electrode along the second direction in the third direction. Wherein, the center point of each of the plurality of insulating structures of the first interlayer source electrode along the first direction and the second direction overlaps with the center line of each of the plurality of second conductive lines of the second interlayer source electrode along the first direction in the third direction. Wherein, the center point of each of the plurality of insulating structures of the second interlayer source electrode along the first direction and the second direction overlaps with the center line of each of the plurality of first conductive lines of the first interlayer source electrode along the second direction in the third direction. Wherein, the center point of each of the plurality of insulating structures of the second interlayer source electrode along the first direction and the second direction overlaps with the center line of each of the plurality of second conductive lines of the first interlayer source electrode along the first direction in the third direction. Wherein, the center line of each of the plurality of first conductive lines of the first interlayer source electrode along the second direction does not overlap with the center line of each of the plurality of first conductive lines of the second interlayer source electrode along the second direction in the third direction, and Wherein, the center line of each of the plurality of second conductive lines of the first interlayer source electrode along the first direction does not overlap with the center line of each of the plurality of second conductive lines of the second interlayer source electrode along the first direction in the third direction.

18. The semiconductor device of claim 16, wherein, The center point of each of the plurality of insulating structures of the first interlayer source electrode along the first direction and the second direction overlaps with the center line of each of the plurality of first conductive lines of the second interlayer source electrode along the second direction in the third direction. Wherein, the center point of each of the plurality of insulating structures of the first interlayer source electrode along the first direction and the second direction does not overlap with the center line of each of the plurality of second conductive lines of the second interlayer source electrode along the first direction in the third direction. Wherein, the center point of each of the plurality of insulating structures of the second interlayer source electrode along the first direction and the second direction overlaps with the center line of each of the plurality of first conductive lines of the first interlayer source electrode along the second direction in the third direction. Wherein, the center point of each of the plurality of insulating structures of the second interlayer source electrode along the first direction and the second direction does not overlap with the center line of each of the plurality of second conductive lines of the first interlayer source electrode along the first direction in the third direction. Wherein, the center line of each of the plurality of first conductive lines of the first interlayer source electrode along the second direction does not overlap with the center line of each of the plurality of first conductive lines of the second interlayer source electrode along the second direction in the third direction, and Wherein, the center line of each of the plurality of second conductive lines of the first interlayer source electrode along the first direction overlaps with the center line of each of the plurality of second conductive lines of the second interlayer source electrode along the first direction in the third direction.

19. The semiconductor device of claim 16, wherein, The center point of each of the plurality of insulating structures of the first interlayer source electrode along the first direction and the second direction does not overlap with the center line of each of the plurality of first conductive lines of the second interlayer source electrode along the second direction in the third direction. Wherein, the center point of each of the plurality of insulating structures of the first interlayer source electrode along the first direction and the second direction overlaps with the center line of each of the plurality of second conductive lines of the second interlayer source electrode along the first direction in the third direction. Wherein, the center point of each of the plurality of insulating structures of the second interlayer source electrode along the first direction and the second direction does not overlap with the center line of each of the plurality of first conductive lines of the first interlayer source electrode along the second direction in the third direction. Wherein, the center point of each of the plurality of insulating structures of the second interlayer source electrode along the first direction and the second direction overlaps with the center line of each of the plurality of second conductive lines of the first interlayer source electrode along the first direction in the third direction. Wherein, the center line of each of the plurality of first conductive lines of the first interlayer source electrode along the second direction overlaps with the center line of each of the plurality of first conductive lines of the second interlayer source electrode along the second direction in the third direction, and Wherein, the center line of each of the plurality of second conductive lines of the first interlayer source electrode along the first direction does not overlap with the center line of each of the plurality of second conductive lines of the second interlayer source electrode along the first direction in the third direction.

20. The semiconductor device of claim 15, wherein, The plurality of insulating structures of the first interlayer source electrode extend in the second direction and are spaced apart from each other in the first direction, and the plurality of conductive lines of the first interlayer source electrode include (i) a plurality of first conductive lines extending in the second direction and (ii) spaced apart from each other in the first direction, wherein each of the plurality of insulating structures is inserted between adjacent first conductive lines in the plurality of first conductive lines, and Wherein, adjacent insulating structures of the plurality of insulating structures of the second interlayer source electrode are spaced apart from each other in the first direction and the second direction, and the plurality of conductive lines of the second interlayer source electrode include: (i) a plurality of first conductive lines extending in the first direction and spaced apart from each other in the second direction, wherein each of the plurality of insulating structures is inserted between adjacent first conductive lines; and (ii) a plurality of second conductive lines extending in the second direction and spaced apart from each other in the first direction, wherein the plurality of insulating structures are located between the plurality of second conductive lines, and wherein the plurality of first conductive lines intersect with the plurality of second conductive lines. Wherein, the center line of each of the plurality of insulating structures of the first interlayer source electrode along the first direction overlaps with the center line of each of the plurality of first conductive lines of the second interlayer source electrode along the second direction in the third direction. Wherein, the center line of each of the plurality of insulating structures of the first interlayer source electrode along the first direction overlaps with the center line of each of the plurality of second conductive lines of the second interlayer source electrode along the first direction in the third direction. The center point of each of the plurality of insulating structures of the second interlayer source electrode along the first direction and the second direction overlaps with the center line of each of the plurality of first conductive lines of the first interlayer source electrode along the second direction in the third direction. The center point of each of the plurality of insulating structures of the second interlayer source electrode along the first direction and the second direction overlaps with the center line of each of the plurality of second conductive lines of the first interlayer source electrode along the first direction in the third direction, and The center line of each of the plurality of second conductive lines of the first interlayer source electrode along the first direction does not overlap with the center line of each of the plurality of second conductive lines of the second interlayer source electrode along the first direction in the third direction.

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