An enhanced HEMT device with gate structure

Abstract

The application discloses an enhanced HEMT device with a gate structure, comprising a substrate layer, a buffer layer, a channel layer, a barrier layer, a gate, a source and a drain, wherein the substrate layer, the buffer layer, the channel layer and the barrier layer are sequentially arranged from bottom to top; the gate comprises a first gate part and a plurality of second gate parts, the plurality of second gate parts are arranged side by side and each extends from the upper surface of the barrier layer to the inside of the channel layer; the first gate part is arranged above the plurality of second gate parts and between adjacent second gate parts, and forms a comb-shaped gate structure together with the plurality of second gate parts; the first gate part is in contact with or spaced apart from the plurality of second gate parts. The HEMT device can obtain higher 2DEG carrier density, reduce the influence of surface defects on the channel layer and thus reduce the current collapse effect, and can also reduce the threshold voltage drift problem of the top gate and further improve the threshold voltage.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, and specifically relates to an enhancement-mode HEMT device with a gate structure. Background Technology

[0002] GaN HEMT (High Electron Mobility Transistor) devices are currently widely used. Their basic structure involves sequentially growing a buffer layer, a channel layer, and a barrier layer on a substrate. The buffer layer includes one or more GaN-based material layers, such as an AlN nucleation layer or a GaN buffer layer. The channel layer comprises one or more GaN-based material layers, such as a high-mobility unintentionally doped GaN channel layer or other doped GaN channel layers. The barrier layer comprises one or more GaN-based material layers, such as an AlGaN barrier layer, an AlN spacer layer, an InAlGaN etching transfer layer, and a GaN cap layer. The principle behind this is the formation of a high-concentration, high-mobility two-dimensional electron gas (2DEG) at the interface of the channel layer near the barrier layer, due to the band difference between the barrier layer and the channel layer, and the polarization effect of the material. By fabricating source and drain electrodes, that is, by fabricating two metal electrodes on the barrier layer with a certain distance between them, the metal electrodes form ohmic contacts with the materials of the barrier layer and the channel layer through an annealing process, i.e., source and drain electrodes. The source and drain electrodes are electrically connected through 2DEG on the channel layer, and a gate electrode is fabricated between the source and drain electrodes.

[0003] HEMT devices are divided into enhancement-mode and depletion-mode types, namely normally-off (NOR) and normally-on (NOT). Compared to depletion-mode (NOT) HEMTs, enhancement-mode (NOT) HEMTs have superior performance characteristics. Therefore, achieving reproducible and stable mass production of enhancement-mode HEMTs has become a research hotspot in recent years. Current enhancement-mode HEMT devices all have some problems. Taking the gate trench etching process as an example, the barrier layer needs to be etched to a certain depth before stopping above the channel layer. Achieving a consistent etching depth across the entire wafer is a major challenge, as different etching depths result in different turn-on voltages. One method is to grow a high-dielectric-constant insulating dielectric on the trench, using the insulating dielectric to control the threshold voltage. However, this method introduces another problem: the threshold voltage drifts over time. This is because the insulating dielectric is constantly under the high-voltage electric field of the gate drain, and changes occur over time. Defects and stresses formed during deposition will gradually alter the device's threshold voltage. Meanwhile, enhancement-mode HEMTs using P-type GaN material as the gate suffer from a relatively low gate turn-on voltage. Currently, the main demand for GaN HEMT devices is for enhancement-mode HEMTs, which have certain requirements for threshold voltage consistency, long-term stability, and absolute value. How to improve the threshold voltage while improving the threshold voltage consistency and long-term stability during device fabrication has become a very big challenge. Summary of the Invention

[0004] To address the aforementioned problems in the prior art, this invention provides an enhancement-mode HEMT device with a gate structure. The technical problem to be solved by this invention is achieved through the following technical solution:

[0005] This invention provides an enhancement-mode HEMT device with a gate structure, comprising a substrate layer, a buffer layer, a channel layer, a barrier layer, a gate, a source, and a drain, wherein...

[0006] The substrate layer, the buffer layer, the channel layer, and the barrier layer are arranged sequentially from bottom to top;

[0007] The gate includes a first gate portion and a plurality of second gate portions, the plurality of second gate portions being arranged in parallel and all extending from the upper surface of the barrier layer into the interior of the channel layer;

[0008] The first gate portion is disposed above the plurality of second gate portions and between adjacent second gate portions, and together with the plurality of second gate portions forms a comb-shaped gate structure; the first gate portion is in contact with or spaced apart from the plurality of second gate portions;

[0009] The portion of each second gate portion that contacts the channel layer and the barrier layer is made of a P-type GaN-based material.

[0010] In one embodiment of the present invention, a dielectric layer is disposed on the area of ​​the upper surface of the barrier layer not covered by the source and the drain.

[0011] Alternatively, a dielectric layer may be provided on the upper surface of the barrier layer in the area not covered by the first gate portion, the source, and the drain.

[0012] In one embodiment of the present invention, both the channel layer and the barrier layer are GaN-based materials.

[0013] In one embodiment of the present invention, the second gate portion is a P-type doped GaN-based material, or a stacked structure of P-type doped and N-type doped GaN-based materials; the first gate portion is made of a metal material.

[0014] In one embodiment of the invention, the lower surface of the first gate portion includes a plurality of downwardly extending protrusions, each protrusion correspondingly extending into a barrier layer between adjacent second gate portions.

[0015] In one embodiment of the present invention, a plurality of holes are arranged in parallel on the upper surface of the barrier layer, the lower surface of the holes extends into the interior of the channel layer, and the second gate portion is formed in the holes by epitaxial growth.

[0016] In one embodiment of the present invention, the second gate portion is formed in the barrier layer and the channel layer by ion implantation.

[0017] In one embodiment of the present invention, the second gate portion is made of a P-type doped GaN-based material; the first gate portion includes a GaN-based material layer located below and a metal material layer located above the GaN-based material layer.

[0018] In one embodiment of the present invention, the second gate portion includes a P-type GaN material layer located below and around it, and a metal material layer surrounded by the P-type GaN material layer; the first gate portion is made of a metal material.

[0019] In one embodiment of the present invention, the second gate portion includes a P-type GaN material layer located below and around it, and a metal material layer surrounded by the P-type GaN material layer;

[0020] The first gate portion includes a GaN-based material layer disposed on a barrier layer between adjacent second gate portions, and a metal material layer disposed above the GaN-based material between adjacent second gate portions and above the second gate portions.

[0021] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0022] 1. This invention relates to an enhancement-mode HEMT device with a gate structure. By embedding gates into the channel layer, a gate structure consisting of spaced embedded gates is formed in the HEMT channel. Since the embedded gates generate a depletion layer of a certain width in the horizontal direction of the communication layer, and the depletion layers generated by adjacent embedded gates overlap, the 2DEGs in the channel layer between any two adjacent embedded gates are in a depleted state, i.e., the channel is normally off. When a positive voltage is applied to the embedded gate, the depletion layer shrinks. When the depletion layers generated by adjacent embedded gates separate, the channel layer between them resumes conduction, i.e., the channel is on. By controlling the distance between two adjacent embedded gates and the material characteristics of the embedded gates, such as the doping concentration of P-type material or the gate metal, the threshold voltage can be modulated, i.e., a larger threshold voltage can be obtained. Since the embedded gates are formed of P-type GaN material, there is no insulating dielectric layer, thus avoiding the problem of threshold voltage drift.

[0023] 2. The enhanced HEMT device of this invention differs from existing FinFET structures. The depletion layers on both sides of the device are provided by P-type GaN material instead of a metal and dielectric layer structure. The P-type GaN material, which directly contacts the channel material, provides better depletion layer control. Furthermore, the sidewall gates in FinFET structures use a metal and insulating dielectric structure, identical to the top gate. This structure, like the previous one, suffers from leakage over time under the high-voltage electric field between the gate and drain. This invention, however, avoids this problem by using an embedded gate made of P-type GaN material. It also optimizes the electric field distribution between the gate and drain through array arrangement and the use of a buried field plate. This invention forms a comb-like embedded gate in the gate region using an array, while the area outside the gate region retains the original epitaxial structure. This differs from the approach of growing P-type GaN material across the entire surface of the barrier layer and then removing it over a large area. This reduces the increase in surface states caused by etching damage and improves the current collapse effect. The first gate portion is formed through the barrier layer / dielectric / metal structure, which increases the 2DEG concentration in the channel.

[0024] 3. In the enhanced HEMT device of this invention, since the embedded gate is fabricated by etching the device to form a hole and then epitaxially growing P-type material or selectively implanting or depositing a medium and metal, its size and spacing can be precisely controlled by the window size defined by the photolithography process, thus easily achieving high uniformity. An embedded gate of a certain depth can also be equivalent to a buried field plate, improving the electric field concentration effect and thereby improving the device's breakdown characteristics. Since the channel's on / off state is mainly controlled by the embedded gate, the control effect of the top gate on the channel is weakened. Therefore, a thicker AlGaN barrier layer can be grown to obtain a higher 2DEG carrier density and reduce the impact of surface defects on the channel layer, thereby reducing the current collapse effect.

[0025] 4. The first gate portion and multiple second gate portions of the present invention can be individually connected to control signals. The second gate portions mainly exert influence on the channel region from both sidewalls in the recessed region, while the first gate portions mainly exert influence on the channel above the channel region. Therefore, by connecting control signals separately, further modulation of the threshold voltage can be achieved, and more modes of the working area of ​​the modulation device can be obtained.

[0026] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of an enhancement-mode HEMT device with a gate structure provided in an embodiment of the present invention;

[0028] Figure 2 yes Figure 1 A schematic diagram of a cross-section taken along the center of the gate of an enhancement-mode HEMT device;

[0029] Figure 3 yes Figure 1 The enhanced HEMT device does not show a top view of the first gate portion;

[0030] Figure 4 This is a top view of a first gate portion having other shapes provided in an embodiment of the present invention;

[0031] Figure 5 This is a schematic diagram of another enhanced HEMT device with a gate structure provided in an embodiment of the present invention;

[0032] Figure 6 yes Figure 5 Another cross-sectional view of an enhancement-mode HEMT device taken along the center of the gate;

[0033] Figure 7This is a schematic diagram of another enhanced HEMT device with a gate structure provided in an embodiment of the present invention;

[0034] Figure 8 yes Figure 7 A schematic diagram of a cross-section taken along AA for an enhanced HEMT device;

[0035] Figure 9 yes Figure 7 A schematic diagram of a cross-section taken along the BB of an enhanced HEMT device;

[0036] Figure 10 This is a schematic diagram of the structure of an enhancement-mode HEMT device with multiple channels provided in an embodiment of the present invention;

[0037] Figure 11 yes Figure 10 A schematic diagram of a cross-section taken along the CC of an enhanced HEMT device;

[0038] Figure 12 yes Figure 10 A schematic diagram of a cross-section taken along the DD of an enhanced HEMT device;

[0039] Figure 13 This is a schematic diagram of another enhanced HEMT device with a gate structure provided in an embodiment of the present invention;

[0040] Figure 14 yes Figure 13 A schematic diagram of a cross-section taken along the center of the gate of an enhancement-mode HEMT device;

[0041] Figure 15 yes Figure 13 The enhanced HEMT device does not show a top view of the first gate portion;

[0042] Figure 16 yes Figure 13 Another cross-sectional view of an enhancement-mode HEMT device taken along the center of the gate;

[0043] Figure 17 This is a cross-sectional schematic diagram of another enhanced HEMT device with a gate structure provided in an embodiment of the present invention;

[0044] Figure 18 This is a schematic diagram of another enhanced HEMT device with a gate structure provided in an embodiment of the present invention;

[0045] Figure 19 yes Figure 18 A schematic diagram of a cross-section taken along the center of the gate of an enhancement-mode HEMT device;

[0046] Figure 20This is a schematic diagram of another enhanced HEMT device with a gate structure provided in an embodiment of the present invention;

[0047] Figure 21 yes Figure 20 A schematic diagram of a cross-section taken along the EE of an enhanced HEMT device;

[0048] Figure 22 yes Figure 20 A schematic diagram of a cross-section taken along the FF of an enhanced HEMT device;

[0049] Figure 23 This is a schematic diagram of another enhancement-mode HEMT device with multiple channels provided in an embodiment of the present invention;

[0050] Figure 24 yes Figure 23 A schematic diagram of a cross-section taken along the GG axis of an enhanced HEMT device;

[0051] Figure 25 yes Figure 23 A schematic diagram of a cross-section taken along HH of an enhanced HEMT device;

[0052] Figure 26 This is a schematic diagram of another enhanced HEMT device with a gate structure provided in an embodiment of the present invention;

[0053] Figure 27 yes Figure 26 A schematic diagram of a cross-section taken along line II of an enhanced HEMT device;

[0054] Figure 28 yes Figure 26 A schematic diagram of a cross-section taken along JJ of an enhanced HEMT device;

[0055] Figure 29 This is a schematic diagram of another enhancement-mode HEMT device with multiple channels provided in an embodiment of the present invention;

[0056] Figure 30 yes Figure 29 A schematic diagram of a cross-section taken along KK of an enhanced HEMT device;

[0057] Figure 31 yes Figure 29 A schematic diagram of a cross-section taken along LL of an enhanced HEMT device;

[0058] Figure 32 This is a schematic diagram of another enhanced HEMT device with a gate structure provided in an embodiment of the present invention;

[0059] Figure 33 yes Figure 32A schematic diagram of a cross-section taken along MM for an enhanced HEMT device;

[0060] Figure 34 yes Figure 32 A schematic diagram of a cross-section taken along the NN of an enhanced HEMT device. Detailed Implementation

[0061] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the following detailed description of an enhanced HEMT device according to the present invention is provided in conjunction with the accompanying drawings and specific embodiments.

[0062] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of specific embodiments in conjunction with the accompanying drawings. Through the description of the specific embodiments, a more in-depth and concrete understanding can be gained of the technical means and effects adopted by the present invention to achieve its intended purpose. However, the accompanying drawings are for reference and illustration only and are not intended to limit the technical solutions of the present invention.

[0063] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations are intended to cover non-exclusive inclusion, such that an article or apparatus comprising a list of elements includes not only those elements but also other elements not expressly listed. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or apparatus that includes said element.

[0064] Example 1

[0065] Please see Figure 1 and Figure 2 , Figure 1 This is a schematic diagram of an enhancement-mode HEMT device with a gate structure provided in an embodiment of the present invention; Figure 2 yes Figure 1 A schematic cross-sectional view of an enhancement-mode HEMT device taken along the center of the gate. The enhancement-mode HEMT device includes a substrate layer 1, a buffer layer 2, a channel layer 3, a barrier layer 4, a gate 5, a source 6, and a drain 7, wherein the substrate layer 1, the buffer layer 2, the channel layer 3, and the barrier layer 4 are arranged sequentially from bottom to top.

[0066] The substrate layer 1 can be made of materials such as Si, SiC, Al2O3 (sapphire), GaAs, ZnO, LaLiO3, AlN, or GaN. The buffer layer 2 can be made of GaN, and the channel layer 3 and barrier layer 4 can be GaN-based materials. The GaN-based materials mainly include GaN, BN, InGaN, and Al. x Ga y In 1-x-y The GaN alloy material (0≤x≤1, 0≤y≤1, 0≤x+y≤1) can be undoped, N-type or P-type doped.

[0067] Furthermore, please also refer to Figure 2 and Figure 3 , Figure 3 yes Figure 1 The enhancement-mode HEMT device does not show a top view of the first gate portion. The gate 5 includes a first gate portion 51 and a plurality of second gate portions 52, which are arranged side-by-side and extend from the upper surface of the barrier layer 4 into the channel layer 3. The first gate portion 51 covers the upper surface of the barrier layer 4 above the plurality of second gate portions 52 and between adjacent second gate portions 52, and is elongated, forming a comb-like gate structure together with the plurality of second gate portions 52. In this embodiment, the top view shape of the plurality of second gate portions 52 is square, and the spacing between them is equal.

[0068] However, in other embodiments, the spacing between the plurality of second gate portions 52 may also be different. When the spacing between adjacent second gate portions 52 is different, the HEMT device can have multiple stepped threshold voltages and multiple stepped maximum saturation currents, thereby forming an effect equivalent to multiple HEMTs of different specifications integrated in parallel. Further, as Figure 4 As shown, the top view shape of the second gate portion 52 can also be a circle, ellipse, trapezoid, rectangle, parallelogram, rhombus, triangle, pentagon, hexagon, polygon, or other different shapes, and adjacent second gate portions 52 can have different shapes. Furthermore, the sidewalls of the second gate portion 52 can be vertical, inwardly inclined, outwardly inclined, or can be arc-shaped or polygonal, or a combination of the above shapes.

[0069] In this embodiment, the second gate portion 52 is made of a P-type doped GaN-based material. The second gate portion 52 can be formed by epitaxial growth or by ion implantation.

[0070] In one specific embodiment, a plurality of parallel holes 9 are provided on the upper surface of the barrier layer 4, and the lower surface of the holes 9 extends into the channel layer 3. The second gate portion 52 is formed in the holes 9 by epitaxial growth. The sidewalls of the holes 9 can be vertical, inclined inward, inclined outward, or can be arc-shaped, polygonal, or a combination of the above shapes. It should be noted that by controlling the depth and shape of the holes 9, the electric field distribution between the source 6 and the drain 7 can be modulated, thereby improving the breakdown voltage and obtaining better breakdown voltage characteristics.

[0071] In another specific embodiment, the second gate portion 52 can be formed in the barrier layer 4 and the channel layer 3 of GaN-based material by ion implantation, thereby forming a second gate portion 52 of P-type doped GaN-based material. Specifically, since both the channel layer 3 and the barrier layer 4 are GaN-based materials, when fabricating the second gate portion 52 on the barrier layer 4, it is not necessary to use the method of etching holes and filling with GaN-based material. Instead, the GaN-based material at the location of the second gate portion 52 can be directly P-type doped by ion implantation to form a second gate portion 52 of P-type doped GaN-based material.

[0072] Furthermore, the material of the second gate portion 52 in this embodiment can also be a combination of a series of materials, or a combination of material layers in which N-type materials and P-type materials are stacked alternately, such as a combination of N-type materials and P-type materials forming a tunneling PN junction.

[0073] The first gate portion 51 in this embodiment is made of a metallic material and can be prepared using a metal deposition process, such as physical vapor deposition, chemical vapor deposition, or electroplating. In this embodiment, the first gate portion 51 has a T-shaped form in the front view direction, and the first gate portion 51 connects all the second gate portions 52 together to form a comb-shaped gate structure.

[0074] In addition, please see Figure 5 , Figure 5 This is a schematic diagram of another enhancement-mode HEMT device with a gate structure provided in an embodiment of the present invention. A dielectric layer 8 may also be disposed on the area of ​​the upper surface of the barrier layer 4 not covered by the first gate portion 51, the source 6, and the drain 7. The dielectric layer 8 can be a single material, such as SiO2, SiN, or SiON, or it can be a dielectric layer composed of different materials such as SiO2, SiN, and Al2O3 grown sequentially in different orders.

[0075] In another specific embodiment, the dielectric layer 8 covers the area on the upper surface of the barrier layer 4 that is not covered by the source 6 and drain 7. In this case, the first gate portion 51 located between adjacent second gate portions 52 includes the dielectric layer 8 between it and the barrier layer 4. From bottom to top, the layers are the barrier layer 4, the dielectric layer 8, and the first gate portion 51 made of metal. Figure 7 As shown, by forming a structure consisting of a barrier layer, a dielectric layer, and a metal first gate portion, the concentration of 2DEG in the channel can be increased.

[0076] Furthermore, such as Figure 6 As shown, the lower surface of the first gate portion 51 includes a plurality of downwardly extending protrusions 511, each protrusion 511 extending into the dielectric layer 8 between adjacent second gate portions 52. Specifically, before depositing the first gate portion 51, a portion of the dielectric layer 8 between the second gate portions 52 can be etched away, and then metal can be deposited on the dielectric layer 8 between the second gate portions 52 and on the second gate portions 52 to form the first gate portion 51, such that the metal material penetrates into a portion between the second gate portions 52 to form the protrusions 511.

[0077] The fabrication method of the enhanced HEMT device in this embodiment is as follows:

[0078] First, a substrate structure is fabricated, comprising a substrate layer 1, a buffer layer 2, a channel layer 3, and a barrier layer 4 stacked sequentially from bottom to top. Subsequently, a dielectric layer 8 is grown on the barrier layer 4. A gate 5, a source 6, and a drain 7 are fabricated on the dielectric layer 8. The gate 5 has a comb-like structure, including a plurality of second gate portions 52 arranged side by side in the substrate structure, and a first gate portion 51 disposed above the second gate portions. The source 6 and the drain 7 are located on opposite sides of the gate 5.

[0079] Taking the epitaxial growth of the second gate portion 52 as an example, a series of holes 9 are formed on the dielectric layer 8 by photolithography. The lower surface of the holes 9 extends into the barrier layer 4, and the opening size of the holes 9 is 0.2-0.5 μm. The barrier layer 4 material is etched further until the channel layer 3, and penetrates into the channel layer 3 to a certain depth. This depth can be adjusted according to the process level. In this embodiment, the depth of the holes 9 into the channel layer 3 is 0.1-0.5 μm. A second epitaxial growth of P-type GaN material is performed on the upper surface of the wafer. Since P-type GaN material will not grow on the dielectric layer 8, during the second epitaxial growth, the P-type GaN material only grows in the holes 9 and fills the holes 9 completely. At this time, the P-type GaN material grown in the second epitaxial growth constitutes the second gate portion 52, which constitutes an embedded gate.

[0080] Subsequently, metal is deposited on the left and right sides of the second gate portion 52 on the dielectric layer 8 to form the source 6 and drain 7, and metal is deposited on the dielectric layer 8 to form the first gate portion 51, which covers the upper surface of the first gate portion 51 and the surface of the dielectric layer 4 between the first gate portions 51. At this time, the first gate portion 51 constitutes a contact gate.

[0081] It should be noted that before fabricating the first gate portion 51 (contact gate), the dielectric layer 8 in the region between the embedded gates can be removed, so that the region between the first gate portion 51 and the second gate portion 52 can directly contact the barrier layer 4.

[0082] The enhancement-mode HEMT device of this embodiment embeds gates into the channel layer, forming a gate structure composed of spaced embedded gates in the HEMT channel. Since the embedded gates generate a depletion layer of a certain width in the horizontal direction of the communication layer, and the depletion layers of adjacent embedded gates overlap, the 2DEGs in the channel layer between any two adjacent embedded gates are in a depleted state, i.e., the channel is normally off. When a positive voltage is applied to the embedded gate, the depletion layer shrinks. When the depletion layers of adjacent embedded gates separate, the channel layer between them resumes conduction, i.e., the channel is on. By controlling the distance between two adjacent embedded gates and the material properties of the embedded gates, such as the doping concentration of P-type material or the gate metal, the threshold voltage can be modulated, i.e., a larger threshold voltage can be obtained. If the embedded gate is formed of P-type material, there is no threshold voltage drift problem because there is no insulating dielectric layer.

[0083] Furthermore, in the enhanced HEMT device of this embodiment, since the embedded gate is fabricated by etching the device to form a hole followed by secondary epitaxy of P-type material or selective ion implantation or deposition of a medium and metal, its size and spacing can be precisely controlled by the window size defined by the photolithography process, thus easily achieving high uniformity. An embedded gate of a certain depth can also be equivalent to a buried field plate, improving the electric field concentration effect and thereby improving the device's breakdown characteristics. Since the channel's on / off state is mainly controlled by the embedded gate, the control effect of the top gate on the channel is weakened. Therefore, a thicker AlGaN barrier layer can be grown to obtain a higher 2DEG carrier density and reduce the impact of surface defects on the channel layer, thereby reducing the current collapse effect.

[0084] In this embodiment, an array is used to form a comb-shaped embedded gate in the gate region. The area outside the gate region retains the original epitaxial structure. Unlike the solution that etches away a large area of ​​epitaxial region, this method can withstand a larger saturation current. The first gate portion is formed by the structure of barrier layer / dielectric / metal, which can increase the 2DEG concentration in the channel.

[0085] Example 2

[0086] Please see Figure 7 , Figure 8 and Figure 9 , Figure 7 This is a schematic diagram of another enhanced HEMT device with a gate structure provided in an embodiment of the present invention; Figure 8 yes Figure 7 A schematic diagram of a cross-section taken along AA for an enhanced HEMT device; Figure 9 yes Figure 7 A schematic cross-sectional view of an enhancement-mode HEMT device taken along the bottom edge (BB). The enhancement-mode HEMT device includes a substrate layer 1, a buffer layer 2, a channel layer 3, a barrier layer 4, a gate 5, a source 6, and a drain 7, wherein the substrate layer 1, the buffer layer 2, the channel layer 3, and the barrier layer 4 are arranged sequentially from bottom to top.

[0087] Further, the gate 5 includes a first gate portion 51 and a plurality of second gate portions 52, which are arranged side by side and extend from the upper surface of the barrier layer 4 into the channel layer 3. The first gate portion 51 is disposed above the plurality of second gate portions 52 and on the upper surface of the barrier layer 4 between adjacent second gate portions 52, and together with the plurality of second gate portions 52, forms a comb-shaped gate structure. In this embodiment, the spacing between the plurality of second gate portions 52 is uniform.

[0088] In this embodiment, the channel layer 3 can be a single channel or multiple channels, that is, multiple channel layers 3 and multiple barrier layers 4 are repeatedly stacked to form multiple channels. For example Figure 10 , Figure 11 and Figure 12 As shown, in one specific embodiment, the enhancement-mode HEMT device is formed by repeatedly stacking multiple channel layers 3 and multiple barrier layers 4 to form a multi-channel configuration. The channel layers 3 and barrier layers 4 can be GaN-based materials. In this case, the lower ends of the multiple second gate portions 52 all extend into the lowermost channel layer 3, or the lower ends of the second gate portions 52 are close to the interface 2DEG between the lowermost barrier layer and the channel layer.

[0089] The second gate portion 52 is made of P-type doped GaN-based material. The second gate portion 52 can be formed by epitaxial growth or by ion implantation.

[0090] In one specific embodiment, a plurality of parallel holes 9 are provided on the upper surface of the barrier layer 4, and the lower surface of the holes 9 extends into the channel layer 3. The second gate portion 52 is formed in the holes 9 by epitaxial growth. It should be noted that the electric field distribution between the source 6 and the drain 7 can be modulated by controlling the depth and shape of the holes 9, thereby improving the breakdown voltage characteristics and obtaining better breakdown voltage characteristics.

[0091] In another specific embodiment, the second gate portion 52 can be formed in the barrier layer 4 and the channel layer 3 of GaN-based material by ion implantation, thereby forming a second gate portion 52 of p-type doped GaN-based material. Specifically, since both the channel layer 3 and the barrier layer 4 are GaN-based materials, when fabricating the second gate portion 52 on the barrier layer 4, it is not necessary to use etching holes and filling with GaN-based material. Instead, p-type doping of the GaN-based material at the location of the second gate portion 52 can be directly performed by ion implantation to form a second gate portion 52 of p-type doped GaN-based material. In this case, the second gate portion 52 constitutes an embedded gate.

[0092] In this embodiment, the first gate portion 51 includes a GaN-based material layer located below and a metal material layer located above the GaN-based material layer. The GaN-based material in the first gate portion 51 constitutes a GaN-based bus gate, and the metal material layer in the first gate portion 51 constitutes a metal contact gate. In other words, the gate 5 in this embodiment is composed of a GaN-based embedded gate, a GaN-based bus gate, and a metal contact gate.

[0093] The fabrication method of the enhanced HEMT device in this embodiment is as follows:

[0094] A substrate structure is prepared, the substrate structure comprising a substrate layer 1, a buffer layer 2, a channel layer 3 and a barrier layer 4 stacked sequentially from bottom to top; a gate 5, a source 6 and a drain 7 are prepared on the barrier layer 4, the gate 5 having a comb-like structure, including a plurality of second gate portions 52 arranged in parallel in the substrate structure, and a first gate portion 51 disposed above the second gate portions; the source 6 and the drain 7 are respectively located on both sides of the gate 5.

[0095] Taking the epitaxial growth of the second gate portion 52 as an example, a series of holes 9 are formed on the barrier layer 4 by photolithography. The lower surface of the holes 9 extends into the interior of the barrier layer 4, and the opening size of the holes 9 is 0.2-0.5 μm. The barrier layer 4 material is etched further until the channel layer 3 is reached, and penetrates into the channel layer 3 to a certain depth. In this embodiment, the depth of the holes 9 into the channel layer 3 is 0.1-0.5 μm. A second epitaxial growth of P-type GaN material is performed on the upper surface of the barrier layer 4. The P-type GaN material grows throughout the upper surface of the barrier layer 4 and in the holes 9, completely filling the holes 9. The P-type GaN material filling the holes 9 is the second gate portion 52, that is, the GaN material embedded gate.

[0096] Subsequently, the unnecessary P-type GaN material on the upper surface of the barrier layer 4 is removed, leaving only the P-type GaN material covering the inside and above the hole 9 and the area between adjacent holes 9, forming a strip. At this time, the P-type GaN material above the hole 9 and the area between adjacent holes 9 constitutes the GaN material bus gate.

[0097] Next, metal is deposited on the barrier layer 4 to form the source 6 and drain 7, and metal is deposited on the bus gate to form the metal contact gate. Thus, the GaN-based embedded gate, the GaN-based bus gate, and the metal contact gate together constitute the gate.

[0098] In another embodiment of the present invention, a dielectric layer 8 may be disposed in the area on the upper surface of the barrier layer 4 that is not covered by the first gate portion 51, the source 6 and the drain 7.

[0099] Example 3

[0100] Please see Figures 13 to 15 , Figure 13 This is a schematic diagram of another enhanced HEMT device with a gate structure provided in an embodiment of the present invention; Figure 14 yes Figure 13 A schematic diagram of a cross-section taken along the center of the gate of an enhancement-mode HEMT device; Figure 15 yes Figure 13 The enhancement-mode HEMT device does not show a top view of the first gate portion. The enhancement-mode HEMT device of this embodiment includes a substrate layer 1, a buffer layer 2, a channel layer 3, a barrier layer 4, a gate 5, a source 6, and a drain 7, wherein the substrate layer 1, the buffer layer 2, the channel layer 3, and the barrier layer 4 are arranged sequentially from bottom to top.

[0101] A dielectric layer 8 is disposed on the upper surface of the barrier layer 4 in the area not covered by the gate 5, source 6, and drain 7. The dielectric layer 8 can be a single material, such as SiO2, SiN, or SiON, or it can be a dielectric layer composed of different materials such as SiO2, SiN, and Al2O3 grown in different orders.

[0102] The gate 5 includes a first gate portion 51 and a plurality of second gate portions 52. The plurality of second gate portions 52 are arranged in parallel and extend from the upper surface of the barrier layer 4 into the interior of the channel layer 3. The first gate portion 51 is disposed above the plurality of second gate portions 52 and on the upper surface of the barrier layer 4 between adjacent second gate portions 52, and together with the plurality of second gate portions 52, forms a comb-shaped gate structure.

[0103] like Figures 13 to 15 As shown, in this embodiment, the second gate portion 52 includes a P-type GaN material layer located below and around it, and a metal material layer surrounded by the P-type GaN material layer. The P-type GaN material layer in the second gate portion 52 forms a GaN-based embedded gate, and the metal material layer in the second gate portion 52 forms a metal field plate embedded gate. By forming a metal material layer in the second gate portion 52, the electric field distribution between the gate and drain can be smoothed, improving the gate-drain withstand voltage.

[0104] In this embodiment, the second gate portion 52 can be formed by epitaxial growth. Specifically, a plurality of holes 9 are arranged in parallel on the upper surface of the dielectric layer 8, and the lower surface of the holes 9 extends into the channel layer 3. The second gate portion 52 is formed in the holes 9 by epitaxial growth.

[0105] Furthermore, the first gate portion 51 is made of a metallic material, constituting a metal contact gate, and can be prepared using a metal deposition process, such as physical vapor deposition, chemical vapor deposition, or electroplating. In this embodiment, the first gate portion 51 has a T-shaped form in the front view direction, and the first gate portion 51 connects all the second gate portions 52 together to form a comb-shaped gate structure.

[0106] The fabrication method of the enhanced HEMT device in this embodiment is as follows:

[0107] First, a substrate structure is fabricated, comprising a substrate layer 1, a buffer layer 2, a channel layer 3, and a barrier layer 4 stacked sequentially from bottom to top. Subsequently, a dielectric layer 8 is grown on the barrier layer 4. A gate 5, a source 6, and a drain 7 are fabricated on the dielectric layer 8. The gate 5 has a comb-like structure, including a plurality of second gate portions 52 arranged side by side in the substrate structure, and a first gate portion 51 disposed above the second gate portions. The source 6 and the drain 7 are located on opposite sides of the gate 5.

[0108] Specifically, a series of holes 9 are formed on the dielectric layer 8 by photolithography, and the lower surface of the holes 9 extends into the channel layer 3. A second epitaxial growth of P-type material is then performed on the wafer. Since P-type material does not grow on the dielectric layer 8, it only grows within the holes 9 during the second epitaxial growth. After growing a certain thickness of P-type material along the inner surface of the holes 9, the hole size shrinks but the morphology remains essentially unchanged. The gate formed by this P-type material is the GaN-based embedded gate.

[0109] Subsequently, metal is deposited on both sides of dielectric layer 8 to form source electrode 6 and drain electrode 7. Metal is then deposited on dielectric layer 8, covering all exposed P-type material and completely filling the remaining holes 9. A certain thickness of metal is then applied to the upper surface of the dielectric layer. At this point, the metal filling the holes 9 is located on the P-type material within the holes 9, forming a metal field plate embedded gate. Unnecessary metal on the upper surface of the dielectric layer is removed, leaving only the metal above the holes 9 and between adjacent holes, thus forming the first gate portion 51, i.e., the metal contact gate, which covers the GaN-based embedded gate and the metal field plate embedded gate.

[0110] It should be noted that before fabricating the first gate portion 51 (contact gate), the dielectric layer 8 in the region between the embedded gates can be removed, allowing the contact gate to directly contact the barrier layer 4 where there is no embedded gate, such as... Figure 16 As shown.

[0111] In another embodiment of the present invention, before depositing the first gate portion 51, a portion of the dielectric layer 8 between the second gate portions 52 can be etched away, and then metal can be deposited on the remaining dielectric layer 8 between the second gate portions 52 and on the second gate portions 52 to form the first gate portion 51, such that the metal material penetrates into a portion between the second gate portions 52, as shown below. Figure 17 As shown.

[0112] Example 4

[0113] Please see Figure 18 and Figure 19 , Figure 18 This is a schematic diagram of another enhanced HEMT device provided in an embodiment of the present invention; Figure 19 yes Figure 18This is a schematic cross-sectional view of an enhancement-mode HEMT device taken along the center of the gate. The enhancement-mode HEMT device in this embodiment includes a substrate layer 1, a buffer layer 2, a channel layer 3, a barrier layer 4, a gate 5, a source 6, and a drain 7, wherein the substrate layer 1, buffer layer 2, channel layer 3, and barrier layer 4 are arranged sequentially from bottom to top. The substrate layer 1 can be made of materials such as Si, SiC, Al2O3 (sapphire), GaAs, ZnO, LaLiO3, AlN, or GaN. The buffer layer 2 can be made of GaN, and both the channel layer 3 and the barrier layer 4 are GaN-based materials.

[0114] The gate 5 includes a first gate portion 51 and a plurality of second gate portions 52. The plurality of second gate portions 52 are arranged in parallel and extend from the upper surface of the barrier layer 4 into the interior of the channel layer 3. The first gate portion 51 is disposed above the plurality of second gate portions 52 and on the upper surface of the barrier layer 4 between adjacent second gate portions 52, and together with the plurality of second gate portions 52, forms a comb-shaped gate structure.

[0115] In this embodiment, the second gate portion 52 includes a GaN-based material layer located below and around it, and a metal material layer surrounded by the P-type GaN-based material layer. The P-type GaN-based material layer in the second gate portion 52 forms a GaN-based embedded gate, and the metal material layer in the second gate portion 52 forms a metal field embedded gate. The second gate portion 52 in this embodiment can be formed by epitaxial growth. Specifically, a plurality of parallel holes 9 are provided on the upper surface of the barrier layer 8, and the lower surface of the holes 9 extends into the channel layer 3. Both the GaN-based material layer and the metal material layer of the second gate portion 52 are formed within the holes 9.

[0116] Furthermore, the first gate portion 51 includes a GaN-based material layer disposed on a barrier layer 4 between adjacent second gate portions 52, and a metal material layer disposed above the GaN-based material between adjacent second gate portions 52 and above the second gate portions 52, wherein the GaN-based material layer on the barrier layer 4 between adjacent second gate portions 52 constitutes a GaN-based top gate, and the metal material layer in the first gate portion 51 constitutes a metal contact gate.

[0117] The fabrication method of the enhanced HEMT device in this embodiment is as follows:

[0118] First, a substrate structure is fabricated, comprising a substrate layer 1, a buffer layer 2, a channel layer 3, and a barrier layer 4 stacked sequentially from bottom to top. Then, a gate 5, a source 6, and a drain 7 are fabricated on the barrier layer 4. The gate 5 has a comb-like structure, including a plurality of second gate portions 52 arranged side by side in the substrate structure, and a first gate portion 51 disposed above the second gate portions. The source 6 and the drain 7 are located on opposite sides of the gate 5.

[0119] Specifically, a series of holes 9 are formed on the dielectric layer 8 by photolithography, and the lower surface of the holes 9 extends into the channel layer 3. A second epitaxial growth of P-type material is performed on the wafer. The P-type material grows along the inner wall of the holes 9. After a certain thickness of P-type material is grown along the inner surface of the holes 9, the hole size shrinks but the morphology remains basically unchanged. At this point, the gate formed by the P-type material inside the holes is the GaN-based embedded gate, and the P-type material grown on the barrier layer between adjacent holes forms the GaN-based top gate.

[0120] Subsequently, the unnecessary P-type material on the upper surface of the barrier layer 4 is removed, leaving only the P-type material covering the holes 9 and the P-type material in the region between adjacent holes 9. Metal is then deposited on the barrier layer 4 to form the source 6 and drain 7. Next, metal is deposited on the P-type material, covering all the P-type material of the GaN-based embedded gate and the GaN-based top gate and completely filling the remaining holes. At this point, the metal filling the holes constitutes the metal field plate embedded gate, and the metal covering the GaN-based embedded gate, the metal field plate embedded gate, and the GaN-based top gate constitutes the metal contact gate. Therefore, the gate in this embodiment includes four parts: the GaN-based embedded gate, the metal field plate embedded gate, the GaN-based top gate, and the metal contact gate.

[0121] Example 5

[0122] Based on the above embodiments, this embodiment provides another enhanced HEMT device with a gate structure, such as... Figure 20 , Figure 21 and Figure 22 As shown, the enhancement-mode HEMT device includes a substrate layer 1, a buffer layer 2, a channel layer 3, a barrier layer 4, a gate 5, a source 6, and a drain 7. The substrate layer 1, buffer layer 2, channel layer 3, and barrier layer 4 are arranged sequentially from bottom to top. The source 6 and drain 7 are disposed on both sides of the upper surface of the barrier layer 4. A dielectric layer 8 may also be disposed in the area of ​​the upper surface of the barrier layer 4 not covered by the source 6 and drain 7.

[0123] The gate 5 includes a first gate portion 51 and a plurality of second gate portions 52. The plurality of second gate portions 52 are arranged side by side and extend from the upper surface of the barrier layer 4 into the channel layer 3. The first gate portion 51 is disposed on the upper surface of the dielectric layer 8. The upper surfaces of the plurality of second gate portions 52 are all in contact with the lower surface of the dielectric layer 8, while the lower surface of the first gate portion 51 is in contact with the upper surface of the upper surface of the dielectric layer 8. That is, the first gate portion 51 and the plurality of second gate portions 52 are separated by the dielectric layer 8, but still form a comb-shaped gate structure overall. In this embodiment, the top view shape of the plurality of second gate portions 52 is square, and the spacing between them is equal.

[0124] However, in other embodiments, the spacing between the plurality of second gate portions 52 may also be different. When the spacing between adjacent second gate portions 52 is different, the HEMT device may have multiple stepped threshold voltages and multiple stepped maximum saturation currents, thereby forming an effect of equivalent multiple HEMTs integrated in parallel.

[0125] The channel layer 3 can be a single channel or multiple channels, meaning that multiple channel layers 3 and multiple barrier layers 4 are repeatedly stacked to form a multi-channel structure. For example... Figure 22 , Figure 23 and Figure 24 As shown, in one specific embodiment, the enhancement-mode HEMT device is formed by repeatedly stacking multiple channel layers 3 and multiple barrier layers 4 to form a multi-channel configuration. The channel layers 3 and barrier layers 4 can be GaN-based materials. In this case, the lower ends of the multiple second gate portions 52 all extend into the lowermost channel layer 3, or the lower ends of the second gate portions 52 are close to the interface 2DEG between the lowermost barrier layer and the channel layer. The multiple second gate portions 52 are in a floating electrode state.

[0126] In this embodiment, the first gate portion and multiple second gate portions can be individually connected to control signals. The second gate portions mainly exert influence on the channel region from both sidewalls in the recessed area, while the first gate portions mainly exert influence on the channel above the channel region. Therefore, by connecting control signals separately, further modulation of the threshold voltage can be achieved, and more modes of the modulating device's operating region can be obtained. For example, by connecting the second gate portion to a signal with a fixed potential and using the first gate portion as the gate input electrode of the transistor, the modulation effect of the gate on the channel is also affected by the fixed potential signal of the second gate portion. Changing the voltage value of the fixed potential signal of the second gate portion can obtain different device operating modes. Similarly, when the gate threshold voltage of the device drifts, or when there is a need to adjust the threshold voltage according to the circuit design, it is not necessary to replace the transistor; only the magnitude of the fixed potential signal connected to the second gate portion needs to be adjusted to achieve the same purpose.

[0127] Furthermore, when the second gate portion is also connected to a continuously varying input signal, in conjunction with the gate input signal connected to the first gate portion, the voltages of the two signals acting simultaneously on the channel can cause changes in the current-voltage characteristic curve of the device, such as enhancing the linearity of the device in certain operating regions or increasing transconductance.

[0128] Example 6

[0129] Please see Figures 26 to 28This embodiment provides another enhancement-mode HEMT device with a gate structure. The enhancement-mode HEMT device includes a substrate layer 1, a buffer layer 2, a channel layer 3, a barrier layer 4, a gate 5, a source 6, and a drain 7. The substrate layer 1, the buffer layer 2, the channel layer 3, and the barrier layer 4 are arranged sequentially from bottom to top. The source 6 and the drain 7 are disposed on both sides of the upper surface of the barrier layer 4. A dielectric layer 8 may also be disposed in the area of ​​the upper surface of the barrier layer 4 that is not covered by the source 6 and the drain 7.

[0130] like Figure 26 As shown, the gate 5 includes a first gate portion 51 and a plurality of second gate portions 52. The main body of the first gate portion 51 is disposed on the upper surface of the dielectric layer 8, and the lower surface of the first gate portion 51 includes a protrusion extending into the interior of the dielectric layer 8.

[0131] Multiple second gate portions 52 are arranged side by side. The upper half of each second gate portion 52 is disposed inside the dielectric layer 8 and located between adjacent protrusions of the first gate portion 51. The lower half of each second gate portion 52 extends from the upper surface of the barrier layer 4 into the channel layer 3. The first gate portion 51 and the multiple second gate portions 52 are spaced apart by the dielectric layer 8.

[0132] The channel layer 3 can be a single channel or multiple channels, meaning that multiple channel layers 3 and multiple barrier layers 4 are repeatedly stacked to form a multi-channel structure. For example... Figure 29 , Figure 30 and Figure 31 As shown, in one specific embodiment, the enhancement-mode HEMT device is formed by repeatedly stacking multiple channel layers 3 and multiple barrier layers 4 to form a multi-channel configuration. The channel layers 3 and barrier layers 4 can be GaN-based materials. In this case, the lower ends of the multiple second gate portions 52 all extend into the lowermost channel layer 3, or the lower ends of the second gate portions 52 are close to the interface 2DEG between the lowermost barrier layer and the channel layer.

[0133] Example 7

[0134] Please see Figures 32 to 34 This embodiment provides another enhancement-mode HEMT device with a gate structure. The enhancement-mode HEMT device includes a substrate layer 1, a buffer layer 2, a channel layer 3, a barrier layer 4, a gate 5, a source 6, and a drain 7. The substrate layer 1, the buffer layer 2, the channel layer 3, and the barrier layer 4 are arranged sequentially from bottom to top. The source 6 and the drain 7 are disposed on both sides of the upper surface of the barrier layer 4. A dielectric layer 8 may also be disposed in the area of ​​the upper surface of the barrier layer 4 that is not covered by the source 6 and the drain 7.

[0135] In this embodiment, the gate 5 includes a first gate portion 51 and a plurality of second gate portions 52. The main body of the first gate portion 51 is disposed on the upper surface of the dielectric layer 8, and the lower surface of the first gate portion 51 includes a protrusion extending into the interior of the dielectric layer 8.

[0136] Multiple second gate portions 52 are arranged side by side. The upper half of each second gate portion 52 is disposed inside the dielectric layer 8 and located between adjacent protrusions of the first gate portion 51. The lower half of each second gate portion 52 extends from the upper surface of the barrier layer 4 into the channel layer 3. The first gate portion 51 and the multiple second gate portions 52 are spaced apart by the dielectric layer 8.

[0137] The only difference between this embodiment and embodiment six is ​​that each second gate portion 52 is an independently led-out gate to form gate 2, and the first gate portion is gate 1. Gate 1 and gate 2 can be connected to two independent input electrodes respectively. The channel can be controlled by controlling the potential difference between gate 1 and gate 2.

[0138] In one specific embodiment, the enhancement-mode HEMT device is formed by repeatedly stacking multiple channel layers 3 and multiple barrier layers 4 to form a multi-channel configuration. The channel layers 3 and barrier layers 4 can be GaN-based materials. In this case, the lower ends of the multiple second gate portions 52 all extend into the bottommost channel layer 3, or the lower ends of the second gate portions 52 are close to the interface 2DEG between the bottommost barrier layer and the channel layer.

[0139] Furthermore, it should be noted that the structures described in the above embodiments are not only applicable to the fabrication of enhancement-mode HEMT devices, but also to depletion-mode HEMT devices.

[0140] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0141] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0142] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. An enhancement-mode HEMT device with a gate structure, characterized in that, It includes a substrate layer (1), a buffer layer (2), a channel layer (3), a barrier layer (4), a gate (5), a source (6), and a drain (7), wherein, The substrate layer (1), the buffer layer (2), the channel layer (3) and the barrier layer (4) are arranged sequentially from bottom to top. A dielectric layer (8) is provided on the upper surface of the barrier layer (4) in the area not covered by the source (6) and the drain (7). The gate (5) includes a first gate portion (51) and a plurality of second gate portions (52). The plurality of second gate portions (52) are arranged side by side and extend from the upper surface of the barrier layer (4) into the interior of the channel layer (3). The upper surfaces of the plurality of second gate portions (52) are in contact with the lower surface of the dielectric layer (8). The first gate portion (51) is disposed above the plurality of second gate portions (52) and between adjacent second gate portions (52). The lower surface of the first gate portion (51) is in contact with the upper surface of the dielectric layer (8). Alternatively, the gate (5) includes a first gate portion (51) and a plurality of second gate portions (52). The lower surface of the gate portion (51) includes a plurality of downwardly extending protrusions, each protrusion correspondingly extending into the dielectric layer (8) between adjacent second gate portions (52). The plurality of second gate portions (52) are arranged side by side, and the upper half of each second gate portion (52) is disposed inside the dielectric layer (8) and located between adjacent protrusions of the first gate portion (51). The lower half of each second gate portion (52) extends from the upper surface of the barrier layer (4) into the channel layer (3). The first gate portion (51) and the plurality of second gate portions (52) are spaced apart by the dielectric layer (8), and each second gate portion (52) is an independently led-out gate.

2. The enhanced HEMT device according to claim 1, characterized in that, Both the channel layer (3) and the barrier layer (4) are GaN-based materials.

3. The enhancement-mode HEMT device with a gate structure according to claim 2, characterized in that, The second gate portion (52) is a P-type doped GaN material, or a stacked structure of P-type doped and N-type doped GaN materials; the first gate portion (51) is made of a metal material.

4. The enhancement-mode HEMT device with a gate structure according to claim 1, characterized in that, A plurality of holes (9) are arranged in parallel on the upper surface of the barrier layer (4), and the lower surface of the holes (9) extends into the interior of the channel layer (3). The second gate portion (52) is formed in the holes (9) by epitaxial growth.

5. The enhancement-mode HEMT device with a gate structure according to claim 1, characterized in that, The second gate portion (52) is formed in the barrier layer (4) and the channel layer (3) by ion implantation.

6. The enhancement-mode HEMT device with a gate structure according to claim 1, characterized in that, The second gate portion (52) is made of a P-type doped GaN material; the first gate portion (51) includes a GaN material layer located below and a metal material layer located above the GaN material layer.

7. The enhancement-mode HEMT device with a gate structure according to claim 1, characterized in that, The second gate portion (52) includes a P-type GaN material layer located below and around it, and a metal material layer surrounded by the P-type GaN material layer; the first gate portion (51) is made of metal material.

8. The enhancement-mode HEMT device with a gate structure according to claim 1, characterized in that, The second gate portion (52) includes a P-type GaN material layer located below and around it, and a metal material layer surrounded by the P-type GaN material layer; The first gate portion (51) includes a GaN-based material layer disposed on a barrier layer (4) between adjacent second gate portions (52), and a metal material layer disposed above the GaN-based material between adjacent second gate portions (52) and above the second gate portion (52).

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