Silicon carbide semiconductor device and power conversion device

Abstract

A silicon carbide semiconductor device and a power conversion device are provided. In a SiC-MOSFET with a built-in Schottky diode, the second well region formed at the terminal sometimes experiences bipolar current conduction, resulting in a reduced breakdown voltage. In the SiC-MOSFET with a built-in Schottky diode, a conductive layer connected to the Schottky of the second well region is provided on the second well region formed at the terminal, electrically connecting the conductive layer to the source electrode of the MOSFET. A conductive layer contact hole is provided that connects only the conductive layer and the source electrode.

Description

[0001] This application is a divisional application of patent application No. 201880012296.5, filed on February 22, 2018, entitled "Silicon Carbide Semiconductor Device and Power Conversion Device". Technical Field

[0002] This invention relates to silicon carbide semiconductor devices and power conversion devices. Background Technology

[0003] It is known that when a bipolar current continuously flows through a pn diode made of silicon carbide (SiC), a reliability problem arises due to the formation of stacking defects in the crystal, leading to a shift in the forward voltage. This is believed to be caused by the recombination energy of minority and majority carriers injected through the pn diode. Starting from surface misalignments or other defects on the silicon carbide substrate, these stacking defects propagate as planar defects. These defects impede current flow, resulting in a decrease in current and an increase in forward voltage, thus reducing the reliability of the semiconductor device.

[0004] This increase in forward voltage also occurs in silicon carbide vertical MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). Vertical MOSFETs have a parasitic pn diode (body diode) between the source and drain; when forward current flows through this body diode, it causes the same reliability degradation as with pn diodes in vertical MOSFETs. When the body diode of a SiC-MOSFET is used as the freewheeling diode of the MOSFET, it sometimes results in a degraded MOSFET performance.

[0005] One method to address reliability issues caused by forward current flowing through parasitic pn diodes, as described above, is as described in Patent Document 1, which involves applying pressure to the parasitic pn diode for an extended period, measuring the change in forward voltage before and after the pressure application, and eliminating (screening out) components with large changes in forward voltage from the product pipeline. However, this method suffers from the drawback of prolonged energizing time, resulting in a large number of defective products when using wafers with numerous defects.

[0006] Alternatively, another method involves embedding a unipolar diode as a freewheeling diode in a semiconductor device such as a MOSFET, which is a unipolar transistor. For example, Patent Documents 2 and 3 describe a method of embedding a Schottky barrier diode (SBD) as a unipolar diode within a unit cell of a MOSFET.

[0007] When a unipolar transistor with a built-in unipolar diode (i.e., a diode that is energized only by majority carriers) in the active region is applied to a silicon carbide semiconductor device, by designing the diffusion potential of the unipolar diode (i.e., the voltage at which the energizing operation begins) to be lower than the diffusion potential of the pn junction, it is possible to prevent bipolar current from flowing through the body diode during freewheeling operation, thereby suppressing the degradation of the characteristics of the unipolar transistor in the active region.

[0008] Furthermore, as in Patent Document 4, an n-type channel epitaxial layer is formed on the p-type well region where the active region is formed. This channel epitaxial layer operates as a unipolar diode at a gate voltage below the threshold voltage. Furthermore, in a MOSFET where the rise voltage of this unipolar diode is designed to be lower than the operating voltage of a pn diode formed from a p-type well region and an n-type drift layer, the same effect as a MOSFET with a built-in SBD can be expected. This MOSFET can also be considered one of the unipolar transistors that integrates a unipolar diode in the active region.

[0009] However, even in unipolar transistors with a built-in unipolar diode in the active region, there are sometimes parasitic pn diodes formed in the terminal region, i.e., outside the active region, where it is difficult to construct a unipolar diode.

[0010] For example, a terminal well region protruding outward from the source electrode is formed in the region near the gate pad and the end of the semiconductor device, and a parasitic pn diode is formed between the terminal well region and the drift layer. Furthermore, no Schottky electrode is formed in this region, and no unipolar diode is formed. Since there is no Schottky electrode in the terminal well region, a voltage between the source and drain electrodes is applied to the pn diode formed by the terminal well region and the drift layer, and a bipolar current flows through the pn diode.

[0011] When substrate misalignment or other starting points exist in such locations, stacking defects can sometimes propagate and reduce the transistor's withstand voltage. Specifically, leakage current is generated when the transistor is in the off state, and sometimes the heat generated by the leakage current can damage components and circuits.

[0012] To avoid this problem, it is necessary to prevent bipolar current from flowing in the pn diode formed by the terminal well region and the drift layer. For example, the applied voltage between the source and drain can be limited to a certain value during semiconductor device operation. This can be achieved by increasing the chip size to reduce the differential resistance of the built-in SBD per chip, thereby reducing the source-drain voltage generated when freewheeling current flows. However, this results in the disadvantage of increased chip size and cost.

[0013] Furthermore, as a method to suppress the forward operation of a pn diode formed by a terminal well region and a drift layer without increasing the chip size, one approach is to increase the resistance of the current-carrying path formed between each part of the terminal well region and the source electrode. Among the methods for increasing the resistance of the current-carrying path are methods that increase the contact resistance between the terminal well region and the source electrode (e.g., Patent Document 5). According to this structure, when a bipolar current flows through the pn diode formed by the terminal well region and the drift layer, a voltage drop occurs due to the resistive component of the contact resistance, causing the potential of the terminal well region to deviate from the source potential, and consequently reducing the forward voltage applied to the pn diode. Therefore, the conduction of the bipolar current can be suppressed.

[0014] Furthermore, as a particularly prominent phenomenon in wide-bandgap semiconductor devices represented by silicon carbide, it is known that devices can sometimes be damaged due to displacement current flowing through the well region during switching. When switching in a silicon carbide semiconductor device with a MOS structure, displacement current flows in the planar direction of the device within the relatively large p-type well region. Due to this displacement current and the thin-film resistance of the well region, a high voltage is generated within the well region. Moreover, this causes insulation breakdown of the insulating film between the device and the electrode formed on the well region, thus damaging the device. For example, when the potential variation in the well region is 50V or more, and a gate electrode with a potential of approximately 0V is formed on it through a 50nm thick silicon oxide film, sometimes a high electric field such as 10MV / cm is applied to the silicon oxide film, causing insulation breakdown.

[0015] The reason why this phenomenon occurs significantly in wide-bandgap semiconductor devices, such as silicon carbide, is based on the following two reasons.

[0016] One reason is that the impurity energy levels in the p-type well region formed in wide-bandgap semiconductors such as silicon carbide are deeper than those in the p-type well region formed in silicon, so the sheet resistance of the p-type well region in wide-bandgap semiconductors is much higher than that in silicon.

[0017] Another reason is that by utilizing the higher insulation breaking electric field of wide bandgap semiconductors compared to silicon semiconductors, and by using an n-type drift layer with low resistance and high impurity concentration in wide bandgap semiconductors, the capacitance of the depletion layer formed in the pn junction between the n-type drift layer and the p-type well region is much larger in wide bandgap semiconductors than in silicon. As a result, a large displacement current flows during switching.

[0018] The higher the switching speed, the greater the displacement current, and the higher the voltage generated in the well region. However, as a method to reduce the voltage generated by this displacement current, for example, a method of forming a low-resistance p-type layer in a part of the p-type well region has been proposed (e.g., Patent Document 6).

[0019] Existing technical documents

[0020] Patent documents

[0021] Patent Document 1: Japanese Patent Application Publication No. 2014-175412

[0022] Patent Document 2: Japanese Patent Application Publication No. 2003-017701

[0023] Patent Document 3: WO2014-038110 International Publication

[0024] Patent Document 4: WO2013-051170 International Publication

[0025] Patent Document 5: WO2014-162969 International Publication

[0026] Patent Document 6: WO2010-098294 International Publication Summary of the Invention

[0027] As previously explained, there are issues such as the problem that to suppress the bipolar current flow during freewheeling operation in the terminal well region, it is best to increase the planar resistance of the terminal well region; and the problem that to reduce the voltage generated by the displacement current flowing through the well region, which is of equal area to the terminal well region, during switching, it is best to decrease the planar resistance of the well region. Because of these contradictory issues, previously, a method was unknown to simultaneously solve the problems of reducing bipolar current during freewheeling operation and preventing component damage during switching.

[0028] The present invention was made to solve the problems described above, and its object is to provide a silicon carbide semiconductor device with improved reliability that reduces bipolar current during freewheeling operation and suppresses component damage during switching.

[0029] This invention provides a silicon carbide semiconductor device comprising: a silicon carbide semiconductor substrate of a first conductivity type; a drift layer of the first conductivity type formed on the semiconductor substrate; a first well region of a second conductivity type disposed on the surface layer of the drift layer; a first exit region of the first conductivity type formed penetrating through the surface of the first well region in a depth direction; a source region of the first conductivity type formed on the surface layer of the first well region; a first Schottky electrode disposed on the first exit region and schottky-bonded to the first exit region; an ohmic electrode disposed on the first well region and ohmically connected to the first well region; and a gate insulating film formed on the first... The drift layer comprises: a second well region of a second conductivity type, independently disposed on the surface of the drift layer from the first well region; a gate electrode formed on the gate insulating film on the first well region and on the insulating film disposed on the second well region; a gate pad formed above the second well region and connected to the gate electrode; a conductive layer formed above the bottom surface of the second well region in a manner not ohmically connected to the second well region, and having a lower sheet resistance than the second well region; a source electrode connected to the first Schottky electrode, the ohmic electrode, and the conductive layer; and a conductive layer contact hole that ohmically connects the conductive layer and the source electrode but does not ohmically connect the conductive layer and the second well region.

[0030] The silicon carbide semiconductor device according to the present invention can reduce bipolar current during freewheeling operation, suppress component damage during switching, and improve component reliability. Attached Figure Description

[0031] Figure 1 This is a plan view of the silicon carbide semiconductor device according to Embodiment 1 of the present invention, viewed from above.

[0032] Figure 2 This is a schematic cross-sectional view of the silicon carbide semiconductor device according to Embodiment 1 of the present invention.

[0033] Figure 3 This is a plan view of the silicon carbide semiconductor device according to Embodiment 1 of the present invention.

[0034] Figure 4 This is a plan view of other structures of the silicon carbide semiconductor device according to Embodiment 1 of the present invention.

[0035] Figure 5 This is a cross-sectional schematic diagram of other structures of the silicon carbide semiconductor device according to Embodiment 1 of the present invention.

[0036] Figure 6 This is a plan view of other structures of the silicon carbide semiconductor device according to Embodiment 1 of the present invention.

[0037] Figure 7This is a plan view of other structures of the silicon carbide semiconductor device according to Embodiment 1 of the present invention.

[0038] Figure 8 This is a cross-sectional schematic diagram of other structures of the silicon carbide semiconductor device according to Embodiment 1 of the present invention.

[0039] Figure 9 This is a cross-sectional schematic diagram of the silicon carbide semiconductor device according to Embodiment 2 of the present invention.

[0040] Figure 10 This is a cross-sectional schematic diagram of the silicon carbide semiconductor device according to Embodiment 2 of the present invention.

[0041] Figure 11 This is a cross-sectional schematic diagram of the silicon carbide semiconductor device according to Embodiment 3 of the present invention.

[0042] Figure 12 This is a cross-sectional schematic diagram of the silicon carbide semiconductor device according to Embodiment 4 of the present invention.

[0043] Figure 13 This is a cross-sectional schematic diagram of the silicon carbide semiconductor device according to Embodiment 5 of the present invention.

[0044] Figure 14 This is a schematic cross-sectional view of the silicon carbide semiconductor device according to Embodiment 6 of the present invention.

[0045] Figure 15 This is a schematic cross-sectional view of the silicon carbide semiconductor device according to Embodiment 6 of the present invention.

[0046] Figure 16 This is a plan view of the silicon carbide semiconductor device according to Embodiment 6 of the present invention.

[0047] Figure 17 This is a schematic cross-sectional view of the silicon carbide semiconductor device according to Embodiment 7 of the present invention.

[0048] Figure 18 This is a plan view of the silicon carbide semiconductor device according to Embodiment 8 of the present invention.

[0049] Figure 19 This is a cross-sectional schematic diagram of the silicon carbide semiconductor device according to Embodiment 9 of the present invention.

[0050] Figure 20 This is a cross-sectional schematic diagram of a silicon carbide semiconductor device with other structures according to Embodiment 9 of the present invention.

[0051] Figure 21 This is a plan view of a silicon carbide semiconductor device with other structures according to Embodiment 9 of the present invention.

[0052] Figure 22 This is a plan view of a silicon carbide semiconductor device with other structures according to Embodiment 9 of the present invention.

[0053] Figure 23 This is a schematic cross-sectional view of the silicon carbide semiconductor device according to Embodiment 10 of the present invention.

[0054] Figure 24 This is a schematic diagram illustrating the structure of the power conversion device according to Embodiment 11 of the present invention.

[0055] (Symbol Explanation)

[0056] 10: Semiconductor substrate; 20: Drift layer; 21: First departure region; 22: Second departure region; 23: Third departure region; 24: Fourth departure region; 25: Fifth departure region; 30: First well region; 31: Second well region; 32: Contact region; 33: Electric field mitigation layer; 34: Auxiliary connection region; 37: JTE region; 40: Source region; 45: Silicon carbide conductive layer; 47: Conductive layer; 49: Channel epitaxial layer; 50: Gate insulating film; 51: Field insulating film; 53: Insulating layer; 55: Interlayer insulating film; 6 0: Gate electrode; 70: Ohmic electrode; 71: First Schottky electrode; 73: Second Schottky electrode; 80: Source electrode, source pad; 81: Gate pad; 82: Gate wiring; 84: Drain electrode; 90: First well region contact hole; 91: Conductive layer contact hole; 92: Second well region contact hole; 93: Schottky contact hole; 94: Schottky contact hole in the second well region; 95: Gate contact hole; 100: Power supply; 200: Power conversion device; 201: Main conversion circuit; 202: Drive circuit; 203: Control circuit; 300: Load. Detailed Implementation

[0057] Hereinafter, embodiments will be described with reference to the accompanying drawings. Furthermore, the drawings are schematic illustrations, and the dimensions and positions of the images shown in different drawings may not be accurately depicted and can be appropriately varied. Additionally, in the following description, the same reference numerals are used to illustrate the same constituent elements, and their names and functions are also the same. Therefore, detailed descriptions of them are sometimes omitted.

[0058] In the embodiments described in this specification, as an example of a semiconductor device, an n-channel silicon carbide MOSFET with the first conductivity type set to n-type and the second conductivity type set to p-type will be used as an example for explanation. The description of the potential level is for the case where the first conductivity type is set to n-type and the second conductivity type is set to p-type. When the first conductivity type is set to p-type and the second conductivity type is set to n-type, the description of the potential level is reversed.

[0059] Furthermore, the region outside the active region, which is periodically arranged as unit cells in the overall semiconductor device, is referred to in this application as the terminal region.

[0060] Implementation method 1.

[0061] First, the structure of the silicon carbide semiconductor device according to Embodiment 1 of the present invention will be described.

[0062] Figure 1 This is a planar schematic diagram of the silicon carbide semiconductor device with a Schottky diode (SBD) integrated into a silicon carbide MOSFET (SBD integrated with SiC-MOSFET) as described in Embodiment 1, viewed from above. Figure 1 In this SiC-MOSFET, a gate pad 81 is formed on a portion of the upper surface, and an active electrode 80 is formed adjacent to it. In addition, a gate wiring 82 is formed extending from the gate pad 81.

[0063] Figure 2 It is shown schematically. Figure 1 A cross-sectional schematic diagram of the a-a' portion of the gate wiring 82 from the source electrode 80 to the outer periphery of the silicon carbide semiconductor device. Additionally, Figure 3 yes Figure 1 The top view is a planar schematic diagram of the main silicon carbide semiconductor portion.

[0064] exist Figure 2 In this process, a drift layer 20, also made of n-type silicon carbide, is formed on the surface of a semiconductor substrate 10 made of n-type, low-resistivity silicon carbide. This drift layer 20 is located on the surface of a semiconductor substrate 10 with an n-type silicon carbide substrate. Figure 1 The area of ​​the gate wiring 82 described in the diagram roughly corresponds to the surface portion of the drift layer 20, such as... Figure 3 As shown, a second well region 31 composed of p-type silicon carbide is provided.

[0065] In the settings Figure 1In the lower part of the source electrode 80 region described herein, on the surface of the drift layer 20, a plurality of first well regions 30 composed of p-type silicon carbide are provided. On the surface of each of the first well regions 30, at a predetermined interval from the outer periphery of the first well region 30 inward, a source region 40 composed of n-type silicon carbide is formed.

[0066] In the surface portion of the first well region 30, further inside the source region 40 of the surface portion of each first well region 30, a contact region 32 made of low-resistance, p-type silicon carbide is formed. Further inside this contact region, a first exit region 21 made of silicon carbide is formed, penetrating the first well region 30. The first exit region 21 is n-type, the same as the drift layer 20. The n-type impurity concentration of the first exit region 21 can be the same as, higher than, or lower than the n-type impurity concentration of the drift layer 20.

[0067] A first Schottky electrode 71 is formed on the surface side of the first departure region 21, and is Schottky connected to the first departure region 21. Here, the first Schottky electrode 71 is preferably formed in such a way that it includes at least the corresponding first departure region 21 when viewed from above.

[0068] Furthermore, an ohmic electrode 70 is formed on the surface of the source region 40, and a source electrode 80, connected to the ohmic electrode 70, the first Schottky electrode 71, and the contact region 32, is formed on the ohmic electrode 70, the first Schottky electrode 71, and the contact region 32. The first well region 30 can easily accept and accept electrons and holes with the ohmic electrode 70 through the low-resistance contact region 32.

[0069] The region of the drift layer 20 between adjacent first well regions 30 is called the second n-type exit region 22. The n-type impurity concentration of the second exit region 22 can be the same as, higher than or lower than, the n-type impurity concentration of the drift layer 20. A gate insulating film 50 is formed on the surface of adjacent first well regions 30, the second exit regions 22 therebetween, and the source region 40 within each first well region 30. A gate electrode 60 is formed on at least the upper part of the first well region 30 on the gate insulating film 50. The surface portion of the first well region 30 opposite to the location where the gate electrode 60 is formed, separated by the gate insulating film 50, is called the channel region.

[0070] A second well region 31 is formed outside the first well region 30 at the outermost periphery of the silicon carbide semiconductor device. A third exit region 23 is formed between the first well region 30 and the second well region 31. The third exit region 23 is n-type, the same as the drift layer 20. The n-type impurity concentration of the third exit region 23 can be the same as the n-type impurity concentration of the drift layer 20, or it can be higher or lower than the n-type impurity concentration of the drift layer 20.

[0071] Additionally, a gate insulating film 50 is also formed on the second well region 31, and a gate electrode 60 electrically connected to the gate electrode 60 formed on the first well region 30 is formed on the upper part of the gate insulating film 50.

[0072] A conductive layer 47 is formed over a large portion of the surface of the second well region 31. The conductive layer 47 is made of a material with a thin-film resistivity lower than that of the second well region 31 and which provides an ohmic connection to the p-type second well region 31. The conductive layer 47 is formed across more than half the width of the cross-section of the second well region 31. The portion of the cross-section of the second well region 31 where the conductive layer 47 is formed need not be the entire cross-section; it may only be a portion of the cross-section.

[0073] Alternatively, the conductive layer 47 can be made of, for example, polycrystalline silicon material with a thickness of 50 nm or more and 1000 nm or less.

[0074] The conductivity type of the polysilicon conductive layer 47 can be either n-type or p-type, but it is set to n-type here. Furthermore, regardless of whether the polysilicon conductive layer 47 is n-type or p-type, it is referred to as a Schottky connection for the second well region 31 composed of 4H-SiC.

[0075] The reason is that the valence band of silicon carbide is at a deeper energy level than that of silicon. Therefore, when silicon carbide and polycrystalline silicon come into contact, the valence band of silicon carbide has a larger potential barrier height than the charge carriers (electrons and holes) in polycrystalline silicon.

[0076] In this case, when a voltage above the diffusion potential of the Schottky connection between the second well region 31 and the conductive layer 47 is applied to the Schottky connection, holes, which are majority carriers in the second well region 31, can move toward the source electrode 80. Conversely, the injection of holes, which are majority carriers in the second well region 31, from the source electrode 80 toward the second well region 31 via the conductive layer 47 can be cut off.

[0077] Furthermore, an interlayer insulating film 55 is formed between the gate electrode 60 and the source electrode 80. The gate electrode 60 and the gate wiring 82 above the second well region 31 are connected via gate contact holes 95 formed in the interlayer insulating film 55. Additionally, a p-type silicon carbide JTE region 37 is formed on the outer periphery of the second well region 31, opposite to the first well region 30. The impurity concentration of the JTE region 37 is assumed to be lower than that of the second well region 31.

[0078] A field insulating film 51 or a gate insulating film 50 with a thickness greater than that of the gate insulating film 50 is formed on the second well region 31 and on the conductive layer 47 formed thereon. An opening, namely a conductive layer contact hole 91, is formed on a portion of the gate insulating film 50 or the field insulating film 51 on the surface of the conductive layer 47, through which the conductive layer 47 is ohmically connected to the source electrode 80 formed thereon. The conductive layer contact hole 91 is configured to also penetrate the interlayer insulating film 55, thereby ohmically connecting the conductive layer 47 and the source electrode 80, but not connecting the conductive layer 47 to the second well region 31. Furthermore, the conductive layer 47 has an area larger than the diameter of the conductive layer contact hole 91.

[0079] Here, it is assumed that the second well region 31 is not directly ohmically connected to the source electrode 80.

[0080] In the active region, the ohmic electrode 70, the first Schottky electrode 71, and the source electrode 80 on the contact region 32 are connected to the source electrode 80 on the interlayer insulating film 55 via the first well region contact hole 90 formed through the interlayer insulating film 55 and the gate insulating film 50.

[0081] A drain electrode 84 is formed on the back side of the semiconductor substrate 10.

[0082] Next, the manufacturing method of the SBD-embedded SiC-MOSFET of the silicon carbide semiconductor device of this embodiment will be described.

[0083] First, on a semiconductor substrate 10 consisting of n-type and low-resistivity silicon carbide with an off-angle (0001) plane and a 4H polytype on the first main plane, chemical vapor deposition (CVD) is used to deposit silicon carbide with an impurity concentration of 1×10⁻⁶. 15 Up to 1×10 17 cm -3 Furthermore, an n-type drift layer 20 composed of silicon carbide with a thickness of 5 to 50 μm is epitaxially grown.

[0084] Next, in a predetermined area on the surface of the drift layer 20, an implantation mask is formed using a photoresist or the like, and Al (aluminum) as a p-type impurity is ion implanted. At this time, the depth of Al ion implantation is set to be no more than 0.5 to 3 μm of the thickness of the drift layer 20. Furthermore, the impurity concentration of the ion-implanted Al is 1 × 10⁻⁶. 17 Up to 1×10 19 cm -3 The range is higher than the impurity concentration of drift layer 20. Afterwards, the implantation mask is removed. The regions implanted with Al ions through this process become the first well region 30 and the second well region 31.

[0085] Next, an implantation mask is formed on the surface of the drift layer 20 using a photoresist or similar agent, and Al ions are implanted at a p-type impurity concentration. The depth of Al ion implantation is set to be no more than 0.5 to 3 μm beyond the thickness of the drift layer 20. Furthermore, the impurity concentration of the implanted Al is 1 × 10⁻⁶. 16 Up to 1×10 18 cm -3 The impurity concentration is higher than that of the drift layer 20 but lower than that of the first well region 30. Afterwards, the implantation mask is removed. The region where Al ions are implanted through this process becomes the JTE region 37. Similarly, by implanting Al ions into a predetermined region at a higher impurity concentration than that of the first well region 30, a contact region 32 is formed.

[0086] Next, by forming an implantation mask using a photoresist or the like to open a predetermined portion inside the first well region 30 on the surface of the drift layer 20, N (nitrogen) as an n-type impurity is implanted. The ion implantation depth of N is set to be shallower than the thickness of the first well region 30. Furthermore, the impurity concentration of the implanted N is set to 1 × 10⁻⁶. 18 Up to 1×10 21 cm -3 The range exceeds the p-type impurity concentration in the first well region 30. The region exhibiting n-type characteristics within the N-type region implanted in this process becomes the source region 40.

[0087] Next, the ion-implanted N and Al are annealed for 30 seconds to 1 hour in an inert gas atmosphere such as argon (Ar) using a heat treatment apparatus at a temperature of 1300 to 1900°C. This annealing process electroactivates the ion-implanted N and Al.

[0088] Next, a conductive layer 47 made of n-type polysilicon is formed on the second well region 31 using CVD, photolithography, and the like. In addition, a field insulating film 51 made of silicon oxide with a thickness of 0.5 to 2 μm is formed on the semiconductor layer in the region other than the active region that roughly corresponds to the region where the first well region 30 is formed, using CVD, photolithography, and the like.

[0089] Next, the silicon carbide surface not covered by the field insulating film 51 is thermally oxidized to form a silicon oxide film of the desired thickness for the gate insulating film 50. Then, a conductive polycrystalline silicon film is formed on the gate insulating film 50 and the field insulating film 51 by reduced-pressure CVD, and patterned to form the gate electrode 60. Next, an interlayer insulating film 55 made of silicon oxide is formed by reduced-pressure CVD. Then, a first well region contact hole 90 is formed through the interlayer insulating film 55 and the gate insulating film 50, reaching the contact region 32 and the source region 40 within the active region, and a conductive layer contact hole 91 is formed, reaching the conductive layer 47.

[0090] Next, after forming a Ni-based metal film using methods such as sputtering, a heat treatment at 600 to 1100°C is performed to react the Ni-based metal film with the silicon carbide layer within the contact hole 90 of the first well region, forming a silicide between the silicon carbide layer and the metal film. Then, the remaining metal film, excluding the silicide formed by the reaction, is removed by wet etching. The remaining silicide then becomes the ohmic electrode 70. Thus, the ohmic electrode 70 is formed.

[0091] Next, a back ohmic electrode (not shown) is formed on the back side of the semiconductor substrate 10 by forming a metal film with Ni as the main component on the back side (second main surface) and performing heat treatment.

[0092] Next, using a pattern formed with a photoresist or the like, the interlayer insulating film 55 and the gate insulating film 50 on the first departure region 21 are removed, as well as the interlayer insulating film 55 at the location of the gate contact hole 95. The removal method is a wet etching that does not damage the surface of the silicon carbide layer that forms the Schottky interface.

[0093] Next, a metal film that forms a Schottky electrode is deposited by sputtering or the like, and a first Schottky electrode 71 is formed on the first exit region 21 within the first well region contact hole 90 using a pattern made with a photoresist or the like.

[0094] Next, by sputtering or vapor deposition, wiring metal such as Al is formed on the surface of the previously processed substrate, and then processed into a predetermined shape using photolithography, an ohmic electrode 70, a first Schottky electrode 71, a source electrode 80 in contact with the conductive layer 47, and a gate pad 81 and gate wiring 82 in contact with the gate electrode 60 are formed on the source side.

[0095] Furthermore, if a drain electrode 84, which serves as a metal film, is formed on the surface of the back ohmic electrode (not shown) formed on the back side of the substrate, then a drain electrode 84 is formed. Figures 1-3 The silicon carbide semiconductor device of this embodiment is shown.

[0096] Next, the operation of the SBD-embedded SiC-MOSFET in the silicon carbide semiconductor device of this embodiment will be explained. Here, a silicon carbide semiconductor device with 4H-type silicon carbide as the semiconductor material will be used as an example. In this case, the diffusion potential of the pn junction is approximately 2V.

[0097] First, let's explain the situation regarding the continuation of the flow.

[0098] During freewheeling operation, the drain voltage (voltage of drain electrode 84) decreases relative to the source voltage (voltage of source electrode 80), generating a voltage of several volts during this period. In the case of a source electrode 80 connected to the second well region 31 via an ohmic electrode 70, in order to apply most of the source-drain voltage to the pn junction formed between the second well region 31 and the drift layer 20, a bipolar current flows through the pn diode formed by the second well region 31 and the drift layer 20.

[0099] However, in the silicon carbide semiconductor device of the present invention, the second well region 31 is not ohm-connected to the source electrode 80 ohms. Furthermore, a reverse bias is applied to the Schottky diode between the conductive layer 47 (ohm-connected to the source electrode 80 ohms) and the second well region 31 during freewheeling operation. Therefore, during freewheeling operation, no majority carriers are injected into the second well region 31. Consequently, no bipolar current, acting as a forward current, flows through the pn junction between the second well region 31 and the drift layer 20, suppressing the propagation of stacking defects in the pn junction and the resulting decrease in insulation withstand voltage.

[0100] In order to achieve the aforementioned effect during freewheeling operation, an effective conduction path for majority carriers to the second well region 31 needs to be formed without the applied voltage during freewheeling operation. That is, the Schottky connection between the conductive layer 47 and the second well region 31 needs to not break down in the reverse direction due to the applied voltage during freewheeling operation, and the PNP structure formed by the second well region 31, the third exit region 23, and the first well region 30 needs to not be punched through due to the applied voltage during freewheeling operation.

[0101] This passage explains the phenomenon of penetration.

[0102] The second well region 31 has an n-type third departure region 23 between itself and the adjacent first well region 30. Within the conduction path from the second well region 31 of the first well region 30, which is ohmically connected to the source electrode 80, to the source electrode 80, there is a pnp structure consisting of the first well region 30, the third departure region 23, and the second well region 31. The second well region 31 is not directly ohmically connected to the source electrode 80.

[0103] In this pnp structure, there is a pn junction with reverse bias in any voltage direction, so no current generally flows through it. However, when the width of the third departure region 23 is short, current is applied by applying a voltage greater than the punch-through voltage.

[0104] Regarding the punch-through voltage, it is assumed that the p-type impurity concentration in the first well region 30 and the p-type impurity concentration in the second well region 31 are both higher than the n-type impurity concentration in the third exit region 23.

[0105] [Formula 1]

[0106] d 2 φ / dx 2 =-qN / ε

[0107] The one-dimensional Poisson equation, as a solution to x = W, is derived as follows:

[0108] [Equation 2]

[0109] V = qN enct W 2 / (2ε).

[0110] Here, q is the elementary charge, and N effct ε is the effective impurity concentration of the third departure region 23, W is the width of the third departure region 23, and ε is the dielectric constant of the silicon carbide semiconductor.

[0111] Therefore, even if the voltage of the second well region 31 changes during the continuous current operation, the punch-through voltage calculated by Equation 2 is not applied to the pnp structure consisting of the first well region 30, the third exit region 23, and the second well region 31.

[0112] Next, the shutdown action will be explained.

[0113] During the turn-off operation, the potential of the drain electrode 84 increases sharply, applying a reverse bias to the pn junction formed between the second well region 31 and the drift layer 20. The depletion layer extends from the pn junction surface to both sides of the second well region 31 and the drift layer 20. At this time, due to the expansion of the depletion layer, the hole density in the undepleted region within the second well region 31 increases. These holes move towards the source electrode 80 via the conductive layer 47, but those generated in the second well region 31 at locations away from the contact point with the source electrode 80 in the planar direction (conductive layer contact hole 91) move in the planar direction within the second well region 31 or within the conductive layer 47 to reach the source electrode 80. This current is called the displacement current. The higher the switching speed (dV / dt), the larger this displacement current. At this time, the current from the second well region 31 to the conductive layer 47 flows in the forward direction of the Schottky diode, so a large voltage, such as the gate insulating film being damaged, is not generated between the second well region 31 and the conductive layer 47.

[0114] Furthermore, in this embodiment, a conductive layer 47 with a thin-film resistance lower than that of the second well region 31 is provided, so the voltage generated by the displacement current flowing from the second well region 31 to the source electrode 80 can be significantly reduced compared to the case where the conductive layer 47 is not provided.

[0115] Finally, the activation process is explained.

[0116] During the turn-on operation, the drain voltage of the drain electrode 84, which is high during the turn-off operation, decreases sharply towards the turn-on voltage of the MOSFET. At this time, the depletion layer formed in the pn junction between the second well region 31 and the drift layer 20 shrinks rapidly. Accompanying this, a displacement current flows from the source electrode 80 towards the second well region 31 in the opposite direction to that during the turn-off operation. The higher the switching speed (dV / dt), the larger the displacement current during turn-on.

[0117] The displacement current in the planar direction flows primarily through the conductive layer 47, which has low thin-film resistance, towards the portion that is in contact with the source electrode 80 (conductive layer contact hole 91). Therefore, the voltage generated by the displacement current is prevented from becoming high enough to cause insulation failure of the insulating layer formed on top of the conductive layer 47. A reverse bias is applied between the second well region 31 and the conductive layer 47, forming a depletion layer between them. However, since AC current flows between them, the displacement current primarily flows through the conductive layer 47, which has low thin-film resistance.

[0118] Here, the carrier concentration in the drift layer 20 is low and the conductive layer 47 has low resistance. Therefore, the depletion layer capacitance per unit area of ​​1V voltage formed between the second well region 31 and the conductive layer 47 is greater than the pn junction capacitance per unit area of ​​1V voltage formed between the second well region 31 and the drift layer 20. Due to the large pn junction capacitance between the second well region 31 and the conductive layer 47, AC current can easily flow through it. High voltage is not generated in the second well region 31, allowing AC displacement current to flow from the second well region 31 to the conductive layer 47.

[0119] In addition, a reverse bias is applied to the Schottky diode formed between the second well region 31 and the conductive layer 47, so no DC current flows between the second well region 31 and the conductive layer 47.

[0120] Thus, during the turn-on operation, there is no DC current path in the second well region 31. Therefore, holes cannot be injected into the second well region 31 during the turn-on operation. Consequently, after the turn-on operation, corresponding to the amount of DC current flowing through the conductive layer 47 to the source electrode 80 in the second well region 31 during the turn-off operation, there are insufficient holes in the second well region 31, and the second well region 31 becomes negatively charged. This charging generates a negative voltage in the second well region 31.

[0121] At this point, the amount of negative charge generated in the second well region 31, which is the amount of depletion layer charge that appears between the drift layer 20 and the second well region 31 when an electric field E is applied in the off state, can be estimated approximately using Gauss's law (divE = ρ / ε, E: electric field, ρ: charge density).

[0122] For example, if the electric field E is close to the insulation breakdown voltage of silicon carbide, which is 2 MV / cm, then the total amount of depletion layer charge generated in the second well region 31 becomes approximately 1.8 μC / cm² per unit area when viewed from the planar direction. 2 Even when only these negative depletion layer charges are generated, it is necessary to ensure that the insulating film such as the gate insulating film 50 formed on the second well region 31 is not damaged.

[0123] The voltage generated in the second well region 31 after the turn-on operation will be set as V. onpw In the case of V, the following formula is used to express it. onpw .

[0124] [Formula 3]

[0125]

[0126] Here, C surround (V) is the capacitance formed between the second well region 31 and the outer region, and is a function of the voltage V in the second well region 31. When V is negative, C surround The main component of (V) becomes the depletion layer capacitance formed between the second well region 31 and the conductive layer 47. Additionally, Q... drift This is the total amount of depletion layer charge in the drift layer 20 when it is in the off state. If C is increased... surround (V) can charge the negative charge generated in the second well region 31 immediately after the turn-on operation to the large depletion layer capacitance formed between the second well region 31 and the conductive layer 47, thereby reducing V onpw The absolute value of.

[0127] In C surround(V) includes, in its specific components, the depletion layer capacitance of the Schottky junction between the conductive layer 47 and the second well region 31, the depletion layer capacitance of the pn junction between the conductive layer 47 and the drift layer 20, and further, the capacitance between the gate electrode 60 or gate pad 81 and the second well region 31. The capacitance of the second well region 31 and the gate electrode 60 or gate pad 81 is small, but in addition to the depletion layer capacitance between the drift layer 20 and the second well region 31, there is also a larger depletion layer capacitance between the conductive layer 47 and the second well region 31, thus sufficiently increasing C. surround (V), therefore, for the negative charge generated during turn-on, the generated voltage V of the second well region 31 can be reduced. onpw The absolute value decreases to a level where the gate insulating film will not be damaged.

[0128] Furthermore, even the capacitance C formed between the second well region 31 and the outer region surround If (V) is not sufficiently large, by appropriately setting the punch-through voltage of the pnp structure consisting of the second well region 31, the third exit region 23, and the first well region 30, the rise in voltage generated in the second well region 31 can be suppressed.

[0129] If the design makes the punch-through voltage of the pnp structure consisting of the second well region 31, the third exit region 23, and the first well region 30 greater than the value obtained by subtracting the diffusion potential of the pn junction from the generation voltage between the source and drain during freewheeling operation, and less than the breakdown voltage of the insulating film formed on the second well region 31, more preferably less than half of the breakdown voltage, then the insulation breakdown of the insulating film formed on the second well region 31 can be prevented.

[0130] Thus, in the silicon carbide semiconductor device according to this embodiment, a conductive layer 47 is provided on the second well region 31, which is Schottky connected to the second well region 31 and has a thin-film resistance lower than that of the second well region 31. The conductive layer 47 and the source electrode 80 are ohmically connected through the conductive layer contact hole 91. Therefore, bipolar operation in the terminal region can be suppressed during the freewheeling operation of the MOSFET, and the voltage generated on the second well region 31 during the turn-off and turn-on operations can be reduced, thereby suppressing the insulation damage of the insulating film on the second well region 31.

[0131] Furthermore, by charging the large depletion layer capacitance formed between the second well region 31 and the conductive layer 47 with the negative charge generated in the second well region immediately after the turn-on operation, the voltage change in the second well region 31 can be reduced, and the insulation damage of the insulating film formed on the second well region 31 can be prevented.

[0132] Furthermore, although it is an auxiliary positioning, by appropriately setting the punch-through voltage of the pnp structure formed between the second well region 31 and the first well region 30, it is also possible to prevent the insulation of the insulating film on the second well region 31 from being damaged.

[0133] Furthermore, in this embodiment, it is described that the conductive layer 47 formed on the second well region 31 is formed of polycrystalline silicon, but the material of the conductive layer 47 is not limited to this, and may also be other semiconductor materials, Ti, or metals that are Schottky connected to the second well region 31.

[0134] Additionally, it is explained that the gate electrode 60 on the second well region 31 is formed with a gate insulating film 50 spaced between it and the second well region 31. However, the insulating film between the gate electrode 60 and the second well region 31 does not need to be the gate insulating film 50, but can also be the field insulating film 51 or an insulating film of other thicknesses.

[0135] Furthermore, previously it was stated that the second well region 31 was not ohm connected to the source electrode 80, but a portion of the second well region 31 could also be ohm connected to the source electrode 80.

[0136] Figure 4 This is a plan view showing another embodiment of the silicon carbide semiconductor device, mainly illustrating the silicon carbide semiconductor portion. Figure 4 In the second well region 31, a second well region contact hole 92 is formed in a part of the second well region 31 to ohmically connect the second well region 31 and the source electrode 80. Figure 5 It shows that it includes the formation of Figure 4 A cross-sectional schematic diagram of the contact hole 92 in the second well region. Figure 5 In the second well region, the contact hole 92 is formed by penetrating the field insulating film 51 and the interlayer insulating film 55. Alternatively, a second well contact region 36 with a higher p-type impurity concentration and lower resistance than the second well region 31 can be provided in the second well region 31 below the contact hole 92.

[0137] The second well region contact hole 92 is formed at least 10 μm away from the conductive layer contact hole 91 in the cross-section along the shortest path within the second well region 31. The distance between the conductive layer contact hole 91 and the second well region contact hole 92 on the shortest path within the second well region 31 is more preferably 50 μm or more.

[0138] Furthermore, in this embodiment, it is described that the first well region 30 and the second well region 31 are separate, but they may also be connected. Additionally, it is described that there are multiple first well regions 30, which are separate from each other, but they may also be connected to each other. Figure 6This is a plan view of a silicon carbide semiconductor device according to this embodiment, showing the case where the first well region 30 and the second well region 31 are connected, and multiple first well regions 30 are connected to each other. In this case, the first well region contact hole 90 formed for the first well region 30 is formed at least 10 μm laterally away from the conductive layer contact hole 91 in cross-section along the shortest path within the first well region 30 or the second well region 31. The distance between the conductive layer contact hole 91 and the first well region contact hole 90 along the shortest path within the first well region 30 or the second well region 31 is more preferably 50 μm or more.

[0139] Furthermore, even when the first well region 30 and the second well region 31 are connected, it is possible to... Figure 4 Similarly, a second well region contact hole 92 is provided in the second well region 31. Figure 7 Shown in Figure 6 The diagram shows a plan view of a silicon carbide semiconductor device where the second well region 31 is provided with a second well region contact hole 92. Even in this case, the distance between the conductive layer contact hole 91 and the second well region contact hole 92 on the shortest path within the second well region 31 is 10 μm or more, and more preferably 50 μm or more.

[0140] Here, in such Figure 6 When the first well region 30 and the second well region 31 are connected in a plane, the second well region 31 should, in principle, be electrically disconnected from the source electrode 80 when a voltage is applied during freewheeling operation. For example, let the area S (cm²) formed at a location away from the connection point of the source electrode 80 be... 2 In the second conductivity type of the trap region, during freewheeling operation, the current density J (A / cm²) flows through it. 2 The bipolar current. At this time, the resistance value of the path between the region of area S and the source electrode 80 is set as R. tot When (Ω), the potential V of the region that makes the potential of the source electrode 80 0V. drop (V) becomes V drop =J×S×R tot .

[0141] For example, consider a region where the first well region 30 and the second well region 31 are connected, located 10 μm away from the connection point towards the second well region 31, with a depth of 50 μm in the opposite direction to the connection point. Let the current density flowing through this 50 μm deep region from the corresponding location be, for example, 5 A / cm², to the extent that stacking defects do not grow. 2 The bipolar current. Additionally, assume the thin-film resistance R of the second well region 31. sheetIt is 100kΩ / sq. Therefore, the resistance value per 1μm width of the current path from the corresponding part to the connection part in this case (R0 per 1μm width) is... tot The total bipolar current flowing through a region 50 μm deep from the corresponding location, becoming 1 MΩ, is 2.5 × 10⁻⁶. - 6 A(J×S), thus V from the corresponding part to the connecting part drop It becomes 2.5V. In this case, set the connection point to 0V, because V drop The diffusion potential of the SiC pn junction, approximately 2V, is added in absolute terms to obtain a value of approximately 4.5V. If the drain voltage during freewheeling operation at the corresponding location is not approximately -4.5V (making the previous absolute value negative), then no bipolar current flows. If the corresponding location is a 50μm portion away from the connection point towards the second well region 31, then V drop If the leakage voltage during freewheeling operation is not approximately -14.5V, no bipolar current will flow.

[0142] Thus, at the connection point where the first well region 30 and the second well region 31 are far apart, but where there is also a second well region 31 in the depth direction, V is generated. drop If the leakage voltage on the negative side is not a very large value during freewheeling operation, then no bipolar current will flow.

[0143] Therefore, the second well region 31 under such conditions is considered to be fully electrically separated from the first well region 30, and the effects of the present invention can be enjoyed in the second well region 31 formed away from the connection point with the first well region 30.

[0144] More precisely, the voltage in the current path from the ohmic electrode 70 in the first well region 30 to the connection portion at the ohmic contact within the active unit also needs to be applied to R. tot For example, when the ohmic electrode 70 is located in a region 10 μm away from the connection portion, the effects of the present invention can be enjoyed in a region further outward than the connection portion. Furthermore, the effects of the present invention can be enjoyed more significantly in a region 40 μm outward from the connection portion. In this case, the distance between the first well region contact hole 90 and the conductive layer contact hole 91 should be 10 μm or more, preferably 50 μm or more.

[0145] In addition, such as Figure 6As shown, even when an ohmic contact (second well region contact hole 92) with the source electrode 80 is formed on the second well region 31, the effects of the present invention can be enjoyed as described above if a distance of 10 μm or more is ensured between the second well region contact hole 92 and the conductive layer contact hole 91. Even in this case, it is more preferable if the distance between the second well region contact hole 92 and the conductive layer contact hole 91 is 50 μm or more.

[0146] Furthermore, in the second well region 31 connected to the source electrode 80 ohms, if V drop If the voltage becomes approximately 2V or higher, then, for example, if the leakage voltage on the negative side becomes approximately 4V, subtract V from the leakage voltage. drop The resulting voltage becomes the diffusion potential of the SiC pn junction, approximately 2V or less, and no current flows in the second well region 31 to the extent of the propagation of stacked defects. Therefore, even if the second well region 31 is located directly below or near the gate pad 81 or gate wiring 82, forming a so-called terminal region, and is within 10μm of the contact hole 90 of the first well region or the contact hole 92 of the second well region, no bipolar current flows in the well region to the extent of the propagation of stacked defects.

[0147] Similarly, in such Figure 6 When the first well region 30 and the second well region 31 are connected, in addition to the limitations mentioned above, there is also a limitation caused by the resistance value of the path from the predetermined well region to the source electrode 80. Let the freewheeling current be, for example, a current density of 5 A / cm², such as when stacked defects do not propagate. 2 A current density flows through this region, which is defined as a 10μm × 10μm region with a resistance of 400kΩ along a path from this region to the source electrode 80. In this case, the previously described V drop (V) is calculated as 2V. For this region, with a leakage voltage of 4V, V is subtracted from the leakage voltage. drop The obtained value is less than the diffusion potential of the pn junction, so it can suppress bipolar operation during freewheeling.

[0148] In this embodiment, an example of ion implantation performed in a predetermined order is shown, but the order of ion implantation can be suitably changed. Furthermore, the formation order of the back-side ohmic electrode, the surface ohmic electrode 70, and the first Schottky electrode 71 can also be suitably changed.

[0149] Furthermore, regarding the ohmic electrode 70 and the first Schottky electrode 71, it is explained that they are independent of the source electrode 80, but can also be formed in one step using a portion of the same material within the scope of their respective functions.

[0150] Furthermore, it is explained that the first conductivity type and the second conductivity type are n-type and p-type, respectively, and it is also explained that the opposite is also possible, but it has a further effect when the first conductivity type is n-type and the second conductivity type is p-type.

[0151] Furthermore, although the ratio of the area of ​​the conductive layer 47 formed on the second well region 31 in plan view is not specifically discussed, since the conductive layer 47 is formed in order to improve the conductivity of the second well region 31, it is preferable to form the conductive layer 47 in a wider proportion in the planar direction of the second well region 31. For example, it can be formed in more than half of the area of ​​the region of the second well region 31, more preferably more than 80%.

[0152] In addition, the conductive layer 47 formed on the second well region 31 does not necessarily need to be formed continuously, and can also be in a shape with gaps in between.

[0153] Furthermore, since the conductive layer 47 aims to reduce the planar lateral resistance in the second well region 31, it is preferably more than half the width of the second well region 31 when viewed in cross-section, and more preferably more than 80% of the width of the second well region 31. Additionally, if the area of ​​the conductive layer 47 is at least larger than the conductive layer contact hole 91, the effects of the present invention can be enjoyed.

[0154] Furthermore, in this embodiment, an example with an SBD-embedded MOSFET in the active region is described. However, instead of an SBD-embedded MOSFET, an n-type channel epitaxial layer 49 is formed on the p-type well region, and the channel epitaxial layer 49 is operated as a unipolar diode at a gate voltage below the threshold voltage. The rise voltage of the unipolar diode is designed to be lower than the operating voltage of the pn diode formed by the p-type well region and the n-type drift layer. Figure 8 Showing will Figure 2 A cross-sectional view of a MOSFET is shown below, replacing the SBD built-in MOSFET with such a MOSFET. Thus, even when reverse current is applied in the channel region of the MOSFET during freewheeling operation, the same effect as the SBD built-in MOSFET can be obtained.

[0155] Implementation method 2.

[0156] In Embodiment 1, an example of a silicon carbide semiconductor device is shown in which a conductive layer 47 is provided on the second well region 31 in a directly connected manner. However, in the silicon carbide semiconductor device of this embodiment, the conductive layer 47 is provided on the second well region 31 with an insulating layer 53 in between. Other aspects are the same as in Embodiment 1, so detailed descriptions are omitted.

[0157] Figure 9This is a schematic illustration of the method used in the description of embodiment 1. Figure 1 A cross-sectional schematic diagram of the silicon carbide semiconductor device of this embodiment, showing a cross-section of the a-a' portion of the gate wiring 82 from the source electrode 80 to the outer periphery of the silicon carbide semiconductor device.

[0158] exist Figure 9 In the terminal region, an insulating layer 53 is formed between the second well region 31 and the conductive layer 47.

[0159] The insulating layer 53 can be formed of an insulating material such as silicon oxide. Alternatively, it can be an insulating material such as silicon nitride or aluminum oxide. Furthermore, it can be formed using the same material and process as the gate insulating film 50. Moreover, it can be formed by thermally oxidizing the silicon carbide layer in the same manner as the gate insulating film 50. In order to increase the capacitive coupling between the upper and lower parts of the insulating layer 53, the thickness of the insulating layer 53 is preferably not too large; for example, if it is silicon oxide, a thickness of 200 nm or less is acceptable.

[0160] Furthermore, the conductive layer 47 on the insulating layer 53 can also be formed using the same material and process as the gate electrode 60.

[0161] By forming the insulating layer 53 using the same material and process as the gate insulating film 50, and forming the conductive layer 47 using the same material and process as the gate electrode 60, the manufacturing process can be simplified.

[0162] When the insulating layer 53 is formed using the same material as the gate insulating film 50 and the same process, and the conductive layer 47 is formed using the same material as the gate electrode 60 and the same process, the following points can be changed compared to the manufacturing method of the silicon carbide semiconductor device in Embodiment 1.

[0163] Furthermore, in Embodiment 1, a conductive layer 47 is formed on the second well region 31 before forming the field insulating film 51, but this step is not performed. Instead, in the step of forming the gate insulating film 50 and the gate electrode 60 in the active region after forming the field insulating film 51, the insulating layer 53 and the conductive layer 47 are formed on the second well region 31 simultaneously.

[0164] Here, the operation of the silicon carbide semiconductor device of this embodiment will be explained.

[0165] In the silicon carbide semiconductor device of this embodiment, a capacitor is formed between the second well region 31 and the conductive layer 47, separated by an insulating layer 53. This capacitor functions as a current path through which the displacement current flowing in the planar direction in the second well region 31 during turn-on / turn-off is transmitted as an alternating current. This capacitor functions similarly to the depletion layer capacitance between the Schottky junction of the second well region 31 and the conductive layer 47 in Embodiment 1 when they are reverse-biased, thus suppressing the voltage generated by the displacement current during voltage switching, as in Embodiment 1. In this way, by charging the capacitor between the second well region 31 and the conductive layer 47 with the positive charge generated in the second well region 31 immediately after turn-off, the voltage generated in the second well region 31 can be suppressed to a low level, preventing insulation damage to the insulating film formed on the second well region 31.

[0166] The structure in which the second well region 31 is not connected to the source electrode 80 ohms suppresses the bipolar current flowing through the second well region 31 in the same way as in Embodiment 1. Alternatively, the second well region 31 may be connected to the source electrode 80 ohms under certain conditions, which is also the same as in Embodiment 1.

[0167] Furthermore, in such Figure 10 As shown in the cross-sectional schematic diagram, a Schottky contact hole 93 is provided to connect the second well region 31 and the source electrode 80, so that when the second well region 31 and the source electrode 80 are connected by Schottky, the charge on the second well region 31 after the turn-off operation can be reduced more effectively.

[0168] Implementation method 3.

[0169] In Embodiment 1, an example is shown where a conductive layer 47 is provided on the second well region 31. However, in the silicon carbide semiconductor device of this embodiment, the upper portion of the second well region 31 of the silicon carbide material of the second conductivity type is set to a low-resistance first conductivity type, and a pn junction is formed between this layer and the second well region 31. Here, the n-type layer serves the same function as the conductive layer 47. Other aspects are the same as in Embodiment 1, so detailed descriptions are omitted.

[0170] Figure 11 This is a schematic illustration of the method used in the description of embodiment 1. Figure 1 A cross-sectional schematic diagram of the silicon carbide semiconductor device of this embodiment, showing a cross-section of the a-a' portion of the gate wiring 82 from the source electrode 80 to the outer periphery of the silicon carbide semiconductor device.

[0171] exist Figure 11In the terminal region, above the second well region 31 of the second conductivity type, a silicon carbide conductive layer 45 of the first conductivity type, made of silicon carbide material, is formed, which has lower resistance and higher impurity concentration than the drift layer. The second well region 31 and the source electrode 80 are not ohmically connected.

[0172] Regarding the silicon carbide conductive layer 45, its thickness can be, for example, 50 nm to 1000 nm, and is less than the thickness of the second well region 31. Furthermore, the impurity concentration of the silicon carbide conductive layer 45 can be, for example, 1 × 10⁻⁶. 17 cm -3 Above and 1×10 19 cm -3 The following is sufficient.

[0173] Alternatively, the silicon carbide conductive layer 45 and the source region 40 can be formed using the same process, with the same thickness and impurity concentration. Furthermore, the silicon carbide conductive layer 45 and the source region 40 can also be formed using different processes, with different thicknesses and different impurity concentrations.

[0174] Next, the manufacturing method of the silicon carbide semiconductor device of this embodiment, in which the silicon carbide conductive layer 45 and the source region 40 are formed in the same process with the same thickness and impurity concentration, will be described.

[0175] In Embodiment 1, a conductive layer 47 is formed on the second well region 31 before forming the field insulating film 51, but this step is not performed. Instead, during the ion implantation step for forming the source region 40, a silicon carbide conductive layer 45 is formed simultaneously in the upper part of the second well region 31.

[0176] This manufacturing method simplifies the manufacturing process of silicon carbide semiconductor devices and reduces manufacturing costs.

[0177] Next, the operation of the silicon carbide semiconductor device of this embodiment will be explained.

[0178] In the silicon carbide semiconductor device of Embodiment 1, a Schottky junction is formed between the second well region 31 and the conductive layer 47. However, in the silicon carbide semiconductor device of this embodiment, a pn junction is formed between the second well region 31 and the silicon carbide conductive layer 45. This pn junction functions the same as the Schottky junction in the silicon carbide semiconductor device of Embodiment 1.

[0179] Therefore, the silicon carbide semiconductor device of this embodiment, like the example described in Embodiment 1, can suppress bipolar operation in the terminal region during the freewheeling operation of the MOSFET, and can reduce the voltage generated on the second well region 31 during the turn-off and turn-on operations, and can suppress the insulation damage of the insulating film on the second well region 31.

[0180] Furthermore, it can be manufactured more easily than the silicon carbide semiconductor device of Embodiment 1.

[0181] Implementation method 4.

[0182] In Embodiment 3, an example was described in which a low-resistance silicon carbide conductive layer 45 of the first conductivity type was formed in the upper part of the second well region 31. However, the silicon carbide conductive layer 45 can also be formed by embedding it within the second well region 31. Other aspects are the same as in Embodiment 3, so detailed descriptions are omitted.

[0183] Figure 12 This is a schematic illustration of the method used in the description of embodiment 1. Figure 1 A cross-sectional schematic diagram of the silicon carbide semiconductor device of this embodiment, showing a cross-section of the a-a' portion of the gate wiring 82 from the source electrode 80 to the outer periphery of the silicon carbide semiconductor device.

[0184] exist Figure 12 In the terminal region, a silicon carbide conductive layer 45 is formed in the center of the second well region 31 of the second conductivity type in the depth direction, and the silicon carbide conductive layer 45 is connected to the second ohmic electrode 72 via the connection region 46 of the first conductivity type.

[0185] The first conductivity type connection region 46 can be formed simultaneously with the source region 40 by ion implantation. Furthermore, the silicon carbide conductive layer 45 can be formed by deep ion implantation.

[0186] According to the silicon carbide semiconductor device of this embodiment, a silicon carbide conductive layer 45 is formed inside the second well region 31, so the area of ​​the pn diode formed between the silicon carbide conductive layer 45 and the second well region 31 can be increased, and the depletion layer capacitance between the silicon carbide conductive layer 45 and the second well region 31 can be increased.

[0187] Therefore, it is possible to further reduce the voltage generated in the second well region 31 and further suppress the insulation breakdown of the insulating film in the second well region 31.

[0188] Implementation method 5.

[0189] In Embodiment 3, an example was described in which a low-resistance silicon carbide conductive layer 45 of the first conductivity type was formed in the upper part of the second well region 31. However, the lower surface of the silicon carbide conductive layer 45 may also have irregularities. Other points are the same as in Embodiment 3, so detailed descriptions are omitted.

[0190] Figure 13 This is a schematic illustration of the method used in the description of embodiment 1. Figure 1A cross-sectional schematic diagram of the silicon carbide semiconductor device of this embodiment, showing a cross-section of the a-a' portion of the gate wiring 82 from the source electrode 80 to the outer periphery of the silicon carbide semiconductor device.

[0191] exist Figure 13 In the terminal region, an unevenness is formed at the connection between the lower surface of the silicon carbide conductive layer 45 and the second well region 31.

[0192] Regarding the unevenness of the lower surface of the silicon carbide conductive layer 45, it can be formed by ion implantation at a deeper depth than the silicon carbide conductive layer 45 before and after ion implantation using a predetermined ion implantation mask.

[0193] According to the silicon carbide semiconductor device of this embodiment, an uneven surface is formed on the lower surface of the silicon carbide conductive layer 45, so the area of ​​the pn diode formed between the silicon carbide conductive layer 45 and the second well region 31 can be increased, and the depletion layer capacitance between the silicon carbide conductive layer 45 and the second well region 31 can be increased.

[0194] Therefore, it is possible to further reduce the voltage generated in the second well region 31 and further suppress the insulation breakdown of the insulating film in the second well region 31.

[0195] Implementation method 6.

[0196] In the terminal region of the silicon carbide semiconductor device in embodiments 1 to 5, no ohmic contact is provided for the source electrode 80 in the second well region 31. Instead, a Schottky connection, pn connection, or capacitive coupling via an insulating film is provided in the second well region 31, so that the source electrode 80 is ohmically connected to this region. Alternatively, similar to the first well region 30 of the active region, a departure region of a first conductivity type may be formed inside the planar direction of the second well region 31, and an electrode with a Schottky connection to this departure region may be provided. Other aspects are the same as in embodiments 1 to 5, so detailed descriptions are omitted.

[0197] Figure 14 This is a schematic illustration of the method used in the description of embodiment 1. Figure 1 A cross-sectional schematic diagram of the silicon carbide semiconductor device of this embodiment, showing a cross-section of the a-a' portion of the gate wiring 82 from the source electrode 80 to the outer periphery of the silicon carbide semiconductor device.

[0198] exist Figure 14In the terminal region, inside the plane of the second well region 31 of the second conductivity type, a fourth exit region 24 of the first conductivity type, made of silicon carbide, is formed. Above the fourth exit region 24, a second Schottky electrode 73 is formed, which is Schottky connected to the fourth exit region 24. The second Schottky electrode 73 is formed within a Schottky contact hole 94 within the second well region. Other aspects are the same as in Embodiment 3.

[0199] Here, it can also be as in Figure 15 and Figure 16 The diagram shows a cross-sectional view and a plan view. In the same contact hole, a conductive layer contact hole 91 is formed to connect the conductive layer 47 or silicon carbide conductive layer 45 of embodiments 1 to 5 and the source electrode 80, and a Schottky contact hole 94 is formed to connect the second Schottky electrode 73 on the fourth departure region 24 and the source electrode 80 in the second well region.

[0200] Through such Figure 15 as well as Figure 16 As shown, by forming conductive layer contact holes 91 connecting conductive layer 47 or silicon carbide conductive layer 45 and source electrode 80, and Schottky contact holes 94 connecting second Schottky electrode 73 on fourth departure region 24 and source electrode 80 in the same contact holes, the area of ​​the formed contact holes can be reduced. Furthermore, by also forming a fourth departure region 24 of the first conductivity type inside the second well region 31, and forming a second Schottky electrode 73 that is Schottky connected to the fourth departure region 24, the bipolar current suppression capability during freewheeling operation can be further improved.

[0201] According to this embodiment of the silicon carbide semiconductor device, the interior of the plane of the second well region 31 is also provided with a structure connected to the Schottky drift layer 20 in the same way as the active region, so that the bipolar current flowing in the second well region 31 of the terminal structure can be further reduced.

[0202] Furthermore, here is shown an example of a construction in which the drift layer 20 is connected to the Schottky layer in the second well region 31 of the second conductivity type, which is applicable to embodiment 3, but of course the same effect is obtained even if it is applied to other embodiments.

[0203] Implementation method 7.

[0204] In the terminal region of the silicon carbide semiconductor device in embodiments 1 to 6, the impurity concentration in the planar transverse direction of the second well region 31 is not specifically described, but it is characterized in that, in the upper layer of the second well region 31, where the gate electrode 60 is located with a gate insulating film 50 at its upper part, a second conductivity type electric field mitigation layer 33 with a lower impurity concentration than that of other second well regions 31 is provided. Other points are the same as in embodiments 1 to 6, so detailed descriptions are omitted.

[0205] exist Figure 17 In the terminal region, in the upper part of the second well region 31 of the second conductivity type where the gate electrode 60 is located separated by the gate insulating film 50, there is an electric field mitigation layer 33 of the second conductivity type with a lower impurity concentration than that of other second well regions 31. Figure 17 The construction is an example of the construction applicable to implementation method 3.

[0206] Here, the impurity concentration of the electric field mitigation layer 33 can be less than half of the impurity concentration of the second well region 31.

[0207] In the silicon carbide semiconductor device of this embodiment, a depletion layer is formed between the gate insulating film 50 and the electric field mitigation layer 33 by the voltage formed by the residual charge generated in the second well region 31 when turned on.

[0208] Even without the formation of the electric field mitigation layer 33, a depletion layer is formed between the gate insulating film 50 and the second well region 31. However, in the silicon carbide semiconductor device of this embodiment, the electric field mitigation layer 33 is formed, so the width of the depletion layer is significantly increased. Therefore, the electric field applied to the gate insulating film 50 by the generation voltage generated from the residual charge in the second well region 31 during turn-on can be significantly reduced, and the reliability of the gate insulating film 50 can be significantly improved.

[0209] The electric field mitigation layer 33 in the silicon carbide semiconductor device of this embodiment can be formed by implanting n-type or p-type ions using a predetermined mask before and after ion implantation to form the second well region 31.

[0210] In the case of implanting p-type ions, this is achieved by first implanting ions into the region of the second well region 31 in a deep region, and then implanting ions into the shallow region using a mask that opens the region except for the region of the electric field mitigation layer 33. In this case, the retrograde profile of ion implantation into the second well region 31, which has a peak in the deep region, functions as the electric field mitigation layer 33 because it reduces the impurity concentration in the shallow region adjacent to the gate insulating film 50.

[0211] Implementation method 8.

[0212] In the terminal region of the silicon carbide semiconductor device in embodiments 1 to 7, the structure in principle where the first well region 30 in the active region and the second well region 31 in the terminal structure are separated and the second well region 31 is not ohm-connected to the source electrode 80 is mainly described. However, in this embodiment, the second well region 31 of the terminal structure is connected to a portion of the first well region 30 via an auxiliary connection region 34. Other structures are the same as in embodiments 1 to 7, so detailed descriptions are omitted.

[0213] Figure 18 This is a plan view of the silicon carbide semiconductor device according to this embodiment. Figure 18 In the active region, the first well region 30 and the second well region 31 of the terminal region are connected via an auxiliary connection region 34 of the second conductivity type. Figure 18 This diagram is applicable to the case of implementation method 1.

[0214] The auxiliary connection region 34 of the second conductivity type can be formed simultaneously with the formation of the second well region 31 by changing the ion implantation mask.

[0215] When the first well region 30 of the active region and the second well region 31 of the terminal structure are completely separated, and the second well region 31 is completely floating, depending on the conditions and structure, there is a possibility that the second well region 31 is charged while the insulating film on the second well region 31 is damaged.

[0216] In the silicon carbide semiconductor device according to this embodiment, the second well region 31 is connected via the auxiliary connection region 34, which can more reliably avoid the insulation damage of the insulating film on the second well region 31, and can further improve reliability.

[0217] At this time, Figure 18 In the region near the center of each side of the silicon carbide semiconductor device, close to the auxiliary connection region 34, current flows through the auxiliary connection region 34 without passing through the third exit region 23, which may cause breakdown voltage. Therefore, in Figure 18 In the regions near the corners of the silicon carbide semiconductor device close to the auxiliary connection region 34, as described in Embodiment 1, current flows in a long horizontal direction in the second well region 31, resulting in a voltage drop due to the thin-film resistance of the second well region 31, and bipolar current flow is suppressed.

[0218] In Implementation Method 1 Figure 6 In the previous embodiment, the first well region 30 and the second well region 31 were connected at numerous locations. However, in this embodiment, the connection points between the first well region 30 and the second well region 31 are limited, thus reducing the number of locations where breakdown voltage degradation may occur. Therefore, breakdown voltage degradation caused by bipolar current flowing into the second well region 31 is also limited.

[0219] Thus, the silicon carbide semiconductor device according to this embodiment can reduce the possibility of insulation failure due to the floating of the second well region 31, and minimize the reliability reduction caused by the bipolar energization of the second well region 31.

[0220] Furthermore, the area where the auxiliary connection region 34 is provided is preferably shorter than the length of the third departure region 23, for example, less than 1 / 10 of the length of the third departure region 23. This reduces the possibility of withstand voltage degradation to less than approximately 1 / 10, significantly improving the reliability of the component.

[0221] Implementation method 9.

[0222] In embodiments 1 to 8, the second well region 31 formed in the MOSFET terminal region is characterized by having a conductive layer contact hole 91. However, to enjoy the effects of the present invention, even if there is no conductive layer contact hole 91 on the second well region 31, the conductive layer 47 formed near the second well region 31 can be ohmically connected to the source electrode 80 at any location, and the second well region 31 can be connected with high resistance when viewed from the source electrode 80. Here, it is assumed that the conductive layer 47 occupies more than half of the area of ​​the second well region 31 located at the bottom of the gate pad 81. Other points are the same as in embodiment 1, etc., so detailed description is omitted.

[0223] Figure 19 A cross-sectional schematic diagram of the terminal region in the silicon carbide semiconductor device of Embodiment 9 is shown. Figure 19 As shown, in the silicon carbide semiconductor device of this embodiment, a connection portion to the conductive layer 47 is provided on a portion of the contact hole 90 in the first well region, closer to the active region than the second well region 31 in the terminal structure. In this configuration, it is unnecessary to form a special contact hole in the second well region 31, and the connection resistance to the source electrode in the second well region 31 can be increased. Furthermore, a conductive layer 47 with low sheet resistance and the same potential as the ohmic electrode 70 is formed on the upper part of the second well region 31. By forming the conductive layer 47 in a wide cross-sectional direction, the cross-sectional resistance of the second well region 31 can be reduced. Therefore, the silicon carbide semiconductor device of this embodiment can reduce the voltage generated on the second well region 31 during high-speed switching, suppress insulation damage to the insulating film on the second well region 31, and suppress bipolar current during freewheeling operation.

[0224] Figure 20 This is a cross-sectional schematic diagram of a modified example of the silicon carbide semiconductor device according to this embodiment. Additionally, Figure 21 This is a plan view of a modified example of the silicon carbide semiconductor device according to this embodiment. Figure 20 , Figure 21 In the second well region 31, a low-resistance n-type silicon carbide conductive layer 45 formed on the upper part of the second well region 31 is connected in a planar direction to a source region 40 formed on the upper part of the first well region 30 at the outermost periphery of the active region, and the second well region 31 and the first well region 30 are connected in a planar direction.

[0225] The source region 40 within the first well region 30 is ohmically connected to the source electrode 80 via the ohmic electrode 70 within the contact hole 90 of the first well region. Therefore, the silicon carbide conductive layer 45 formed on the upper part of the second well region 31 is ohmically connected to the source electrode 80 with low resistance. Thus, the silicon carbide semiconductor device of this embodiment can reduce the voltage generated on the second well region 31 during high-speed switching operations.

[0226] Furthermore, the first well region 30 and the second well region 31, which are at the same potential as the source electrode 80, are connected by a relatively high-resistance p-type semiconductor, so that bipolar current flowing in the second well region 31 during switching can be suppressed.

[0227] Furthermore, the silicon carbide semiconductor device of this embodiment can also be as follows: Figure 22 The diagram shows a planar schematic, in which the first well region 30 of the active region, which is formed in a striped pattern, is connected to the second well region 31 of the terminal region, and the source region 40 in the first well region 30 is connected to the silicon carbide conductive layer 45 in the second well region 31.

[0228] Even in Figure 22 In the illustrated configuration, no ohmic contact is formed to the source electrode 80 on the second well region 31 side, and a wide-area silicon carbide conductive layer 45 formed on the upper part of the second well region 31 is ohmically connected to the source electrode 80 with low resistance via the source region 40 within the first well region 30. Furthermore, the second well region 31 and the first well region 30 are interconnected, but because they are connected via a relatively high-resistance p-type semiconductor, bipolar current flowing through the second well region 31 during switching can be suppressed. Therefore, in this silicon carbide semiconductor device configuration, the voltage generated on the second well region 31 during high-speed switching can also be reduced, and insulation breakdown of the insulating film on the second well region 31 can be suppressed. Additionally, bipolar current during freewheeling operation can be suppressed.

[0229] The silicon carbide semiconductor device of this embodiment can be referred to as an embodiment that integrates the functions of the conductive layer contact hole 91 and the first well region contact hole 90 of the silicon carbide semiconductor device of embodiments 1 to 8 into a single contact hole.

[0230] Furthermore, the silicon carbide semiconductor device of this embodiment can be manufactured using a process that is substantially the same as the manufacturing process of the silicon carbide semiconductor devices of embodiments 1 to 8.

[0231] Implementation method 10.

[0232] In embodiments 1 to 9, the conductive layer 47 or the silicon carbide conductive layer 45 formed on the second well region 31 of the MOSFET terminal region is not in direct contact with the drift layer 20. However, in the silicon carbide semiconductor device of this embodiment, a portion of the second well region 31 has an n-type departure region, which is Schottky connected to the conductive layer 47 formed thereon. Other points are the same as in the embodiments described above, so detailed descriptions are omitted.

[0233] As an embodiment that further improves the effect of the present invention, in this embodiment, such as in Figure 23 A cross-sectional schematic diagram is shown. An n-shaped fifth departure region 25 is provided in the second well region 31 below the conductive layer 47, allowing the fifth departure region 25, which is connected to the drift layer 20, to directly Schottky contact with the conductive layer 47. In this embodiment, any size and number of fifth departure regions 25 can be formed in the second well region 31 regardless of the size of the conductive layer contact hole 91. This further improves the effect of suppressing bipolar current flow in the terminal region.

[0234] Furthermore, the fifth departure region 25 can have the same impurity concentration as the drift layer 20, or it can have a different impurity concentration.

[0235] Furthermore, since the conductive layer 47 is formed over a wide area on the second well region 31, the displacement current generated in the second well region 31 can flow to the source electrode with low resistance through the large depletion layer capacitance between the second well region 31 and the conductive layer 47. Therefore, the voltage generated in the second well region 31 during high-speed switching can be reduced, and the insulation breakdown of the insulating film on the second well region 31 can be suppressed.

[0236] Furthermore, the silicon carbide semiconductor device of this embodiment can be manufactured using a process that is essentially the same as the manufacturing process of the silicon carbide semiconductor devices of embodiments 1 to 8, simply by changing the resist pattern during ion implantation when the second well region 31 is formed.

[0237] Furthermore, in this embodiment, the conductive layer 47 can be made of a material capable of Schottky bonding with both the drift layer 20 of the first conductivity type and the second well region 31 of the second conductivity type. For example, it can be n-type or p-type polycrystalline silicon, Al, Ti, or other metals.

[0238] Furthermore, in embodiments 1 to 10, the first conductivity type was described as n-type and the second conductivity type as p-type, but this is not a limitation; the same effect is achieved even if the first conductivity type is p-type and the second conductivity type is n-type. Additionally, N is used as the n-type (first conductivity type) impurity, but phosphorus or arsenic can also be used. Al is used as the p-type (second conductivity type) impurity, but boron or gallium can also be used.

[0239] Furthermore, in the MOSFETs described in embodiments 1 to 10, the gate insulating film 50 does not necessarily have to be an oxide film such as silicon oxide; it can be an insulating film other than an oxide film, or a film formed by combining an insulating film other than an oxide film and an oxide film. Additionally, silicon oxide formed by thermal oxidation of silicon carbide is used as the gate insulating film 50, but it can also be silicon oxide deposited using a CVD method. Furthermore, the present invention can also be used in MOSFETs having a superstructure.

[0240] Furthermore, while the above embodiments describe a MOSFET with a gate insulating film 50, the present invention can be applied to any unipolar device. For example, the present invention can also be used in JFETs (Junction FETs) and MESFETs (Metal-Semiconductor Field Effect Transistors) that do not have a gate insulating film 50.

[0241] Furthermore, in the above embodiment, the ohmic electrode 70 and the first Schottky electrode 71 on the source side are fabricated separately, but they can also be formed continuously using the same material or continuously using different materials.

[0242] In addition, the first Schottky electrode 71 and the second Schottky electrode 73 can be formed using the same material or different materials.

[0243] Furthermore, in the above embodiments, specific examples such as crystal structure, face orientation of the main face, deviation angle, and various injection conditions were used for illustration, but the scope of application is not limited to these numerical ranges.

[0244] Implementation method 11.

[0245] This embodiment applies the silicon carbide semiconductor device described in Embodiments 1 to 10 to a power conversion device. The present invention is not limited to a specific power conversion device, but Embodiment 11 illustrates its application in a three-phase inverter.

[0246] Figure 24 This is a block diagram illustrating the structure of a power conversion system to which the power conversion device according to this embodiment is applicable.

[0247] Figure 24 The power conversion system shown includes a power source 100, a power conversion device 200, and a load 300. The power source 100 is a DC power source that supplies DC power to the power conversion device 200. The power source 100 can be constructed from various examples, such as a DC system, a solar cell, or a battery, or it can be constructed from a rectifier circuit connected to an AC system or an AC / DC converter. Alternatively, the power source 100 can also be constructed from a DC / DC converter that converts DC power output from a DC system into a predetermined power.

[0248] The power conversion device 200 is a three-phase inverter connected between the power source 100 and the load 300. It converts the DC power supplied from the power source 100 into AC power and supplies AC power to the load 300. The power conversion device 200 is as follows: Figure 24 As shown, it includes: a main converter circuit 201 that converts DC power into AC power and outputs it; a drive circuit 202 that outputs drive signals for each switching element of the main converter circuit 201; and a control circuit 203 that outputs control signals for the drive circuit 202 to the drive circuit 202.

[0249] The load 300 is a three-phase motor driven by AC power supplied from the power conversion device 200. Furthermore, the load 300 is not limited to a specific application; it is a motor mounted on various electrical equipment, such as those used in hybrid vehicles, electric vehicles, railway vehicles, elevators, or air conditioning systems.

[0250] The power conversion device 200 will now be described in detail. The main conversion circuit 201 includes switching elements and freewheeling diodes (not shown). By switching the switching elements, it converts the DC power supplied from the power source 100 into AC power, which is then supplied to the load 300. Various examples exist for the specific circuit structure of the main conversion circuit 201, but the main conversion circuit 201 according to this embodiment is a two-level three-phase full-bridge circuit, which includes six switching elements and six freewheeling diodes connected in anti-parallel to each switching element. The silicon carbide semiconductor device according to any of the embodiments 1 to 6 described above is used in each of the switching elements of the main conversion circuit 201. Regarding the six switching elements, every two switching elements are connected in series to form upper and lower arms, and each upper and lower arm constitutes a phase (U phase, V phase, W phase) of the full-bridge circuit. Furthermore, the output terminals of each upper and lower arm, i.e., the three output terminals of the main conversion circuit 201, are connected to the load 300.

[0251] The drive circuit 202 generates drive signals for the switching elements of the main converter circuit 201 and supplies them to the control electrodes of the switching elements of the main converter circuit 201. Specifically, according to the control signal from the control circuit 203 (described later), drive signals that turn the switching elements on and off are output to the control electrodes of each switching element. When the switching element is kept on, the drive signal is a voltage signal above the threshold voltage of the switching element (on signal); when the switching element is kept off, the drive signal is a voltage signal below the threshold voltage of the switching element (off signal).

[0252] The control circuit 203 controls the switching elements of the main converter circuit 201 to supply the desired power to the load 300. Specifically, based on the power to be supplied to the load 300, the control circuit 203 calculates the time (on-time) during which each switching element of the main converter circuit 201 should be in the on state. For example, the main converter circuit 201 can be controlled by PWM control that modulates the on-time of the switching elements according to the output voltage. Furthermore, the control circuit 203 outputs a control command (control signal) to the drive circuit 202 in such a way that it outputs an on signal to the switching elements that should be in the on state and an off signal to the switching elements that should be in the off state at each time point. The drive circuit 202 outputs an on signal or an off signal as a drive signal to the control electrode of each switching element according to the control signal.

[0253] In the power conversion device according to this embodiment, the switching element of the main conversion circuit 201 is a silicon carbide semiconductor device according to embodiments 1 to 10, so a power conversion device with low loss and improved reliability of high-speed switching can be realized.

[0254] This embodiment illustrates an example of applying the present invention to a 2-level three-phase inverter, but the present invention is not limited thereto and can be applied to various power conversion devices. While this embodiment describes a 2-level power conversion device, it can also be a 3-level or multi-level power conversion device. The present invention can also be applied to a single-phase inverter when supplying power to a single-phase load. Furthermore, when supplying power to DC loads, the present invention can also be applied to DC / DC converters and AC / DC converters.

[0255] Furthermore, the power conversion device applicable to the present invention is not limited to the case where the load is an electric motor. For example, it can be used as a power supply device for electrical discharge machining, laser processing machine, induction heating cooker, or contactless power supply system, and can also be used as a power regulator for solar power generation system, energy storage system, etc.

Claims

1. A silicon carbide semiconductor device, characterized in that, have: Silicon carbide semiconductor substrate of the first conductivity type; A drift layer of the first conductivity type is formed on the semiconductor substrate; The active region, having a source region of a first conductivity type connected to the source electrode, is periodically arranged in the drift layer; The terminal region is disposed independently of the active region in the drift layer; The second well region of the second conductivity type is disposed on the surface of the drift layer in the terminal region; A conductive layer is formed above the bottom surface of the second well region in a manner that does not ohmically connect with the second well region, and the resistance of the thin layer is lower than that of the second well region. as well as The conductive layer contact hole enables the conductive layer to be ohmically connected to the source electrode, but prevents the conductive layer from being ohmically connected to the second well region.

2. A silicon carbide semiconductor device, characterized in that, have: Silicon carbide semiconductor substrate of the first conductivity type; A drift layer of the first conductivity type is formed on the semiconductor substrate; An active region, a source region having a first conductivity type and a first well region having a second conductivity type, and a MOSFET having an ohmic electrode ohmically connected to the first well region are periodically arranged in the drift layer. The terminal region is disposed independently of the active region in the drift layer; A second well region of a second conductivity type is connected to at least one of the first well regions of the second conductivity type within the MOSFET and is disposed on the surface of the drift layer in the terminal region; The gate electrode is formed on the insulating film in the first well region and on the insulating film in the second well region; A gate pad is formed above the second well region and connected to the gate electrode; A conductive layer is formed above the bottom surface of the second well region in a manner that does not ohmically connect with the second well region, has an area of ​​more than half that of the second well region formed at the bottom of the gate pad, and has a thin-layer resistance lower than that of the second well region. as well as The source electrode is connected to the ohmic electrode and the conductive layer. The second well region is ohmically connected to the source electrode via a first well region contact hole on the first well region.

3. The silicon carbide semiconductor device according to claim 1 or 2, wherein, The MOSFET includes a unipolar diode whose rise voltage is lower than the operating voltage of the pn diode formed by the second well region of the second conductivity type and the drift layer of the first conductivity type. The unipolar diode is a layer of the first conductivity type formed on the first well region.

4. The silicon carbide semiconductor device according to claim 1 or 2, wherein, The MOSFET includes a unipolar diode whose rise voltage is lower than the operating voltage of the pn diode formed by the second well region of the second conductivity type and the drift layer of the first conductivity type. The unipolar diode is a Schottky barrier diode formed in the active region.

5. The silicon carbide semiconductor device according to claim 1 or 2, wherein, The conductive layer is formed across more than half the width of the cross-sectional transverse width of the second well region.

6. The silicon carbide semiconductor device according to claim 1 or 2, wherein, The conductive layer is a silicon carbide conductive layer of the first conductivity type formed on the surface portion of the second well region.

7. The silicon carbide semiconductor device according to claim 1 or 2, wherein, The conductive layer is made of polycrystalline silicon.

8. A power conversion device, comprising: A main converter circuit having a silicon carbide semiconductor device as described in any one of claims 1 to 7, the main converter circuit converting input power to output power; The driving circuit outputs a driving signal to the silicon carbide semiconductor device. as well as The control circuit outputs control signals to the drive circuit.

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