Light-emitting diode chip with improved light efficiency and preparation method thereof

Abstract

The present disclosure provides a light-emitting diode chip with improved light efficiency and a method for preparing the same, belonging to the field of optoelectronic manufacturing technology. The light-emitting diode chip includes: a substrate, a light-emitting structure, a first electrode, and a second electrode; the light-emitting structure includes a first semiconductor layer, a multi-quantum well layer, and a second semiconductor layer sequentially stacked on the substrate, one of the first semiconductor layer and the second semiconductor layer is a p-type layer, the surface of the second semiconductor layer has a groove exposing the first semiconductor layer, the first electrode is located in the groove, and the second electrode is located on the side of the second semiconductor layer away from the substrate; silicon ions are implanted in a local area of the p-type layer, and the local area surrounds the groove. The embodiment of the present disclosure can avoid the problem of leakage caused by defects generated after etching the groove on the semiconductor layer, thereby improving the light efficiency of the chip.

Description

Technical Field

[0001] The present disclosure relates to the field of optoelectronic manufacturing technology, and in particular to a light-emitting diode chip with improved light efficiency and a preparation method thereof. Background Art

[0002] Micro LEDs (Micro Light Emitting Diodes) refer to ultra-small light-emitting diodes with side lengths ranging from 10μm to 100μm. Due to their small size, micro LEDs can be arranged more densely, significantly improving resolution. They also have self-luminous properties, and have the characteristics of high brightness, high contrast, high responsiveness, and energy saving.

[0003] In related technologies, a light-emitting diode chip generally includes a substrate, a light-emitting structure, and two electrodes. The light-emitting structure includes an n-type layer, a multi-quantum well layer, and a p-type layer stacked in sequence on the substrate. One electrode is located on the p-type layer and electrically connected to the p-type layer. A groove is also provided on the p-type layer to expose the n-type layer. The other electrode is located in the groove and electrically connected to the n-type layer.

[0004] After the p-type layer is etched to form grooves, some defects will be generated in the areas corresponding to the grooves on the p-type layer. These defects will form some energy levels, which will cause leakage and thus reduce the actual light efficiency of the chip. Summary of the Invention

[0005] The present disclosure provides a light-emitting diode chip with improved light efficiency and a method for manufacturing the same, which can avoid the problem of leakage caused by defects caused by etching grooves on the semiconductor layer and improve the light efficiency of the chip. The technical solution is as follows:

[0006] On the one hand, an embodiment of the present disclosure provides a light-emitting diode chip with improved light efficiency, the light-emitting diode chip comprising: a substrate, a light-emitting structure, a first electrode, and a second electrode; the light-emitting structure comprises a first semiconductor layer, a multi-quantum well layer, and a second semiconductor layer stacked in sequence on the substrate, one of the first semiconductor layer and the second semiconductor layer is a p-type layer, the surface of the second semiconductor layer has a groove exposing the first semiconductor layer, the first electrode is located in the groove, and the second electrode is located on a side of the second semiconductor layer away from the substrate; silicon ions are implanted in a local area of the p-type layer, and the local area surrounds the groove.

[0007] Optionally, the local area includes a first part and a second part, the first part is adjacent to the groove and surrounds the groove, the second part is located on the side of the first part away from the groove, and the amount of silicon ions injected per unit volume in the first part is higher than the amount of silicon ions injected per unit volume in the second part.

[0008] Optionally, in a direction of a line connecting the first electrode and the second electrode, a ratio of a length of the first portion to a length of the second portion is 1:1.5 to 1:3.

[0009] Optionally, the groove is an arc-shaped groove, and the first part and the second part are both fan-shaped.

[0010] Optionally, in a thickness direction of the p-type layer, the local region is located in a middle portion of the p-type layer.

[0011] Optionally, in the thickness direction of the p-type layer, a distance between the surface of the local region close to the multi-quantum well layer and the multi-quantum well layer is 500 angstroms to 1500 angstroms.

[0012] Optionally, the thickness of the local region is 8000 angstroms to 12000 angstroms.

[0013] On the other hand, an embodiment of the present disclosure also provides a method for preparing a light-emitting diode chip with improved luminous efficiency, the preparation method comprising: providing an epitaxial wafer, the epitaxial wafer comprising a substrate and a light-emitting structure located on the substrate, the light-emitting structure comprising a first semiconductor layer, a multi-quantum well layer, and a second semiconductor layer stacked in sequence on the substrate, one of the first semiconductor layer and the second semiconductor layer being a p-type layer, and a surface of the second semiconductor layer having a groove exposing the first semiconductor layer; silicon ions are implanted in a local area of the p-type layer, and the local area surrounds the groove; a first electrode and a second electrode are fabricated on the epitaxial wafer, the first electrode being located in the groove, and the second electrode being located on a side of the second semiconductor layer away from the substrate.

[0014] Optionally, when growing the p-type layer, the preparation method includes: growing a first p-type material layer; forming a photoresist layer on the surface of the first p-type material layer, the photoresist layer having an injection groove exposing the first p-type material layer, the orthographic projection of the injection groove on the substrate coincides with the orthographic projection of the local area on the substrate; injecting silicon ions into the first p-type material layer through the injection groove; removing the photoresist layer, growing a second p-type material layer, and obtaining the p-type layer.

[0015] Optionally, before forming the first electrode and the second electrode on the epitaxial wafer, the preparation method further includes: etching the second semiconductor layer to form a groove exposing the second semiconductor layer; and treating the groove with a hydrofluoric acid solution for 30s to 120s.

[0016] The beneficial effects of the technical solutions provided by the embodiments of the present disclosure include at least:

[0017] The light-emitting diode chip provided by the embodiment of the present disclosure includes a light-emitting structure stacked on a substrate, and a first electrode and a second electrode are also provided on the light-emitting structure. The first electrode is located in the groove and connected to the first semiconductor layer, and the second electrode is connected to the second semiconductor layer. In this way, when the first electrode and the second electrode are energized, the light-emitting diode chip can be controlled to be energized and emit light.

[0018] The localized region of the p-type layer is located near the groove, and the localized region is distributed along the edge of the groove and around the groove. Silicon ions are also injected into the localized region, replacing gallium ions in the semiconductor layer. Gallium ions are typically trivalent, while silicon ions are tetravalent. When silicon ions replace gallium ions, an additional electron is generated in the semiconductor layer. Since the p-type layer is rich in holes, injecting silicon ions into the localized region neutralizes the holes, reducing the number of neutralized carriers entering the localized region from the n-type layer, resulting in a sharp drop in the current in the localized region. Since the localized region is distributed along the edge of the groove, it effectively reduces the current in the region where the groove is located, preventing leakage caused by defects in the semiconductor layer after etching the groove, and improving the light efficiency of the LED chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0020] Figure 1 is a structural schematic diagram of a light-emitting diode chip provided by an embodiment of the present disclosure;

[0021] Figure 2 is a top view of a light-emitting diode chip provided by an embodiment of the present disclosure;

[0022] Figure 3 is a schematic diagram of a hierarchical structure of a light-emitting structure provided by an embodiment of the present disclosure;

[0023] Figure 4 yes Figure 1 A top view of a light emitting diode chip is provided;

[0024] Figure 5 This is a flow chart of a method for preparing a light-emitting diode chip provided by an embodiment of the present disclosure;

[0025] Figure 6 This is a schematic diagram of a process for preparing a light-emitting diode chip provided by an embodiment of the present disclosure;

[0026] Figure 7This is a schematic diagram of a process for preparing a light-emitting diode chip provided by an embodiment of the present disclosure;

[0027] Figure 8 This is a schematic diagram of a process for preparing a light-emitting diode chip provided in an embodiment of the present disclosure.

[0028] The descriptions of the marks in the figure are as follows:

[0029] 10. Substrate; 11. GaAs chip;

[0030] 20. Light-emitting structure; 21. First semiconductor layer; 210. Local region; 211. First portion; 212. Second portion; 22. Multi-quantum well layer; 23. Second semiconductor layer; 24. Groove;

[0031] 31. First electrode; 32. Second electrode;

[0032] 40. passivation layer; 41. first through hole; 42. second through hole;

[0033] 51. First soldering point block; 52. Second soldering point block;

[0034] 60. Protective layer; 61. Bonding layer. DETAILED DESCRIPTION

[0035] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0036] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by a person of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," "third," and similar words used in the patent specification and claims of this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish between different components. Similarly, terms such as "a" or "an" do not indicate a quantitative limitation, but rather indicate the presence of at least one. Terms such as "include" or "comprise" mean that the elements or objects preceding "include" or "comprises" encompass the elements or objects listed after "include" or "comprises," and their equivalents, and do not exclude other elements or objects. Terms such as "connected" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," "right," "top," and "bottom" are used only to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0037] Figure 1 FIG. 1 is a schematic diagram of the structure of a light-emitting diode chip provided by an embodiment of the present disclosure. Figure 1 As shown, the light emitting diode chip includes: a substrate 10 , a light emitting structure 20 , a first electrode 31 and a second electrode 32 .

[0038] like Figure 1 As shown, the light-emitting structure 20 includes a first semiconductor layer 21, a multi-quantum well layer 22, and a second semiconductor layer 23 stacked in sequence on a substrate 10, one of the first semiconductor layer 21 and the second semiconductor layer 23 is a p-type layer, and the surface of the second semiconductor layer 23 has a groove 24 exposing the first semiconductor layer 21, the first electrode 31 is located in the groove 24, and the second electrode 32 is located on the side of the second semiconductor layer 23 away from the substrate 10.

[0039] Figure 2 FIG. 1 is a top view of a light emitting diode chip provided by an embodiment of the present disclosure. Figure 2 As shown, a local region 210 of the p-type layer is implanted with silicon ions, and the local region 210 surrounds the groove 24 .

[0040] The light-emitting diode chip provided by the embodiment of the present disclosure includes a light-emitting structure 20 stacked on a substrate 10. A first electrode 31 and a second electrode 32 are also provided on the light-emitting structure 20. The first electrode 31 is located in the groove 24 and is connected to the first semiconductor layer 21. The second electrode 32 is connected to the second semiconductor layer 23. In this way, when the first electrode 31 and the second electrode 32 are energized, the light-emitting diode chip can be controlled to be energized and emit light.

[0041] Localized region 210 of the p-type layer is located near groove 24, and localized region 210 is distributed along the edge of groove 24 and around groove 24. Silicon ions are also injected into localized region 210, which replace gallium ions in the semiconductor layer. Gallium ions are typically trivalent, while silicon ions are tetravalent. After silicon ions replace gallium ions, an additional electron is generated in the semiconductor layer. Because a large number of holes are distributed in the p-type layer, injecting silicon ions into localized region 210 can neutralize the holes in localized region 210, thereby reducing the number of neutralized carriers entering localized region 210 from the n-type layer, causing a sharp drop in the current in localized region 210. Since localized region 210 is distributed along the edge of groove 24, it can effectively reduce the current in the area where groove 24 is located, preventing leakage caused by defects in the semiconductor layer after etching groove 24, thereby improving the light efficiency of the LED chip.

[0042] Optionally, the substrate 10 is a sapphire substrate 10. The sapphire substrate 10 has a relatively high light transmittance, that is, the substrate 10 is a transparent substrate 10. In addition, the sapphire material is relatively hard and has relatively stable chemical properties, so that the light-emitting diode has good light-emitting effect and stability.

[0043] In the embodiment of the present disclosure, one of the first semiconductor layer 21 and the second semiconductor layer 23 is a p-type layer, and the other of the first semiconductor layer 21 and the second semiconductor layer 23 is an n-type layer.

[0044] As an example, the first semiconductor layer 21 is a p-type layer, the first electrode 31 is a p-type electrode, the second semiconductor layer 23 is an n-type layer, and the second electrode 32 is an n-type electrode.

[0045] Optionally, the first semiconductor layer 21 is an n-type AlGaInP layer, and the thickness of the n-type AlGaInP layer may be 0.5 μm to 3 μm.

[0046] Optionally, the multi-quantum well layer 22 includes alternately grown AlGaInP quantum well layers and AlGaInP quantum barrier layers, wherein the Al content in the AlGaInP quantum well layers and the AlGaInP quantum barrier layers is different. The multi-quantum well layer 22 may include 3 to 8 periods of alternately stacked AlGaInP quantum well layers and AlGaInP quantum barrier layers.

[0047] As an example, in the embodiment of the present disclosure, the multi-quantum well layer 22 includes five periods of alternately stacked AlGaInP quantum well layers and AlGaInP quantum barrier layers.

[0048] Optionally, the thickness of the multi-quantum well layer 22 may be 150 nm to 200 nm.

[0049] Optionally, the second semiconductor layer 23 is an indium-doped p-type AlInP layer, and the thickness of the p-type AlInP layer may be 0.5 μm to 3 μm.

[0050] Alternatively, as Figure 2 As shown, the local area 210 includes a first part 211 and a second part 212. The first part 211 is adjacent to the groove 24 and surrounds the groove 24. The second part 212 is located on the side of the first part 211 away from the groove 24. The amount of silicon ions injected per unit volume in the first part 211 is higher than the amount of silicon ions injected per unit volume in the second part 212.

[0051] In the embodiment of the present disclosure, the first portion 211 is closer to the groove 24, so the amount of silicon ions injected per unit volume in the first portion 211 is greater, so as to neutralize most of the holes in the first portion 211, thereby significantly reducing the current in the first portion 211, effectively preventing the problem of leakage caused by defects generated after etching the groove 24 on the semiconductor layer, and improving the light efficiency of the light-emitting diode chip.

[0052] For example, the amount of silicon ions implanted in the first portion 211 may neutralize 75% to 85% of the holes in the first portion 211 .

[0053] In the embodiment of the present disclosure, the second portion 212 is a region connected to the first portion 211. The second portion 212 is farther from the groove 24 than the first portion 211. Therefore, the amount of silicon ions injected per unit volume in the second portion 212 can be less than that in the first portion 211, so as to neutralize a portion of the holes in the second portion 212 and reduce the current in the second portion 212. In this way, the second portion 212 is provided as a transition structure between the first portion 211 and other film layers of the p-type layer, which can prevent the current density in the other film layers of the p-type layer from being too high and easily diffusing to the first portion 211, that is, preventing the current from diffusing to the area where the groove 24 is located, so that the light efficiency is significantly improved, thereby improving the brightness of the light-emitting diode chip.

[0054] For example, the amount of silicon ions implanted in the second portion 212 may neutralize 35% to 45% of the holes in the second portion 212 .

[0055] In the embodiment of the present disclosure, the use of silicon ions to neutralize holes has a better effect, can effectively reduce the current density in the local area 210, and effectively prevent the problem of leakage caused by defects generated after etching the grooves 24 on the semiconductor layer.

[0056] Alternatively, as Figure 2 As shown, the groove 24 is an arc-shaped groove, with the first portion 211 and the second portion 212 both in a fan-shaped ring shape. The first portion 211 can be a fan-shaped ring structure surrounding the groove 24, while the second portion 212 can be a fan-shaped ring structure surrounding the first portion 211. This ensures that the local area 210 completely surrounds the groove 24, reducing the current density in the area where the groove 24 is located, preventing defects caused by etching the groove 24 in the semiconductor layer and causing leakage, thereby improving the light efficiency of the LED chip.

[0057] Optionally, in a direction of a line connecting the first electrode 31 and the second electrode 32 , a ratio of a length of the first portion 211 to a length of the second portion 212 is 1:1.5 to 1:3.

[0058] In the above implementation, the length of the first portion 211 is smaller than the length of the second portion 212. That is, in a direction parallel to the substrate 10, the area of the first portion 211 is smaller than the area of the second portion 212. This rationally controls the size of the first portion 211 to minimize the area with low current density on the p-type layer, thereby ensuring the chip's luminous efficiency. The larger size of the second portion 212 allows it to fully utilize its transition structure to prevent current from diffusing into the area where the groove 24 is located, significantly improving luminous efficiency.

[0059] For example, in the embodiment of the present disclosure, the ratio of the length of the first portion 211 to the length of the second portion 212 can be 1:2. Under this ratio, the light emitting effect of the chip can be effectively improved without affecting the brightness of the chip.

[0060] Figure 3 FIG. 2 is a schematic diagram of a hierarchical structure of a light emitting structure 20 provided in an embodiment of the present disclosure. Figure 3 As shown, in the thickness direction of the p-type layer, the local region 210 is located in the middle of the p-type layer.

[0061] In this way, the local region 210 is spaced apart from the multi-quantum well layer 22 , thereby preventing the local region 210 from directly contacting the multi-quantum well layer 22 and blocking current transmission.

[0062] Optionally, in the thickness direction of the p-type layer, the distance between the surface of the local region 210 close to the multi-quantum well layer 22 and the multi-quantum well layer 22 is 500 angstroms to 1500 angstroms.

[0063] By setting the distance between the local region 210 and the multi-quantum well layer 22 within the above range, it is avoided that the distance between the local region 210 and the multi-quantum well layer 22 is too small, so that the local region 210 blocks current transmission.

[0064] For example, in the embodiment of the present disclosure, the distance between the local region 210 and the multi-quantum well layer 22 is 1000 angstroms.

[0065] Optionally, the thickness of the local region 210 is 8000 angstroms to 12000 angstroms.

[0066] By setting the thickness of the local area 210 within the above range, it is possible to avoid the problem of leakage caused by defects generated after etching the groove 24 due to the thickness of the local area 210 being too small; it is also possible to avoid the problem of leakage caused by defects generated after etching the groove 24 due to the thickness of the local area 210 being too large, thereby increasing the amount of silicon ions injected, thereby increasing the preparation cost of the light-emitting diode chip.

[0067] Illustratively, in the embodiment of the present disclosure, the thickness of the local region 210 is 10,000 angstroms.

[0068] Alternatively, as Figure 1 As shown, the light-emitting diode chip also includes: a passivation layer 40, a first solder block 51 and a second solder block 52, the passivation layer 40 is located at least on the second semiconductor layer 23, the first electrode 31, the groove 24 and the second electrode 32, the passivation layer 40 has a first through hole 41 exposing the first electrode 31 and a second through hole 42 exposing the second electrode 32, the first solder block 51 and the second solder block 52 are located on the passivation layer 40, the first solder block 51 is connected to the first electrode 31 through the first through hole 41, and the second solder block 52 is connected to the second electrode 32 through the second through hole 42.

[0069] Figure 4 yes Figure 1 A top view of a light emitting diode chip is provided. Figure 4 As shown, the first soldering point block 51 and the second soldering point block 52 are both rectangular blocks, which increase the area and facilitate electrical conduction. In addition, the first soldering point block 51 and the second soldering point block 52 are spaced apart on the surface of the passivation layer 40.

[0070] Alternatively, the passivation layer 40 may be a distributed Bragg reflector (DBR) layer, which includes a plurality of periodically alternating SiO2 layers and TiO2 layers. The number of periods in the DBR layer may be between 20 and 50. For example, the number of periods in the DBR layer is 32.

[0071] The thickness of the SiO2 layer in the DBR layer may be 800 angstroms to 1200 angstroms, and the thickness of the TiO2 layer may be 500 angstroms to 900 angstroms.

[0072] In addition to the passivation function, the DBR layer is also used to reflect the light emitted from the multi-quantum well layer 22 to the DBR layer to the substrate 10, thereby improving the light extraction effect.

[0073] Alternatively, as Figure 1 As shown, a protective layer 60 is further provided on the surface of the passivation layer 40, and the protective layer 60 extends from the surface of the passivation layer 40 to the substrate 10, and the protective layer 60 has through holes exposing the first solder block 51 and the second solder block 52 to facilitate electrical connection.

[0074] For example, in the embodiment of the present disclosure, the protective layer 60 may be a silicon oxide layer, and the thickness of the silicon oxide layer is 2000 angstroms.

[0075] Figure 5 This is a flow chart of a method for preparing a light emitting diode chip provided by an embodiment of the present disclosure. Figure 1 The light emitting diode chip shown. Figure 5 As shown, the preparation method comprises:

[0076] S11 : providing an epitaxial wafer, wherein the epitaxial wafer includes a substrate 10 and a light emitting structure 20 located on the substrate 10 .

[0077] Among them, the light-emitting structure 20 includes a first semiconductor layer 21, a multi-quantum well layer 22, and a second semiconductor layer 23 stacked in sequence on the substrate 10. One of the first semiconductor layer 21 and the second semiconductor layer 23 is a p-type layer. The surface of the second semiconductor layer 23 has a groove 24 exposing the first semiconductor layer 21. A local area 210 of the p-type layer is implanted with silicon ions, and the local area 210 surrounds the groove 24.

[0078] S12: forming a first electrode 31 and a second electrode 32 on the epitaxial wafer.

[0079] The first electrode 31 is located in the groove 24 , and the second electrode 32 is located on a side of the second semiconductor layer 23 away from the substrate 10 .

[0080] The light-emitting diode chip prepared by this preparation method includes a light-emitting structure 20 stacked on a substrate 10. A first electrode 31 and a second electrode 32 are also provided on the light-emitting structure 20. The first electrode 31 is located in the groove 24 and connected to the first semiconductor layer 21, while the second electrode 32 is connected to the second semiconductor layer 23. Thus, when the first and second electrodes 31 and 32 are energized, the light-emitting diode chip can be controlled to emit light. A local region 210 of the p-type layer is located near the groove 24 and is distributed along the edge of the groove 24 and around the groove 24. Silicon ions are also injected into the local region 210. The silicon ions replace the gallium ions in the semiconductor layer. Gallium ions are typically trivalent, while silicon ions are tetravalent. When the silicon ions replace the gallium ions, an additional electron is generated in the semiconductor layer. Since a large number of holes are distributed in the p-type layer, the holes in the local area 210 can be neutralized by injecting silicon ions into the local area 210, thereby reducing the carriers entering the local area 210 from the n-type layer for neutralization, thereby causing the current in the local area 210 to drop sharply. Since the local area 210 is distributed along the edge of the groove 24, the current in the area where the groove 24 is located can be effectively reduced, preventing the defects caused by etching the groove 24 on the semiconductor layer from causing leakage problems, thereby improving the light efficiency of the light-emitting diode chip.

[0081] Figure 6 FIG. 1 is a schematic diagram of a process for preparing a light-emitting diode chip according to an embodiment of the present disclosure. Figure 6 As shown, the epitaxial wafer fabrication in step S11 may include the following steps:

[0082] In the first step, a GaAs wafer 11 is provided.

[0083] In the second step, a light emitting structure 20 is grown on the GaAs wafer 11 . The light emitting structure 20 includes a second semiconductor layer 23 , a multi-quantum well layer 22 and a first semiconductor layer 21 stacked in sequence.

[0084] In the embodiment of the present disclosure, one of the first semiconductor layer 21 and the second semiconductor layer 23 is a p-type layer, and the other of the first semiconductor layer 21 and the second semiconductor layer 23 is an n-type layer.

[0085] For example, the second semiconductor layer 23 may be an n-type AlGaInP layer, and the thickness of the n-type AlGaInP layer may be 0.5 μm to 3 μm.

[0086] For example, the first semiconductor layer 21 is an indium-doped p-type AlInP layer, and the thickness of the p-type AlInP layer may be 0.5 μm to 3 μm.

[0087] Optionally, the multi-quantum well layer 22 includes alternately grown AlGaInP quantum well layers and AlGaInP quantum barrier layers, wherein the Al content in the AlGaInP quantum well layers and the AlGaInP quantum barrier layers is different. The multi-quantum well layer 22 may include 3 to 8 periods of alternately stacked AlGaInP quantum well layers and AlGaInP quantum barrier layers.

[0088] As an example, in the embodiment of the present disclosure, the multi-quantum well layer 22 includes five periods of alternately stacked AlGaInP quantum well layers and AlGaInP quantum barrier layers.

[0089] Optionally, the thickness of the multi-quantum well layer 22 may be 150 nm to 200 nm.

[0090] In the second step, an etching stop layer may be grown before growing the second semiconductor layer 23 , and an AlInP carrier confinement layer may be grown before growing the multi-quantum well layer 22 .

[0091] For example, in the embodiment of the present disclosure, the first semiconductor layer 21 may be a p-type layer.

[0092] When growing the p-type layer, the preparation method may include:

[0093] A first p-type material layer is grown; a photoresist layer is formed on a surface of the first p-type material layer, the photoresist layer having an injection groove exposing the first p-type material layer, the orthographic projection of the injection groove on the substrate coincides with the orthographic projection of the local area on the substrate; silicon ions are injected into the first p-type material layer through the injection groove; the photoresist layer is removed, and a second p-type material layer is grown to obtain a p-type layer.

[0094] Specifically, when growing the first semiconductor layer 21 , a first p-type material layer may be formed first.

[0095] The thickness of the first p-type material layer may be 8500 angstroms to 13500 angstroms.

[0096] For example, a first p-type material layer is grown to a thickness of 11,000 angstroms.

[0097] Next, a first photoresist layer is formed on the surface of the grown first p-type material layer. The first photoresist layer exposes a first region of the first p-type material layer. Silicon ions are implanted into the first region to form a first portion 211 of the local region 210 .

[0098] Then, the first photoresist layer is removed and a second photoresist layer is formed on the surface of the first p-type material layer. The second photoresist layer exposes a second region of the first p-type material layer. Silicon ions are implanted into the second region to form a second portion 212 of the local region 210.

[0099] The amount of silicon ions implanted per unit volume in the first portion 211 is greater than the amount of silicon ions implanted per unit volume in the second portion 212 .

[0100] In the embodiment of the present disclosure, the first portion 211 is closer to the groove 24, so the amount of silicon ions injected per unit volume in the first portion 211 is greater, so as to neutralize most of the holes in the first portion 211, thereby significantly reducing the current in the first portion 211, effectively preventing the problem of leakage caused by defects generated after etching the groove 24 on the semiconductor layer, and improving the light efficiency of the light-emitting diode chip.

[0101] Next, the second photoresist layer is removed, and a second p-type material layer is grown to form a p-type layer.

[0102] After growing the first semiconductor layer 21 , a GaP window layer may be further grown, wherein the thickness of the GaP window layer is 10,000 angstroms to 20,000 angstroms.

[0103] Illustratively, the thickness of the GaP window layer is 11,000 angstroms.

[0104] The third step, such as Figure 7 As shown, a bonding layer 61 is formed between the first semiconductor layer 21 and the sapphire substrate 10 , the light emitting structure 20 is bonded to the sapphire substrate 10 , and the GaAs wafer 11 is removed.

[0105] Since the sapphire substrate 10 has a relatively high light transmittance, and the sapphire material is relatively hard and has relatively stable chemical properties, the use of the sapphire substrate 10 can enable the light-emitting diode to have good light-emitting effect and stability.

[0106] Specifically, the process may include coating silicon oxide liquid on the surface of the second semiconductor layer 23, placing the sapphire substrate 10 on the surface of the second semiconductor layer 23, and heating the epitaxial wafer to heat and solidify the silicon oxide liquid to form a bonding layer 61 between the second semiconductor layer 23 and the sapphire substrate 10.

[0107] Optionally, the heating temperature of the epitaxial wafer is 250° C. to 350° C. Exemplarily, the heating temperature may be 300° C.

[0108] like Figure 8 As shown, before step S12, the preparation method further includes the following steps:

[0109] In the first step, the second semiconductor layer 23 is etched to form a groove 24 exposing the second semiconductor layer 23 .

[0110] Specifically, the method may include: etching the second semiconductor layer 23 by dry etching to expose the first semiconductor layer 21 .

[0111] In the second step, the groove is treated with a hydrofluoric acid solution for 30s to 120s.

[0112] The concentration of hydrogen fluoride in the hydrofluoric acid solution may be 2% to 5%.

[0113] For example, the groove 24 is treated with a 3% hydrofluoric acid solution for 60 seconds, which can etch away defects at the edge of the groove 24 and form a smooth groove 24 at the quantum well, thereby improving light efficiency.

[0114] like Figure 1 As shown, in step S12 , preparing the first electrode 31 and the second electrode 32 may include: forming the first electrode 31 in the groove 24 , and forming the second electrode 32 on the second semiconductor layer 23 .

[0115] The forming of the first electrode 31 and the second electrode 32 may include: processing the first electrode 31 and the second electrode 32 separately by using a negative resist stripping method.

[0116] Among them, the first electrode 31 uses gold beryllium as the main component, and the second electrode 32 uses gold germanium as the base material for vapor deposition. When evaporating the gold germanium alloy, the evaporation power must be guaranteed to avoid the evaporation time exceeding seconds to prevent the deviation of the alloy composition, and annealing is performed.

[0117] After step S12, the preparation method may further include the following steps:

[0118] The first step, such as Figure 1 As shown, a passivation layer 40 is formed on the epitaxial wafer. The passivation layer 40 is at least located on the surface of the second semiconductor layer 23 , the first electrode 31 , the second electrode 32 and the groove 24 .

[0119] The passivation layer 40 may be a distributed Bragg reflector layer, which may be a DBR layer. The DBR layer includes a plurality of periodically alternating SiO2 layers and TiO2 layers. The number of periods in the DBR layer may be between 20 and 50. For example, the number of periods in the DBR layer is 32.

[0120] The thickness of the SiO2 layer in the DBR layer may be 800 angstroms to 1200 angstroms, and the thickness of the TiO2 layer may be 500 angstroms to 900 angstroms.

[0121] In a second step, a first through hole 41 and a second through hole 42 are formed on the passivation layer 40 . The first through hole 41 extends to the first electrode 31 , and the second through hole 42 extends to the second electrode 32 .

[0122] After the passivation layer 40 is formed, a first through hole 41 and a second through hole 42 are formed on a surface of the passivation layer 40 away from the substrate 10 . The first through hole 41 extends to the first electrode 31 , and the second through hole 42 extends to the second electrode 32 .

[0123] In the third step, a first soldering block 51 and a second soldering block 52 are made on the surface of the passivation layer 40 . The first soldering block 51 is connected to the first electrode 31 through the first through hole 41 , and the second soldering block 52 is connected to the second electrode 32 through the second through hole 42 .

[0124] A first solder joint block 51 is formed on the surface of the passivation layer 40 by photolithography, so that the first solder joint block 51 is connected to the first electrode 31 through the first through hole 41; then, a second solder joint block 52 is formed on the surface of the passivation layer 40 by photolithography, so that the second solder joint block 52 is connected to the second electrode 32 through the second through hole 42.

[0125] In the embodiment of the present disclosure, the first soldering block 51 and the second soldering block 52 may include a Ti layer, a first Ni layer, an Au layer, a second Ni layer, and a Sn alloy layer stacked in sequence.

[0126] Illustratively, the thickness of the Ti layer may be 500 angstroms to 1500 angstroms, for example, the thickness of the Ti layer may be 1000 angstroms.

[0127] Illustratively, the thickness of the first Ni layer may be 500 angstroms to 1500 angstroms. For example, the thickness of the first Ni layer may be 1000 angstroms.

[0128] Illustratively, the thickness of the Au layer may be 8,000 angstroms to 12,000 angstroms. For example, the thickness of the Au layer may be 10,000 angstroms.

[0129] Illustratively, the thickness of the second Ni layer may be 2000 angstroms to 4000 angstroms. For example, the thickness of the second Ni layer may be 3000 angstroms.

[0130] Illustratively, the thickness of the Sn alloy layer may be 80,000 angstroms to 100,000 angstroms. For example, the thickness of the Sn alloy layer may be 90,000 angstroms.

[0131] In the embodiment of the present disclosure, after the first solder joint block 51 and the second solder joint block 52 are manufactured, the preparation method may further include: manufacturing a protective layer 60 on the surface of the passivation layer 40 , and the protective layer 60 extends from the surface of the passivation layer 40 to the substrate 10 .

[0132] For example, in the embodiment of the present disclosure, the protective layer 60 may be a silicon oxide layer, and the thickness of the silicon oxide layer is 2000 angstroms.

[0133] It should be noted that after the protective layer 60 is grown on the surface of the passivation layer 40 , a photolithography technique may be used to etch through holes on the surface of the protective layer 60 to expose the solder joints for electrical connection.

[0134] Finally, the sapphire can be subjected to invisible cutting and cleaving, which can effectively reduce the loss of brightness. Then, the light-emitting diode chip is obtained by testing.

[0135] The above description is merely an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the scope of protection of the present disclosure.

Claims

1. A light-emitting diode chip with improved light efficiency, characterized in that: The light-emitting diode chip comprises: a substrate (10), a light-emitting structure (20), a first electrode (31) and a second electrode (32); The light emitting structure (20) comprises a first semiconductor layer (21), a multi-quantum well layer (22), and a second semiconductor layer (23) stacked in sequence on the substrate (10); one of the first semiconductor layer (21) and the second semiconductor layer (23) is a p-type layer; a surface of the second semiconductor layer (23) has a groove (24) exposing the first semiconductor layer (21); the first electrode (31) is located in the groove (24); and the second electrode (32) is located on a side of the second semiconductor layer (23) away from the substrate (10); Silicon ions are implanted into a local region (210) of the p-type layer, and the local region (210) surrounds the groove (24) along an edge of the groove (24).

2. The light-emitting diode chip according to claim 1, characterized in that The local area (210) includes a first portion (211) and a second portion (212), wherein the first portion (211) is adjacent to the groove (24) and surrounds the groove (24), and the second portion (212) is located on a side of the first portion (211) away from the groove (24), and the amount of silicon ions implanted per unit volume in the first portion (211) is greater than the amount of silicon ions implanted per unit volume in the second portion (212).

3. The light-emitting diode chip according to claim 2, characterized in that In the direction of a line connecting the first electrode (31) and the second electrode (32), the ratio of the length of the first portion (211) to the length of the second portion (212) is 1:1.5 to 1:

3.

4. The light-emitting diode chip according to claim 2, characterized in that: The groove (24) is an arc-shaped groove, and the first portion (211) and the second portion (212) are both in a fan-shaped ring shape.

5. The light-emitting diode chip according to any one of claims 1 to 4, characterized in that: In the thickness direction of the p-type layer, the local region (210) is located in the middle of the p-type layer.

6. The light-emitting diode chip according to claim 5, characterized in that In the thickness direction of the p-type layer, the distance between the surface of the local region (210) close to the multi-quantum well layer (22) and the multi-quantum well layer (22) is 500 angstroms to 1500 angstroms.

7. The light-emitting diode chip according to claim 5, characterized in that The thickness of the local region (210) is 8000 angstroms to 12000 angstroms.

8. A method for preparing a light-emitting diode chip with improved light efficiency, characterized in that: The preparation method comprises: An epitaxial wafer is provided, comprising a substrate and a light-emitting structure located on the substrate, the light-emitting structure comprising a first semiconductor layer, a multi-quantum well layer, and a second semiconductor layer sequentially stacked on the substrate, one of the first semiconductor layer and the second semiconductor layer being a p-type layer, and a surface of the second semiconductor layer having a groove exposing the first semiconductor layer; silicon ions are implanted in a local region of the p-type layer, the local region surrounding the groove along an edge of the groove; A first electrode and a second electrode are manufactured on the epitaxial wafer, wherein the first electrode is located in the groove, and the second electrode is located on a side of the second semiconductor layer away from the substrate.

9. The preparation method according to claim 8, characterized in that When growing the p-type layer, the preparation method includes: growing a first p-type material layer; forming a photoresist layer on a surface of the first p-type material layer, wherein the photoresist layer has an injection groove exposing the first p-type material layer, and an orthographic projection of the injection groove on the substrate coincides with an orthographic projection of the local area on the substrate; implanting silicon ions into the first p-type material layer through the implantation groove; The photoresist layer is removed, and a second p-type material layer is grown to obtain the p-type layer.

10. The preparation method according to claim 8, characterized in that Before fabricating the first electrode and the second electrode on the epitaxial wafer, the preparation method further comprises: etching the second semiconductor layer to form a groove exposing the second semiconductor layer; The groove is treated with a hydrofluoric acid solution for 30s to 120s.

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