Light-emitting diode chip with improved sorting damage and preparation method thereof

Abstract

The present disclosure provides a light-emitting diode chip with improved sorting damage and a preparation method thereof, belonging to the field of optoelectronic manufacturing technology. The light-emitting diode chip includes: a substrate, a light-emitting structure, a first electrode, a second electrode and a passivation layer; the light-emitting structure is stacked on the substrate, the first electrode and the second electrode are located on the surface of the light-emitting structure away from the substrate, the passivation layer is located on the surface of the light-emitting structure away from the substrate, the passivation layer includes a connected top pin part and a surrounding part, the surrounding part surrounds the top pin part, and the surrounding part covers the first electrode and the second electrode, the top pin part is located between the first electrode and the second electrode; the top pin part includes a silicon nitride layer, the roughness of the surface of the silicon nitride layer away from the substrate is higher than the roughness of the surface of the surrounding part away from the substrate. The embodiment of the present disclosure can improve the problem that the epitaxial structure of the chip is easily cracked when sorting the chip.

Description

Technical Field

[0001] The present disclosure relates to the field of optoelectronic manufacturing technology, and in particular to a light emitting diode chip with improved sorting damage and a preparation method thereof. Background Art

[0002] Micro LEDs (Micro Light Emitting Diodes) refer to ultra-small light-emitting diodes with side lengths ranging from 10μm to 100μm. Due to their small size, micro LEDs can be arranged more densely, significantly improving resolution. They also have self-luminous properties, and have the characteristics of high brightness, high contrast, high responsiveness, and energy saving.

[0003] In related technologies, LED chips typically consist of a substrate, a light-emitting structure, a passivation layer, and two electrodes. Before being installed in a product, these LED chips must be sorted into their corresponding packaging structures using sorting equipment. During this process, the ejector pins of the sorting equipment directly penetrate the front of the LED, exerting a significant impact.

[0004] However, since the epitaxial material of the light-emitting diode is relatively brittle and has low hardness, the epitaxial structure is easily cracked by the ejector pin after being impacted by the ejector pin. If the multi-quantum well layer in the epitaxial structure is damaged, leakage problems will occur, affecting the use of the light-emitting diode chip. Summary of the Invention

[0005] The present disclosure provides a light-emitting diode chip with improved sorting damage and a method for manufacturing the same, which can improve the problem of the chip's epitaxial structure being easily cracked during chip sorting and effectively reduce the possibility of chip damage during the sorting process. The technical solution is as follows:

[0006] On the one hand, an embodiment of the present disclosure provides a light-emitting diode chip with improved sorting damage, the light-emitting diode chip comprising: a substrate, a light-emitting structure, a first electrode, a second electrode and a passivation layer; the light-emitting structure is stacked on the substrate, the first electrode and the second electrode are located on the surface of the light-emitting structure away from the substrate, the passivation layer is located on the surface of the light-emitting structure away from the substrate, the passivation layer comprises a connected top pin portion and a surrounding portion, the surrounding portion surrounds the top pin portion, and the surrounding portion covers the first electrode and the second electrode, the top pin portion is located between the first electrode and the second electrode; the top pin portion comprises a silicon nitride layer, the roughness of the surface of the silicon nitride layer away from the substrate is higher than the roughness of the surface of the surrounding portion away from the substrate.

[0007] Optionally, the silicon nitride layer includes a first sublayer and a second sublayer sequentially stacked on the surface of the light emitting structure, the density of the first sublayer is higher than the density of the second sublayer, and the thickness of the first sublayer is greater than the thickness of the second sublayer.

[0008] Optionally, the thickness of the first sub-layer is 3.8 μm to 4.2 μm, and the thickness of the second sub-layer is 0.4 μm to 0.6 μm.

[0009] Optionally, the ejector portion further includes a light guiding layer, which is located on a side of the silicon nitride layer close to the light emitting structure; the light guiding layer is used to reflect light incident from the surface of the light guiding layer close to the light emitting structure to the surrounding portion.

[0010] Optionally, the light guiding layer includes a first silicon oxide layer, a metal layer, and a second silicon oxide layer stacked in sequence, and a surface of the first silicon oxide layer away from the substrate has a protruding structure.

[0011] Optionally, the metal layer is an Al layer, and the thickness of the metal layer is 1500 angstroms to 2500 angstroms.

[0012] Optionally, the light guiding layer further includes a Cr layer, and the Cr layer is located between the first silicon oxide layer and the metal layer.

[0013] Optionally, the Cr layer has a thickness of 30 angstroms to 100 angstroms.

[0014] On the other hand, the present disclosure also provides a method for preparing a light-emitting diode chip with improved sorting damage, the method comprising:

[0015] providing a substrate;

[0016] Growing a light-emitting structure on the substrate, and forming a first electrode and a second electrode on a surface of the light-emitting structure away from the substrate;

[0017] A passivation layer is formed on a surface of the light-emitting structure away from the substrate, the passivation layer covers the first electrode and the second electrode, the passivation layer has a connected top needle portion and a surrounding portion, and the surrounding portion covers the first electrode and the second electrode, the top needle portion is located between the first electrode and the second electrode, the top needle portion includes a silicon nitride layer, and the roughness of the surface of the silicon nitride layer away from the substrate is higher than the roughness of the surface of the surrounding portion away from the substrate.

[0018] Optionally, the silicon nitride layer includes a first sublayer and a second sublayer sequentially stacked on the surface of the light-emitting structure; the growth rate of the first sublayer is less than the growth rate of the second sublayer, the growth rate of the second sublayer is not less than 100 Å / S, the thickness of the first sublayer is 3.8 μm to 4.2 μm, and the thickness of the second sublayer is 0.4 μm to 0.6 μm.

[0019] The beneficial effects of the technical solutions provided by the embodiments of the present disclosure include at least:

[0020] The light-emitting diode chip provided by the embodiment of the present disclosure includes a light-emitting structure stacked on a substrate, and the light-emitting structure also has a first electrode and a second electrode, and a passivation layer is provided on the surface of the light-emitting structure away from the substrate. The passivation layer has a connected ejector pin portion and a surrounding portion, the surrounding portion surrounds the ejector pin portion, and the ejector pin portion includes a silicon nitride layer stacked on the surface of the light-emitting structure. Since the ejector pin portion is used for sorting chips, the area on the passivation layer that contacts the ejector pin is a whole layer of silicon nitride layer, that is, the silicon nitride layer is relatively thick, and the thick silicon nitride layer has high toughness and strength, so the silicon nitride layer can better block the impact of the ejector pin; at the same time, the roughness of the surface of the silicon nitride layer away from the substrate is higher than the roughness of the top surface of the passivation layer, so the surface of the silicon nitride layer in contact with the ejector pin is relatively rough, so as to effectively prevent the ejector pin from sliding toward the surrounding portion, ensuring that the ejector pin is always in contact with the ejector pin portion during sorting, thereby obtaining a good impact resistance effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0022] Figure 1 1 is a schematic structural diagram of a light-emitting diode chip with improved sorting damage provided by an embodiment of the present disclosure;

[0023] Figure 2 1 is a schematic structural diagram of an ejector pin portion provided by an embodiment of the present disclosure;

[0024] Figure 3 is a top view of a light-emitting diode chip provided by an embodiment of the present disclosure;

[0025] Figure 4 is a structural schematic diagram of a light guiding layer provided by an embodiment of the present disclosure;

[0026] Figure 5 is a schematic diagram of a first silicon oxide layer provided by an embodiment of the present disclosure;

[0027] Figure 6 This is a flow chart of a method for preparing a light-emitting diode chip with improved sorting damage provided by an embodiment of the present disclosure;

[0028] Figure 7 This is a schematic diagram of a process for preparing a light-emitting diode chip provided by an embodiment of the present disclosure;

[0029] Figure 8 This is a schematic diagram of a process for preparing a light-emitting diode chip provided in an embodiment of the present disclosure.

[0030] The descriptions of the marks in the figure are as follows:

[0031] 10. Substrate; 11. GaAs substrate;

[0032] 20. Light-emitting structure; 21. First semiconductor layer; 22. Multi-quantum well layer; 23. Second semiconductor layer; 24. Groove;

[0033] 31. First electrode; 32. Second electrode;

[0034] 40. Passivation layer; 41. Ejector pin portion; 410. Silicon nitride layer; 411. First sublayer; 412. Second sublayer; 413. Light guiding layer; 414. First silicon oxide layer; 415. Metal layer; 416. Second silicon oxide layer; 417. Protrusion structure; 418. Cr layer; 42. Peripheral portion; 421. Through hole;

[0035] 51. First soldering point block; 52. Second soldering point block. DETAILED DESCRIPTION

[0036] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0037] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by a person of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," "third," and similar words used in the patent specification and claims of this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish between different components. Similarly, terms such as "a" or "an" do not indicate a quantitative limitation, but rather indicate the presence of at least one. Terms such as "include" or "comprise" mean that the elements or objects preceding "include" or "comprises" encompass the elements or objects listed after "include" or "comprises," and their equivalents, and do not exclude other elements or objects. Terms such as "connected" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," "right," "top," and "bottom" are used only to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0038] Figure 1 Schematic diagram of the structure of a light emitting diode chip with improved sorting damage provided by an embodiment of the present disclosure. Figure 1 As shown, the light emitting diode chip includes: a substrate 10 , a light emitting structure 20 , a first electrode 31 , a second electrode 32 and a passivation layer 40 .

[0039] like Figure 1 As shown, the light emitting structure 20 is stacked on the substrate 10, the first electrode 31 and the second electrode 32 are located on the surface of the light emitting structure 20 away from the substrate 10, and the passivation layer 40 is located on the surface of the light emitting structure 20 away from the substrate 10. The passivation layer 40 includes a connected ejector portion 41 and a surrounding portion 42. The surrounding portion 42 surrounds the ejector portion 41 and covers the first electrode 31 and the second electrode 32. The ejector portion 41 is located between the first electrode 31 and the second electrode 32.

[0040] Figure 2 Schematic diagram of the structure of a ejector pin provided by an embodiment of the present disclosure. Figure 2 As shown, the ejector pin portion 41 includes a silicon nitride layer 410 , and the roughness of the surface of the silicon nitride layer 410 away from the substrate 10 is higher than the roughness of the surface of the surrounding portion 42 away from the substrate 10 .

[0041] The light-emitting diode chip provided by the embodiment of the present disclosure includes a light-emitting structure 20 stacked on a substrate 10. A first electrode 31 and a second electrode 32 are also provided on the light-emitting structure 20. In addition, a passivation layer 40 is provided on the surface of the light-emitting structure 20 away from the substrate 10. The passivation layer 40 includes a connected ejector portion 41 and a surrounding portion 42. The surrounding portion 42 surrounds the ejector portion 41. The ejector portion 41 includes a silicon nitride layer 410 stacked on the surface of the light-emitting structure 20. Since the ejector pin portion 41 is used for sorting chips, the area on the passivation layer 40 that contacts the ejector pin is a whole layer of silicon nitride layer 410, that is, the silicon nitride layer 410 is relatively thick, and the thick silicon nitride layer 410 has high toughness and strength, so the silicon nitride layer 410 can better block the impact of the ejector pin; at the same time, the roughness of the surface of the silicon nitride layer 410 away from the substrate 10 is higher than the roughness of the top surface of the passivation layer 40, so the surface of the silicon nitride layer 410 in contact with the ejector pin is relatively rough, which effectively prevents the ejector pin from sliding toward the surrounding part, ensuring that the ejector pin is always in contact with the ejector pin portion 41 during sorting, thereby achieving good impact resistance.

[0042] Alternatively, as Figure 2 As shown, the silicon nitride layer 410 includes a first sublayer 411 and a second sublayer 412 sequentially stacked on the surface of the light emitting structure 20 , the density of the first sublayer 411 is higher than the density of the second sublayer 412 , and the thickness of the first sublayer 411 is greater than the thickness of the second sublayer 412 .

[0043] The first sub-layer and the second sub-layer are both film layers made of silicon nitride material.

[0044] In the above implementation, the ejector portion 41 includes a first sub-layer 411 and a second sub-layer 412 sequentially stacked on the surface of the light emitting structure 20 . Among them, the growth rate of the first sublayer 411 is slower than that of the second sublayer 412, so the density of the first sublayer 411 is higher than that of the second sublayer 412, so the first sublayer 411 has good impact resistance. Moreover, the thickness of the first sublayer 411 is greater than that of the second sublayer 412 to ensure that the thickness of the first sublayer 411 is large enough so that the silicon nitride layer 410 has good toughness and strength, so that the silicon nitride layer 410 can better block the impact of the ejector pin. A thinner second sublayer 412 is provided on the surface of the first sublayer 411. Since the density of the second sublayer 412 is lower, the surface roughness of the second sublayer 412 is higher than the roughness of the top surface of the passivation layer 40. In this way, the second sublayer 412 can effectively prevent the ejector pin from sliding toward the surrounding portion 42, ensuring that the ejector pin is always in contact with the ejector pin portion 41 during sorting, thereby achieving good impact resistance.

[0045] Optionally, the substrate 10 is a sapphire substrate 10. The sapphire substrate 10 has a relatively high light transmittance, that is, the substrate 10 is a transparent substrate 10. In addition, the sapphire material is relatively hard and has relatively stable chemical properties, so that the light-emitting diode has good light-emitting effect and stability.

[0046] Alternatively, as Figure 1 As shown, the light-emitting structure 20 includes: a first semiconductor layer 21, a multi-quantum well layer 22, and a second semiconductor layer 23. The first semiconductor layer 21, the multi-quantum well layer 22, and the second semiconductor layer 23 are sequentially stacked on the substrate 10. The second electrode 32 is located on the surface of the second semiconductor layer 23. The surface of the second semiconductor layer 23 has a groove 24 that exposes the first semiconductor layer 21. The first electrode 31 is located on the surface of the first semiconductor layer 21 and on the bottom of the groove 24. The passivation layer 40 covers at least the surfaces of the first semiconductor layer 21, the first electrode 31, the groove 24, the second semiconductor layer 23, and the second electrode 32. In this way, a portion of the second semiconductor layer 23 and the multi-quantum well layer 22 are removed through the groove 24, so that the first electrode 31 is directly disposed on the surface of the first semiconductor layer 21 through the connection groove, thereby reducing the overall thickness of the epitaxial structure.

[0047] Alternatively, as Figure 1 As shown, the light-emitting diode chip further includes a first soldering block 51 and a second soldering block 52, both of which are located on the surface of the passivation layer 40. The peripheral portion 42 also has a through hole 421 that exposes the first electrode 31 and the second electrode 32. The first soldering block 51 is connected to the first electrode 31 through the through hole 421, and the second soldering block 52 is connected to the second electrode 32 through the through hole 421.

[0048] In the embodiment of the present disclosure, Figure 1 As shown, the ejector pin portion 41 is located between the first soldering block 51 and the second soldering block 52 , and the ejector pin portion 41 is in the middle of the passivation layer 40 .

[0049] Figure 3 FIG. 1 is a top view of a light emitting diode chip provided by an embodiment of the present disclosure. Figure 3 As shown, the first soldering point block 51 and the second soldering point block 52 are both rectangular blocks, which increase the area and facilitate electrical conduction. In addition, the first soldering point block 51 and the second soldering point block 52 are spaced apart on the surface of the passivation layer 40.

[0050] In the embodiment of the present disclosure, one of the first semiconductor layer 21 and the second semiconductor layer 23 is a p-type layer, and the other of the first semiconductor layer 21 and the second semiconductor layer 23 is an n-type layer.

[0051] As an example, the first semiconductor layer 21 is an n-type layer, the first electrode 31 is an n-type electrode, the second semiconductor layer 23 is a p-type layer, and the second electrode 32 is a p-type electrode.

[0052] Optionally, the first semiconductor layer 21 is an n-type AlGaInP layer, and the thickness of the n-type AlGaInP layer may be 0.5 μm to 3 μm.

[0053] Optionally, the multi-quantum well layer 22 includes alternately grown AlGaInP quantum well layers and AlGaInP quantum barrier layers, wherein the Al content in the AlGaInP quantum well layers and the AlGaInP quantum barrier layers is different. The multi-quantum well layer 22 may include 3 to 8 periods of alternately stacked AlGaInP quantum well layers and AlGaInP quantum barrier layers.

[0054] As an example, in the embodiment of the present disclosure, the multi-quantum well layer 22 includes five periods of alternately stacked AlGaInP quantum well layers and AlGaInP quantum barrier layers.

[0055] Optionally, the thickness of the multi-quantum well layer 22 may be 150 nm to 200 nm.

[0056] Optionally, the second semiconductor layer 23 is an indium-doped p-type AlInP layer, and the thickness of the p-type AlInP layer may be 0.5 μm to 3 μm.

[0057] Alternatively, the peripheral portion 42 may be a distributed Bragg reflector (DBR) layer, which includes a plurality of periodically alternating SiO2 layers and TiO2 layers. The number of periods in the DBR layer may be between 20 and 50. For example, the number of periods in the DBR layer is 32.

[0058] The thickness of the SiO2 layer in the DBR layer may be 800 angstroms to 1200 angstroms, and the thickness of the TiO2 layer may be 500 angstroms to 900 angstroms.

[0059] In addition to the passivation function, the DBR layer is also used to reflect the light emitted from the multi-quantum well layer 22 to the surrounding portion 42 to the substrate 10, thereby improving the light extraction effect.

[0060] Optionally, the thickness of the first sub-layer 411 is 3.8 μm to 4.2 μm.

[0061] The thickness of the first sublayer 411 is greater than that of the second sublayer 412. The ejector pin portion 41 is the area that contacts the ejector pins during chip sorting. Setting the thickness of the first sublayer 411 within the aforementioned range ensures a relatively high thickness. Thick silicon nitride layers have high toughness and strength, so the first sublayer 411 can effectively resist the impact of the ejector pins.

[0062] Exemplarily, the thickness of the first sub-layer 411 is 4 μm.

[0063] Optionally, the thickness of the second sublayer 412 is 0.4 μm to 0.6 μm. By setting the thickness of the second sublayer 412 within the above range, the second sublayer 412 is prevented from being too thick, which would reduce the growth rate of the second sublayer 412 and affect its rapid growth; and the second sublayer 412 is prevented from being too thin, which would not improve the roughness between the ejector pins and the ejector pin portion 41.

[0064] Exemplarily, the thickness of the second sub-layer 412 is 0.5 μm.

[0065] Alternatively, as Figure 2 As shown, the pin portion 41 further includes a light guiding layer 413 , which is located on a side of the silicon nitride layer 410 close to the light emitting structure 20 ; the light guiding layer 413 is used to reflect light incident from the surface of the light guiding layer 413 close to the light emitting structure 20 to the surrounding portion 42 .

[0066] In the above implementation, by providing the light guiding layer 413 , the photons incident on the ejector portion 41 can be effectively transferred toward the surrounding portion 42 , thereby preventing the photons from entering the first sublayer 411 to be absorbed, thereby improving the luminous effect of the LED chip.

[0067] Illustratively, the thickness of the light guiding layer 413 is 1.5 μm to 2.5 μm.

[0068] By setting the thickness of the light guiding layer 413 within the above range, the thickness of the light guiding layer 413 can be avoided from being too large, thereby increasing the production cost; and the thickness of the light guiding layer 413 can be avoided from being too small, thereby failing to guide photons to the surrounding part 42.

[0069] Illustratively, the thickness of the light guiding layer 413 is 2 μm.

[0070] Figure 4 Schematic diagram of the structure of a light guide layer 413 provided by an embodiment of the present disclosure. Figure 4 As shown, the light guiding layer 413 includes a first silicon oxide layer 414, a metal layer 415 and a second silicon oxide layer 416 stacked in sequence.

[0071] Figure 5 FIG. 4 is a schematic diagram of a first silicon oxide layer 414 provided in an embodiment of the present disclosure. Figure 5 As shown, the surface of the first silicon oxide layer 414 away from the substrate 10 has a protrusion structure 417 .

[0072] like Figure 5As shown, the protrusion structure 417 is a plate-like protrusion distributed at intervals on the first silicon oxide layer 414, and a metal layer 415 is attached to the surface of the plate-like protrusion. In this way, after the light is incident on the first silicon oxide layer 414, it can be reflected at the position of the plate-like protrusion to guide the light to the surrounding part 42, preventing photons from entering the first sub-layer 411 and being absorbed, thereby improving the luminous effect of the light-emitting diode chip.

[0073] Optionally, the metal layer 415 is an Al layer, and the thickness of the metal layer 415 is 1500 angstroms to 2500 angstroms.

[0074] Since metal aluminum has good reflective properties, using metal aluminum as the metal layer 415 can effectively enhance the luminous effect of the metal layer 415 , allowing most of the light incident on the first silicon oxide layer 414 to be reflected at the plate-shaped protrusions to guide the light toward the surrounding portion 42 .

[0075] Illustratively, the thickness of the metal layer 415 is 1000 angstroms.

[0076] Optionally, the light guiding layer 413 further includes a Cr layer 418 , and the Cr layer 418 is located between the first silicon oxide layer 414 and the metal layer 415 .

[0077] Since metallic chromium has good adhesion properties, the Cr layer 418 is used to connect the first silicon oxide layer 414 and the metal layer 415 , which can effectively improve the connection tightness between the first silicon oxide layer 414 and the metal layer 415 .

[0078] Optionally, the thickness of the Cr layer 418 is 30 angstroms to 100 angstroms.

[0079] By setting the thickness of the Cr layer 418 within the above range, the thickness of the Cr layer 418 can be prevented from being too large, thereby increasing the manufacturing cost; and the thickness of the Cr layer 418 can be prevented from being too small, thereby failing to play the role of the first silicon oxide layer 414 and the metal layer 415.

[0080] Illustratively, the thickness of the Cr layer 418 is 50 angstroms.

[0081] Figure 6 This is a flow chart of a method for preparing a light-emitting diode chip with improved sorting damage provided by an embodiment of the present disclosure. Figure 1 The light emitting diode chip shown. Figure 6 As shown, the preparation method comprises:

[0082] S11: providing a substrate 10.

[0083] S12 : forming the light emitting structure 20 on the substrate 10 in sequence, and fabricating the first electrode 31 and the second electrode 32 on the surface of the light emitting structure 20 away from the substrate 10 .

[0084] S13 : forming a passivation layer 40 on a surface of the light emitting structure 20 away from the substrate 10 .

[0085] Among them, the passivation layer 40 covers the first electrode 31 and the second electrode 32, the passivation layer 40 has a pin portion 41 and a surrounding portion 42, the surrounding portion 42 surrounds the pin portion 41, and the surrounding portion 42 covers the first electrode 31 and the second electrode 32, the pin portion 41 is located between the first electrode 31 and the second electrode 32, the pin portion 41 includes a silicon nitride layer 410, and the roughness of the surface of the silicon nitride layer 410 away from the substrate 10 is higher than the roughness of the surface of the surrounding portion 42 away from the substrate 10.

[0086] The light-emitting diode chip manufactured by this method includes a light-emitting structure 20 stacked on a substrate 10. The light-emitting structure 20 also has a first electrode 31 and a second electrode 32. Furthermore, a passivation layer 40 is provided on the surface of the light-emitting structure 20 away from the substrate 10. The passivation layer 40 includes a connected ejector portion 41 and a surrounding portion 42. The surrounding portion 42 surrounds the ejector portion 41. The ejector portion 41 includes a silicon nitride layer 410 stacked on the surface of the light-emitting structure 20. Since the ejector pin portion 41 is used for sorting chips, the area on the passivation layer 40 that contacts the ejector pin is a whole layer of silicon nitride layer 410, that is, the silicon nitride layer 410 is relatively thick, and the thick silicon nitride layer 410 has high toughness and strength, so the silicon nitride layer 410 can better block the impact of the ejector pin; at the same time, the roughness of the surface of the silicon nitride layer 410 away from the substrate 10 is higher than the roughness of the top surface of the passivation layer 40, so the surface of the silicon nitride layer 410 in contact with the ejector pin is relatively rough, which effectively prevents the ejector pin from sliding toward the surrounding part, ensuring that the ejector pin is always in contact with the ejector pin portion 41 during sorting, thereby achieving good impact resistance.

[0087] like Figure 7 As shown, in step S12 , the process of growing the light emitting structure 20 may include: first, growing a second semiconductor layer 23 on the GaAs substrate 11 .

[0088] For example, the second semiconductor layer 23 is an indium-doped p-type AlInP layer, and the thickness of the p-type AlInP layer may be 0.5 μm to 3 μm.

[0089] like Figure 7 As shown, after the second semiconductor layer 23 is grown, the multi-quantum well layer 22 is grown on the second semiconductor layer 23 .

[0090] The multi-quantum well layer 22 includes alternately grown AlGaInP quantum well layers and AlGaInP quantum barrier layers, wherein the Al content in the AlGaInP quantum well layers and the AlGaInP quantum barrier layers is different. The multi-quantum well layer 22 may include 3 to 8 periods of alternately stacked AlGaInP quantum well layers and AlGaInP quantum barrier layers.

[0091] As an example, in the embodiment of the present disclosure, the multi-quantum well layer 22 includes five periods of alternately stacked AlGaInP quantum well layers and AlGaInP quantum barrier layers.

[0092] Optionally, the thickness of the multi-quantum well layer 22 may be 150 nm to 200 nm.

[0093] like Figure 7 As shown, after the multi-quantum well layer 22 is grown, the first semiconductor layer 21 is grown on the multi-quantum well layer 22 .

[0094] The first semiconductor layer 21 is an n-type AlGaInP layer, and the thickness of the n-type AlGaInP layer may be 0.5 μm to 3 μm.

[0095] In step S12 , a GaAs layer and an etching stop layer may be grown before growing the second semiconductor layer 23 , and an AlInP carrier confinement layer may be grown before growing the multi-quantum well layer 22 .

[0096] After growing the first semiconductor layer 21 , a GaP window layer may be further grown, wherein the thickness of the GaP window layer is 2 μm to 5 μm.

[0097] Exemplarily, the thickness of the GaP window layer is 3 μm.

[0098] After step S12, the process further includes bonding the substrate 10 and the light-emitting structure 20. Specifically, this process may include coating the surface of the first semiconductor layer 21 of the light-emitting structure 20 with liquid silicon oxide; and curing the liquid silicon oxide at a curing temperature of 250°C to 350°C to form a bonding layer. After bonding the light-emitting structure 20 to the substrate 10, the GaAs substrate 11 is removed.

[0099] Illustratively, the bonding temperature may be 300°C.

[0100] In the embodiment of the present disclosure, the substrate 10 and the light emitting structure 20 are bonded to form a complete light emitting structure 20 .

[0101] First, the groove 24 of the first semiconductor layer 21 is exposed by etching on the surface of the second semiconductor layer 23 .

[0102] like Figure 8As shown, the method may specifically include: removing a portion of the second semiconductor layer by dry etching until the first semiconductor layer 21 is exposed. The etching depth is 1 μm to 2 μm, for example, 1.5 μm.

[0103] After etching the groove 24 , a first electrode 31 may be formed on the first semiconductor layer 21 , and a second electrode 32 may be formed on the second semiconductor layer 23 .

[0104] The forming of the first electrode 31 and the second electrode 32 may include: processing the first electrode 31 and the second electrode 32 separately by using a negative resist stripping method.

[0105] like Figure 8 As shown, the second electrode 32 is located on the surface of the second semiconductor layer 23 , and the first electrode 31 is located on the bottom surface of the groove 24 .

[0106] The first electrode 31 is mainly composed of gold-beryllium, and the second electrode 32 is evaporated with gold-germanium as the base material. When evaporating the gold-germanium alloy, the evaporation power must be guaranteed and the evaporation time must not exceed 5 seconds to prevent the deviation of the alloy composition, and annealing is performed.

[0107] After forming the first electrode 31 and the second electrode 32, the light-emitting structure 20 can be etched through, and then the quantum well protection structure can be made. First, a protective negative photolithography pattern is made and the vertical surface is etched. Then, a positive photolithography pattern is used to form an inclined surface etching. Finally, the aluminum layer is attached to the vertical surface by placing the wafer at an angle. The depth of the quantum well protection structure needs to be adjusted accordingly according to the final thinning thickness. The goal of the adjustment is to be able to block laser photons to the greatest extent.

[0108] In step S13, Figure 1 As shown, when the passivation layer 40 is manufactured, the top needle part 41 is manufactured first. The top needle part 41 includes a light guiding layer 413 and a silicon nitride layer 410 sequentially stacked on the surface of the light emitting structure 20. The silicon nitride layer 410 includes a first sub-layer 411 and a second sub-layer 412 sequentially stacked on the surface of the light emitting structure 20. The density of the first sub-layer 411 is higher than the density of the second sub-layer 412.

[0109] The preparation method of the ejector portion 41 may include the following steps:

[0110] In the first step, a light guiding layer 413 is formed on the surface of the light emitting structure 20 .

[0111] The light guiding layer 413 includes a first silicon oxide layer 414, a metal layer 415, and a second silicon oxide layer 416. The surface of the first silicon oxide layer 414 away from the substrate 10 has a protruding structure 417, and the metal layer 415 is located on the first silicon oxide layer 414 and covers the protruding structure 417. Figure 4, the second silicon oxide layer 416 covers the metal layer 415 .

[0112] like Figure 5 As shown, the protrusion structure 417 is a plate-like protrusion distributed at intervals on the first silicon oxide layer 414, and a metal layer 415 is attached to the surface of the plate-like protrusion. In this way, after the light is incident on the first silicon oxide layer 414, it can be reflected at the position of the plate-like protrusion to guide the light to the surrounding part 42, preventing photons from entering the first sub-layer 411 and being absorbed, thereby improving the luminous effect of the light-emitting diode chip.

[0113] The protruding structure 417 may be a plate-like structure formed on the first sub-layer 411 by etching. The metal layer 415 is a film layer deposited on the first sub-layer 411 after etching.

[0114] Optionally, the metal layer 415 is an Al layer, and the thickness of the metal layer 415 is 1500 angstroms to 2500 angstroms. Exemplarily, the thickness of the metal layer 415 is 1000 angstroms.

[0115] Optionally, the light guiding layer 413 further includes a Cr layer 418 , and the Cr layer 418 is located between the first silicon oxide layer 414 and the metal layer 415 .

[0116] Optionally, the thickness of the Cr layer 418 is 30 angstroms to 100 angstroms. For example, the thickness of the Cr layer 418 is 50 angstroms.

[0117] In the second step, a first sub-layer 411 is formed on the light guiding layer 413 .

[0118] The thickness of the first sub-layer 411 is 3.8 μm to 4.2 μm. For example, the thickness of the first sub-layer 411 is 4 μm. The growth rate of the first sub-layer 411 may be 20 angstroms / second.

[0119] In the third step, a second sub-layer 412 is formed on the first sub-layer 411 .

[0120] The thickness of the second sub-layer 412 is 0.4 μm to 0.6 μm. For example, the thickness of the second sub-layer 412 is 0.5 μm.

[0121] In the third step, the growth rate of the second sub-layer 412 is not less than 100 angstroms / second. For example, the growth rate of the second sub-layer 412 is 200 angstroms / second.

[0122] After the ejector pin portion 41 is fabricated, the surrounding portion 42 is fabricated. The surrounding portion 42 may be a distributed Bragg reflector layer, which may be a DBR layer. The DBR layer comprises multiple SiO2 layers and TiO2 layers that are periodically and alternately stacked. The number of periods in the DBR layer may be between 20 and 50. For example, the number of periods in the DBR layer is 32.

[0123] The thickness of the SiO2 layer in the DBR layer may be 800 angstroms to 1200 angstroms, and the thickness of the TiO2 layer may be 500 angstroms to 900 angstroms.

[0124] After forming the distributed Bragg reflector layer, the preparation method may further include: forming through holes 421 on a surface of the distributed Bragg reflector layer away from the substrate 10 , one through hole 421 extending to the first electrode 31 and another through hole 421 extending to the second electrode 32 .

[0125] After step S13, a first solder block 51 is formed on the surface of the passivation layer 40 by photolithography, so that the first solder block 51 is connected to the first electrode 31 through a through hole 421; then, a second solder block 52 is formed on the surface of the passivation layer 40 by photolithography, so that the second solder block 52 is connected to the second electrode 32 through another through hole 421.

[0126] When forming the solder joint block, a large-angle plating pot is used for processing, which helps the metal material to better enter the jagged side wall of the through hole 421.

[0127] Finally, the sapphire can be subjected to invisible cutting and cleaving, which can effectively reduce the loss of brightness. Then, the light-emitting diode chip is obtained by testing.

[0128] The above description is merely an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the scope of protection of the present disclosure.

Claims

1. A light-emitting diode chip with improved sorting damage, characterized in that: The light-emitting diode chip comprises: a substrate (10), a light-emitting structure (20), a first electrode (31), a second electrode (32) and a passivation layer (40); The light-emitting structure (20) is stacked on the substrate (10); the first electrode (31) and the second electrode (32) are located on a surface of the light-emitting structure (20) away from the substrate (10); the passivation layer (40) is located on a surface of the light-emitting structure (20) away from the substrate (10); the passivation layer (40) comprises a connected ejector portion (41) and a surrounding portion (42); the surrounding portion (42) surrounds the ejector portion (41), and the surrounding portion (42) covers the first electrode (31) and the second electrode (32); the ejector portion (41) is located between the first electrode (31) and the second electrode (32); The ejector portion (41) includes a silicon nitride layer (410), the roughness of the surface of the silicon nitride layer (410) away from the substrate (10) is higher than the roughness of the surface of the surrounding portion (42) away from the substrate (10), the silicon nitride layer (410) includes a first sublayer (411) and a second sublayer (412) sequentially stacked on the surface of the light-emitting structure (20), the density of the first sublayer (411) is higher than the density of the second sublayer (412), and the thickness of the first sublayer (411) is greater than the thickness of the second sublayer (412).

2. The light-emitting diode chip according to claim 1, characterized in that The thickness of the first sub-layer (411) is 3.8 μm to 4.2 μm, and the thickness of the second sub-layer (412) is 0.4 μm to 0.6 μm.

3. The light-emitting diode chip according to claim 1, characterized in that The ejector portion (41) further includes a light guiding layer (413), and the light guiding layer (413) is located on a side of the silicon nitride layer (410) close to the light emitting structure (20); The light guiding layer (413) is used to reflect light incident from the surface of the light guiding layer (413) close to the light emitting structure (20) to the surrounding portion (42).

4. The light-emitting diode chip according to claim 3, characterized in that The light guiding layer (413) comprises a first silicon oxide layer (414), a metal layer (415) and a second silicon oxide layer (416) stacked in sequence, wherein the surface of the first silicon oxide layer (414) away from the substrate (10) has a protruding structure (417).

5. The light-emitting diode chip according to claim 4, characterized in that: The metal layer (415) is an Al layer, and the thickness of the metal layer (415) is 1500 angstroms to 2500 angstroms.

6. The light-emitting diode chip according to claim 4, characterized in that The light guiding layer (413) further comprises a Cr layer (418), wherein the Cr layer (418) is located between the first silicon oxide layer (414) and the metal layer (415).

7. The light-emitting diode chip according to claim 6, characterized in that The thickness of the Cr layer (418) is 30 angstroms to 100 angstroms.

8. A method for preparing a light-emitting diode chip with improved sorting damage, characterized in that: The preparation method comprises: providing a substrate; Growing a light-emitting structure on the substrate, and forming a first electrode and a second electrode on a surface of the light-emitting structure away from the substrate; A passivation layer is formed on a surface of the light-emitting structure away from the substrate, the passivation layer covers the first electrode and the second electrode, the passivation layer has a connected top needle portion and a surrounding portion, and the surrounding portion covers the first electrode and the second electrode, the top needle portion is located between the first electrode and the second electrode, the top needle portion includes a silicon nitride layer, the roughness of the surface of the silicon nitride layer away from the substrate is higher than the roughness of the surface of the surrounding portion away from the substrate, the silicon nitride layer includes a first sublayer and a second sublayer sequentially stacked on the surface of the light-emitting structure, the density of the first sublayer is higher than the density of the second sublayer, and the thickness of the first sublayer is greater than the thickness of the second sublayer.

9. The preparation method according to claim 8, characterized in that The growth rate of the first sublayer is lower than that of the second sublayer, and the growth rate of the second sublayer is not less than 100 angstroms / second. The thickness of the first sublayer is 3.8 μm to 4.2 μm, and the thickness of the second sublayer is 0.4 μm to 0.6 μm.

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