Laser radar multi-junction vcsel array chip based on p-substrate growth and preparation method thereof

Abstract

The present invention relates to a method for preparing a multi-junction VCSEL array chip for a laser radar grown on a P-type substrate, comprising the following steps: S1, selecting a P-type substrate and growing multiple pairs of P-type Bragg reflectors on the P-type substrate; S2, after the growth is complete, growing multiple groups of quantum wells on the P-type Bragg reflectors as light-emitting regions, the light-emitting regions comprising one or more tunnel junctions and an oxide layer; S3, then growing multiple pairs of N-type Bragg reflectors on the light-emitting regions; S4, after the growth is complete, growing a highly doped surface contact layer on the N-type Bragg reflectors. Also included is a multi-junction VCSEL array chip for a laser radar grown on a P-type substrate. By growing the P-type Bragg reflectors on a P-type substrate, the present invention brings the heat source closer to a heat sink substrate with good thermal conductivity, rapidly dissipating heat generated during operation of the VCSEL device, lowering the junction temperature and helping to reduce the temperature drift of the gain curve of the active region, thereby ensuring high gain from room temperature to high temperatures.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of lasers, in particular to a laser radar multi-junction VCSEL array chip based on P-substrate growth and a preparation method thereof. BACKGROUND

[0002] VCSEL (Vertical Cavity Surface Emitting Laser), the English abbreviation of vertical cavity surface emitting laser, is a kind of semiconductor laser diode based on different from the traditional top and side emitting light LED and edge emitting laser, VCSEL can emit more efficient light beam from its surface vertically. Since 1977, when Kenichi Iga of Tokyo Institute of Technology proposed the concept, it has been developed for more than 40 years. Because of its low threshold, small far-field divergence angle, high modulation rate, easy to realize single longitudinal mode operation and easy to two-dimensional integration, etc. After years of development, VCSEL has been widely used in wideband Ethernet, high-speed data communication, optical interconnection, three-dimensional sensing, optical integrated components and other fields.

[0003] In recent years, due to the rise of laser radar application and the hot market, VCSEL as one of its important light-emitting components has also been concerned. Its two-dimensional addressable function and cost have advantages compared with other schemes, but compared with edge emitting laser light source, VCSEL has a deficiency in power density. In order to improve the power density of VCSEL, the current mainly adopts multi-PN junction VCSEL chip to improve the light power output. However, due to the existence of multiple groups of active regions and multiple groups of tunnel junctions in the structure, the heat generated during work is significantly higher than that of the traditional single-junction VCSEL.

[0004] Existing VCSEL array structure for laser radar Figure 1The cross-sectional view of two adjacent light emitting holes is drawn. The structure is grown by epitaxial material on an N-substrate, and AlGaAs material system is used in the 850 / 905 / 940nm waveband, including about 35 pairs of N-doped DBR (Bragg reflector), multiple groups of active region, tunnel junction, and about 20 pairs of P-doped DBR. The heat sources are the heat generated by the electron-hole recombination in the active region, the Joule heat generated by the current passing through the P-type Bragg reflector, and the Joule heat generated by the current passing through the N-type Bragg reflector. Since the hole mobility (~150cm2 / V / s) is much smaller than the electron mobility (~2500cm2 / V / s), the resistance of the P-semiconductor (with holes as the majority carriers) is much larger than that of the N-semiconductor (with electrons as the majority carriers), so the heat generated in the P-type Bragg reflector is much larger than that in the N-type Bragg reflector. At the same time, since the multi-junction VCSEL chip generally needs to be attached to an aluminum nitride heat sink for use, its high thermal conductivity (320W / m.K) is conducive to heat dissipation, and air as a poor conductor of heat has a thermal conductivity of only 0.03W / m.K, which is not conducive to heat dissipation. Under the existing structure, the heat source generated by the P-type Bragg reflector needs to pass through the oxide layer / active region / N-type Bragg reflector before entering the heat sink for heat dissipation, further increasing the junction temperature of the active region, which will lead to a decrease in output power and a decrease in service life. SUMMARY

[0005] The purpose of the present application is to provide a laser radar multi-junction VCSEL array chip based on P-substrate growth and a preparation method thereof, which can at least solve some defects in the prior art.

[0006] To achieve the above-mentioned purpose, the embodiments of the present application provide the following technical solutions: a laser radar multi-junction VCSEL array chip based on P-substrate growth and a preparation method thereof, comprising the following steps:

[0007] S1, selecting a P-type substrate and growing multiple pairs of P-type Bragg reflectors on the P-type substrate;

[0008] S2, after the growth is completed, growing multiple groups of quantum wells as a light emitting region on the P-type Bragg reflector, the light emitting region including one or more groups of tunnel junctions and oxide layers;

[0009] S3, then growing multiple pairs of N-type Bragg reflectors on the light emitting region;

[0010] S4, after the growth is completed, growing a surface highly doped contact layer on the N-type Bragg reflector.

[0011] Further, the doping concentration of the P-type substrate is between 1-2E18 / cm 3 .

[0012] Further, the P-type Bragg mirror has 30-40 pairs.

[0013] Further, the P-type Bragg mirror is composed of 5-20% AlGaAs or 82-92% AlGaAs.

[0014] Further, the N-type Bragg mirror has 18-26 pairs.

[0015] Further, the N-type Bragg mirror is composed of 5-20% AlGaAs / 82-92% AlGaAs.

[0016] Further, the contact layer is highly doped at 1E19cm-3. 3 The above.

[0017] Further, a photoetching is used to define a layer on the surface of the N-type Bragg mirror, and RIE-ICP is used to etch downward, and the N-type Bragg mirror, the quantum well and part of the P-type Bragg mirror are etched in sequence.

[0018] Further, the contact layer is an N-contact layer, silicon nitride is opened on the N-contact layer, and electroplating is performed.

[0019] Further, after electroplating is completed, etching of a chip front cutting path is performed, the back substrate is thinned to a thickness of 100 μm, back metal evaporation and electroplating are performed, and high-temperature alloying is performed.

[0020] Compared with the prior art, the beneficial effects of the present application are: a preparation method of a laser radar multi-junction VCSEL array chip based on P-substrate growth, since the P-type Bragg mirror and the active region in the VCSEL device are the main heat sources, the P-type Bragg mirror is grown by the P-substrate, the heat source is closer to the heat sink substrate (320W / m.K) with good thermal conductivity, the heat generated during the operation of the VCSEL device is quickly dissipated, thereby reducing the junction temperature. It helps to reduce the drift amount of the gain curve of the active region with temperature, thereby ensuring that the substrate temperature has a high gain from room temperature to high temperature, which is 15% higher than the traditional N-substrate growth power. BRIEF DESCRIPTION OF DRAWINGS

[0021] Figure 1 It is a schematic diagram of a traditional laser radar multi-junction VCSEL array chip;

[0022] Figure 2 It is a schematic diagram of a laser radar multi-junction VCSEL array chip based on P-substrate growth provided by the embodiment of the present application;

[0023] Figure 3 It is a power comparison diagram of a traditional N-substrate and a P-type substrate provided by the embodiment. DETAILED DESCRIPTION

[0024] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0025] See also Figure 2 and Figure 3 The embodiment of the present invention provides a laser radar multi-junction VCSEL array chip, including a heat sink substrate 1, on which a P-type substrate 2, a P-type Bragg reflector 3, a light-emitting area 4, and an N-type Bragg reflector 5 are sequentially provided. The light-emitting area 4 is used to generate laser light. A groove is formed on the N-type Bragg reflector 5, which sequentially passes through the N-type Bragg reflector 5 and the light-emitting area 4, and the bottom of the groove extends to the P-type Bragg reflector 3. N contact metal 6 is provided on the surface of the N-type Bragg reflector 5 and in the groove. Figure 1 and Figure 2 In the figure, a represents electron-resistance heat, b represents heat generated by electron-hole pairs, c represents hole-resistance heat, and the arrow at the notch 12 represents the emitted laser. In this embodiment, the groove extends all the way to the P-type Bragg reflector 3, and then the N contact metal 6 is prepared in the groove. Since the P-type Bragg reflector 3 and the active area are the main heat sources in the VCSEL device, the P-type Bragg reflector 3 is grown on a P substrate, so that the heat source is closer to the heat sink substrate 1 (320W / mK) with good thermal conductivity, and the heat generated during the operation of the VCSEL device is quickly dissipated, thereby reducing the junction temperature. It helps to reduce the drift of the gain curve of the active area with temperature, thereby ensuring that the substrate temperature has a higher gain from room temperature to high temperature, which is comparable to chips grown on traditional N-substrates, such as Figure 1 The chip shown has 15% higher power.

[0026] As an optimization solution of the embodiment of the present invention, please refer to Figure 2 and Figure 3The light emitting region 4 has quantum wells 7, an oxide layer 8 and a tunnel junction 9. The quantum wells 7, the oxide layer 8 and the tunnel junction 9 are arranged in sequence from the P-type substrate 2 to the N-type Bragg mirror 5. The quantum wells 7, the oxide layer 8 and the tunnel junction 9 are arranged in groups. In the embodiment, only the quantum wells 7, the oxide layer 8 and the tunnel junction 9 in the lowermost group are shown. Figure 2 and Figure 3 The light emitting region 4 has quantum wells 7, an oxide layer 8 and a tunnel junction 9. The quantum wells 7, the oxide layer 8 and the tunnel junction 9 are arranged in sequence from the P-type substrate 2 to the N-type Bragg mirror 5. The quantum wells 7, the oxide layer 8 and the tunnel junction 9 are arranged in groups. In the embodiment, only the quantum wells 7, the oxide layer 8 and the tunnel junction 9 in the lowermost group are shown. The working principle of the light emitting region 4 is as follows: electrons and holes flow into the semiconductor material through the metal covering the P-type substrate 2 and the N-type substrate respectively, and recombine in the quantum wells 7 through the P-type Bragg mirror 3 and the N-type Bragg mirror 5 respectively, and the energy released in the recombination appears in the form of laser. The region between the P-type Bragg mirror 3 and the N-type Bragg mirror 5 constitutes the optical resonant cavity of the laser, and the oxide layer 8 controls the electrons and photons in the lateral direction, thereby ensuring high photoelectric conversion efficiency.

[0027] As an optimization of the embodiment of the present application, please refer to Figure 2 and Figure 3 The P-type metal 10 is arranged between the heat sink substrate 1 and the P-type substrate 2. In the embodiment, the heat conduction efficiency is improved by the P-type metal 10. The P-type metal 10 is a prior art, for example, the Ti / Pt / Au system can be used.

[0028] As an optimization of the embodiment of the present application, please refer to Figure 2 and Figure 3 The light emitting region 4 has at least one light emitting hole 11. The N-type contact metal 6 can use the Ge / Au system, and has a notch 12 for the laser emitted by the light emitting hole 11. In the embodiment, the laser generated in the light emitting hole 11 is emitted from the notch 12. Preferably, an electrically insulating region 13 is further included, and the light emitting hole 11 is located in the electrically insulating region 13. The electrically insulating region 13 is an ion implantation region.

[0029] As an optimization of the embodiment of the present application, the P-type Bragg mirror 3 has 30-40 pairs. The N-type Bragg mirror 5 has 18-26 pairs. The thickness of the P-type substrate 2 is 100 μm.

[0030] Please refer to Figure 2 and Figure 3The chip has a corresponding preparation method, which specifically comprises the following steps: S1, selecting a P-type substrate 2, and growing a plurality of pairs of P-type Bragg reflectors 3 on the P-type substrate 2; S2, after the growth is completed, growing a plurality of groups of quantum wells 7 as a light-emitting region 4 on the P-type Bragg reflectors 3, the light-emitting region 4 comprising one or more groups of tunnel junctions 9 and oxide layers 8; S3, then growing a plurality of pairs of N-type Bragg reflectors 5 on the light-emitting region 4; S4, after the growth is completed, growing a surface highly doped contact layer on the N-type Bragg reflectors 5. In the embodiment, since the P-type Bragg reflectors 3 and the active region in the VCSEL device are the main heat sources, the P-type Bragg reflectors 3 are grown through the P substrate, so that the heat sources are closer to the heat sink substrate 1 (320 W / m.K) with good thermal conductivity, and the heat generated during the operation of the VCSEL device is quickly dissipated, thereby reducing the junction temperature. It helps to reduce the drift amount of the gain curve of the active region with temperature, thereby ensuring that the gain is higher from the substrate temperature from room temperature to high temperature, which is 15% higher than the power of the traditional N-substrate growth. Specifically, when the chip is prepared, the P-type Bragg reflectors 3 are grown on the P-type substrate 2, so that the P-type Bragg reflectors 3 with the most heat can quickly transfer the heat to the P-metal and dissipate the heat through the heat sink substrate 1, which can greatly improve the heat dissipation efficiency compared with the conventional air cooling, thereby reducing the junction temperature. Under the condition of a given 50℃ substrate temperature, a driving circuit at 5ns, 0.1% duty cycle, and a typical working current, Figure 1 The traditional VCSEL junction temperature can reach about 85-95℃ junction temperature. The structure of the embodiment, under the same working temperature, the junction temperature is only 70-75℃. According to the equation for evaluating the Arrhenius lifetime, the optimized lifetime can reach about 3.2 times of the original.

[0031] As an optimization scheme of the embodiment of the application, please refer to Figure 2 and Figure 3 The doping concentration of the P-type substrate 2 is between 1-2E18 / cm 3 The P-type Bragg reflectors 3 have 30-40 pairs. The P-type Bragg reflectors 3 are composed of 5-20% AlGaAs or 82-92% AlGaAs. The N-type Bragg reflectors 5 have 18-26 pairs. The N-type Bragg reflectors 5 are composed of 5-20% AlGaAs / 82-92% AlGaAs. The contact layer is highly doped at 1E19cm 3 In the embodiment, the above material parameters can obtain the best heat dissipation effect.

[0032] As an optimization scheme of the embodiment of the application, please refer to Figure 2 and Figure 3The growth contact layer is defined by photoetching, and a ring-shaped N contact metal 6 is plated on the surface of the epitaxial layer, and silicon nitride is plated for protection.

[0033] As an optimization of the embodiment of the present application, refer to Figure 2 and Figure 3 A photoetching layer is defined on the surface of the N-type Bragg reflector 5, and RIE-ICP is used to etch downward, sequentially etching the N-type Bragg reflector 5, the quantum well 7, and part of the P-type Bragg reflector 3. The N contact metal 6 enters the etching depth.

[0034] As an optimization of the embodiment of the present application, refer to Figure 2 and Figure 3 The preparation of the plurality of oxide layers 8 is as follows: an oxidation process is performed in a water-oxygen furnace to form one or more oxide layers 8, silicon nitride is plated for protection. Ion implantation is used to assist in defining the current limiting region, the silicon nitride on the N-contact layer is opened, and electroplating is performed. Then, the front side of the chip is cut, the back side of the chip is thinned to a thickness of 100 microns, back side metal evaporation and electroplating are performed, high-temperature alloying is performed, and finally the chip is cut, tested, and sorted.

[0035] Although the embodiments of the present application have been shown and described, it is understood that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and spirit of the present application, and the scope of the present application is defined by the appended claims and their equivalents.

Claims

1. A method for preparing a laser radar multi-junction VCSEL array chip grown on a P substrate, characterized in that: The steps include: S1, selecting a P-type substrate, growing the P-type substrate on a heat sink substrate, and growing a plurality of pairs of P-type Bragg reflectors on the P-type substrate; S2, after the growth is completed, multiple groups of quantum wells are grown on the P-type Bragg reflector as light-emitting areas, wherein the light-emitting areas include one or more groups of tunnel junctions and oxide layers; S3, then growing a plurality of pairs of N-type Bragg reflectors on the light-emitting region; S4, after the growth is completed, growing a surface highly doped contact layer on the N-type Bragg reflector.

2. The method for preparing a laser radar multi-junction VCSEL array chip grown on a P substrate according to claim 1, wherein: The doping concentration of the P-type substrate is 1~2E18 / cm 3 between.

3. The method for preparing a laser radar multi-junction VCSEL array chip grown on a P substrate according to claim 1, characterized in that: There are 30 to 40 pairs of P-type Bragg reflectors.

4. The method for preparing a laser radar multi-junction VCSEL array chip grown on a P substrate according to claim 1, wherein: The P-type Bragg reflector comprises 5-20% AlGaAs or 82-92% AlGaAs.

5. The method for preparing a laser radar multi-junction VCSEL array chip grown on a P substrate according to claim 1, wherein: There are 18 to 26 pairs of N-type Bragg reflectors.

6. The method for preparing a laser radar multi-junction VCSEL array chip grown on a P substrate according to claim 1, wherein: The composition of the N-type Bragg reflector is 5-20% AlGaAs / 82-92% AlGaAs.

7. The method for preparing a laser radar multi-junction VCSEL array chip grown on a P substrate according to claim 1, wherein: The contact layer is highly doped at 1E19 cm 3 above.

8. The method for preparing a laser radar multi-junction VCSEL array chip grown on a P substrate according to claim 1, wherein: A layer is defined on the surface of the N-type Bragg reflector by photolithography, and RIE-ICP is used to perform downward etching, sequentially etching the N-type Bragg reflector, the quantum well, and a portion of the P-type Bragg reflector.

9. The method for preparing a laser radar multi-junction VCSEL array chip grown on a P substrate according to claim 1, wherein: The contact layer is an N-contact layer, and a silicon nitride hole is opened on the N-contact layer and electroplating is performed.

10. A multi-junction VCSEL array chip for laser radar grown on a P substrate, characterized by: The heat sink is prepared by the preparation method according to any one of claims 1 to 9, comprising a heat sink substrate, on which a P-type substrate, a P-type Bragg reflector, a light-emitting area and an N-type Bragg reflector are sequentially provided, wherein the light-emitting area is used to generate laser light; a groove is formed on the N-type Bragg reflector, the groove sequentially passes through the N-type Bragg reflector and the light-emitting area, and the bottom of the groove extends into the P-type Bragg reflector, and an N-type contact metal is provided on the surface of the N-type Bragg reflector and in the groove.

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