Electrostatic protection circuit and semiconductor chip
By introducing detection, delay, discharge, and reset circuits into the electrostatic discharge (ESD) protection circuit, the problems of large area occupation and latch-up effect of ESD protection circuit are solved, achieving efficient ESD protection and improved chip reliability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2022-06-17
- Publication Date
- 2026-06-26
AI Technical Summary
Existing electrostatic discharge (ESD) protection circuits have the problems of large footprint and easy latch-up effect, especially in highly integrated semiconductor devices where ESD can easily cause damage.
An electrostatic discharge (ESD) protection circuit is designed, including a detection circuit, a delay circuit, a discharge circuit, a control circuit, and a reset circuit. The circuit generates a transient control signal by detecting ESD pulses, delays or enhances the signal driving capability, and resets the potential at the control terminal of the discharge circuit after ESD discharge, thereby reducing the RC time constant and avoiding latch-up effects.
While achieving electrostatic protection, it reduces the circuit footprint, improves the flexibility and reliability of chip design, and avoids electrostatic damage and latch-up effects.
Smart Images
Figure CN115275955B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of integrated circuit technology, and to, but is not limited to, an electrostatic discharge protection circuit and a semiconductor chip. Background Technology
[0002] With the continuous development of science and technology, semiconductor manufacturing processes are becoming increasingly advanced, and the size of integrated circuits and semiconductor devices is shrinking. This includes shallower junction depths, thinner gate oxides, lightly doped drain (LDD) structures, shallow trench isolation (STI) structures, and self-aligned silicide processes. All of these advancements pose increasing challenges to the reliability of semiconductor integrated circuits.
[0003] Statistics show that over 30% of semiconductor product failures are caused by electrostatic discharge (ESD). ESD makes highly integrated semiconductor devices more susceptible to damage. For example, the gate dielectric is particularly vulnerable to ESD damage. Therefore, ESD protection circuits are built onto the chip to protect the devices and circuits within the semiconductor chip by discharging static electricity to ground. However, existing ESD protection circuits suffer from problems such as large footprint and susceptibility to latch-up. Summary of the Invention
[0004] In view of this, the present disclosure provides an electrostatic discharge protection circuit and a semiconductor chip.
[0005] In a first aspect, embodiments of this disclosure provide an electrostatic discharge (ESD) protection circuit, including:
[0006] A detection circuit is connected between the first voltage terminal and the second voltage terminal, and is used to generate a transient control signal in response to an electrostatic pulse between the first voltage terminal and the second voltage terminal.
[0007] A delay circuit, connected to the output of the detection circuit, is used to delay or enhance the driving capability of the transient control signal and output a delayed signal.
[0008] A discharge circuit is connected between the first voltage terminal and the second voltage terminal;
[0009] A control circuit is connected to the output terminal of the delay circuit and the control terminal of the discharge circuit, and is used to control the discharge circuit to discharge static electricity according to the delay signal.
[0010] A reset circuit, connected to the control terminal of the discharge circuit and the output terminal of the detection circuit, is used to reset the potential of the control terminal of the discharge circuit according to the potential of the output terminal of the detection circuit after the electrostatic discharge is completed.
[0011] In some embodiments, the reset circuit includes:
[0012] A reset transistor is connected to the second voltage terminal and the control terminal of the discharge circuit, and the control terminal of the reset transistor is connected to the output terminal of the detection circuit;
[0013] The reset transistor is used to reset the potential of the discharge circuit control terminal by turning on the potential at the output terminal of the detection circuit after the electrostatic discharge is completed.
[0014] In some embodiments, the reset transistor is an NMOS transistor.
[0015] In some embodiments, the delay circuit includes:
[0016] At least one inverter is provided for outputting the delayed signal upon receiving the transient control signal.
[0017] In some embodiments, the at least one inverter includes:
[0018] A first inverter is connected between the first voltage terminal and the second voltage terminal, and the input terminal of the first inverter is connected to the output terminal of the detection circuit.
[0019] A second inverter is connected between the first voltage terminal and the second voltage terminal. The input terminal of the second inverter is connected to the output terminal of the first inverter, and the second inverter outputs the delayed signal.
[0020] In some embodiments, the output of the first inverter is also connected to the control terminal of the discharge circuit.
[0021] In some embodiments, the first inverter includes:
[0022] A first inverting transistor, wherein the first terminal of the first inverting transistor is connected to the first voltage terminal;
[0023] The second inverter transistor, wherein the first terminal of the second inverter transistor is connected to the second voltage terminal;
[0024] The control terminal of the first inverter transistor is connected to the control terminal of the second inverter transistor, and together they serve as the input terminal of the first inverter.
[0025] The second terminal of the first inverter transistor is connected to the second terminal of the second inverter transistor, and together they serve as the output terminal of the first inverter.
[0026] In some embodiments, when the transient control signal is received at the input of the first inverter, the first inverter transistor is turned on and the second inverter transistor is turned off.
[0027] In some embodiments, the first inverting transistor is a PMOS transistor and the second inverting transistor is an NMOS transistor.
[0028] In some embodiments, the second inverter includes:
[0029] The third inverting transistor, wherein the first terminal of the third inverting transistor is connected to the first voltage terminal;
[0030] A fourth inverting transistor, wherein the first terminal of the fourth inverting transistor is connected to the second voltage terminal;
[0031] The control terminal of the third inverter transistor is connected to the control terminal of the fourth inverter transistor, and together they serve as the input terminal of the second inverter.
[0032] The second terminal of the third inverter transistor is connected to the second terminal of the fourth inverter transistor, and together they serve as the output terminal of the second inverter.
[0033] In some embodiments, when the transient control signal is received at the input of the first inverter, the third inverter transistor is turned off and the fourth inverter transistor is turned on, and the second inverter outputs the delayed signal.
[0034] In some embodiments, the third inverting transistor is a PMOS transistor and the fourth inverting transistor is an NMOS transistor.
[0035] In some embodiments, the electrostatic protection circuit further includes:
[0036] At least one diode is connected in series between the second terminal of the third inverting transistor and the second terminal of the fourth inverting transistor, the at least one diode being used to allow current to conduct unidirectionally from the second terminal of the third inverting transistor to the second terminal of the fourth inverting transistor.
[0037] In some embodiments, the control circuit includes:
[0038] A control transistor, wherein a first terminal of the control transistor is connected to the first voltage terminal, and a second terminal of the control transistor is connected to the control terminal of the discharge circuit; the control terminal of the control transistor is connected to the output terminal of the delay circuit.
[0039] In some embodiments, the discharge circuit includes:
[0040] A bleeder transistor, wherein a first terminal of the bleeder transistor is connected to the first voltage terminal, and a second terminal of the bleeder transistor is connected to the second voltage terminal; the control terminal of the bleeder transistor is connected to the output terminal of the control transistor.
[0041] In some embodiments, the control transistor is a PMOS transistor and the discharge transistor is an NMOS transistor.
[0042] In some embodiments, the potential of the first voltage terminal is greater than the potential of the second voltage terminal, and the second voltage terminal is a ground terminal.
[0043] In some embodiments, the detection circuit includes:
[0044] A detection resistor, wherein the first end of the detection resistor is connected to the first voltage terminal;
[0045] A detection capacitor, wherein the second terminal of the detection capacitor is connected to the second voltage terminal;
[0046] The first end of the detection capacitor is connected to the second end of the detection resistor, and together they serve as the output end of the detection circuit.
[0047] In some embodiments, the detection resistor is a polysilicon resistor or a doped region resistor.
[0048] On the other hand, this disclosure provides a semiconductor chip, including: a first voltage terminal, a second voltage terminal, and any of the electrostatic discharge protection circuits described in the above embodiments.
[0049] In the electrostatic discharge (ESD) protection circuit provided in this embodiment, a detection circuit generates a transient control signal in response to an ESD pulse, a delay circuit outputs a delayed signal based on the transient control signal, a control circuit controls the discharge circuit to discharge ESD based on the delayed signal, and a reset circuit resets the potential at the control terminal of the discharge circuit after ESD discharge is completed. Thus, on the one hand, the delay circuit and control circuit enable the ESD protection circuit to have a small resistor-capacitor (RC) time constant while achieving the desired ESD protection effect, thereby reducing the area occupied by the ESD protection circuit; on the other hand, the reset circuit can promptly shut down the discharge circuit after ESD discharge is completed, thereby reducing the occurrence of latch-up effects. Attached Figure Description
[0050] Figure 1 A schematic diagram of an electrostatic discharge protection circuit provided in an embodiment of this disclosure;
[0051] Figure 2 A schematic diagram of another electrostatic discharge protection circuit provided in an embodiment of this disclosure;
[0052] Figure 3A schematic diagram illustrating the voltage change over time during the power-on process of a semiconductor chip, provided as an embodiment of this disclosure;
[0053] Figure 4 A schematic diagram illustrating transient overshoot of the operating voltage in a semiconductor chip, provided as an embodiment of this disclosure;
[0054] Figure 5 A schematic diagram illustrating the application of a positive rectangular voltage pulse to a power supply pin, provided for an embodiment of this disclosure;
[0055] Figure 6 An equivalent circuit for performing latch-up overload testing is provided in an embodiment of this disclosure;
[0056] Figure 7 A schematic diagram illustrating the voltage change over time during a latch overload test, provided as an embodiment of this disclosure;
[0057] Figure 8 A schematic diagram of yet another electrostatic discharge protection circuit provided in an embodiment of this disclosure;
[0058] Figure 9 A schematic diagram of yet another electrostatic discharge protection circuit provided in an embodiment of this disclosure;
[0059] Figure 10 A schematic diagram of yet another electrostatic discharge protection circuit provided in an embodiment of this disclosure;
[0060] Figure 11 This is a schematic diagram of a semiconductor chip provided in an embodiment of this disclosure. Detailed Implementation
[0061] To facilitate understanding of this disclosure, exemplary embodiments of the disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the disclosure are shown in the drawings, it should be understood that the disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the disclosure and to fully convey the scope of the disclosure to those skilled in the art.
[0062] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In some embodiments, to avoid confusion with this disclosure, certain technical features well-known in the art are not described; that is, not all features of actual embodiments, nor well-known functions and structures, may be described herein.
[0063] Generally, terms can be understood at least in part from their use in context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a" or "described" can also be understood to convey either a singular or a plural usage, depending at least in part on the context. Additionally, the use of "based on" can be understood to not necessarily convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, also depending at least in part on the context.
[0064] Unless otherwise defined, the terminology used herein is intended only to describe particular embodiments and is not intended to limit the scope of this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0065] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.
[0066] In some embodiments, such as Figure 1 As shown, the electrostatic discharge protection circuit 100 is connected between the first voltage terminal 101 and the second voltage terminal 102, and includes:
[0067] The detection circuit 110 is used to generate a transient control signal 11a in response to an electrostatic pulse between the first voltage terminal 101 and the second voltage terminal 102.
[0068] The delay circuit 120 is connected to the output terminal of the detection circuit 110 and is used to delay or enhance the driving capability of the transient control signal 11a and output the delayed signal 12a.
[0069] The discharge circuit 130 is connected between the first voltage terminal 101 and the second voltage terminal 102, and is used to discharge static electricity according to the delay signal 12a.
[0070] In this embodiment, the potential of the first voltage terminal 101 is greater than the potential of the second voltage terminal 102. Exemplarily, the second voltage terminal 102 can be connected to ground voltage Vss, i.e., a low potential, while the first voltage terminal 101 can be connected to the operating voltage Vdd, i.e., a high potential. The detection circuit 110 includes a detection resistor 111 and a detection capacitor 112, i.e., an RC circuit. The first end of the detection resistor 111 is connected to the first voltage terminal 101, and the second end of the detection capacitor 112 is connected to the second voltage terminal 102. The first end of the detection capacitor 112 and the second end of the detection resistor 111 are connected together, serving as the output terminal of the detection circuit 110. The delay circuit 120 includes an inverter 121 composed of a first inverting transistor 122 and a second inverting transistor 123. The first terminal of the first inverting transistor 122 is connected to the first voltage terminal 101, and the first terminal of the second inverting transistor 123 is connected to the second voltage terminal 102. The control terminals of the first inverting transistor 122 and the second inverting transistor 123 are connected together, serving as the input terminal of the delay circuit 120. The second terminal of the first inverting transistor 122 and the first terminal of the second inverting transistor 123 are connected together, serving as the output terminal of the delay circuit 120. The discharge circuit 130 includes a discharge transistor 131, the first terminal of which is connected to the first voltage terminal 101, the second terminal of which is connected to the second voltage terminal 102, and the control terminal of which is connected to the output terminal of the delay circuit 120.
[0071] In this embodiment of the present disclosure, when electrostatic discharge occurs between the first voltage terminal 101 and the second voltage terminal 102, since the rising edge of the electrostatic pulse is on the order of nanoseconds and much smaller than the RC delay time (approximately 1µs), the potential at both ends of the detection capacitor 112 in the detection circuit 110 does not have time to change. That is, relative to the high level of the first voltage terminal 101 at this time, the transient control signal 11a output by the detection circuit 110 is at a low level.
[0072] The inverter 121 in the delay circuit 120 can delay or enhance the driving capability of the transient control signal 11a and convert the low-level transient control signal 11a into a high-level delayed signal 12a. For example, the first inverter transistor 122 can be a PMOS (Positive Channel Metal Oxide Semiconductor) transistor, and the second inverter transistor 123 can be an NMOS (Negative Channel Metal Oxide Semiconductor) transistor. When the input terminal of the delay circuit 120 receives a low-level transient control signal 11a, the first inverter transistor 122 is turned on, and the second inverter transistor 123 is turned off. At this time, the output terminal potential of the delay circuit 120 is pulled up to a high level, i.e., the delayed signal 12a is output.
[0073] The discharge transistor 131 in the discharge circuit 130 can be an NMOS transistor. When the control terminal of the discharge transistor 131 receives a high-level delayed signal 12a, the discharge transistor 131 turns on, thereby releasing the electrostatic charge on the first voltage terminal 101 to the second voltage terminal 102, i.e., the ground terminal Vss. This prevents the internal circuitry of the chip from experiencing a very large electrostatic discharge current, avoiding damage to the internal circuitry and devices caused by electrostatic discharge. However, electrostatic discharge requires hundreds of nanoseconds or even microseconds to last. During this time period, the channel of the discharge transistor 131 needs to remain in the open state. To keep the discharge transistor 131 in the open state during electrostatic discharge, the electrostatic protection circuit 100 needs to have a large RC time constant, such as 100ns to 1us. This results in a large area for the electrostatic protection circuit 100, occupying a large design space. In addition, as semiconductor manufacturing processes become more advanced, the thickness of the oxide layer that provides isolation is becoming thinner, making larger capacitors more prone to leakage and reducing the reliability of the semiconductor chip.
[0074] In some embodiments, such as Figure 2 The diagram shows another electrostatic discharge (ESD) protection circuit 200. The ESD protection circuit 200 is connected between a first voltage terminal 201 and a second voltage terminal 202, and includes:
[0075] The detection circuit 210 is used to generate a transient control signal 21a in response to an electrostatic pulse between the first voltage terminal 201 and the second voltage terminal 202.
[0076] The delay circuit 220 is connected to the output terminal of the detection circuit 210 and is used to delay or enhance the driving capability of the transient control signal 21a and output the delayed signal 22a.
[0077] The discharge circuit 230 is connected between the first voltage terminal 201 and the second voltage terminal 202.
[0078] The control circuit 240 is connected to the output terminal of the delay circuit 220 and the control terminal of the discharge circuit 230, and is used to control the discharge circuit 230 to discharge static electricity according to the delay signal 22a.
[0079] In this embodiment, the potential of the first voltage terminal 201 is greater than the potential of the second voltage terminal 202. The detection circuit 210 includes a detection resistor 211 and a detection capacitor 212, i.e., an RC circuit. The delay circuit 220 includes a first inverter 221 composed of a first inverter transistor 222 and a second inverter transistor 223, and a second inverter 224 composed of a third inverter transistor 225 and a fourth inverter transistor 226. The input terminal of the first inverter 221 is connected to the output terminal of the detection circuit 210, the input terminal of the second inverter 224 is connected to the output terminal of the first inverter 221, and the output terminal of the second inverter 224 serves as the output terminal of the delay circuit 220. The discharge circuit 230 includes a discharge transistor 231, the first terminal of which is connected to the first voltage terminal 201, and the second terminal of which is connected to the second voltage terminal 202. The control circuit 240 includes a third inverter 241 composed of a fifth inverting transistor 242 and a sixth inverting transistor 243, and a feedback unit 244 composed of a first feedback transistor 245 and a second feedback transistor 246. The input terminal of the third inverter 241 is connected to the output terminal of the delay circuit 220, and the output terminal of the third inverter 241 is connected to the control terminal of the discharge circuit 230; the input terminal of the feedback unit 244 is connected to the output terminal of the third inverter 241, and the output terminal of the feedback unit 244 is connected to the input terminal of the third inverter 241.
[0080] In this embodiment, when electrostatic discharge occurs between the first voltage terminal 201 and the second voltage terminal 202, the detection circuit 210 outputs a low-level transient control signal 21a. The delay circuit 220 can output a delay signal 22a based on the transient control signal 21a, wherein the delay signal 22a can be low-level. Exemplarily, the first inverter transistor 222 and the third inverter transistor 225 are PMOS transistors, and the second inverter transistor 223 and the fourth inverter transistor 226 are NMOS transistors. When the input terminal of the first inverter 221 receives a low-level transient control signal 21a, the first inverter transistor 222 is turned on, the second inverter transistor 223 is turned off, and the output terminal potential of the first inverter 221 is pulled up to a high level; when the input terminal of the second inverter 224 is high-level, the third inverter transistor 225 is turned off, the fourth inverter transistor 226 is turned on, and the output terminal potential of the second inverter 224 is pulled down to a low level, i.e., the delay signal 22a is output.
[0081] The control circuit 240 can control the discharge circuit 230 to discharge static electricity according to the delay signal 22a, and extend the discharge time of the discharge circuit 230. For example, the fifth inverting transistor 242 and the first feedback transistor 245 are PMOS transistors; the sixth inverting transistor 243, the second feedback transistor 246, and the discharge transistor 231 are NMOS transistors. When the input terminal of the third inverter 241 receives a low-level delay signal 22a, the fifth inverting transistor 242 is turned on, the sixth inverting transistor 243 is turned off, and the output terminal of the third inverter 241 is pulled up to a high level, that is, the control terminal of the discharge transistor 231 is high. At this time, the discharge transistor 231 is turned on, thereby discharging static electricity. Furthermore, the output of the third inverter 241 is at a high level, causing the first feedback transistor 245 to be cut off and the second feedback transistor 246 to be turned on. This further ensures that the input potential of the third inverter 241 is at a low level. That is, the third inverter 241 and the feedback unit 244 form a positive feedback loop, extending the conduction time of the discharge transistor 231. As a result, the electrostatic protection circuit 200 can have a smaller RC time constant and occupy a smaller area.
[0082] However, after the discharge of static electricity is completed, due to the positive feedback effect of the third inverter 241 and the feedback unit 244, the discharge transistor 231 may not be able to turn off in time, resulting in a latch-up effect. Furthermore, in some embodiments, during the power-on process of the chip, voltage overshoot during operation, transient latch-up (TLU) testing, and latch-up overstress testing, the discharge transistor 231, acting as a power clamp device, may fail to turn off, triggering a latch-up effect. For example... Figure 3 The diagram illustrates the change in power supply voltage over time during chip power-up. Here, CMOS IC (Complementary Metal Oxide Semiconductor Integrated Circuit) represents the power supply voltage, Vdd is the operating voltage, I / O represents the input / output port, GND is the ground port, and Tr represents the time it takes for the power supply voltage to rise from 0V to Vdd. Figure 4 The diagram illustrates the transient overshoot of the operating voltage caused by noise coupling under system or environmental interference. Figure 5 The image shows a positive rectangular voltage pulse applied to the power supply pin of a CMOS IC during a transient inductive latch-up test to simulate operating voltage overshoot. Figure 6 The diagram shows the equivalent circuit for a latch-up overload test, where Vsupply is the supply voltage and Isupply is the operating current. Figure 7The diagram illustrates the voltage change over time during a latch-up overload test, with parameters shown in Table 1. The specific steps of the latch-up overload test include: measuring the normal operating current of the CMOS IC during the time interval T1 to T2; the waiting time required before applying the overload voltage pulse to the Vdd pin during the time interval T2 to T3; applying the overload voltage pulse to the Vdd pin during the time interval T3 to T4; the waiting time before measuring the operating current during the time interval T4 to T5; measuring the operating current at time T5; if any operating current is greater than or equal to the fault current standard at time T6, a latch-up effect is determined to have occurred, and the power supply must be removed from the unit under test; the cooling time after applying the overload voltage pulse is from time T4 to T7; and the next test begins at time T7.
[0083]
[0084] Table 1
[0085] like Figure 8 As shown, this embodiment of the disclosure provides an electrostatic discharge (ESD) protection circuit 300, which is connected between a first voltage terminal 301 and a second voltage terminal 302, and includes:
[0086] The detection circuit 310 is connected between the first voltage terminal 301 and the second voltage terminal 302, and is used to generate a transient control signal 31a in response to the electrostatic pulse between the first voltage terminal 301 and the second voltage terminal 302.
[0087] The delay circuit 320 is connected to the output terminal of the detection circuit 310 and is used to delay or enhance the driving capability of the transient control signal 31a and output the delayed signal 32a.
[0088] A discharge circuit 330 is connected between the first voltage terminal 301 and the second voltage terminal 302;
[0089] A control circuit 340 is connected to the output terminal of the delay circuit 320 and the control terminal of the discharge circuit 330, and is used to control the discharge circuit 330 to discharge static electricity according to the delay signal 32a.
[0090] The reset circuit 350 is connected to the control terminal of the discharge circuit 330 and the output terminal of the detection circuit 310, and is used to reset the potential of the control terminal of the discharge circuit 330 according to the potential of the output terminal of the detection circuit 310 after the electrostatic discharge is completed.
[0091] In this embodiment, the detection circuit 310 can be used to detect whether electrostatic discharge occurs between the first voltage terminal 301 and the second voltage terminal 302. For example, the first voltage terminal 301 can be connected to the operating voltage Vdd, and the second voltage terminal 302 can be connected to the ground voltage Vss. When electrostatic discharge occurs, an electrostatic pulse is generated between the first voltage terminal 301 and the second voltage terminal 302, meaning the potential of the first voltage terminal 301 changes. At this time, the RC circuit in the detection circuit 310 prevents the potential at the output terminal of the detection circuit 310 from changing with the potential of the first voltage terminal 301, resulting in a potential difference between the output terminal of the detection circuit 310 and the first voltage terminal 301. Therefore, the detection circuit 310 generates a transient control signal 31a.
[0092] The input of the delay circuit 320 is connected to the output of the detection circuit 310 to generate and output a delayed signal 32a based on the received transient control signal 31a. The level type of the delayed signal 32a can be the same as or opposite to the level type of the transient control signal 31a, including high and low levels. For example, the delay circuit 320 may include at least one CMOS inverter, which causes the output delayed signal 32a to have a certain propagation delay time relative to the input transient control signal 31a. Furthermore, multiple CMOS inverters can increase the driving capability of the transient control signal 31a to improve the rising and falling edges of the delayed signal 32a. In some embodiments, the delay circuit 320 may include multiple CMOS inverters connected in series, and the output of each stage of the CMOS inverter can be connected to other circuits within the electrostatic protection circuit 300. For example, the output of the first-stage CMOS inverter in the delay circuit 320 is connected to the discharge circuit 330 to directly control the opening or closing of the discharge circuit 330; while the output of the second-stage CMOS inverter is connected to the control circuit 340 to control the discharge circuit 330, thereby extending the discharge time and ensuring the effect of electrostatic protection.
[0093] The discharge circuit 330 can be connected between the first voltage terminal 301 and the second voltage terminal 302 to release the electrostatic charge in the first voltage terminal 301 to the second voltage terminal 302 when an electrostatic pulse is generated between the first voltage terminal 301 and the second voltage terminal 302. Exemplarily, the discharge circuit 330 includes at least one MOS transistor, which performs electrostatic discharge when it is turned on. The gate of the MOS transistor can serve as the control terminal of the discharge circuit 330, allowing the MOS transistor to be turned on or off according to control signals generated by other circuits in the electrostatic protection circuit 300.
[0094] The control circuit 340 can be connected to the output terminal of the delay circuit 320 and the control terminal of the discharge circuit 330 to control the discharge circuit 330 to discharge static electricity according to the received delay signal 32a. Exemplarily, the control circuit 340 includes at least one MOS transistor, the gate of which can serve as the control terminal of the control circuit 340 and is connected to the output terminal of the delay circuit 320. The MOS transistor in the control circuit 340 can be turned on or off according to the delay signal 32a, thereby changing the level of the output terminal of the control circuit 340 to achieve the purpose of controlling the discharge circuit 330 to discharge static electricity. In some embodiments, the control circuit 340 and / or the delay circuit 320 can also form a feedback loop to extend the turn-on time of the discharge circuit 330 when electrostatic discharge occurs. Thus, the electrostatic protection circuit 300 can have a small RC time constant and occupy a small area.
[0095] The reset circuit 350 can be connected to the control terminal of the discharge circuit 330 and the output terminal of the detection circuit 310. After the electrostatic discharge is completed, it resets the potential of the control terminal of the discharge circuit 330 according to the potential of the output terminal of the detection circuit 310, so as to shut down the discharge circuit 330 in a timely manner and reduce the occurrence of latch-up effect. For example, the reset circuit 350 includes at least one MOS transistor. The gate of the MOS transistor can serve as the control terminal of the reset circuit 350 and is connected to the output terminal of the detection circuit 310. The MOS transistor in the reset circuit 350 can be turned on or off according to the transient control signal 31a, thereby changing the level type of the output terminal of the reset circuit 350 to directly shut down the discharge circuit 330. Thus, while ensuring that the electrostatic protection circuit 300 achieves the required electrostatic protection effect, the reset circuit 350 can reduce the occurrence of latch-up effect, and the electrostatic protection circuit 300 occupies a smaller area, improving the flexibility and reliability of chip design.
[0096] In some embodiments, such as Figure 9 As shown, the potential of the first voltage terminal 301 is greater than the potential of the second voltage terminal 302, and the second voltage terminal 302 is a ground terminal.
[0097] In this embodiment, the first voltage terminal 301 can be connected to the operating voltage Vdd, i.e., a high potential, and the second voltage terminal 302 can be connected to the ground voltage Vss, i.e., a low potential. When electrostatic discharge occurs between the first voltage terminal 301 and the second voltage terminal 302, an electrostatic pulse will be generated on the first voltage terminal 301. At this time, the detection circuit 310 responds to the electrostatic pulse and generates a transient control signal 31a. It can be understood that the potential of the first voltage terminal 301 can also be lower than the potential of the second voltage terminal 302, in which case the first voltage terminal 301 is a ground terminal.
[0098] In some embodiments, the detection circuit 310 includes:
[0099] A detection resistor 311, the first end of which is connected to the first voltage terminal 301;
[0100] A detection capacitor 312, the second end of which is connected to the second voltage terminal 302;
[0101] The first end of the detection capacitor 312 is connected to the second end of the detection resistor 311, and together they serve as the output end of the detection circuit 310.
[0102] In the embodiments disclosed herein, such as Figure 9 As shown, the detection circuit 310 may include a detection resistor 311 and a detection capacitor 312 connected between the first voltage terminal 301 and the second voltage terminal 302, i.e., an RC circuit. Exemplarily, when electrostatic discharge occurs between the first voltage terminal 301 and the second voltage terminal 302, because the rising edge of the electrostatic pulse is on the order of nanoseconds and much shorter than the RC delay time, the potential across the detection capacitor 312 in the detection circuit 310 does not have time to change. That is, relative to the high level of the first voltage terminal 301 at this time, the transient control signal 31a output by the detection circuit 310 is at a low level. In some embodiments, the detection capacitor 312 may also be connected to the first voltage terminal 301, while the detection resistor 311 is connected to the second voltage terminal 302. When electrostatic discharge occurs, the transient control signal 31a output by the detection circuit 310 is at a high level.
[0103] In some embodiments, the detection resistor 311 is a polysilicon resistor or a doped region resistor.
[0104] In this embodiment, the detection resistor 311 includes, but is not limited to, a polysilicon resistor or a doped region resistor. The manufacturing process of the polysilicon resistor on the substrate is relatively simple, while the resistance value of the detection resistor 311 can be precisely controlled by controlling the doping concentration of the doped region resistor.
[0105] In some embodiments, the detection capacitor 312 is a metal-dielectric-metal capacitor or a MOS capacitor.
[0106] In this embodiment, the detection capacitor 312 includes, but is not limited to, a metal-dielectric-metal capacitor or a MOS capacitor. The metal-dielectric-metal capacitor has better withstand voltage characteristics, while the MOS capacitor has a smaller area and better process compatibility with other MOS devices in the circuit.
[0107] In some embodiments, the delay circuit 320 includes:
[0108] At least one inverter is provided for outputting the delayed signal 32a upon receiving the transient control signal 31a.
[0109] In this embodiment, the delay circuit 320 may include at least one CMOS inverter for outputting a delayed signal 32a upon receiving a transient control signal 31a. The level type of the delayed signal 32a may be the same as or opposite to the level type of the transient control signal 31a, and the level type includes high and low levels. The inverter allows the output delayed signal 32a to have a certain propagation delay time relative to the input transient control signal 31a. Furthermore, multiple inverters can increase the driving capability of the transient control signal 31a to improve the rising and falling edges of the delayed signal 32a.
[0110] In some embodiments, the at least one inverter includes:
[0111] The first inverter 321 is connected between the first voltage terminal 301 and the second voltage terminal 302, and the input terminal of the first inverter 321 is connected to the output terminal of the detection circuit 310.
[0112] The second inverter 324 is connected between the first voltage terminal 301 and the second voltage terminal 302. The input terminal of the second inverter 324 is connected to the output terminal of the first inverter 321. The second inverter 324 outputs the delayed signal 32a.
[0113] In the embodiments disclosed herein, such as Figure 9 As shown, the delay circuit 320 includes a first inverter 321 and a second inverter 324 connected in series. Exemplarily, when a transient control signal 31a is received at the input of the first inverter 321, the transient control signal 31a undergoes two 180-degree phase inversions, thereby generating a delayed signal 32a with the same level as the transient control signal 31a at the output of the second inverter 324. Thus, the first inverter 321 and the second inverter 324 can ensure that the output delayed signal 32a has a certain propagation delay time relative to the input transient control signal 31a, and increase the driving capability of the transient control signal 31a, thereby improving the rising and falling edges of the delayed signal 32a.
[0114] In some embodiments, the first inverter 321 includes:
[0115] The first inverter transistor 322 has its first terminal connected to the first voltage terminal 301;
[0116] The second inverter transistor 323 has its first terminal connected to the second voltage terminal 302;
[0117] The control terminal of the first inverter transistor 322 is connected to the control terminal of the second inverter transistor 323, and together they serve as the input terminal of the first inverter 321;
[0118] The second terminal of the first inverter transistor 322 is connected to the second terminal of the second inverter transistor 323, and together they serve as the output terminal of the first inverter 321.
[0119] In the embodiments disclosed herein, such as Figure 9 As shown, the first inverter 321 includes a first inverting transistor 322 connected to a first voltage terminal 301 and a second inverting transistor 323 connected to a second voltage terminal 302. Here, the first terminal and the second terminal refer to the source or drain of the transistor, and the control terminal refers to the gate of the transistor. The first inverting transistor 322 and the second inverting transistor 323 can be different types of MOS transistors. When a transient control signal 31a is received at the input terminal of the first inverter 321, one of the first inverting transistor 322 and the second inverting transistor 323 is turned on, thereby making the output level of the first inverter 321 opposite to the level of the transient control signal 31a.
[0120] In some embodiments, the first inverting transistor 322 is a PMOS transistor and the second inverting transistor 323 is an NMOS transistor.
[0121] In some embodiments, when the transient control signal 31a is received at the input terminal of the first inverter 321, the first inverter transistor 322 is turned on and the second inverter transistor 323 is turned off.
[0122] In the embodiments disclosed herein, such as Figure 9 As shown, the first inverter transistor 322 is a PMOS transistor, and the second inverter transistor 323 is an NMOS transistor. For example, when electrostatic discharge occurs between the first voltage terminal 301 and the second voltage terminal 302, the detection circuit 310 outputs a low-level transient control signal 31a. At this time, the first inverter transistor 322 turns on in response to the low level of the control terminal, causing the output potential of the first inverter 321 to be pulled up to a high level; while the second inverter transistor 323 turns off in response to the low level of the control terminal.
[0123] In some embodiments, the second inverter 324 includes:
[0124] A third inverter transistor 325, the first terminal of which is connected to the first voltage terminal 301; a fourth inverter transistor 326, the first terminal of which is connected to the second voltage terminal 302;
[0125] The control terminal of the third inverter transistor 325 is connected to the control terminal of the fourth inverter transistor 326, and together they serve as the input terminal of the second inverter 324;
[0126] The second terminal of the third inverter transistor 325 is connected to the second terminal of the fourth inverter transistor 326, and together they serve as the output terminal of the second inverter 324.
[0127] In the embodiments disclosed herein, such as Figure 9 As shown, the second inverter 324 includes a third inverter transistor 325 connected to the first voltage terminal 301 and a fourth inverter transistor 326 connected to the second voltage terminal 302. Here, the first terminal and the second terminal refer to the source or drain of the transistor, and the control terminal refers to the gate of the transistor. The third inverter transistor 325 and the fourth inverter transistor 326 can be different types of MOS transistors. Depending on the potential of the input terminal of the second inverter 324, one of the third inverter transistor 325 and the fourth inverter transistor 326 can be turned on, thereby outputting a delayed signal 32a with the same level as the transient control signal 31a.
[0128] In some embodiments, the third inverting transistor 325 is a PMOS transistor and the fourth inverting transistor 326 is an NMOS transistor.
[0129] In some embodiments, when the transient control signal 31a is received at the input of the first inverter 321, the third inverter 325 is turned off and the fourth inverter 326 is turned on, and the second inverter 324 outputs the delayed signal 32a.
[0130] In the embodiments disclosed herein, such as Figure 9 As shown, the third inverter 325 is a PMOS transistor, and the fourth inverter 326 is an NMOS transistor. For example, when electrostatic discharge occurs between the first voltage terminal 301 and the second voltage terminal 302, the detection circuit 310 outputs a low-level transient control signal 31a, and the output potential of the first inverter 321 is pulled up to a high level. The third inverter 325 is turned off in response to the high level of the control terminal; while the fourth inverter 326 is turned on in response to the high level of the control terminal. At this time, the output potential of the second inverter 324 is pulled down to a low level, that is, the delayed signal 32a is low.
[0131] In some embodiments, such as Figure 9As shown, the output of the first inverter 321 is also connected to the discharge circuit 330 to directly control the opening or closing of the discharge circuit 330; while the output of the second inverter 324 is connected to the control circuit 340 to control the discharge circuit 330, thereby extending the discharge time and ensuring the effect of electrostatic protection.
[0132] In some embodiments, the control circuit 340 includes:
[0133] A control transistor 341 is provided, with its first terminal connected to the first voltage terminal 301 and its second terminal connected to the control terminal of the discharge circuit 330; the control terminal of the control transistor 341 is connected to the output terminal of the delay circuit 320.
[0134] In the embodiments disclosed herein, such as Figure 9 As shown, the control circuit 340 includes a control transistor 341. The control terminal of the control transistor 341 is connected to the output terminal of the delay circuit 320, i.e., the output terminal of the second inverter 324. The first terminal of the control transistor 341 can be connected to the first voltage terminal 301, and the second terminal can be connected to the control terminal of the discharge circuit 330. Here, the first terminal and the second terminal refer to the source or drain of the transistor, and the control terminal refers to the gate of the transistor. Thus, depending on the level of the delay signal 32a, the control transistor 341 can be turned on or off, thereby changing the potential of the second terminal of the control transistor 341 and realizing the opening or closing of the discharge circuit 330.
[0135] In some embodiments, the discharge circuit 330 includes:
[0136] A discharge transistor 331 is provided, with its first terminal connected to the first voltage terminal 301 and its second terminal connected to the second voltage terminal 302; the control terminal of the discharge transistor 331 is connected to the output terminal of the control transistor 341.
[0137] In the embodiments disclosed herein, such as Figure 9 As shown, the discharge circuit 330 includes a discharge transistor 331 connected between a first voltage terminal 301 and a second voltage terminal 302. The control terminal of the discharge transistor 331 is connected to the output terminal of a control transistor 341. Here, the first terminal and the second terminal refer to the source or drain of the transistor, and the control terminal refers to the gate of the transistor. Thus, depending on the potential of the output terminal of the control transistor 341, the discharge transistor 331 can be turned on or off, thereby releasing the electrostatic charge in the first voltage terminal 301 to the second voltage terminal 302 when the discharge transistor 331 is turned on.
[0138] In some embodiments, the control transistor 341 is a PMOS transistor and the discharge transistor 331 is an NMOS transistor.
[0139] In the embodiments disclosed herein, such as Figure 9 As shown, when electrostatic discharge occurs between the first voltage terminal 301 and the second voltage terminal 302, the detection circuit 310 outputs a low-level transient control signal 31a. The output potential of the first inverter 321 is pulled up to a high level, and the output potential of the second inverter 324 is pulled down to a low level, meaning the delay signal 32a is low. Since the control transistor 341 is a PMOS transistor, it turns on in response to the low-level delay signal 32a. At this time, the output potential of the control transistor 341 is pulled up to a high level, which in turn turns on the discharge transistor 331 to discharge static electricity. It can be understood that since the output of the first inverter 321 is also connected to the control terminal of the discharge transistor 331, the high level of the output of the control transistor 341 promotes the high level of the output of the first inverter 321. That is, the second inverter 324 and the control transistor 341 form a positive feedback loop, extending the conduction time of the discharge transistor 331. Therefore, the electrostatic protection circuit 300 can have a small RC time constant and occupy a small area.
[0140] In some embodiments, the reset circuit 350 includes:
[0141] The reset transistor 351 is connected to the second voltage terminal 302 and the control terminal of the discharge circuit 330, and the control terminal of the reset transistor 351 is connected to the output terminal of the detection circuit 310.
[0142] The reset transistor 351 is used to reset the potential of the control terminal of the discharge circuit 330 after the electrostatic discharge is completed, based on the potential of the output terminal of the detection circuit 310.
[0143] In the embodiments disclosed herein, such as Figure 9As shown, the reset circuit 350 includes a reset transistor 351. The control terminal of the reset transistor 351 is connected to the output terminal of the detection circuit 310. The first terminal of the reset transistor 351 can be connected to the second voltage terminal 302, and the second terminal can be connected to the control terminal of the discharge circuit 330. Here, the first and second terminals refer to the source or drain of the transistor, and the control terminal refers to the gate of the transistor. For example, after electrostatic discharge, the potential at the output terminal of the detection circuit 310 recovers. The reset transistor 351 turns on according to the potential at the output terminal of the detection circuit 310 to reset the potential at the control terminal of the discharge circuit 330 to the potential of the second voltage terminal 302, thereby turning off the discharge circuit 330. Thus, after electrostatic discharge, the discharge circuit 330 can be turned off directly by the reset transistor 351 without going through a series of potential changes via the delay circuit 320 and the control circuit 340, reducing the occurrence of latch-up effects.
[0144] In some embodiments, the reset transistor 351 is an NMOS transistor.
[0145] In the embodiments disclosed herein, such as Figure 9 As shown, after the electrostatic discharge ends, the potential at the output of the detection circuit 310 returns to a high level. Since the reset transistor 351 is an NMOS transistor, it turns on in response to a high level at the control terminal. At this time, the output potential of the reset transistor 351 is pulled down to a low level, thereby turning off the discharge transistor 331 to reduce the occurrence of latch-up effect.
[0146] In some embodiments, such as Figure 10 As shown, the electrostatic discharge protection circuit 300 further includes:
[0147] At least one diode 327 is connected in series between the second terminal of the third inverting transistor 325 and the second terminal of the fourth inverting transistor 326, the at least one diode 327 being used to allow current to conduct unidirectionally from the second terminal of the third inverting transistor 325 to the second terminal of the fourth inverting transistor 326.
[0148] In the embodiments disclosed herein, such as Figure 10As shown, at least one diode 327 can be connected in series between the second terminal of the third inverting transistor 325 and the second terminal of the fourth inverting transistor 326, so that current flows unidirectionally only from the second terminal of the third inverting transistor 325 to the second terminal of the fourth inverting transistor 326, thus performing a rectification function. Exemplarily, the anode of at least one diode 327 is connected to the second terminal of the third inverting transistor 325 and the control terminal of the control transistor 341; the cathode of at least one diode 327 is connected to the second terminal of the fourth inverting transistor 326. It can be understood that by controlling the number of diodes in at least one diode 327, the voltage at the control terminal of the control transistor 341, i.e., the voltage of the delayed signal 32a, can also be adjusted, thereby adapting the voltage of the delayed signal 32a to the semiconductor chip.
[0149] like Figure 11 As shown, this disclosure also provides a semiconductor chip 400, including: a first voltage terminal 401, a second voltage terminal 402, and an electrostatic discharge protection circuit 300 as described in any of the above embodiments.
[0150] For example, the semiconductor chip 400 includes an electrostatic discharge (ESD) protection circuit 300 and an internal circuit 403 connected between a first voltage terminal 401 and a second voltage terminal 402. When an ESD event occurs, the ESD protection circuit 300 can protect the internal circuit 403 to avoid or reduce damage to the internal circuit 403. It is understood that the ESD protection circuit 300 also has a small RC time constant to reduce its footprint; furthermore, the reset circuit in the ESD protection circuit 300 can promptly shut down the discharge circuit after the ESD discharge is completed, thereby reducing the occurrence of latch-up effects.
[0151] It should be noted that the features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined to obtain new method or device embodiments without conflict.
[0152] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.
Claims
1. An electrostatic protection circuit connected between a first voltage terminal and a second voltage terminal, characterized by, The electrostatic protection circuit includes: A detection circuit is connected between the first voltage terminal and the second voltage terminal, and is used to generate a transient control signal in response to an electrostatic pulse between the first voltage terminal and the second voltage terminal. A delay circuit, connected to the output of the detection circuit, is used to delay or enhance the driving capability of the transient control signal and output a delayed signal. A discharge circuit is connected between the first voltage terminal and the second voltage terminal; A control circuit is connected to the output terminal of the delay circuit and the control terminal of the discharge circuit, and is used to control the discharge circuit to discharge static electricity according to the delay signal. A reset circuit is connected to the control terminal of the discharge circuit and the output terminal of the detection circuit, and is used to reset the potential of the control terminal of the discharge circuit according to the potential of the output terminal of the detection circuit after the electrostatic discharge is completed. The reset circuit includes: A reset transistor is connected to the second voltage terminal and the control terminal of the discharge circuit, and the control terminal of the reset transistor is connected to the output terminal of the detection circuit; The reset transistor is used to reset the potential of the discharge circuit control terminal by turning on the potential at the output terminal of the detection circuit after the electrostatic discharge is completed.
2. The electrostatic protection circuit of claim 1, wherein The reset transistor is an NMOS transistor.
3. The electrostatic protection circuit of claim 1, wherein, The delay circuit includes: At least one inverter is provided for outputting the delayed signal upon receiving the transient control signal.
4. The electrostatic protection circuit of claim 3, wherein, The at least one inverter includes: A first inverter is connected between the first voltage terminal and the second voltage terminal, and the input terminal of the first inverter is connected to the output terminal of the detection circuit. A second inverter is connected between the first voltage terminal and the second voltage terminal. The input terminal of the second inverter is connected to the output terminal of the first inverter, and the second inverter outputs the delayed signal.
5. The electrostatic protection circuit of claim 4, wherein, The output terminal of the first inverter is also connected to the control terminal of the discharge circuit.
6. The electrostatic protection circuit of claim 4, wherein, The first inverter includes: A first inverting transistor, wherein the first terminal of the first inverting transistor is connected to the first voltage terminal; The second inverter transistor, wherein the first terminal of the second inverter transistor is connected to the second voltage terminal; The control terminal of the first inverter transistor is connected to the control terminal of the second inverter transistor, and together they serve as the input terminal of the first inverter. The second terminal of the first inverter transistor is connected to the second terminal of the second inverter transistor, and together they serve as the output terminal of the first inverter.
7. The electrostatic discharge protection circuit according to claim 6, characterized in that, When the transient control signal is received at the input of the first inverter, the first inverter transistor is turned on and the second inverter transistor is turned off.
8. The electrostatic protection circuit of claim 6, wherein, The first inverting transistor is a PMOS transistor, and the second inverting transistor is an NMOS transistor.
9. The electrostatic protection circuit of claim 4, wherein, The second inverter includes: A third inverting transistor, wherein the first terminal of the third inverting transistor is connected to the first voltage terminal; The fourth inverting transistor, wherein the first terminal of the fourth inverting transistor is connected to the second voltage terminal; The control terminal of the third inverter transistor is connected to the control terminal of the fourth inverter transistor, and together they serve as the input terminal of the second inverter. The second terminal of the third inverter transistor is connected to the second terminal of the fourth inverter transistor, and together they serve as the output terminal of the second inverter.
10. The electrostatic discharge protection circuit according to claim 9, characterized in that, When the transient control signal is received at the input of the first inverter, the third inverter transistor is turned off and the fourth inverter transistor is turned on, and the second inverter outputs the delayed signal.
11. The electrostatic protection circuit of claim 9, wherein, The third inverting transistor is a PMOS transistor, and the fourth inverting transistor is an NMOS transistor.
12. The electrostatic protection circuit of claim 9, wherein, Also includes: At least one diode is connected in series between the second terminal of the third inverting transistor and the second terminal of the fourth inverting transistor, the at least one diode being used to allow current to conduct unidirectionally from the second terminal of the third inverting transistor to the second terminal of the fourth inverting transistor.
13. The electrostatic discharge protection circuit according to claim 1, characterized in that, The control circuit includes: A control transistor, wherein a first terminal of the control transistor is connected to the first voltage terminal, and a second terminal of the control transistor is connected to the control terminal of the discharge circuit; the control terminal of the control transistor is connected to the output terminal of the delay circuit.
14. The electrostatic discharge protection circuit according to claim 13, characterized in that, The discharge circuit includes: A bleeder transistor, wherein a first terminal of the bleeder transistor is connected to the first voltage terminal, and a second terminal of the bleeder transistor is connected to the second voltage terminal; the control terminal of the bleeder transistor is connected to the output terminal of the control transistor.
15. The electrostatic discharge protection circuit according to claim 14, characterized in that, The control transistor is a PMOS transistor, and the discharge transistor is an NMOS transistor.
16. The electrostatic discharge protection circuit according to claim 1, characterized in that, The potential of the first voltage terminal is greater than the potential of the second voltage terminal, which is a ground terminal.
17. The electrostatic discharge protection circuit according to any one of claims 1 to 16, characterized in that, The detection circuit includes: A detection resistor, wherein the first end of the detection resistor is connected to the first voltage terminal; A detection capacitor, wherein the second terminal of the detection capacitor is connected to the second voltage terminal; The first end of the detection capacitor is connected to the second end of the detection resistor, and together they serve as the output end of the detection circuit.
18. The electrostatic discharge protection circuit according to claim 17, characterized in that, The detection resistor is a polycrystalline silicon resistor or a doped region resistor.
19. A semiconductor chip, characterized in that, The semiconductor chip includes: The first voltage terminal, the second voltage terminal, and the electrostatic protection circuit as described in any one of claims 1 to 18.