Improved Noise Interference Suppression for Power Supplies

Abstract

The disclosed apparatus and related methods relate to a power supply noise disturbance rejection circuit NDRC having a first circuit reference potential CRP1, a second circuit reference potential CRP2, and a current link that conducts between the two and provides a non-zero resistance return path for at least one current mode signal CMS. In an illustrative example, a power supply monitoring circuit PSMC may reference the first circuit reference potential CRP1, and a control circuit may reference the second circuit reference potential CRP2. For example, the power supply monitoring circuit PMSC may generate a voltage mode signal VMS relative to the first circuit reference potential CRP1 and representative of an output parameter of a power supply circuit PSC, and convert the voltage mode signal VMS to a first current mode signal CMS1. For example, the control circuit may generate a control signal for the power supply circuit PSC from the first current mode signal CMS1. Various embodiments may advantageously attenuate the noise tolerance of the current mode signal CMS presented at the control circuit by at least a factor of 10 relative to an equivalent voltage mode signal VMS.

Description

Technical Field

[0001] Each embodiment of the present invention mainly relates to noise interference suppression in a power supply circuit, and specifically relates to improved noise interference suppression for a power supply. Background Art

[0002] Electronic devices receive power in various ways. For example, consumer electronic devices can receive power from a wall outlet (such as a power supply) or various portable power sources (such as batteries, renewable energy sources, generators). The operating time of a battery-powered device depends on the battery capacity and the average current consumption. Manufacturers of battery-driven devices may strive to reduce the average battery current of their products in order to provide longer device usage time between battery replacement or charging operations. In some examples, manufacturers of mains-powered devices may strive to improve the power efficiency of their products to minimize the heat load and / or maximize the performance per watt of power consumption.

[0003] In some electronic devices, an input voltage power supply (such as a battery input, a rectified power supply, an intermediate DC power supply) can be converted into different voltages through various voltage conversion circuits. Switching mode power supplies have been widely used as voltage conversion circuits due to their high efficiency, and thus are widely used in various electronic devices.

[0004] A switching mode power supply uses a switching device to convert the voltage. The switching device turns on with a very low resistance and turns off with a very high resistance. The switching mode power supply can charge the output inductor for a period of time and can release some or all of the inductor energy in a subsequent period. The output energy can be transferred to a set of output capacitors, which provide filtering to generate a DC output voltage. In a buck switching mode power supply, the output voltage at steady state can be approximated as the input voltage multiplied by a duty cycle, where the duty cycle is the on-time of the on-off switch divided by the total on-time and off-time of the on-off switch within a switching cycle. Summary of the Invention

[0005] The apparatus and related methods provided by the present invention relate to a power supply noise interference suppression circuit NDRC having a first circuit reference potential CRP1, a second circuit reference potential CRP2, and a current link that conductively connects the first circuit reference potential CRP1 and the second circuit reference potential CRP2 and provides a non-zero resistance return path for at least one current mode signal CMS. In an illustrative example, a power supply monitoring circuit PSMC may reference the first circuit reference potential CRP1, and a control circuit may reference the second circuit reference potential CRP2. For example, the power supply monitoring circuit PMSC may generate a voltage mode signal VMS relative to the first circuit reference potential CRP1 and representative of an output parameter of the power supply circuit PSC, and convert the voltage mode signal VMS into a first current mode signal CMS1. For example, the control circuit may generate a control signal for the power supply circuit PSC from the first current mode signal CMS1. Various embodiments may advantageously attenuate the noise tolerance of the current mode signal CMS presented at the control circuit by at least a factor of 10 relative to an equivalent voltage mode signal VMS.

[0006] To achieve the above object, the present invention is implemented by the following technical solutions:

[0007] A noise interference suppression circuit, comprising:

[0008] A power supply monitoring circuit PSMC operably referencing a first circuit reference potential CRP and configured to generate a first voltage mode signal relative to the first circuit reference potential CRP1, the first voltage mode signal corresponding to a first output parameter of a power supply output delivered from a power supply circuit PSC to a load, and convert the first voltage mode signal into a first current mode signal;

[0009] A control circuit operably referencing a second circuit reference potential CRP2 and configured to generate a control signal from the first current mode signal, the control circuit being operably coupled to the power supply circuit PSC such that the power supply circuit PSC determines the first output parameter based on the control signal; and

[0010] A current link conductively connecting the first circuit reference potential CRP1 and the second circuit reference potential CRP2, the current link being configured to convey a return path for the first current mode signal via a non-zero resistance path,

[0011] wherein the noise tolerance of the first current mode signal presented at the control circuit is less than or equal to ten percent of the noise tolerance of an equivalent voltage mode signal.

[0012] Optionally, the first output parameter includes the output voltage of the power supply circuit PSC.

[0013] Optionally, the power supply monitoring circuit PSMC includes a voltage-to-current converter circuit configured to convert a first voltage mode signal into a first current mode signal.

[0014] Optionally, the power supply monitoring circuit PSMC is configured to generate a second current mode signal proportional to a second output parameter of the power output.

[0015] Optionally, the second output parameter includes the output power of the power supply circuit PSC.

[0016] Optionally, the second output parameter includes the output current of the power supply circuit PSC.

[0017] Optionally, the power supply monitoring circuit PMSC is further configured to generate a second voltage mode signal proportional to the second output parameter and convert the second voltage mode signal into the second current mode signal.

[0018] Optionally, the power supply monitoring circuit PSMC is further configured to:

[0019] generate a first voltage mode signal by measuring a first voltage reference of the power output relative to a first circuit reference potential CRP1, and,

[0020] generate a second voltage mode signal by measuring the first voltage reference of the power output relative to a second voltage reference of the power output.

[0021] Optionally, the second current mode signal represents the current at the power output terminal; and

[0022] configure the power supply monitoring circuit PSMC to generate a third current mode signal representing the power of the power output by multiplying the first current mode signal and the second current mode signal.

[0023] Optionally, the control circuit converts the first current mode signal into a received voltage mode signal.

[0024] The present invention has the following advantages compared with the prior art:

[0025] Various embodiments can achieve one or more advantages. For example, some embodiments can advantageously reduce the noise interference of the output parameter to at least ten percent (10%) of the output parameter noise interference transmitted via the voltage mode signal. Therefore, the control signal can more accurately respond to the current output parameter of the power supply.

[0026] Various embodiments can advantageously meet or exceed the power signal parameter requirements of a load, for example, by way of example only and not by way of limitation, a high-performance processor. In various embodiments, for example, a power circuit can advantageously meet a more stringent (e.g., smaller) error tolerance when supplying a power signal to a load than a power circuit that transmits output parameter signals across one or more circuit reference domains in voltage mode. Various embodiments can advantageously provide, for example, improved noise suppression at any higher frequency than achievable by a voltage mode output parameter signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Details of various embodiments are set forth in the accompanying drawings and the following description. Other features and advantages will be apparent from the specification, drawings, and claims.

[0028] Figure 1 Exemplary noise disturbance rejection circuit NDRC in an illustrative use case scenario of a power circuit for powering a load in the present invention, wherein the noise disturbance rejection circuit NDRC is configured to transmit output parameters as a current mode signal between two circuit reference domains CRD;

[0029] Figure 2 Exemplary noise disturbance rejection circuit NDRC in a multi-potential power circuit of the present invention;

[0030] Figure 3 Block diagram of an exemplary monitoring module circuit of the noise disturbance rejection circuit NDRC of the present invention, which is configured to detect at least one output parameter in voltage mode and convert it to current mode;

[0031] Figure 4 Block diagram of an exemplary digital monitor module circuit of the noise disturbance rejection circuit NDRC of the present invention, which is configured to detect at least one output parameter in voltage mode and convert it to current mode;

[0032] Figure 5 An exemplary implementation of the noise disturbance rejection circuit NDRC of the present invention, the noise disturbance rejection circuit NDRC being configured to transmit output parameters from a power circuit reference domain CRD to an analog circuit reference domain CRD in current mode;

[0033] Like reference symbols in the various drawings indicate like elements. DETAILED DESCRIPTION

[0034] For ease of understanding, the present specification is organized as follows. First, to aid in introducing the discussion of the various embodiments, reference is made to Figure 1 introduce a noise disturbance rejection circuit NDRC configured to transmit output parameters across at least two circuit reference domains CRDs in current mode. Second, the introduction refers to Figures 2 - 5Description of some exemplary embodiments of noise disturbance rejection circuits NDRCs and related circuits. Finally, this specification discusses further embodiments, exemplary applications, and aspects related to noise disturbance rejection circuits NDRCs.

[0035] Figure 1 An exemplary noise disturbance rejection circuit NDRC configured to send an output parameter as a current mode signal between two circuit reference domains CRDs. In the example described, the noise disturbance rejection circuit NDRC is used in an illustrative use case scenario of a power supply circuit for powering a load. In the depicted illustrative use case scenario 100, the server 105 is powered by a power supply circuit 110. The power supply circuit 110 supplies power to the load domain 115 of the server 105 (e.g., via a voltage output V OUT ). By way of example, but not limitation, the power supply circuit 110 may include one or more switched-mode power supplies. As Figure 1 shown, the load domain 115 of the server 105 includes a load circuit 116. By way of example, but not limitation, the depicted load circuit 116 includes a processor 117A (labeled CPU), a memory 117B, other related peripheral devices 117C, or some combination thereof.

[0036] As Figure 1 shown, the power supply 110 includes respective power supply units PSU1 120A, PSU2 120B, …, PSUN 120N. Each power supply unit outputs a corresponding power supply voltage (e.g., 12V DC) VPSU-1, VPSU-2, …, VPSU-N. The power supply voltages are input to a multi-potential power control circuit MPPC125. The multi-potential power control circuit MPPC 125 includes a system power monitor circuit SPMC130 and a voltage converter circuit 135. The system power monitor circuit SPMC 130 monitors at least one voltage signal (VPSU-N) of the power output of at least one power supply unit. The voltage converter circuit 135 may be configured to operate on the voltage signal VPSU and provide a regulated voltage output V OUT . In the depicted example, the power stage 140 of the voltage converter circuit 135 converts the voltage signal VPSU to a voltage output V OUT . The power stage 140 may exemplarily include an interleaved switched power stage, a step-down transformer, a step-up transformer, or some combination thereof.

[0037] In the depicted example, power stage 140 responds to control signal CS from controller 145. Controller 145 receives current output parameter signal ISYS and voltage output parameter signal VSYS from system power monitor circuit SPMC 130. Controller 145 may determine control signal CS as a function of at least one output parameter signal. The path between system power monitor circuit SPMC 130 and controller 145 has a non-zero impedance, which may include transfer resistance RT as its real component. By way of example, and not limitation, transfer resistance RT includes trace resistance, conductor resistance, wire resistance, backplane resistance, ground plane resistance, or combinations thereof. In various embodiments, the resistance may include combinations of real and / or imaginary parts of, for example, resistance, inductance, and / or capacitance.

[0038] In the example shown, system power monitor circuit SPMC 130 and power stage 140 are located in a first circuit reference domain CRD1 operably referenced to a first circuit reference potential CRP1. Controller 145 is located in a second circuit reference domain CRD2 operably referenced to a second circuit reference potential CRP2. The first circuit reference potential CRP1 and the second circuit reference potential CRP2 are electrically connected by a current circuit reference potential CRP link 155. At least one output parameter signal of current output parameter signal ISYS and current mode voltage signal IVSYS is sensed in voltage mode and converted to current mode before being sent to controller 145. For example, current circuit reference potential CRP link 155 may provide a non-zero resistance return path for the output parameter signal.

[0039] Thus, by sending the output parameter signal in current mode and providing current circuit reference potential CRP link 155 between the first circuit reference potential CRP1 and the second circuit reference potential CRP2, noise interference (e.g., DC offset, loss, impedance discontinuity, crosstalk) of the output parameter can be advantageously reduced to at least ten percent (10%) of the output parameter transmitted via voltage mode signal. Thus, control signal CS can more accurately respond to the current output parameter of voltage signal VPSU (e.g., where VPSU-N = VPSU). Thus, a more stable power output, i.e., voltage output V, can be provided to load domain 115. OUT For example, processor 117A may be equipped with an increased stability power supply by improving noise suppression in the output parameter signal to controller 145.

[0040] Figure 2Represents an exemplary noise disturbance suppression circuit NDRC in a multi-potential power supply circuit. The system power monitor circuit 130 of the multi-potential power control circuit MPPC 125 includes monitor modules 205A, 205B, …, and 205N corresponding to the input voltage signals VPSU-1 to VPSU-N. Each monitor module 205 includes a voltage-current converter circuit 210 (210A, 210B, …, 210N corresponding to 205A, 205B, …, 205N). In the described example, the voltages are in parallel such that VPSU1 = VPSU2 = … VPSU-N = VPSU. By way of example, but not limitation, various embodiments may be configured in series, e.g., VPSU = VPSU1 + VPSU2 + … + VPSUN. Each voltage-current converter circuit 210 can measure one or more output parameters of the power supply output with reference to V+ and a first circuit reference potential CRP1 (e.g., the voltage signal VPSU), and with reference to V+ and V- (e.g., generating a signal corresponding to the current and / or power of the power supply output through a resistor of the resistor RSENSE). The voltage-current converter circuit 210 can measure the output parameters output by the power supply in voltage mode and convert them to current mode before sending the resulting signal out of the first circuit reference domain CRD1.

[0041] In the example shown, each monitor module 205 outputs a current-mode output parameter ISYS. For example, the current output parameter signal ISYS may correspond to the current of the power output, the power of the power output, or some combination thereof. For example, the individual current output parameter signals ISYS-N signals can be summed. For example, a single current output parameter signal ISYS-N can be selected for monitoring. In the example shown, the single monitor module 205N further outputs a current-mode voltage signal IVSYS corresponding to the voltage of the voltage output parameter signal VPSU (e.g., where VPSU = VPSU-1 = VPSU-2 = VPSU-N). In various embodiments, as shown, the current-mode voltage signal IVSYS can be measured from a single power supply unit PSU unit (e.g., VPSU-N). In various embodiments, the current-mode voltage signal IVSYS can be measured from the voltage output parameter signal VPSU signal. In the example depicted, the converter circuit 210N has a transconductance G1 between the voltage output parameter signal VPSU and the current-mode output voltage signal IVSYS. Accordingly, the voltage of the power supply output is given by Equation 1, where the current-mode output voltage signal IVSYS is the current at the converter 210N and VPSU = VPSU-N:

[0042] Equation 1 VPSU = IVSYS * G1

[0043] The current-mode output voltage signal IVSYS is transmitted to the controller 145 via a link having a transfer resistance RT. If the voltage signal were transmitted in voltage mode, the voltage upon arrival would be less than the original voltage, with the loss being proportional to the transfer resistance RT. By transmitting in current mode, the current (IVSYSR) seen (received) by the controller 145 is substantially equal to the current (IVSYS) from the converter 210N. For example, secondary effects (such as passive coupling to noise) can be ignored, as shown in Equation 2.

[0044] Equation 2 IVSYS≈IVSYSR

[0045] As shown, the controller 145 is equipped with an amplifier 215, which is configured to reconstruct the current-voltage of the power supply output by converting the current-mode signal IVSYS into a voltage-mode signal VSYS by referring to a second circuit reference potential CRP2 and a resistor RS1, such that:

[0046] Equation 3 VSYS=IVSYSR*RS1

[0047] Equation 1 can be replaced by Equation 3, expressing VSYS in terms of IVSYS:

[0048] Equation 4 VSYS≈IVSYS*RS1

[0049] Equation 1 can be solved for IVSYS to obtain Equation 5.

[0050] Equation 5 IVSYS=VPSU / G1

[0051] Substituting Equation 5 into Equation 4 gives Equation 6, expressing VSYS in terms of the power supply output voltage and transconductance.

[0052] Equation 6 VSYS≈(VPSU / G1)*RS1

[0053] Solving Equation 6 for VPSU gives Equation 7.

[0054] Equation 7 VPSU≈VSYS*G1

[0055] For example, the amplifier 215 can be configured to scale VSYS by a factor substantially equal to the transconductance G1. Thus, the controller 145 can advantageously reconstruct the voltage signal VPSU from a signal transmitted in current mode between the first circuit reference domain CRD1 and the second circuit reference domain CRD2.

[0056] As shown, the controller 145 is equipped with an amplifier 216, which is configured to represent the measured current of the power supply output in voltage mode by converting the current-mode signal ISYS into a voltage-mode signal VISYS by referring to a second circuit reference potential CRP2 and a resistor RS2, such that:

[0057] Formula 8: VISYS = ISYS * RS2

[0058] For example, amplifier 216 may be configured to scale the voltage mode signal VISYS by a factor to generate a scaled voltage mode signal VISYS representing the current mode signal ISYS.

[0059] In various embodiments, the current CRP link 155 may provide a return path with non - zero resistance for, e.g., current mode operation parameter signals (e.g., IVSYS, ISYS). Thus, by transmitting output parameters in current mode between circuit reference domains CRD that reference different circuit reference potentials CRP, significant noise (e.g., 90% or more) can be advantageously rejected.

[0060] Figure 3 Block diagram of an exemplary monitor module circuit representing a noise disturbance rejection circuit NDRC, which is configured to detect at least one output parameter in voltage mode and convert it to current mode. The monitor module circuit 205 is operatively connected to nodes V + and V - through a voltage difference (e.g., through a resistor, e.g., RSENSE). The monitor module 205 is also operatively referenced to a first circuit reference potential CRP1.

[0061] The first voltage - current converter 305A converts the voltage V + of reference V to a first current output signal IIN (e.g., corresponding to the current of the power output). The second voltage - current converter 305B converts the voltage V + of reference to the first circuit reference potential CRP1 to a second current output signal IVSYS (e.g., corresponding to the voltage VPSU of the power output). The multiplier circuit 310 may multiply V + (e.g., representing VSYS) and the first current output signal IIN (e.g., representing ISYS) to generate a third current output signal PIN (e.g., corresponding to the power of the power output). In various embodiments, the multiplier circuit 310 may, for example, reference V +, V -, the difference between V + and V -, or some combination thereof. The multiplexer circuit MUX320 may selectively send the first current output signal IIN and the third current output signal PIN as ISYS and PSYS via a single node. Thus, the monitor module circuit 205 can advantageously send current mode signals corresponding to the current, power, and voltage of the power output. For example, the monitor module 205 may be configured as an analog circuit, a digital circuit, or some combination thereof.

[0062] Figure 4A block diagram of an exemplary digital monitor module circuit representing a noise disturbance rejection circuit NDRC, which is configured to detect at least one output parameter in voltage mode and convert it to current mode. In the depicted example, the exemplary monitor module circuit 205 is configured with digital circuitry. The monitor module circuit 205 is operatively connected to nodes V+ and V- through a voltage difference (e.g., through a resistor, such as RSENSE). The monitor module 205 is also operatively referenced to a first circuit reference potential CRP1.

[0063] As shown, the first sampling circuit 405A samples the voltage V+ with reference to V (e.g., corresponding to the current and / or power of the power output, detected in voltage mode), and provides the result to the analog-to-digital converter ADC410. The second sampling circuit 405B samples the voltage V+ with reference to the first circuit reference potential CRP1 (e.g., corresponding to the voltage (VPSU) of the power output detected in voltage mode), and provides the result to the analog-to-digital converter ADC 410. The analog-to-digital converter ADC 410 can convert the analog (voltage) signal into a digital (voltage) signal for the measurement circuit 415.

[0064] The measurement circuit 415 includes a power calculation module 420 and an output module 425. By way of example, but not limitation, the power calculation module 420 can calculate voltage, current, power, or some combination thereof from the signals generated by the analog-to-digital converter ADC 410 from the signals from the sampling circuits 405A and 405B. For example, the power calculation module 420 can determine the voltage (e.g., VPSU) from the signal generated by the sampling circuit 405B, the current from the signal generated by the sampling circuit 405A, and / or the power from the combination of the signals generated by the sampling circuits 405A and 405B. The measurement circuit 415 can include, for example, at least one processor, non-volatile memory, random access memory, look-up table, integrated circuit, ASIC, FPGA, or some combination thereof. By way of example, but not limitation, the power calculation module can include computer code configured to cause the processor to execute steps to generate certain combinations of voltage, current, power, other appropriate parameters, or signals.

[0065] The output module 425 can adjust the output, e.g., scale, transform (e.g., electrical, mathematical), convert to a specific standard, code, and / or format, or some combination thereof. The output module 425 can identify and / or address a specific data signal received from the power calculation module 420 to a specific output node (e.g., current, power, and / or voltage). In the depicted example, the output module 425 provides an output signal related to the current and / or power output parameter to the first voltage-current converter VCC circuit 430A. The output module 425 further provides an output signal related to the voltage output parameter to the second VCC circuit 430B.

[0066] Exemplarily, the first voltage - current converter VCC circuit 430A and the second voltage - current converter VCC circuit 430B can convert the corresponding output parameter signals from the output module 425 from voltage - mode signals to current - mode signals. The second voltage - current converter VCC circuit 430B can convert the received voltage output parameter signal from voltage - mode to current - mode signal ISYS. The first voltage - current converter VCC circuit 430A can convert the received current and / or power output parameter signals from voltage - mode to current - mode signals ISYS (current output parameter) and / or PSYS (power output parameter). By way of example, but not limitation, the power calculation module 420, the analog - to - digital converter ADC 410, the measurement circuit 415, and / or the output module 425 can include a multiplexer circuit configured to selectively calculate and / or output (e.g., select one or more, alternate between multiple signals) different output parameter signals. For example, the first voltage - current converter VCC circuit 430A can selectively (e.g., via an analog and / or digital multiplexer in the first voltage - current converter VCC circuit 430A and / or upstream) output the current - mode current output parameter signal ISYS and the current - mode power output parameter signal PSYS.

[0067] Figure 5 An exemplary implementation of the noise disturbance rejection circuit NDRC is depicted. The noise disturbance rejection circuit NDRC is configured to send output parameters from the power circuit reference domain CRD to the analog circuit reference domain CRD in the current mode. Circuit 500 has a load 115 provided by a power output with voltage VPSU - N. The system power monitor circuit SPMC 130 measures the voltage - mode current VISYS of the power output through resistors RSENSE at nodes V+ and V - of the system power monitor circuit SPMC 130. The system power monitor circuit SPMC 130 measures the voltage of the power output in voltage - mode with reference to the first circuit reference potential CRP1. In the described example, the first circuit reference potential CRP1 is the power ground reference PGND. The system power monitor circuit SPMC 130 converts the voltage - mode current output parameter signal VISYS to a current - mode signal ISYS. The system power monitor circuit SPMC 130 converts the voltage - mode voltage output parameter signal VSYS to a current - mode signal IVSYS.

[0068] The current mode output parameter signals (ISYS and IVSYS) are sent from the system power monitor circuit SPMC 130 in the first circuit reference domain CRD1150A located at the reference power ground reference PGND to the controller 145. The controller 145 is located in the second circuit reference domain CRD2150B that references the second circuit reference potential CRP2. In the example described, the second circuit reference potential CRP2 is the analog ground AGND. Thus, the output parameter signals are sent from the power ground circuit reference domain CRD to the analog ground circuit reference domain CRD. In the depicted example, the current mode signals are converted back to voltage mode at the controller 145 by a resistor operably referencing the analog ground AGND circuit reference potential CRP. As shown, ISYS is converted to a scaled voltage mode signal VISYS_SCALED scaled by a first resistor having a resistance RSCALE1, and IVSYS is converted to a scaled voltage mode signal VSYS_SCALED scaled by a second resistor having a resistance RSCALE2.

[0069] In the example shown, the physical transmission link between the various components of circuit 500 has a resistance 505. For example, the resistance can be the resistance in a path through one or more printed circuit boards PCBs, wires, cables, buses, other suitable conductors, or some combination thereof. As Figure 5 shown, the resistance encountered by the current mode output parameter signal between the system power monitor circuit SPMC 130 and the controller 145 can be at least partially the resistance of the trace from to in the PCB board (having a resistance RTRACE). Similarly, the transmission link for the power supply output to a load in the first circuit reference domain CRD 150A can, for example, be at least partially from a conductor in the backplane (having a resistance RPLANE).

[0070] As shown, the transmission link resistance 505 (e.g., RTRACE) can introduce a voltage difference dV between the two circuit reference potentials CRP analog ground AGND and power ground PGND of the corresponding circuit reference domain CRD. In various embodiments, the voltage difference dV can be between 1 - 3%. The voltage difference dV will introduce noise in the output parameter signals sent in voltage mode from the system power monitor circuit SPMC 130 in the power circuit reference domain CRD (CRD1) and the controller 145 in the analog circuit reference domain CRD (CRD2). This relationship is represented by Equation 9, where VS CRD1 is the voltage mode signal at the system power monitor circuit SPMC 130 in the power ground circuit reference domain PGND CRD, and VS CRD2 is the voltage mode signal seen / measured at the controller 145 in the analog ground circuit reference domain AGND CRD:

[0071] Equation 9 VSCRD2 = VS CRD1 + dV ≠ VS CRD1

[0072] However, in various embodiments, load 115 may require a more stable and / or more precisely controlled power output from the power supply unit PSU. For example, load 115 may include a high-performance processor that requires tightly controlled power input (e.g., from the power supply unit PSU). In various embodiments, by way of example but not limitation, load 115 may require that the variance of the output parameters (e.g., voltage) of the power supplied to the load be less than 5%, 3%, or 1%.

[0073] In the example shown, the first circuit reference domain CRD1 and the second circuit reference domain CRD2 are connected by a current circuit reference potential CRP link 155. The current circuit reference potential CRP link 155 provides a non-zero resistance (RL) return path between the analog ground AGND and the power ground PGND (the second circuit reference potential CRP2 and the first circuit reference potential CRP1, respectively) for one or more current-mode signals (e.g., ISYS, IVSYS). Thus, the current-mode output parameter signals (e.g., ISYS, IVSYS) at the system power monitor circuit SPMC 130 in the power ground circuit reference domain PGND CRD (CRD1) are substantially equivalent to the corresponding current-mode output parameter signals (e.g., ISYS, IVSYS, respectively) seen at the controller 145 in the analog ground circuit reference domain AGND CRD (CRD2). The noise introduced in the current mode (e.g., ground noise) may be at least one order of magnitude lower than in the voltage mode. Thus, precise output parameters (e.g., voltage, current, power) can be determined from the current-mode signals. For example, the voltage of the voltage signal VPSU can be accurately determined from IVSYS. Thus, when compared to transmitting the corresponding output parameter signals in the voltage mode, the noise interference in the output parameter signals can be attenuated by a factor of at least 10, 100, or more by way of example but not limitation. The reduced noise can advantageously provide a more stable and / or more tightly controlled voltage power output to load 115. Thus, compared to a power supply circuit that transmits output parameter signals across one or more circuit reference domains CRD in the voltage mode, a power supply circuit including a noise disturbance rejection circuit NDRC 500 can advantageously meet a more stringent (e.g., smaller) error tolerance when providing a power signal to load 115.

[0074] Although various embodiments have been described with reference to the drawings, other embodiments are possible. For example, although an exemplary system has been described with reference to the drawings, other implementations may be deployed in other industrial, scientific, medical, commercial, and / or residential applications.

[0075] In various embodiments, multiple circuit reference domains (CRDs) and corresponding circuit reference potentials (CRPs) may be provided, by way of example and not limitation, including 2, 3, 4, 5, 10 or more. Current circuit reference potential CRP links may connect any combination (as appropriate) of circuit reference domains CRD. In various embodiments, the voltage difference (e.g., dV) between two different circuit reference potentials CRP may be substantially zero at low frequencies, but may increase at high frequencies. Accordingly, various embodiments may advantageously provide improved noise suppression at any higher frequency than achievable with voltage-mode output parameter signals.

[0076] In various embodiments, some bypass circuit implementations may be controlled in response to signals from analog or digital components, which may be discrete, integrated, or some combination thereof. Some embodiments may include programmed, programmable devices, or some combination thereof (e.g., PLA, PLD, ASIC, microcontroller, microprocessor), and may include one or more data memories (e.g., cells, registers, blocks, pages) that provide single-level or multi-level digital data storage capabilities, and may be volatile, non-volatile, or some combination thereof. Some control functions may be implemented in hardware, software, firmware, or some combination thereof.

[0077] For example, a temporary auxiliary energy input may be received from a rechargeable or disposable battery, which may be used for portable or remote applications. Some embodiments may work with other DC voltage sources (e.g., batteries). An alternating current (AC) input may be received through a rectifier and appropriate scaling, and the AC input may be provided, for example, from a 50 / 60 Hz power port or a portable generator. The AC (e.g., sine wave, square wave, triangular wave) input means may include a line frequency transformer to provide voltage boost, voltage buck, and / or isolation.

[0078] Various examples of modules may be implemented using circuits that include various electronic hardware. By way of example and not limitation, the hardware may include transistors, resistors, capacitors, switches, integrated circuits, other modules, or some combination thereof. In various examples, the module may include analog logic, digital logic, discrete components, traces, and / or memory circuits fabricated on a silicon substrate, including various integrated circuits (e.g., FPGAs, ASICs), or some combination thereof. In some embodiments, the module may involve the execution of pre-programmed instructions, software executed by a processor, or some combination thereof. For example, various modules may involve both hardware and software simultaneously.

[0079] This specification has described some embodiments. However, it should be understood that various modifications can also be made. For example, favorable results can be achieved if the steps of the disclosed technology are performed in a different order, or if the components of the disclosed system are combined in a different manner, or if the components are supplemented with other components. Accordingly, other embodiments are within the scope of the following claims.

Claims

1. A noise interference suppression circuit, characterized in that, Comprising: A power supply monitoring circuit PSMC, operably referencing a first circuit reference potential CRP, and configured to generate a first voltage mode signal relative to the first circuit reference potential CRP1, the first voltage mode signal corresponding to a first output parameter of a power output delivered from a power supply circuit PSC to a load, and to convert the first voltage mode signal into a first current mode signal; A control circuit, operably referencing a second circuit reference potential CRP2, and configured to generate a control signal from the first current mode signal, the control circuit being operably coupled to the power supply circuit PSC such that the power supply circuit PSC determines the first output parameter based on the control signal; And A current link electrically connecting the first circuit reference potential CRP1 and the second circuit reference potential CRP2, the current link being configured to carry a return path of the first current mode signal via a non-zero resistance path, Wherein a noise tolerance of the first current mode signal presented at the control circuit is less than or equal to ten percent of a noise tolerance of an equivalent voltage mode signal.

2. The noise interference suppression circuit according to claim 1, wherein The first output parameter includes an output voltage of the power supply circuit PSC.

3. The noise interference suppression circuit according to claim 1, characterized in that, The power supply monitoring circuit PSMC includes a configured voltage-to-current converter circuit to convert the first voltage mode signal into the first current mode signal.

4. The noise interference suppression circuit according to claim 1, characterized in that Configure the power supply monitoring circuit PSMC to generate a second current mode signal proportional to a second output parameter of the power output.

5. The noise interference suppression circuit according to claim 4, wherein The second output parameter includes an output power of the power supply circuit PSC.

6. The noise interference suppression circuit according to claim 4, characterized in that, The second output parameter includes an output current of the power supply circuit PSC.

7. The noise interference suppression circuit according to claim 4, wherein The power supply monitoring circuit PMSC is further configured to generate a second voltage mode signal proportional to the second output parameter and to convert the second voltage mode signal into the second current mode signal.

8. The noise interference suppression circuit according to claim 7, characterized in that, Further configure the power supply monitoring circuit PSMC to: Generate the first voltage mode signal by measuring a first voltage reference of the power output relative to the first circuit reference potential CRP1, and, Generate the second voltage mode signal by measuring the first voltage reference of the power output relative to a second voltage reference of the power output.

9. The noise interference suppression circuit according to claim 1, wherein The second current mode signal represents a current at the power output end; and Configure the power supply monitoring circuit PSMC to generate a third current mode signal representing the power of the power output by multiplying the first current mode signal and the second current mode signal.

10. The noise interference suppression circuit according to claim 1, wherein, The control circuit converts the first current mode signal into a received voltage mode signal.

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