A signal detection circuit and method

Abstract

The present disclosure provides a signal detection circuit and method, which can include a first pulse clock module, a second pulse clock module and a sampling circuit; the first pulse clock module is connected with the second pulse clock module, and is used to output a first pulse clock signal to the second pulse clock module; the second pulse clock module is used to receive the first pulse clock signal and output a second pulse clock signal; the sampling circuit is connected with the first pulse clock module and the second pulse clock module respectively, and is used to acquire the first pulse clock signal and the second pulse clock signal, and judge whether the first pulse clock signal overlaps with the second pulse clock signal, and output a detection signal in the case of yes. By judging whether the first pulse clock signal overlaps with the second pulse clock signal, the chip fault can be accurately located, the subsequent fault troubleshooting is facilitated, and the efficiency is improved.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to, but is not limited to, the technical field of semiconductor manufacturing technology, and in particular, to a signal detection circuit and method. BACKGROUND

[0002] A chip is a kind of integrated circuit (IC), which is composed of a large number of transistors. Different chips have different integration scales, as large as hundreds of millions, and as small as tens or hundreds of transistors. The transistors have two states, on and off, represented by 1 and 0. Multiple 1 and 0 signals generated by multiple transistors are set to specific functions (i.e. instructions and data) to represent or process letters, numbers, colors and graphics, etc. After the chip is powered on, a start instruction is first generated to start the chip, and then new instructions and data are continuously accepted to complete the function.

[0003] During the operation of the chip, the specific phase of the internal clock of the chip is difficult to capture, so that once the chip fails, it is difficult to locate the device position and the failure cause, affecting the subsequent troubleshooting. SUMMARY

[0004] The present disclosure provides a signal detection circuit and method to accurately locate chip failure, facilitate subsequent troubleshooting, and improve efficiency.

[0005] In a first aspect, the present disclosure provides a signal detection circuit, comprising: a first pulse clock module, a second pulse clock module and a sampling circuit, wherein the first pulse clock module is connected with the second pulse clock module, and is configured to output a first pulse clock signal to the second pulse clock module; the second pulse clock module is configured to receive the first pulse clock signal and output a second pulse clock signal; the sampling circuit is connected with the first pulse clock module and the second pulse clock module respectively, and is configured to acquire the first pulse clock signal and the second pulse clock signal, and determine whether the first pulse clock signal overlaps with the second pulse clock signal, and output a detection signal in the case that the determination result is yes.

[0006] In a possible implementation, the sampling circuit comprises: a logic gate and a register, wherein the logic gate is configured to receive the first pulse clock signal, the second pulse clock signal, a sampling signal and a sampling output signal, and input a determination result of the first pulse clock signal, the second pulse clock signal, the sampling signal and the sampling output signal after logical determination into the register; the register is connected with the logic gate, and is configured to determine whether the first pulse clock signal overlaps with the second pulse clock signal according to the determination result, and output the detection signal in the case that the determination result is yes.

[0007] In a possible implementation, the logic gate comprises an NOR gate and an NAND gate, wherein the NOR gate is configured to receive the sampling signal and the sampling output signal, and perform an NOR judgment according to the sampling signal and the sampling output signal, and output a first logic judgment result; and the NAND gate is configured to obtain the first pulse clock signal, the second pulse clock signal and the sampling signal, and perform an NAND judgment according to the first pulse clock signal, the second pulse clock signal and the sampling signal, and output a second logic judgment result.

[0008] In a possible implementation, the register is configured to receive the first logic judgment result and the second logic judgment result, and when the sampling signal is the first level signal, judge whether the first pulse clock signal and the second pulse clock signal are simultaneously at the first level signal according to the first logic judgment result and the second logic judgment result, and output the second level signal as the detection signal in a case where the judgment result is yes.

[0009] In a possible implementation, the first level signal is a high level signal, and the second level signal is a low level signal; or, the first level signal is a low level signal, and the second level signal is a high level signal.

[0010] In a second aspect, the present disclosure provides a signal detection method, which is applied to the signal detection circuit in the first aspect and any possible implementation thereof, and comprises: obtaining a first pulse clock signal and a second pulse clock signal; judging whether the first pulse clock signal overlaps with the second pulse clock signal; and outputting a detection signal in a case where the judgment result is yes.

[0011] In a possible implementation, the obtaining of the first pulse clock signal and the second pulse clock signal comprises: obtaining the first pulse clock signal from a first pulse clock module, and obtaining the second pulse clock signal from a second pulse clock module.

[0012] In a possible implementation, the signal detection method further comprises: receiving a sampling signal and a sampling output signal.

[0013] In a possible implementation, the judging of whether the first pulse clock signal overlaps with the second pulse clock signal comprises: performing a logic judgment on the first pulse clock signal, the second pulse clock signal, the sampling signal and the sampling output signal to obtain a judgment result; and judging whether the first pulse clock signal overlaps with the second pulse clock signal according to the judgment result.

[0014] In one possible implementation, performing logical judgments on the first pulse clock signal, the second pulse clock signal, the sampling signal, and the sampling output signal to obtain a judgment result includes: receiving the sampling signal and the sampling output signal, performing NOR logic judgments based on the sampling signal and the sampling output signal, and outputting a first logical judgment result; acquiring the first pulse clock signal, the second pulse clock signal, and the sampling signal, performing NAND logic judgments based on the first pulse clock signal, the second pulse clock signal, and the sampling signal, and outputting a second logical judgment result; and generating a judgment result based on the first logical judgment result and the second logical judgment result.

[0015] In one possible implementation, determining whether the first pulse clock signal overlaps with the second pulse clock signal based on the judgment result includes: receiving the judgment result; when the sampled signal in the judgment result is a first level signal, determining whether the first pulse clock signal and the second pulse clock signal are simultaneously at the first level signal based on the first logic judgment result and the second logic judgment result.

[0016] In one possible implementation, the output detection signal includes: when the first pulse clock signal and the second pulse clock signal are both at the first level signal, outputting a second level signal and using the second level signal as the detection signal; wherein the first level signal is a high level signal and the second level signal is a low level signal; or, the first level signal is a low level signal and the second level signal is a high level signal.

[0017] The technical solution provided in this disclosure may include the following beneficial effects:

[0018] In this disclosure, in the signal detection circuit composed of the first pulse clock module, the second pulse clock module, and the sampling circuit, by performing logical judgment on the first pulse clock signal, the second pulse clock signal, the sampling signal, and the sampling output signal, it is determined whether the first pulse clock signal and the second pulse clock signal overlap. This can accurately locate chip faults, facilitate subsequent fault diagnosis, and improve efficiency.

[0019] Furthermore, the internal clock status can be observed after the chip is returned to the die, providing data for board-level debugging;

[0020] In addition, the signal detection circuit has a simple structure and few circuit units, which makes it small in size and low in power consumption.

[0021] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit the scope of protection of this disclosure. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of a first structure of the signal detection circuit in an embodiment of this disclosure;

[0023] Figure 2 This is a schematic diagram of a second structure of the signal detection circuit in an embodiment of this disclosure;

[0024] Figure 3 This is a schematic diagram of a sampling circuit in one embodiment of the present disclosure;

[0025] Figure 4 This is a timing diagram of a signal detection circuit in an embodiment of this disclosure. Detailed Implementation

[0026] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses consistent with some aspects of this disclosure as detailed in the appended claims.

[0027] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0028] To illustrate the technical solutions described in this disclosure, specific embodiments are provided below.

[0029] A chip is a silicon wafer containing integrated circuits, hence it is also called an integrated circuit. A chip generally refers to the carrier of an integrated circuit, and is the result of the integrated circuit's design, manufacturing, packaging, and testing. It is usually a self-contained unit that can be used immediately. As the most important part of electronic devices, the chip undertakes the functions of computation and storage.

[0030] Currently, in chip design, due to the lack of detection of pulse clock signals, it is difficult for technicians to understand the specific phase of the internal clock of the chip. In particular, when two clocks overlap, the chip may not work.

[0031] To address the aforementioned problems, this disclosure provides a signal detection circuit to solve the issue that a chip cannot function due to a lack of signal detection for clock overlap.

[0032] So, Figure 1 This is a schematic diagram of a first structure of the signal detection circuit in an embodiment of this disclosure.

[0033] See Figure 1 As shown, the signal detection circuit 100 may include: a first pulse clock module 101, a second pulse clock module 102, and a sampling circuit 101.

[0034] In some possible implementations, a first pulse clock module p1 is connected to a second pulse clock module p2. The first pulse clock module p1 is used to output a first pulse clock signal to the second pulse clock module p2. The second pulse clock module p2 is used to receive the first pulse clock signal and output a second pulse clock signal. A sampling circuit 101 is connected to the first pulse clock module p1 and the second pulse clock module p2 respectively. The sampling circuit 101 is used to acquire the first pulse clock signal and the second pulse clock signal, and determine whether the first pulse clock signal overlaps with the second pulse clock signal. If the determination result is yes, a detection signal is output.

[0035] The first clock module p1 and the second clock module p2 may include, but are not limited to, clock generators, general-purpose timers, and clock circuits. The sampling circuit 101 may include, but is not limited to, NOR gates, NAND gates, and registers.

[0036] The signal detection circuit 100 will be described in detail below, taking the first clock module p1 and the second clock module p2 as clock generators as examples.

[0037] For example, clock generator A (i.e., the first clock module) and clock generator B (i.e., the second clock module) are connected, and clock generator A and clock generator B are respectively connected to a sampling circuit. Clock generator A outputs a first pulse clock signal to clock generator B and the sampling circuit. Clock generator B receives the first pulse clock signal and outputs a second pulse clock signal to the sampling circuit. The sampling circuit receives the first pulse clock signal and the second pulse clock signal, performs logical judgment on the first pulse clock signal and the second pulse clock signal, and then outputs a detection signal.

[0038] It should be noted that the signal detection circuit may include a first pulse clock module, a second pulse clock module, and a sampling circuit, or it may include multiple pulse clock modules and multiple sampling circuits.

[0039] The signal detection circuit will be explained in detail below using a six-pulse clock module and five sampling circuits as an example.

[0040] Figure 2 This is a schematic diagram of a second structural embodiment of the signal detection circuit in this disclosure. See also... Figure 2As shown, the signal detection circuit 100 may include: a first pulse clock module p1, a second pulse clock module p2, a third pulse clock module p3, a fourth pulse clock module p4, a fifth pulse clock module p5, a sixth pulse clock module p6, a first sampling circuit s1, a second sampling circuit s2, a third sampling circuit s3, a fourth sampling circuit s4, and a fifth sampling circuit s5.

[0041] In some possible implementations, the first pulse clock module p1 is connected to the second pulse clock module p2, outputting a first pulse clock signal CK1 to the second pulse clock module p2. The second pulse clock module p2 is connected to both the first pulse clock module p1 and the third pulse clock module p1. The second pulse clock module p2 receives the first pulse clock signal CK1 and outputs a second pulse clock signal CK2 to the third pulse clock module p3. The first sampling circuit s1 is connected to the first pulse clock module p1, the second pulse clock module p2, and the second sampling circuit s2, respectively, to acquire the first pulse clock signal CK1 and the second pulse clock signal CK2, and to determine whether the first pulse clock signal CK1 is synchronized with the second pulse clock signal CK2. If the pulse clock signals CK2 overlap, and the judgment result is yes, the detection signal Q1 is output to the second sampling circuit s2. The third pulse clock module p3 is connected to the second pulse clock module p2 and the fourth pulse clock module p4 respectively. The third pulse clock module p3 receives the second pulse clock signal CK2 and outputs the third pulse clock signal CK3 to the fourth pulse clock module p4. The second sampling circuit s2 is connected to the second pulse clock module p2, the third pulse clock module p3, the first sampling circuit s1, and the third sampling circuit s3 respectively, to acquire the second pulse clock signal CK2 and the third pulse clock signal CK3, and to determine whether the second pulse clock signal CK2 overlaps with the third pulse clock signal CK3. If the judgment result is yes, the detection signal Q2 is output to the third sampling circuit s3; the fourth pulse clock module p4 is connected to the third pulse clock module p3 and the fifth pulse clock module p5 respectively. The fourth pulse clock module p4 receives the third pulse clock signal CK3 and outputs the fourth pulse clock signal CK4 to the fifth pulse clock module p5. The third sampling circuit s3 is connected to the third pulse clock module p3, the fourth pulse clock module p4, the second sampling circuit s2 and the fourth sampling circuit s4 respectively, to acquire the third pulse clock signal CK3 and the fourth pulse clock signal CK4, and to determine whether the third pulse clock signal CK3 overlaps with the fourth pulse clock signal CK4. If the judgment result is yes, the detection signal Q2 is output to the third sampling circuit s3. The detection signal Q3 is sent to the fourth sampling circuit s4; the fifth pulse clock module p5 is connected to the fourth pulse clock module p4 and the sixth pulse clock module p6 respectively. The fifth pulse clock module p5 receives the fourth pulse clock signal CK4 and outputs the fifth pulse clock signal CK5 to the sixth pulse clock module p6. The fourth sampling circuit s4 is connected to the fourth pulse clock module p4, the third sampling circuit s3 and the fifth sampling circuit s5 respectively. It acquires the fourth pulse clock signal CK4 and the fifth pulse clock signal CK5, and determines whether the fourth pulse clock signal CK4 overlaps with the fifth pulse clock signal CK5. If the determination result is yes, the detection signal Q4 is output to the fifth sampling circuit s5.The sixth pulse clock module p6 is connected to the fifth pulse clock module p5. The sixth pulse clock module p6 receives the fifth pulse clock signal CK5 and outputs the sixth pulse clock signal CK6. The fifth sampling circuit s5 is connected to the fifth pulse clock module p5, the sixth pulse clock module p6, and the fourth sampling circuit s4, respectively, to acquire the fifth pulse clock signal CK5 and the sixth pulse clock signal CK6, and to determine whether the fifth pulse clock signal CK5 overlaps with the sixth pulse clock signal CK6. If the determination result is yes, a detection signal Q5 is output.

[0042] Figure 3 This is a schematic diagram of one embodiment of the sampling circuit in this disclosure. See also... Figure 3 As shown, the sampling circuit 101 may include: NOR gate 301, NAND gate 302 and register 303.

[0043] The following is combined with Figure 3 The schematic diagram shown illustrates some possible implementations of the sampling circuit 101.

[0044] In some possible implementations, the NOR gate 301 and NAND gate 302 in the sampling circuit 101 are used to receive the first pulse clock signal CK1, the second pulse clock signal CK2, the sampling signal SAMPLE, and the sampling output signal Qn-1, and after logically judging the first pulse clock signal CK1, the second pulse clock signal CK2, the sampling signal SAMPLE, and the sampling output signal Qn-1, the judgment result is input into the register 303.

[0045] It should be noted that the sampling output signal is the sampling signal output by the previous stage sampling circuit of the current sampling circuit.

[0046] In some possible implementations, the NOR gate 301 can receive the sampling signal SAMPLE and the sampling output signal Qn-1, and perform NOR judgment based on the sampling signal SAMPLE and the sampling output signal Qn-1 to output the first logic judgment result.

[0047] For example, the NOR gate 301 may include two pins (denoted as pin a1 and pin a2). Pin a1 serves as the input terminal of the NOR gate 301, inputting the sampled output signal Qn-1. Pin a2 serves as the input terminal of the NOR gate 301, inputting the sampled signal SAMPLE. Pin N1 serves as the output terminal of the NOR gate 301, inputting the first logic judgment result to register 303.

[0048] In some possible implementations, the NAND gate circuit 302 can acquire the first pulse clock signal CK1, the second pulse clock signal CK2 and the sampling signal SAMPLE, and perform NAND judgment based on the first pulse clock signal CK1, the second pulse clock signal CK2 and the sampling signal SAMPLE to output the second logic judgment result.

[0049] For example, the NAND gate 302 may include three pins (denoted as pin b1, pin b2 and pin b3). Pin b1 serves as the input of the NAND gate 302, receiving the sampling signal SAMPLE. Pin b2 serves as the input of the NAND gate 302, receiving the first pulse clock signal CK1. Pin b3 serves as the input of the NAND gate 302, receiving the second pulse clock signal CK2. Pin N2 serves as the output of the NAND gate 302, inputting the second logic judgment result to register 303.

[0050] In some possible implementations, register 303 is connected to logic gates (i.e., NOR gate 301 and NAND gate 302) and can be used to determine whether the first pulse clock signal CK1 overlaps with the second pulse clock signal CK2 based on the judgment result. If the judgment result is yes, a detection signal is output.

[0051] In some possible implementations, register 303 receives the first logic judgment result and the second logic judgment result. When the sampling signal SAMPLE is a first level signal, it determines whether the first pulse clock signal CK1 and the second pulse clock signal CK2 are simultaneously at the first level signal based on the first logic judgment result and the second logic judgment result. If the judgment result is yes, it outputs the second level signal and uses the second level signal as the detection signal.

[0052] Wherein, when the first level signal is a high level signal, the second level signal is a low level signal; or, when the first level signal is a low level signal, the second level signal is a high level signal.

[0053] For example, in some possible implementations, the input port D of register 303 is input by the output port (i.e., pin N1) of NOR gate 301, the input port CK is input by external input CK, the input port CDN is input by the output port (i.e., pin N2) of NAND gate 302, and the output port Q outputs the detection signal Qn.

[0054] It should be noted that the CDN input port uses a low-level active clear signal.

[0055] Figure 4 This is a timing diagram of a signal detection circuit in an embodiment of this disclosure. For example... Figure 4As shown, the timing diagram includes: a sampling signal SAMPLE, a first pulse clock signal CK1, a second pulse clock signal CK2, and a detection signal Qn.

[0056] Among them, the waveforms of the sampling signal SAMPLE, the first pulse clock signal CK1, the second pulse clock signal CK2, and the detection signal Qn alternately change to high or low levels.

[0057] For example, when the sampling signal SAMPLE is a high-level signal, sampling begins. The logic gate outputs the first logic judgment result and the second logic judgment result. In the judgment result, the sampling signal SAMPLE is a high-level signal, and both the CK1 signal and the CK2 signal are high-level signals, which indicates that the CK1 signal and the CK2 signal overlap. At this time, the detection signal Qn is output, and the detection signal Qn is a low-level signal.

[0058] In another embodiment, when the sampling signal SAMPLE is a high-level signal, sampling begins. The logic gate outputs a first logic judgment result and a second logic judgment result. In the judgment result, the sampling signal SAMPLE is a high-level signal, and both the CK1 and CK2 signals are low-level signals, indicating that the CK1 and CK2 signals overlap. At this time, the detection signal Qn is output, and the detection signal Qn is a high-level signal.

[0059] In this disclosure, in the signal detection circuit composed of the first pulse clock module, the second pulse clock module, and the sampling circuit, by performing logical judgment on the first pulse clock signal, the second pulse clock signal, the sampling signal, and the sampling output signal, it is determined whether the first pulse clock signal and the second pulse clock signal overlap. This can accurately locate chip faults, facilitate subsequent fault diagnosis, and improve efficiency.

[0060] Furthermore, the internal clock status can be observed after the chip is returned to the die, providing data for board-level debugging;

[0061] In addition, the signal detection circuit has a simple structure and few circuit units, which makes it small in size and low in power consumption.

[0062] The above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit it. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or some of the technical features can be replaced. Such modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this disclosure, and should all be included within the protection scope of this disclosure.

Claims

1. A signal detection circuit, characterized in that, include: The system comprises a first pulse clock module, a second pulse clock module, and a sampling circuit, wherein... The first pulse clock module is connected to the second pulse clock module and is used to output a first pulse clock signal to the second pulse clock module; the second pulse clock module is used to receive the first pulse clock signal and output a second pulse clock signal. The sampling circuit is connected to the first pulse clock module and the second pulse clock module respectively, and is used to acquire the first pulse clock signal and the second pulse clock signal, and determine whether the first pulse clock signal overlaps with the second pulse clock signal. If the determination result is yes, a detection signal is output. The sampling circuit includes a logic gate and a register. The logic gate is used to receive the first pulse clock signal, the second pulse clock signal, the sampling signal, and the sampling output signal, and after logical judgment, input the judgment result into the register. The register is connected to the logic gate and is used to determine whether the first pulse clock signal overlaps with the second pulse clock signal based on the judgment result. If the judgment result is yes, a detection signal is output.

2. The signal detection circuit according to claim 1, characterized in that, The logic gates include: NOR gates and NAND gates, wherein... The NOR gate is used to receive the sampling signal and the sampling output signal, and to perform NOR judgment based on the sampling signal and the sampling output signal, and output a first logic judgment result; The NAND gate is used to acquire the first pulse clock signal, the second pulse clock signal, and the sampled signal, and to perform NAND judgment based on the first pulse clock signal, the second pulse clock signal, and the sampled signal, and output the second logic judgment result.

3. The signal detection circuit according to claim 1, characterized in that, The register is used to receive the first logic judgment result and the second logic judgment result. When the sampling signal is a first level signal, it determines whether the first pulse clock signal and the second pulse clock signal are simultaneously at the first level signal based on the first logic judgment result and the second logic judgment result. If the judgment result is yes, it outputs a second level signal and uses the second level signal as the detection signal.

4. The signal detection circuit according to claim 3, characterized in that, The first level signal is a high level signal, and the second level signal is a low level signal; or, the first level signal is a low level signal, and the second level signal is a high level signal.

5. A signal detection method, characterized in that, The method, applied to the signal detection circuit according to any one of claims 1 to 4, comprises: Acquire the first pulse clock signal and the second pulse clock signal; Determine whether the first pulse clock signal overlaps with the second pulse clock signal; If the judgment result is yes, output a detection signal; The step of obtaining the first pulse clock signal and the second pulse clock signal includes: obtaining the first pulse clock signal from the first pulse clock module and obtaining the second pulse clock signal from the second pulse clock module; The method further includes: receiving a sampling signal and a sampling output signal; The step of determining whether the first pulse clock signal overlaps with the second pulse clock signal includes: performing logical judgment on the first pulse clock signal, the second pulse clock signal, the sampling signal, and the sampling output signal to obtain a judgment result; and determining whether the first pulse clock signal overlaps with the second pulse clock signal based on the judgment result.

6. The method according to claim 5, characterized in that, The step of performing logical judgment on the first pulse clock signal, the second pulse clock signal, the sampling signal, and the sampling output signal to obtain the judgment result includes: Receive the sampling signal and the sampling output signal, and perform a NOR logic judgment based on the sampling signal and the sampling output signal, and output a first logic judgment result; Acquire the first pulse clock signal, the second pulse clock signal, and the sampled signal, and perform NAND logic judgment based on the first pulse clock signal, the second pulse clock signal, and the sampled signal to output the second logic judgment result; The judgment result is generated based on the first logical judgment result and the second logical judgment result.

7. The method according to claim 6, characterized in that, The step of determining whether the first pulse clock signal overlaps with the second pulse clock signal based on the determination result includes: Receive the judgment result; When the sampled signal in the judgment result is a first level signal, the first pulse clock signal and the second pulse clock signal are judged to be simultaneously at the first level signal based on the first logic judgment result and the second logic judgment result.

8. The method according to claim 7, characterized in that, The output detection signal includes: When the first pulse clock signal and the second pulse clock signal are both at the first level signal, the second level signal is output and the second level signal is used as the detection signal; Wherein, the first level signal is a high level signal and the second level signal is a low level signal; or, the first level signal is a low level signal and the second level signal is a high level signal.

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